1 /*
2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33 
34 
35 #include <linux/if_vlan.h>
36 
37 #include <linux/mlx4/device.h>
38 #include <linux/mlx4/cmd.h>
39 
40 #include "en_port.h"
41 #include "mlx4_en.h"
42 
43 
44 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv)
45 {
46 	struct mlx4_cmd_mailbox *mailbox;
47 	struct mlx4_set_vlan_fltr_mbox *filter;
48 	int i;
49 	int j;
50 	int index = 0;
51 	u32 entry;
52 	int err = 0;
53 
54 	mailbox = mlx4_alloc_cmd_mailbox(dev);
55 	if (IS_ERR(mailbox))
56 		return PTR_ERR(mailbox);
57 
58 	filter = mailbox->buf;
59 	for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) {
60 		entry = 0;
61 		for (j = 0; j < 32; j++)
62 			if (test_bit(index++, priv->active_vlans))
63 				entry |= 1 << j;
64 		filter->entry[i] = cpu_to_be32(entry);
65 	}
66 	err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
67 		       MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
68 	mlx4_free_cmd_mailbox(dev, mailbox);
69 	return err;
70 }
71 
72 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
73 {
74 	struct mlx4_en_query_port_context *qport_context;
75 	struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
76 	struct mlx4_en_port_state *state = &priv->port_state;
77 	struct mlx4_cmd_mailbox *mailbox;
78 	int err;
79 
80 	mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
81 	if (IS_ERR(mailbox))
82 		return PTR_ERR(mailbox);
83 	err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
84 			   MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
85 			   MLX4_CMD_WRAPPED);
86 	if (err)
87 		goto out;
88 	qport_context = mailbox->buf;
89 
90 	/* This command is always accessed from Ethtool context
91 	 * already synchronized, no need in locking */
92 	state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
93 	switch (qport_context->link_speed & MLX4_EN_SPEED_MASK) {
94 	case MLX4_EN_100M_SPEED:
95 		state->link_speed = SPEED_100;
96 		break;
97 	case MLX4_EN_1G_SPEED:
98 		state->link_speed = SPEED_1000;
99 		break;
100 	case MLX4_EN_10G_SPEED_XAUI:
101 	case MLX4_EN_10G_SPEED_XFI:
102 		state->link_speed = SPEED_10000;
103 		break;
104 	case MLX4_EN_20G_SPEED:
105 		state->link_speed = SPEED_20000;
106 		break;
107 	case MLX4_EN_40G_SPEED:
108 		state->link_speed = SPEED_40000;
109 		break;
110 	case MLX4_EN_56G_SPEED:
111 		state->link_speed = SPEED_56000;
112 		break;
113 	default:
114 		state->link_speed = -1;
115 		break;
116 	}
117 
118 	state->transceiver = qport_context->transceiver;
119 
120 	state->flags = 0; /* Reset and recalculate the port flags */
121 	state->flags |= (qport_context->link_up & MLX4_EN_ANC_MASK) ?
122 		MLX4_EN_PORT_ANC : 0;
123 	state->flags |= (qport_context->autoneg & MLX4_EN_AUTONEG_MASK) ?
124 		MLX4_EN_PORT_ANE : 0;
125 
126 out:
127 	mlx4_free_cmd_mailbox(mdev->dev, mailbox);
128 	return err;
129 }
130 
131 /* Each counter set is located in struct mlx4_en_stat_out_mbox
132  * with a const offset between its prio components.
133  * This function runs over a counter set and sum all of it's prio components.
134  */
135 static unsigned long en_stats_adder(__be64 *start, __be64 *next, int num)
136 {
137 	__be64 *curr = start;
138 	unsigned long ret = 0;
139 	int i;
140 	int offset = next - start;
141 
142 	for (i = 0; i < num; i++) {
143 		ret += be64_to_cpu(*curr);
144 		curr += offset;
145 	}
146 
147 	return ret;
148 }
149 
150 void mlx4_en_fold_software_stats(struct net_device *dev)
151 {
152 	struct mlx4_en_priv *priv = netdev_priv(dev);
153 	struct mlx4_en_dev *mdev = priv->mdev;
154 	unsigned long packets, bytes;
155 	int i;
156 
157 	if (!priv->port_up || mlx4_is_master(mdev->dev))
158 		return;
159 
160 	packets = 0;
161 	bytes = 0;
162 	for (i = 0; i < priv->rx_ring_num; i++) {
163 		const struct mlx4_en_rx_ring *ring = priv->rx_ring[i];
164 
165 		packets += READ_ONCE(ring->packets);
166 		bytes   += READ_ONCE(ring->bytes);
167 	}
168 	dev->stats.rx_packets = packets;
169 	dev->stats.rx_bytes = bytes;
170 
171 	packets = 0;
172 	bytes = 0;
173 	for (i = 0; i < priv->tx_ring_num[TX]; i++) {
174 		const struct mlx4_en_tx_ring *ring = priv->tx_ring[TX][i];
175 
176 		packets += READ_ONCE(ring->packets);
177 		bytes   += READ_ONCE(ring->bytes);
178 	}
179 	dev->stats.tx_packets = packets;
180 	dev->stats.tx_bytes = bytes;
181 }
182 
183 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
184 {
185 	struct mlx4_counter tmp_counter_stats;
186 	struct mlx4_en_stat_out_mbox *mlx4_en_stats;
187 	struct mlx4_en_stat_out_flow_control_mbox *flowstats;
188 	struct net_device *dev = mdev->pndev[port];
189 	struct mlx4_en_priv *priv = netdev_priv(dev);
190 	struct net_device_stats *stats = &dev->stats;
191 	struct mlx4_cmd_mailbox *mailbox;
192 	u64 in_mod = reset << 8 | port;
193 	int err;
194 	int i, counter_index;
195 	unsigned long sw_tx_dropped = 0;
196 	unsigned long sw_rx_dropped = 0;
197 
198 	mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
199 	if (IS_ERR(mailbox))
200 		return PTR_ERR(mailbox);
201 	err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
202 			   MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
203 			   MLX4_CMD_NATIVE);
204 	if (err)
205 		goto out;
206 
207 	mlx4_en_stats = mailbox->buf;
208 
209 	spin_lock_bh(&priv->stats_lock);
210 
211 	mlx4_en_fold_software_stats(dev);
212 
213 	priv->port_stats.rx_chksum_good = 0;
214 	priv->port_stats.rx_chksum_none = 0;
215 	priv->port_stats.rx_chksum_complete = 0;
216 	priv->port_stats.rx_alloc_pages = 0;
217 	priv->xdp_stats.rx_xdp_drop    = 0;
218 	priv->xdp_stats.rx_xdp_tx      = 0;
219 	priv->xdp_stats.rx_xdp_tx_full = 0;
220 	for (i = 0; i < priv->rx_ring_num; i++) {
221 		const struct mlx4_en_rx_ring *ring = priv->rx_ring[i];
222 
223 		sw_rx_dropped			+= READ_ONCE(ring->dropped);
224 		priv->port_stats.rx_chksum_good += READ_ONCE(ring->csum_ok);
225 		priv->port_stats.rx_chksum_none += READ_ONCE(ring->csum_none);
226 		priv->port_stats.rx_chksum_complete += READ_ONCE(ring->csum_complete);
227 		priv->port_stats.rx_alloc_pages += READ_ONCE(ring->rx_alloc_pages);
228 		priv->xdp_stats.rx_xdp_drop	+= READ_ONCE(ring->xdp_drop);
229 		priv->xdp_stats.rx_xdp_tx	+= READ_ONCE(ring->xdp_tx);
230 		priv->xdp_stats.rx_xdp_tx_full	+= READ_ONCE(ring->xdp_tx_full);
231 	}
232 	priv->port_stats.tx_chksum_offload = 0;
233 	priv->port_stats.queue_stopped = 0;
234 	priv->port_stats.wake_queue = 0;
235 	priv->port_stats.tso_packets = 0;
236 	priv->port_stats.xmit_more = 0;
237 
238 	for (i = 0; i < priv->tx_ring_num[TX]; i++) {
239 		const struct mlx4_en_tx_ring *ring = priv->tx_ring[TX][i];
240 
241 		sw_tx_dropped			   += READ_ONCE(ring->tx_dropped);
242 		priv->port_stats.tx_chksum_offload += READ_ONCE(ring->tx_csum);
243 		priv->port_stats.queue_stopped     += READ_ONCE(ring->queue_stopped);
244 		priv->port_stats.wake_queue        += READ_ONCE(ring->wake_queue);
245 		priv->port_stats.tso_packets       += READ_ONCE(ring->tso_packets);
246 		priv->port_stats.xmit_more         += READ_ONCE(ring->xmit_more);
247 	}
248 
249 	if (mlx4_is_master(mdev->dev)) {
250 		stats->rx_packets = en_stats_adder(&mlx4_en_stats->RTOT_prio_0,
251 						   &mlx4_en_stats->RTOT_prio_1,
252 						   NUM_PRIORITIES);
253 		stats->tx_packets = en_stats_adder(&mlx4_en_stats->TTOT_prio_0,
254 						   &mlx4_en_stats->TTOT_prio_1,
255 						   NUM_PRIORITIES);
256 		stats->rx_bytes = en_stats_adder(&mlx4_en_stats->ROCT_prio_0,
257 						 &mlx4_en_stats->ROCT_prio_1,
258 						 NUM_PRIORITIES);
259 		stats->tx_bytes = en_stats_adder(&mlx4_en_stats->TOCT_prio_0,
260 						 &mlx4_en_stats->TOCT_prio_1,
261 						 NUM_PRIORITIES);
262 	}
263 
264 	/* net device stats */
265 	stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
266 			   be32_to_cpu(mlx4_en_stats->RJBBR) +
267 			   be32_to_cpu(mlx4_en_stats->RCRC) +
268 			   be32_to_cpu(mlx4_en_stats->RRUNT) +
269 			   be64_to_cpu(mlx4_en_stats->RInRangeLengthErr) +
270 			   be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr) +
271 			   be32_to_cpu(mlx4_en_stats->RSHORT) +
272 			   en_stats_adder(&mlx4_en_stats->RGIANT_prio_0,
273 					  &mlx4_en_stats->RGIANT_prio_1,
274 					  NUM_PRIORITIES);
275 	stats->tx_errors = en_stats_adder(&mlx4_en_stats->TGIANT_prio_0,
276 					  &mlx4_en_stats->TGIANT_prio_1,
277 					  NUM_PRIORITIES);
278 	stats->multicast = en_stats_adder(&mlx4_en_stats->MCAST_prio_0,
279 					  &mlx4_en_stats->MCAST_prio_1,
280 					  NUM_PRIORITIES);
281 	stats->rx_dropped = be32_to_cpu(mlx4_en_stats->RDROP) +
282 			    sw_rx_dropped;
283 	stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength);
284 	stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC);
285 	stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
286 	stats->tx_dropped = be32_to_cpu(mlx4_en_stats->TDROP) +
287 			    sw_tx_dropped;
288 
289 	/* RX stats */
290 	priv->pkstats.rx_multicast_packets = stats->multicast;
291 	priv->pkstats.rx_broadcast_packets =
292 			en_stats_adder(&mlx4_en_stats->RBCAST_prio_0,
293 				       &mlx4_en_stats->RBCAST_prio_1,
294 				       NUM_PRIORITIES);
295 	priv->pkstats.rx_jabbers = be32_to_cpu(mlx4_en_stats->RJBBR);
296 	priv->pkstats.rx_in_range_length_error =
297 		be64_to_cpu(mlx4_en_stats->RInRangeLengthErr);
298 	priv->pkstats.rx_out_range_length_error =
299 		be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr);
300 
301 	/* Tx stats */
302 	priv->pkstats.tx_multicast_packets =
303 		en_stats_adder(&mlx4_en_stats->TMCAST_prio_0,
304 			       &mlx4_en_stats->TMCAST_prio_1,
305 			       NUM_PRIORITIES);
306 	priv->pkstats.tx_broadcast_packets =
307 		en_stats_adder(&mlx4_en_stats->TBCAST_prio_0,
308 			       &mlx4_en_stats->TBCAST_prio_1,
309 			       NUM_PRIORITIES);
310 
311 	priv->pkstats.rx_prio[0][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
312 	priv->pkstats.rx_prio[0][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_0);
313 	priv->pkstats.rx_prio[1][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
314 	priv->pkstats.rx_prio[1][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_1);
315 	priv->pkstats.rx_prio[2][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
316 	priv->pkstats.rx_prio[2][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_2);
317 	priv->pkstats.rx_prio[3][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
318 	priv->pkstats.rx_prio[3][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_3);
319 	priv->pkstats.rx_prio[4][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
320 	priv->pkstats.rx_prio[4][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_4);
321 	priv->pkstats.rx_prio[5][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
322 	priv->pkstats.rx_prio[5][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_5);
323 	priv->pkstats.rx_prio[6][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
324 	priv->pkstats.rx_prio[6][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_6);
325 	priv->pkstats.rx_prio[7][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
326 	priv->pkstats.rx_prio[7][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_7);
327 	priv->pkstats.rx_prio[8][0] = be64_to_cpu(mlx4_en_stats->RTOT_novlan);
328 	priv->pkstats.rx_prio[8][1] = be64_to_cpu(mlx4_en_stats->ROCT_novlan);
329 	priv->pkstats.tx_prio[0][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
330 	priv->pkstats.tx_prio[0][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_0);
331 	priv->pkstats.tx_prio[1][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
332 	priv->pkstats.tx_prio[1][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_1);
333 	priv->pkstats.tx_prio[2][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
334 	priv->pkstats.tx_prio[2][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_2);
335 	priv->pkstats.tx_prio[3][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
336 	priv->pkstats.tx_prio[3][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_3);
337 	priv->pkstats.tx_prio[4][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
338 	priv->pkstats.tx_prio[4][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_4);
339 	priv->pkstats.tx_prio[5][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
340 	priv->pkstats.tx_prio[5][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_5);
341 	priv->pkstats.tx_prio[6][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
342 	priv->pkstats.tx_prio[6][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_6);
343 	priv->pkstats.tx_prio[7][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
344 	priv->pkstats.tx_prio[7][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_7);
345 	priv->pkstats.tx_prio[8][0] = be64_to_cpu(mlx4_en_stats->TTOT_novlan);
346 	priv->pkstats.tx_prio[8][1] = be64_to_cpu(mlx4_en_stats->TOCT_novlan);
347 
348 	spin_unlock_bh(&priv->stats_lock);
349 
350 	memset(&tmp_counter_stats, 0, sizeof(tmp_counter_stats));
351 	counter_index = mlx4_get_default_counter_index(mdev->dev, port);
352 	err = mlx4_get_counter_stats(mdev->dev, counter_index,
353 				     &tmp_counter_stats, reset);
354 
355 	/* 0xffs indicates invalid value */
356 	memset(mailbox->buf, 0xff, sizeof(*flowstats) * MLX4_NUM_PRIORITIES);
357 
358 	if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN) {
359 		memset(mailbox->buf, 0,
360 		       sizeof(*flowstats) * MLX4_NUM_PRIORITIES);
361 		err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma,
362 				   in_mod | MLX4_DUMP_ETH_STATS_FLOW_CONTROL,
363 				   0, MLX4_CMD_DUMP_ETH_STATS,
364 				   MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
365 		if (err)
366 			goto out;
367 	}
368 
369 	flowstats = mailbox->buf;
370 
371 	spin_lock_bh(&priv->stats_lock);
372 
373 	if (tmp_counter_stats.counter_mode == 0) {
374 		priv->pf_stats.rx_bytes   = be64_to_cpu(tmp_counter_stats.rx_bytes);
375 		priv->pf_stats.tx_bytes   = be64_to_cpu(tmp_counter_stats.tx_bytes);
376 		priv->pf_stats.rx_packets = be64_to_cpu(tmp_counter_stats.rx_frames);
377 		priv->pf_stats.tx_packets = be64_to_cpu(tmp_counter_stats.tx_frames);
378 	}
379 
380 	for (i = 0; i < MLX4_NUM_PRIORITIES; i++)	{
381 		priv->rx_priority_flowstats[i].rx_pause =
382 			be64_to_cpu(flowstats[i].rx_pause);
383 		priv->rx_priority_flowstats[i].rx_pause_duration =
384 			be64_to_cpu(flowstats[i].rx_pause_duration);
385 		priv->rx_priority_flowstats[i].rx_pause_transition =
386 			be64_to_cpu(flowstats[i].rx_pause_transition);
387 		priv->tx_priority_flowstats[i].tx_pause =
388 			be64_to_cpu(flowstats[i].tx_pause);
389 		priv->tx_priority_flowstats[i].tx_pause_duration =
390 			be64_to_cpu(flowstats[i].tx_pause_duration);
391 		priv->tx_priority_flowstats[i].tx_pause_transition =
392 			be64_to_cpu(flowstats[i].tx_pause_transition);
393 	}
394 
395 	/* if pfc is not in use, all priorities counters have the same value */
396 	priv->rx_flowstats.rx_pause =
397 		be64_to_cpu(flowstats[0].rx_pause);
398 	priv->rx_flowstats.rx_pause_duration =
399 		be64_to_cpu(flowstats[0].rx_pause_duration);
400 	priv->rx_flowstats.rx_pause_transition =
401 		be64_to_cpu(flowstats[0].rx_pause_transition);
402 	priv->tx_flowstats.tx_pause =
403 		be64_to_cpu(flowstats[0].tx_pause);
404 	priv->tx_flowstats.tx_pause_duration =
405 		be64_to_cpu(flowstats[0].tx_pause_duration);
406 	priv->tx_flowstats.tx_pause_transition =
407 		be64_to_cpu(flowstats[0].tx_pause_transition);
408 
409 	spin_unlock_bh(&priv->stats_lock);
410 
411 out:
412 	mlx4_free_cmd_mailbox(mdev->dev, mailbox);
413 	return err;
414 }
415 
416