1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <linux/kernel.h> 35 #include <linux/ethtool.h> 36 #include <linux/netdevice.h> 37 #include <linux/mlx4/driver.h> 38 #include <linux/mlx4/device.h> 39 #include <linux/in.h> 40 #include <net/ip.h> 41 #include <linux/bitmap.h> 42 43 #include "mlx4_en.h" 44 #include "en_port.h" 45 46 #define EN_ETHTOOL_QP_ATTACH (1ull << 63) 47 #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff) 48 #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff) 49 50 int mlx4_en_moderation_update(struct mlx4_en_priv *priv) 51 { 52 int i, t; 53 int err = 0; 54 55 for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) { 56 for (i = 0; i < priv->tx_ring_num[t]; i++) { 57 priv->tx_cq[t][i]->moder_cnt = priv->tx_frames; 58 priv->tx_cq[t][i]->moder_time = priv->tx_usecs; 59 if (priv->port_up) { 60 err = mlx4_en_set_cq_moder(priv, 61 priv->tx_cq[t][i]); 62 if (err) 63 return err; 64 } 65 } 66 } 67 68 if (priv->adaptive_rx_coal) 69 return 0; 70 71 for (i = 0; i < priv->rx_ring_num; i++) { 72 priv->rx_cq[i]->moder_cnt = priv->rx_frames; 73 priv->rx_cq[i]->moder_time = priv->rx_usecs; 74 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; 75 if (priv->port_up) { 76 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]); 77 if (err) 78 return err; 79 } 80 } 81 82 return err; 83 } 84 85 static void 86 mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) 87 { 88 struct mlx4_en_priv *priv = netdev_priv(dev); 89 struct mlx4_en_dev *mdev = priv->mdev; 90 91 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); 92 strlcpy(drvinfo->version, DRV_VERSION, 93 sizeof(drvinfo->version)); 94 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 95 "%d.%d.%d", 96 (u16) (mdev->dev->caps.fw_ver >> 32), 97 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff), 98 (u16) (mdev->dev->caps.fw_ver & 0xffff)); 99 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev), 100 sizeof(drvinfo->bus_info)); 101 } 102 103 static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = { 104 "blueflame", 105 "phv-bit" 106 }; 107 108 static const char main_strings[][ETH_GSTRING_LEN] = { 109 /* main statistics */ 110 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", 111 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", 112 "rx_length_errors", "rx_over_errors", "rx_crc_errors", 113 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", 114 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", 115 "tx_heartbeat_errors", "tx_window_errors", 116 117 /* port statistics */ 118 "tso_packets", 119 "xmit_more", 120 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_pages", 121 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload", 122 123 /* pf statistics */ 124 "pf_rx_packets", 125 "pf_rx_bytes", 126 "pf_tx_packets", 127 "pf_tx_bytes", 128 129 /* priority flow control statistics rx */ 130 "rx_pause_prio_0", "rx_pause_duration_prio_0", 131 "rx_pause_transition_prio_0", 132 "rx_pause_prio_1", "rx_pause_duration_prio_1", 133 "rx_pause_transition_prio_1", 134 "rx_pause_prio_2", "rx_pause_duration_prio_2", 135 "rx_pause_transition_prio_2", 136 "rx_pause_prio_3", "rx_pause_duration_prio_3", 137 "rx_pause_transition_prio_3", 138 "rx_pause_prio_4", "rx_pause_duration_prio_4", 139 "rx_pause_transition_prio_4", 140 "rx_pause_prio_5", "rx_pause_duration_prio_5", 141 "rx_pause_transition_prio_5", 142 "rx_pause_prio_6", "rx_pause_duration_prio_6", 143 "rx_pause_transition_prio_6", 144 "rx_pause_prio_7", "rx_pause_duration_prio_7", 145 "rx_pause_transition_prio_7", 146 147 /* flow control statistics rx */ 148 "rx_pause", "rx_pause_duration", "rx_pause_transition", 149 150 /* priority flow control statistics tx */ 151 "tx_pause_prio_0", "tx_pause_duration_prio_0", 152 "tx_pause_transition_prio_0", 153 "tx_pause_prio_1", "tx_pause_duration_prio_1", 154 "tx_pause_transition_prio_1", 155 "tx_pause_prio_2", "tx_pause_duration_prio_2", 156 "tx_pause_transition_prio_2", 157 "tx_pause_prio_3", "tx_pause_duration_prio_3", 158 "tx_pause_transition_prio_3", 159 "tx_pause_prio_4", "tx_pause_duration_prio_4", 160 "tx_pause_transition_prio_4", 161 "tx_pause_prio_5", "tx_pause_duration_prio_5", 162 "tx_pause_transition_prio_5", 163 "tx_pause_prio_6", "tx_pause_duration_prio_6", 164 "tx_pause_transition_prio_6", 165 "tx_pause_prio_7", "tx_pause_duration_prio_7", 166 "tx_pause_transition_prio_7", 167 168 /* flow control statistics tx */ 169 "tx_pause", "tx_pause_duration", "tx_pause_transition", 170 171 /* packet statistics */ 172 "rx_multicast_packets", 173 "rx_broadcast_packets", 174 "rx_jabbers", 175 "rx_in_range_length_error", 176 "rx_out_range_length_error", 177 "tx_multicast_packets", 178 "tx_broadcast_packets", 179 "rx_prio_0_packets", "rx_prio_0_bytes", 180 "rx_prio_1_packets", "rx_prio_1_bytes", 181 "rx_prio_2_packets", "rx_prio_2_bytes", 182 "rx_prio_3_packets", "rx_prio_3_bytes", 183 "rx_prio_4_packets", "rx_prio_4_bytes", 184 "rx_prio_5_packets", "rx_prio_5_bytes", 185 "rx_prio_6_packets", "rx_prio_6_bytes", 186 "rx_prio_7_packets", "rx_prio_7_bytes", 187 "rx_novlan_packets", "rx_novlan_bytes", 188 "tx_prio_0_packets", "tx_prio_0_bytes", 189 "tx_prio_1_packets", "tx_prio_1_bytes", 190 "tx_prio_2_packets", "tx_prio_2_bytes", 191 "tx_prio_3_packets", "tx_prio_3_bytes", 192 "tx_prio_4_packets", "tx_prio_4_bytes", 193 "tx_prio_5_packets", "tx_prio_5_bytes", 194 "tx_prio_6_packets", "tx_prio_6_bytes", 195 "tx_prio_7_packets", "tx_prio_7_bytes", 196 "tx_novlan_packets", "tx_novlan_bytes", 197 198 /* xdp statistics */ 199 "rx_xdp_drop", 200 "rx_xdp_redirect", 201 "rx_xdp_redirect_fail", 202 "rx_xdp_tx", 203 "rx_xdp_tx_full", 204 205 /* phy statistics */ 206 "rx_packets_phy", "rx_bytes_phy", 207 "tx_packets_phy", "tx_bytes_phy", 208 }; 209 210 static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= { 211 "Interrupt Test", 212 "Link Test", 213 "Speed Test", 214 "Register Test", 215 "Loopback Test", 216 }; 217 218 static u32 mlx4_en_get_msglevel(struct net_device *dev) 219 { 220 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable; 221 } 222 223 static void mlx4_en_set_msglevel(struct net_device *dev, u32 val) 224 { 225 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val; 226 } 227 228 static void mlx4_en_get_wol(struct net_device *netdev, 229 struct ethtool_wolinfo *wol) 230 { 231 struct mlx4_en_priv *priv = netdev_priv(netdev); 232 struct mlx4_caps *caps = &priv->mdev->dev->caps; 233 int err = 0; 234 u64 config = 0; 235 u64 mask; 236 237 if ((priv->port < 1) || (priv->port > 2)) { 238 en_err(priv, "Failed to get WoL information\n"); 239 return; 240 } 241 242 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : 243 MLX4_DEV_CAP_FLAG_WOL_PORT2; 244 245 if (!(caps->flags & mask)) { 246 wol->supported = 0; 247 wol->wolopts = 0; 248 return; 249 } 250 251 if (caps->wol_port[priv->port]) 252 wol->supported = WAKE_MAGIC; 253 else 254 wol->supported = 0; 255 256 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); 257 if (err) { 258 en_err(priv, "Failed to get WoL information\n"); 259 return; 260 } 261 262 if ((config & MLX4_EN_WOL_ENABLED) && (config & MLX4_EN_WOL_MAGIC)) 263 wol->wolopts = WAKE_MAGIC; 264 else 265 wol->wolopts = 0; 266 } 267 268 static int mlx4_en_set_wol(struct net_device *netdev, 269 struct ethtool_wolinfo *wol) 270 { 271 struct mlx4_en_priv *priv = netdev_priv(netdev); 272 u64 config = 0; 273 int err = 0; 274 u64 mask; 275 276 if ((priv->port < 1) || (priv->port > 2)) 277 return -EOPNOTSUPP; 278 279 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : 280 MLX4_DEV_CAP_FLAG_WOL_PORT2; 281 282 if (!(priv->mdev->dev->caps.flags & mask)) 283 return -EOPNOTSUPP; 284 285 if (wol->supported & ~WAKE_MAGIC) 286 return -EINVAL; 287 288 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); 289 if (err) { 290 en_err(priv, "Failed to get WoL info, unable to modify\n"); 291 return err; 292 } 293 294 if (wol->wolopts & WAKE_MAGIC) { 295 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED | 296 MLX4_EN_WOL_MAGIC; 297 } else { 298 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC); 299 config |= MLX4_EN_WOL_DO_MODIFY; 300 } 301 302 err = mlx4_wol_write(priv->mdev->dev, config, priv->port); 303 if (err) 304 en_err(priv, "Failed to set WoL information\n"); 305 306 return err; 307 } 308 309 struct bitmap_iterator { 310 unsigned long *stats_bitmap; 311 unsigned int count; 312 unsigned int iterator; 313 bool advance_array; /* if set, force no increments */ 314 }; 315 316 static inline void bitmap_iterator_init(struct bitmap_iterator *h, 317 unsigned long *stats_bitmap, 318 int count) 319 { 320 h->iterator = 0; 321 h->advance_array = !bitmap_empty(stats_bitmap, count); 322 h->count = h->advance_array ? bitmap_weight(stats_bitmap, count) 323 : count; 324 h->stats_bitmap = stats_bitmap; 325 } 326 327 static inline int bitmap_iterator_test(struct bitmap_iterator *h) 328 { 329 return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap); 330 } 331 332 static inline int bitmap_iterator_inc(struct bitmap_iterator *h) 333 { 334 return h->iterator++; 335 } 336 337 static inline unsigned int 338 bitmap_iterator_count(struct bitmap_iterator *h) 339 { 340 return h->count; 341 } 342 343 static int mlx4_en_get_sset_count(struct net_device *dev, int sset) 344 { 345 struct mlx4_en_priv *priv = netdev_priv(dev); 346 struct bitmap_iterator it; 347 348 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 349 350 switch (sset) { 351 case ETH_SS_STATS: 352 return bitmap_iterator_count(&it) + 353 (priv->tx_ring_num[TX] * 2) + 354 (priv->rx_ring_num * (3 + NUM_XDP_STATS)); 355 case ETH_SS_TEST: 356 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags 357 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2; 358 case ETH_SS_PRIV_FLAGS: 359 return ARRAY_SIZE(mlx4_en_priv_flags); 360 default: 361 return -EOPNOTSUPP; 362 } 363 } 364 365 static void mlx4_en_get_ethtool_stats(struct net_device *dev, 366 struct ethtool_stats *stats, uint64_t *data) 367 { 368 struct mlx4_en_priv *priv = netdev_priv(dev); 369 int index = 0; 370 int i; 371 struct bitmap_iterator it; 372 373 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 374 375 spin_lock_bh(&priv->stats_lock); 376 377 mlx4_en_fold_software_stats(dev); 378 379 for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it)) 380 if (bitmap_iterator_test(&it)) 381 data[index++] = ((unsigned long *)&dev->stats)[i]; 382 383 for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it)) 384 if (bitmap_iterator_test(&it)) 385 data[index++] = ((unsigned long *)&priv->port_stats)[i]; 386 387 for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it)) 388 if (bitmap_iterator_test(&it)) 389 data[index++] = 390 ((unsigned long *)&priv->pf_stats)[i]; 391 392 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX; 393 i++, bitmap_iterator_inc(&it)) 394 if (bitmap_iterator_test(&it)) 395 data[index++] = 396 ((u64 *)&priv->rx_priority_flowstats)[i]; 397 398 for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it)) 399 if (bitmap_iterator_test(&it)) 400 data[index++] = ((u64 *)&priv->rx_flowstats)[i]; 401 402 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX; 403 i++, bitmap_iterator_inc(&it)) 404 if (bitmap_iterator_test(&it)) 405 data[index++] = 406 ((u64 *)&priv->tx_priority_flowstats)[i]; 407 408 for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it)) 409 if (bitmap_iterator_test(&it)) 410 data[index++] = ((u64 *)&priv->tx_flowstats)[i]; 411 412 for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it)) 413 if (bitmap_iterator_test(&it)) 414 data[index++] = ((unsigned long *)&priv->pkstats)[i]; 415 416 for (i = 0; i < NUM_XDP_STATS; i++, bitmap_iterator_inc(&it)) 417 if (bitmap_iterator_test(&it)) 418 data[index++] = ((unsigned long *)&priv->xdp_stats)[i]; 419 420 for (i = 0; i < NUM_PHY_STATS; i++, bitmap_iterator_inc(&it)) 421 if (bitmap_iterator_test(&it)) 422 data[index++] = ((unsigned long *)&priv->phy_stats)[i]; 423 424 for (i = 0; i < priv->tx_ring_num[TX]; i++) { 425 data[index++] = priv->tx_ring[TX][i]->packets; 426 data[index++] = priv->tx_ring[TX][i]->bytes; 427 } 428 for (i = 0; i < priv->rx_ring_num; i++) { 429 data[index++] = priv->rx_ring[i]->packets; 430 data[index++] = priv->rx_ring[i]->bytes; 431 data[index++] = priv->rx_ring[i]->dropped; 432 data[index++] = priv->rx_ring[i]->xdp_drop; 433 data[index++] = priv->rx_ring[i]->xdp_redirect; 434 data[index++] = priv->rx_ring[i]->xdp_redirect_fail; 435 data[index++] = priv->rx_ring[i]->xdp_tx; 436 data[index++] = priv->rx_ring[i]->xdp_tx_full; 437 } 438 spin_unlock_bh(&priv->stats_lock); 439 440 } 441 442 static void mlx4_en_self_test(struct net_device *dev, 443 struct ethtool_test *etest, u64 *buf) 444 { 445 mlx4_en_ex_selftest(dev, &etest->flags, buf); 446 } 447 448 static void mlx4_en_get_strings(struct net_device *dev, 449 uint32_t stringset, uint8_t *data) 450 { 451 struct mlx4_en_priv *priv = netdev_priv(dev); 452 int index = 0; 453 int i, strings = 0; 454 struct bitmap_iterator it; 455 456 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 457 458 switch (stringset) { 459 case ETH_SS_TEST: 460 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++) 461 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); 462 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) 463 for (; i < MLX4_EN_NUM_SELF_TEST; i++) 464 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); 465 break; 466 467 case ETH_SS_STATS: 468 /* Add main counters */ 469 for (i = 0; i < NUM_MAIN_STATS; i++, strings++, 470 bitmap_iterator_inc(&it)) 471 if (bitmap_iterator_test(&it)) 472 strcpy(data + (index++) * ETH_GSTRING_LEN, 473 main_strings[strings]); 474 475 for (i = 0; i < NUM_PORT_STATS; i++, strings++, 476 bitmap_iterator_inc(&it)) 477 if (bitmap_iterator_test(&it)) 478 strcpy(data + (index++) * ETH_GSTRING_LEN, 479 main_strings[strings]); 480 481 for (i = 0; i < NUM_PF_STATS; i++, strings++, 482 bitmap_iterator_inc(&it)) 483 if (bitmap_iterator_test(&it)) 484 strcpy(data + (index++) * ETH_GSTRING_LEN, 485 main_strings[strings]); 486 487 for (i = 0; i < NUM_FLOW_STATS; i++, strings++, 488 bitmap_iterator_inc(&it)) 489 if (bitmap_iterator_test(&it)) 490 strcpy(data + (index++) * ETH_GSTRING_LEN, 491 main_strings[strings]); 492 493 for (i = 0; i < NUM_PKT_STATS; i++, strings++, 494 bitmap_iterator_inc(&it)) 495 if (bitmap_iterator_test(&it)) 496 strcpy(data + (index++) * ETH_GSTRING_LEN, 497 main_strings[strings]); 498 499 for (i = 0; i < NUM_XDP_STATS; i++, strings++, 500 bitmap_iterator_inc(&it)) 501 if (bitmap_iterator_test(&it)) 502 strcpy(data + (index++) * ETH_GSTRING_LEN, 503 main_strings[strings]); 504 505 for (i = 0; i < NUM_PHY_STATS; i++, strings++, 506 bitmap_iterator_inc(&it)) 507 if (bitmap_iterator_test(&it)) 508 strcpy(data + (index++) * ETH_GSTRING_LEN, 509 main_strings[strings]); 510 511 for (i = 0; i < priv->tx_ring_num[TX]; i++) { 512 sprintf(data + (index++) * ETH_GSTRING_LEN, 513 "tx%d_packets", i); 514 sprintf(data + (index++) * ETH_GSTRING_LEN, 515 "tx%d_bytes", i); 516 } 517 for (i = 0; i < priv->rx_ring_num; i++) { 518 sprintf(data + (index++) * ETH_GSTRING_LEN, 519 "rx%d_packets", i); 520 sprintf(data + (index++) * ETH_GSTRING_LEN, 521 "rx%d_bytes", i); 522 sprintf(data + (index++) * ETH_GSTRING_LEN, 523 "rx%d_dropped", i); 524 sprintf(data + (index++) * ETH_GSTRING_LEN, 525 "rx%d_xdp_drop", i); 526 sprintf(data + (index++) * ETH_GSTRING_LEN, 527 "rx%d_xdp_redirect", i); 528 sprintf(data + (index++) * ETH_GSTRING_LEN, 529 "rx%d_xdp_redirect_fail", i); 530 sprintf(data + (index++) * ETH_GSTRING_LEN, 531 "rx%d_xdp_tx", i); 532 sprintf(data + (index++) * ETH_GSTRING_LEN, 533 "rx%d_xdp_tx_full", i); 534 } 535 break; 536 case ETH_SS_PRIV_FLAGS: 537 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++) 538 strcpy(data + i * ETH_GSTRING_LEN, 539 mlx4_en_priv_flags[i]); 540 break; 541 542 } 543 } 544 545 static u32 mlx4_en_autoneg_get(struct net_device *dev) 546 { 547 struct mlx4_en_priv *priv = netdev_priv(dev); 548 struct mlx4_en_dev *mdev = priv->mdev; 549 u32 autoneg = AUTONEG_DISABLE; 550 551 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) && 552 (priv->port_state.flags & MLX4_EN_PORT_ANE)) 553 autoneg = AUTONEG_ENABLE; 554 555 return autoneg; 556 } 557 558 static void ptys2ethtool_update_supported_port(unsigned long *mask, 559 struct mlx4_ptys_reg *ptys_reg) 560 { 561 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); 562 563 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) 564 | MLX4_PROT_MASK(MLX4_1000BASE_T) 565 | MLX4_PROT_MASK(MLX4_100BASE_TX))) { 566 __set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask); 567 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) 568 | MLX4_PROT_MASK(MLX4_10GBASE_SR) 569 | MLX4_PROT_MASK(MLX4_56GBASE_SR4) 570 | MLX4_PROT_MASK(MLX4_40GBASE_CR4) 571 | MLX4_PROT_MASK(MLX4_40GBASE_SR4) 572 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { 573 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask); 574 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) 575 | MLX4_PROT_MASK(MLX4_40GBASE_KR4) 576 | MLX4_PROT_MASK(MLX4_20GBASE_KR2) 577 | MLX4_PROT_MASK(MLX4_10GBASE_KR) 578 | MLX4_PROT_MASK(MLX4_10GBASE_KX4) 579 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { 580 __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mask); 581 } 582 } 583 584 static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg) 585 { 586 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper); 587 588 if (!eth_proto) /* link down */ 589 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); 590 591 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) 592 | MLX4_PROT_MASK(MLX4_1000BASE_T) 593 | MLX4_PROT_MASK(MLX4_100BASE_TX))) { 594 return PORT_TP; 595 } 596 597 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR) 598 | MLX4_PROT_MASK(MLX4_56GBASE_SR4) 599 | MLX4_PROT_MASK(MLX4_40GBASE_SR4) 600 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { 601 return PORT_FIBRE; 602 } 603 604 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) 605 | MLX4_PROT_MASK(MLX4_56GBASE_CR4) 606 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) { 607 return PORT_DA; 608 } 609 610 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) 611 | MLX4_PROT_MASK(MLX4_40GBASE_KR4) 612 | MLX4_PROT_MASK(MLX4_20GBASE_KR2) 613 | MLX4_PROT_MASK(MLX4_10GBASE_KR) 614 | MLX4_PROT_MASK(MLX4_10GBASE_KX4) 615 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { 616 return PORT_NONE; 617 } 618 return PORT_OTHER; 619 } 620 621 #define MLX4_LINK_MODES_SZ \ 622 (sizeof_field(struct mlx4_ptys_reg, eth_proto_cap) * 8) 623 624 enum ethtool_report { 625 SUPPORTED = 0, 626 ADVERTISED = 1, 627 }; 628 629 struct ptys2ethtool_config { 630 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 631 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised); 632 u32 speed; 633 }; 634 635 static unsigned long *ptys2ethtool_link_mode(struct ptys2ethtool_config *cfg, 636 enum ethtool_report report) 637 { 638 switch (report) { 639 case SUPPORTED: 640 return cfg->supported; 641 case ADVERTISED: 642 return cfg->advertised; 643 } 644 return NULL; 645 } 646 647 #define MLX4_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \ 648 ({ \ 649 struct ptys2ethtool_config *cfg; \ 650 static const unsigned int modes[] = { __VA_ARGS__ }; \ 651 unsigned int i; \ 652 cfg = &ptys2ethtool_map[reg_]; \ 653 cfg->speed = speed_; \ 654 bitmap_zero(cfg->supported, \ 655 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 656 bitmap_zero(cfg->advertised, \ 657 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 658 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ 659 __set_bit(modes[i], cfg->supported); \ 660 __set_bit(modes[i], cfg->advertised); \ 661 } \ 662 }) 663 664 /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */ 665 static struct ptys2ethtool_config ptys2ethtool_map[MLX4_LINK_MODES_SZ]; 666 667 void __init mlx4_en_init_ptys2ethtool_map(void) 668 { 669 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_100BASE_TX, SPEED_100, 670 ETHTOOL_LINK_MODE_100baseT_Full_BIT); 671 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_T, SPEED_1000, 672 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 673 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_CX_SGMII, SPEED_1000, 674 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 675 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_KX, SPEED_1000, 676 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 677 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_T, SPEED_10000, 678 ETHTOOL_LINK_MODE_10000baseT_Full_BIT); 679 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CX4, SPEED_10000, 680 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 681 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KX4, SPEED_10000, 682 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 683 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KR, SPEED_10000, 684 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 685 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CR, SPEED_10000, 686 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 687 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_SR, SPEED_10000, 688 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 689 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_20GBASE_KR2, SPEED_20000, 690 ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT, 691 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT); 692 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_CR4, SPEED_40000, 693 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT); 694 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_KR4, SPEED_40000, 695 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT); 696 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_SR4, SPEED_40000, 697 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT); 698 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_KR4, SPEED_56000, 699 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT); 700 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_CR4, SPEED_56000, 701 ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT); 702 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_SR4, SPEED_56000, 703 ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT); 704 }; 705 706 static void ptys2ethtool_update_link_modes(unsigned long *link_modes, 707 u32 eth_proto, 708 enum ethtool_report report) 709 { 710 int i; 711 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 712 if (eth_proto & MLX4_PROT_MASK(i)) 713 bitmap_or(link_modes, link_modes, 714 ptys2ethtool_link_mode(&ptys2ethtool_map[i], 715 report), 716 __ETHTOOL_LINK_MODE_MASK_NBITS); 717 } 718 } 719 720 static u32 ethtool2ptys_link_modes(const unsigned long *link_modes, 721 enum ethtool_report report) 722 { 723 int i; 724 u32 ptys_modes = 0; 725 726 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 727 if (bitmap_intersects( 728 ptys2ethtool_link_mode(&ptys2ethtool_map[i], 729 report), 730 link_modes, 731 __ETHTOOL_LINK_MODE_MASK_NBITS)) 732 ptys_modes |= 1 << i; 733 } 734 return ptys_modes; 735 } 736 737 /* Convert actual speed (SPEED_XXX) to ptys link modes */ 738 static u32 speed2ptys_link_modes(u32 speed) 739 { 740 int i; 741 u32 ptys_modes = 0; 742 743 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 744 if (ptys2ethtool_map[i].speed == speed) 745 ptys_modes |= 1 << i; 746 } 747 return ptys_modes; 748 } 749 750 static int 751 ethtool_get_ptys_link_ksettings(struct net_device *dev, 752 struct ethtool_link_ksettings *link_ksettings) 753 { 754 struct mlx4_en_priv *priv = netdev_priv(dev); 755 struct mlx4_ptys_reg ptys_reg; 756 u32 eth_proto; 757 int ret; 758 759 memset(&ptys_reg, 0, sizeof(ptys_reg)); 760 ptys_reg.local_port = priv->port; 761 ptys_reg.proto_mask = MLX4_PTYS_EN; 762 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, 763 MLX4_ACCESS_REG_QUERY, &ptys_reg); 764 if (ret) { 765 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)", 766 ret); 767 return ret; 768 } 769 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n", 770 ptys_reg.proto_mask); 771 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n", 772 be32_to_cpu(ptys_reg.eth_proto_cap)); 773 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n", 774 be32_to_cpu(ptys_reg.eth_proto_admin)); 775 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n", 776 be32_to_cpu(ptys_reg.eth_proto_oper)); 777 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n", 778 be32_to_cpu(ptys_reg.eth_proto_lp_adv)); 779 780 /* reset supported/advertising masks */ 781 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); 782 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); 783 784 ptys2ethtool_update_supported_port(link_ksettings->link_modes.supported, 785 &ptys_reg); 786 787 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap); 788 ptys2ethtool_update_link_modes(link_ksettings->link_modes.supported, 789 eth_proto, SUPPORTED); 790 791 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin); 792 ptys2ethtool_update_link_modes(link_ksettings->link_modes.advertising, 793 eth_proto, ADVERTISED); 794 795 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, 796 Pause); 797 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, 798 Asym_Pause); 799 800 if (priv->prof->tx_pause) 801 ethtool_link_ksettings_add_link_mode(link_ksettings, 802 advertising, Pause); 803 if (priv->prof->tx_pause ^ priv->prof->rx_pause) 804 ethtool_link_ksettings_add_link_mode(link_ksettings, 805 advertising, Asym_Pause); 806 807 link_ksettings->base.port = ptys_get_active_port(&ptys_reg); 808 809 if (mlx4_en_autoneg_get(dev)) { 810 ethtool_link_ksettings_add_link_mode(link_ksettings, 811 supported, Autoneg); 812 ethtool_link_ksettings_add_link_mode(link_ksettings, 813 advertising, Autoneg); 814 } 815 816 link_ksettings->base.autoneg 817 = (priv->port_state.flags & MLX4_EN_PORT_ANC) ? 818 AUTONEG_ENABLE : AUTONEG_DISABLE; 819 820 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv); 821 822 ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising); 823 ptys2ethtool_update_link_modes( 824 link_ksettings->link_modes.lp_advertising, 825 eth_proto, ADVERTISED); 826 if (priv->port_state.flags & MLX4_EN_PORT_ANC) 827 ethtool_link_ksettings_add_link_mode(link_ksettings, 828 lp_advertising, Autoneg); 829 830 link_ksettings->base.phy_address = 0; 831 link_ksettings->base.mdio_support = 0; 832 link_ksettings->base.eth_tp_mdix = ETH_TP_MDI_INVALID; 833 link_ksettings->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 834 835 return ret; 836 } 837 838 static void 839 ethtool_get_default_link_ksettings( 840 struct net_device *dev, struct ethtool_link_ksettings *link_ksettings) 841 { 842 struct mlx4_en_priv *priv = netdev_priv(dev); 843 int trans_type; 844 845 link_ksettings->base.autoneg = AUTONEG_DISABLE; 846 847 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); 848 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, 849 10000baseT_Full); 850 851 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); 852 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, 853 10000baseT_Full); 854 855 trans_type = priv->port_state.transceiver; 856 if (trans_type > 0 && trans_type <= 0xC) { 857 link_ksettings->base.port = PORT_FIBRE; 858 ethtool_link_ksettings_add_link_mode(link_ksettings, 859 supported, FIBRE); 860 ethtool_link_ksettings_add_link_mode(link_ksettings, 861 advertising, FIBRE); 862 } else if (trans_type == 0x80 || trans_type == 0) { 863 link_ksettings->base.port = PORT_TP; 864 ethtool_link_ksettings_add_link_mode(link_ksettings, 865 supported, TP); 866 ethtool_link_ksettings_add_link_mode(link_ksettings, 867 advertising, TP); 868 } else { 869 link_ksettings->base.port = -1; 870 } 871 } 872 873 static int 874 mlx4_en_get_link_ksettings(struct net_device *dev, 875 struct ethtool_link_ksettings *link_ksettings) 876 { 877 struct mlx4_en_priv *priv = netdev_priv(dev); 878 int ret = -EINVAL; 879 880 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port)) 881 return -ENOMEM; 882 883 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n", 884 priv->port_state.flags & MLX4_EN_PORT_ANC, 885 priv->port_state.flags & MLX4_EN_PORT_ANE); 886 887 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) 888 ret = ethtool_get_ptys_link_ksettings(dev, link_ksettings); 889 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */ 890 ethtool_get_default_link_ksettings(dev, link_ksettings); 891 892 if (netif_carrier_ok(dev)) { 893 link_ksettings->base.speed = priv->port_state.link_speed; 894 link_ksettings->base.duplex = DUPLEX_FULL; 895 } else { 896 link_ksettings->base.speed = SPEED_UNKNOWN; 897 link_ksettings->base.duplex = DUPLEX_UNKNOWN; 898 } 899 return 0; 900 } 901 902 /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */ 903 static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed, 904 __be32 proto_cap) 905 { 906 __be32 proto_admin = 0; 907 908 if (!speed) { /* Speed = 0 ==> Reset Link modes */ 909 proto_admin = proto_cap; 910 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n", 911 be32_to_cpu(proto_cap)); 912 } else { 913 u32 ptys_link_modes = speed2ptys_link_modes(speed); 914 915 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap; 916 en_info(priv, "Setting Speed to %d\n", speed); 917 } 918 return proto_admin; 919 } 920 921 static int 922 mlx4_en_set_link_ksettings(struct net_device *dev, 923 const struct ethtool_link_ksettings *link_ksettings) 924 { 925 struct mlx4_en_priv *priv = netdev_priv(dev); 926 struct mlx4_ptys_reg ptys_reg; 927 __be32 proto_admin; 928 u8 cur_autoneg; 929 int ret; 930 931 u32 ptys_adv = ethtool2ptys_link_modes( 932 link_ksettings->link_modes.advertising, ADVERTISED); 933 const int speed = link_ksettings->base.speed; 934 935 en_dbg(DRV, priv, 936 "Set Speed=%d adv={%*pbl} autoneg=%d duplex=%d\n", 937 speed, __ETHTOOL_LINK_MODE_MASK_NBITS, 938 link_ksettings->link_modes.advertising, 939 link_ksettings->base.autoneg, 940 link_ksettings->base.duplex); 941 942 if (!(priv->mdev->dev->caps.flags2 & 943 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) || 944 (link_ksettings->base.duplex == DUPLEX_HALF)) 945 return -EINVAL; 946 947 memset(&ptys_reg, 0, sizeof(ptys_reg)); 948 ptys_reg.local_port = priv->port; 949 ptys_reg.proto_mask = MLX4_PTYS_EN; 950 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, 951 MLX4_ACCESS_REG_QUERY, &ptys_reg); 952 if (ret) { 953 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n", 954 ret); 955 return 0; 956 } 957 958 cur_autoneg = ptys_reg.flags & MLX4_PTYS_AN_DISABLE_ADMIN ? 959 AUTONEG_DISABLE : AUTONEG_ENABLE; 960 961 if (link_ksettings->base.autoneg == AUTONEG_DISABLE) { 962 proto_admin = speed_set_ptys_admin(priv, speed, 963 ptys_reg.eth_proto_cap); 964 if ((be32_to_cpu(proto_admin) & 965 (MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII) | 966 MLX4_PROT_MASK(MLX4_1000BASE_KX))) && 967 (ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP)) 968 ptys_reg.flags |= MLX4_PTYS_AN_DISABLE_ADMIN; 969 } else { 970 proto_admin = cpu_to_be32(ptys_adv); 971 ptys_reg.flags &= ~MLX4_PTYS_AN_DISABLE_ADMIN; 972 } 973 974 proto_admin &= ptys_reg.eth_proto_cap; 975 if (!proto_admin) { 976 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n"); 977 return -EINVAL; /* nothing to change due to bad input */ 978 } 979 980 if ((proto_admin == ptys_reg.eth_proto_admin) && 981 ((ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP) && 982 (link_ksettings->base.autoneg == cur_autoneg))) 983 return 0; /* Nothing to change */ 984 985 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n", 986 be32_to_cpu(proto_admin)); 987 988 ptys_reg.eth_proto_admin = proto_admin; 989 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE, 990 &ptys_reg); 991 if (ret) { 992 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)", 993 be32_to_cpu(ptys_reg.eth_proto_admin), ret); 994 return ret; 995 } 996 997 mutex_lock(&priv->mdev->state_lock); 998 if (priv->port_up) { 999 en_warn(priv, "Port link mode changed, restarting port...\n"); 1000 mlx4_en_stop_port(dev, 1); 1001 if (mlx4_en_start_port(dev)) 1002 en_err(priv, "Failed restarting port %d\n", priv->port); 1003 } 1004 mutex_unlock(&priv->mdev->state_lock); 1005 return 0; 1006 } 1007 1008 static int mlx4_en_get_coalesce(struct net_device *dev, 1009 struct ethtool_coalesce *coal, 1010 struct kernel_ethtool_coalesce *kernel_coal, 1011 struct netlink_ext_ack *extack) 1012 { 1013 struct mlx4_en_priv *priv = netdev_priv(dev); 1014 1015 coal->tx_coalesce_usecs = priv->tx_usecs; 1016 coal->tx_max_coalesced_frames = priv->tx_frames; 1017 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit; 1018 1019 coal->rx_coalesce_usecs = priv->rx_usecs; 1020 coal->rx_max_coalesced_frames = priv->rx_frames; 1021 1022 coal->pkt_rate_low = priv->pkt_rate_low; 1023 coal->rx_coalesce_usecs_low = priv->rx_usecs_low; 1024 coal->pkt_rate_high = priv->pkt_rate_high; 1025 coal->rx_coalesce_usecs_high = priv->rx_usecs_high; 1026 coal->rate_sample_interval = priv->sample_interval; 1027 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal; 1028 1029 return 0; 1030 } 1031 1032 static int mlx4_en_set_coalesce(struct net_device *dev, 1033 struct ethtool_coalesce *coal, 1034 struct kernel_ethtool_coalesce *kernel_coal, 1035 struct netlink_ext_ack *extack) 1036 { 1037 struct mlx4_en_priv *priv = netdev_priv(dev); 1038 1039 if (!coal->tx_max_coalesced_frames_irq) 1040 return -EINVAL; 1041 1042 if (coal->tx_coalesce_usecs > MLX4_EN_MAX_COAL_TIME || 1043 coal->rx_coalesce_usecs > MLX4_EN_MAX_COAL_TIME || 1044 coal->rx_coalesce_usecs_low > MLX4_EN_MAX_COAL_TIME || 1045 coal->rx_coalesce_usecs_high > MLX4_EN_MAX_COAL_TIME) { 1046 netdev_info(dev, "%s: maximum coalesce time supported is %d usecs\n", 1047 __func__, MLX4_EN_MAX_COAL_TIME); 1048 return -ERANGE; 1049 } 1050 1051 if (coal->tx_max_coalesced_frames > MLX4_EN_MAX_COAL_PKTS || 1052 coal->rx_max_coalesced_frames > MLX4_EN_MAX_COAL_PKTS) { 1053 netdev_info(dev, "%s: maximum coalesced frames supported is %d\n", 1054 __func__, MLX4_EN_MAX_COAL_PKTS); 1055 return -ERANGE; 1056 } 1057 1058 priv->rx_frames = (coal->rx_max_coalesced_frames == 1059 MLX4_EN_AUTO_CONF) ? 1060 MLX4_EN_RX_COAL_TARGET : 1061 coal->rx_max_coalesced_frames; 1062 priv->rx_usecs = (coal->rx_coalesce_usecs == 1063 MLX4_EN_AUTO_CONF) ? 1064 MLX4_EN_RX_COAL_TIME : 1065 coal->rx_coalesce_usecs; 1066 1067 /* Setting TX coalescing parameters */ 1068 if (coal->tx_coalesce_usecs != priv->tx_usecs || 1069 coal->tx_max_coalesced_frames != priv->tx_frames) { 1070 priv->tx_usecs = coal->tx_coalesce_usecs; 1071 priv->tx_frames = coal->tx_max_coalesced_frames; 1072 } 1073 1074 /* Set adaptive coalescing params */ 1075 priv->pkt_rate_low = coal->pkt_rate_low; 1076 priv->rx_usecs_low = coal->rx_coalesce_usecs_low; 1077 priv->pkt_rate_high = coal->pkt_rate_high; 1078 priv->rx_usecs_high = coal->rx_coalesce_usecs_high; 1079 priv->sample_interval = coal->rate_sample_interval; 1080 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce; 1081 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq; 1082 1083 return mlx4_en_moderation_update(priv); 1084 } 1085 1086 static int mlx4_en_set_pauseparam(struct net_device *dev, 1087 struct ethtool_pauseparam *pause) 1088 { 1089 struct mlx4_en_priv *priv = netdev_priv(dev); 1090 struct mlx4_en_dev *mdev = priv->mdev; 1091 u8 tx_pause, tx_ppp, rx_pause, rx_ppp; 1092 int err; 1093 1094 if (pause->autoneg) 1095 return -EINVAL; 1096 1097 tx_pause = !!(pause->tx_pause); 1098 rx_pause = !!(pause->rx_pause); 1099 rx_ppp = (tx_pause || rx_pause) ? 0 : priv->prof->rx_ppp; 1100 tx_ppp = (tx_pause || rx_pause) ? 0 : priv->prof->tx_ppp; 1101 1102 err = mlx4_SET_PORT_general(mdev->dev, priv->port, 1103 priv->rx_skb_size + ETH_FCS_LEN, 1104 tx_pause, tx_ppp, rx_pause, rx_ppp); 1105 if (err) { 1106 en_err(priv, "Failed setting pause params, err = %d\n", err); 1107 return err; 1108 } 1109 1110 mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap, 1111 rx_ppp, rx_pause, tx_ppp, tx_pause); 1112 1113 priv->prof->tx_pause = tx_pause; 1114 priv->prof->rx_pause = rx_pause; 1115 priv->prof->tx_ppp = tx_ppp; 1116 priv->prof->rx_ppp = rx_ppp; 1117 1118 return err; 1119 } 1120 1121 static void mlx4_en_get_pause_stats(struct net_device *dev, 1122 struct ethtool_pause_stats *stats) 1123 { 1124 struct mlx4_en_priv *priv = netdev_priv(dev); 1125 struct bitmap_iterator it; 1126 1127 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 1128 1129 spin_lock_bh(&priv->stats_lock); 1130 if (test_bit(FLOW_PRIORITY_STATS_IDX_TX_FRAMES, 1131 priv->stats_bitmap.bitmap)) 1132 stats->tx_pause_frames = priv->tx_flowstats.tx_pause; 1133 if (test_bit(FLOW_PRIORITY_STATS_IDX_RX_FRAMES, 1134 priv->stats_bitmap.bitmap)) 1135 stats->rx_pause_frames = priv->rx_flowstats.rx_pause; 1136 spin_unlock_bh(&priv->stats_lock); 1137 } 1138 1139 static void mlx4_en_get_pauseparam(struct net_device *dev, 1140 struct ethtool_pauseparam *pause) 1141 { 1142 struct mlx4_en_priv *priv = netdev_priv(dev); 1143 1144 pause->tx_pause = priv->prof->tx_pause; 1145 pause->rx_pause = priv->prof->rx_pause; 1146 } 1147 1148 static int mlx4_en_set_ringparam(struct net_device *dev, 1149 struct ethtool_ringparam *param) 1150 { 1151 struct mlx4_en_priv *priv = netdev_priv(dev); 1152 struct mlx4_en_dev *mdev = priv->mdev; 1153 struct mlx4_en_port_profile new_prof; 1154 struct mlx4_en_priv *tmp; 1155 u32 rx_size, tx_size; 1156 int port_up = 0; 1157 int err = 0; 1158 1159 if (param->rx_jumbo_pending || param->rx_mini_pending) 1160 return -EINVAL; 1161 1162 if (param->rx_pending < MLX4_EN_MIN_RX_SIZE) { 1163 en_warn(priv, "%s: rx_pending (%d) < min (%d)\n", 1164 __func__, param->rx_pending, 1165 MLX4_EN_MIN_RX_SIZE); 1166 return -EINVAL; 1167 } 1168 if (param->tx_pending < MLX4_EN_MIN_TX_SIZE) { 1169 en_warn(priv, "%s: tx_pending (%d) < min (%lu)\n", 1170 __func__, param->tx_pending, 1171 MLX4_EN_MIN_TX_SIZE); 1172 return -EINVAL; 1173 } 1174 1175 rx_size = roundup_pow_of_two(param->rx_pending); 1176 tx_size = roundup_pow_of_two(param->tx_pending); 1177 1178 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size : 1179 priv->rx_ring[0]->size) && 1180 tx_size == priv->tx_ring[TX][0]->size) 1181 return 0; 1182 1183 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 1184 if (!tmp) 1185 return -ENOMEM; 1186 1187 mutex_lock(&mdev->state_lock); 1188 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile)); 1189 new_prof.tx_ring_size = tx_size; 1190 new_prof.rx_ring_size = rx_size; 1191 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true); 1192 if (err) 1193 goto out; 1194 1195 if (priv->port_up) { 1196 port_up = 1; 1197 mlx4_en_stop_port(dev, 1); 1198 } 1199 1200 mlx4_en_safe_replace_resources(priv, tmp); 1201 1202 if (port_up) { 1203 err = mlx4_en_start_port(dev); 1204 if (err) 1205 en_err(priv, "Failed starting port\n"); 1206 } 1207 1208 err = mlx4_en_moderation_update(priv); 1209 out: 1210 kfree(tmp); 1211 mutex_unlock(&mdev->state_lock); 1212 return err; 1213 } 1214 1215 static void mlx4_en_get_ringparam(struct net_device *dev, 1216 struct ethtool_ringparam *param) 1217 { 1218 struct mlx4_en_priv *priv = netdev_priv(dev); 1219 1220 memset(param, 0, sizeof(*param)); 1221 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE; 1222 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE; 1223 param->rx_pending = priv->port_up ? 1224 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size; 1225 param->tx_pending = priv->tx_ring[TX][0]->size; 1226 } 1227 1228 static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev) 1229 { 1230 struct mlx4_en_priv *priv = netdev_priv(dev); 1231 1232 return rounddown_pow_of_two(priv->rx_ring_num); 1233 } 1234 1235 static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev) 1236 { 1237 return MLX4_EN_RSS_KEY_SIZE; 1238 } 1239 1240 static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc) 1241 { 1242 struct mlx4_en_priv *priv = netdev_priv(dev); 1243 1244 /* check if requested function is supported by the device */ 1245 if (hfunc == ETH_RSS_HASH_TOP) { 1246 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) 1247 return -EINVAL; 1248 if (!(dev->features & NETIF_F_RXHASH)) 1249 en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n"); 1250 return 0; 1251 } else if (hfunc == ETH_RSS_HASH_XOR) { 1252 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR)) 1253 return -EINVAL; 1254 if (dev->features & NETIF_F_RXHASH) 1255 en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n"); 1256 return 0; 1257 } 1258 1259 return -EINVAL; 1260 } 1261 1262 static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key, 1263 u8 *hfunc) 1264 { 1265 struct mlx4_en_priv *priv = netdev_priv(dev); 1266 u32 n = mlx4_en_get_rxfh_indir_size(dev); 1267 u32 i, rss_rings; 1268 1269 rss_rings = priv->prof->rss_rings ?: n; 1270 rss_rings = rounddown_pow_of_two(rss_rings); 1271 1272 for (i = 0; i < n; i++) { 1273 if (!ring_index) 1274 break; 1275 ring_index[i] = i % rss_rings; 1276 } 1277 if (key) 1278 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE); 1279 if (hfunc) 1280 *hfunc = priv->rss_hash_fn; 1281 return 0; 1282 } 1283 1284 static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index, 1285 const u8 *key, const u8 hfunc) 1286 { 1287 struct mlx4_en_priv *priv = netdev_priv(dev); 1288 u32 n = mlx4_en_get_rxfh_indir_size(dev); 1289 struct mlx4_en_dev *mdev = priv->mdev; 1290 int port_up = 0; 1291 int err = 0; 1292 int i; 1293 int rss_rings = 0; 1294 1295 /* Calculate RSS table size and make sure flows are spread evenly 1296 * between rings 1297 */ 1298 for (i = 0; i < n; i++) { 1299 if (!ring_index) 1300 break; 1301 if (i > 0 && !ring_index[i] && !rss_rings) 1302 rss_rings = i; 1303 1304 if (ring_index[i] != (i % (rss_rings ?: n))) 1305 return -EINVAL; 1306 } 1307 1308 if (!rss_rings) 1309 rss_rings = n; 1310 1311 /* RSS table size must be an order of 2 */ 1312 if (!is_power_of_2(rss_rings)) 1313 return -EINVAL; 1314 1315 if (hfunc != ETH_RSS_HASH_NO_CHANGE) { 1316 err = mlx4_en_check_rxfh_func(dev, hfunc); 1317 if (err) 1318 return err; 1319 } 1320 1321 mutex_lock(&mdev->state_lock); 1322 if (priv->port_up) { 1323 port_up = 1; 1324 mlx4_en_stop_port(dev, 1); 1325 } 1326 1327 if (ring_index) 1328 priv->prof->rss_rings = rss_rings; 1329 if (key) 1330 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE); 1331 if (hfunc != ETH_RSS_HASH_NO_CHANGE) 1332 priv->rss_hash_fn = hfunc; 1333 1334 if (port_up) { 1335 err = mlx4_en_start_port(dev); 1336 if (err) 1337 en_err(priv, "Failed starting port\n"); 1338 } 1339 1340 mutex_unlock(&mdev->state_lock); 1341 return err; 1342 } 1343 1344 #define all_zeros_or_all_ones(field) \ 1345 ((field) == 0 || (field) == (__force typeof(field))-1) 1346 1347 static int mlx4_en_validate_flow(struct net_device *dev, 1348 struct ethtool_rxnfc *cmd) 1349 { 1350 struct ethtool_usrip4_spec *l3_mask; 1351 struct ethtool_tcpip4_spec *l4_mask; 1352 struct ethhdr *eth_mask; 1353 1354 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1355 return -EINVAL; 1356 1357 if (cmd->fs.flow_type & FLOW_MAC_EXT) { 1358 /* dest mac mask must be ff:ff:ff:ff:ff:ff */ 1359 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest)) 1360 return -EINVAL; 1361 } 1362 1363 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1364 case TCP_V4_FLOW: 1365 case UDP_V4_FLOW: 1366 if (cmd->fs.m_u.tcp_ip4_spec.tos) 1367 return -EINVAL; 1368 l4_mask = &cmd->fs.m_u.tcp_ip4_spec; 1369 /* don't allow mask which isn't all 0 or 1 */ 1370 if (!all_zeros_or_all_ones(l4_mask->ip4src) || 1371 !all_zeros_or_all_ones(l4_mask->ip4dst) || 1372 !all_zeros_or_all_ones(l4_mask->psrc) || 1373 !all_zeros_or_all_ones(l4_mask->pdst)) 1374 return -EINVAL; 1375 break; 1376 case IP_USER_FLOW: 1377 l3_mask = &cmd->fs.m_u.usr_ip4_spec; 1378 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto || 1379 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 || 1380 (!l3_mask->ip4src && !l3_mask->ip4dst) || 1381 !all_zeros_or_all_ones(l3_mask->ip4src) || 1382 !all_zeros_or_all_ones(l3_mask->ip4dst)) 1383 return -EINVAL; 1384 break; 1385 case ETHER_FLOW: 1386 eth_mask = &cmd->fs.m_u.ether_spec; 1387 /* source mac mask must not be set */ 1388 if (!is_zero_ether_addr(eth_mask->h_source)) 1389 return -EINVAL; 1390 1391 /* dest mac mask must be ff:ff:ff:ff:ff:ff */ 1392 if (!is_broadcast_ether_addr(eth_mask->h_dest)) 1393 return -EINVAL; 1394 1395 if (!all_zeros_or_all_ones(eth_mask->h_proto)) 1396 return -EINVAL; 1397 break; 1398 default: 1399 return -EINVAL; 1400 } 1401 1402 if ((cmd->fs.flow_type & FLOW_EXT)) { 1403 if (cmd->fs.m_ext.vlan_etype || 1404 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == 1405 0 || 1406 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == 1407 cpu_to_be16(VLAN_VID_MASK))) 1408 return -EINVAL; 1409 1410 if (cmd->fs.m_ext.vlan_tci) { 1411 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID) 1412 return -EINVAL; 1413 1414 } 1415 } 1416 1417 return 0; 1418 } 1419 1420 static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd, 1421 struct list_head *rule_list_h, 1422 struct mlx4_spec_list *spec_l2, 1423 unsigned char *mac) 1424 { 1425 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16); 1426 1427 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH; 1428 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN); 1429 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN); 1430 1431 if ((cmd->fs.flow_type & FLOW_EXT) && 1432 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) { 1433 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci; 1434 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK); 1435 } 1436 1437 list_add_tail(&spec_l2->list, rule_list_h); 1438 1439 return 0; 1440 } 1441 1442 static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv, 1443 struct ethtool_rxnfc *cmd, 1444 struct list_head *rule_list_h, 1445 struct mlx4_spec_list *spec_l2, 1446 __be32 ipv4_dst) 1447 { 1448 #ifdef CONFIG_INET 1449 unsigned char mac[ETH_ALEN]; 1450 1451 if (!ipv4_is_multicast(ipv4_dst)) { 1452 if (cmd->fs.flow_type & FLOW_MAC_EXT) 1453 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN); 1454 else 1455 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN); 1456 } else { 1457 ip_eth_mc_map(ipv4_dst, mac); 1458 } 1459 1460 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]); 1461 #else 1462 return -EINVAL; 1463 #endif 1464 } 1465 1466 static int add_ip_rule(struct mlx4_en_priv *priv, 1467 struct ethtool_rxnfc *cmd, 1468 struct list_head *list_h) 1469 { 1470 int err; 1471 struct mlx4_spec_list *spec_l2 = NULL; 1472 struct mlx4_spec_list *spec_l3 = NULL; 1473 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec; 1474 1475 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); 1476 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1477 if (!spec_l2 || !spec_l3) { 1478 err = -ENOMEM; 1479 goto free_spec; 1480 } 1481 1482 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2, 1483 cmd->fs.h_u. 1484 usr_ip4_spec.ip4dst); 1485 if (err) 1486 goto free_spec; 1487 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; 1488 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src; 1489 if (l3_mask->ip4src) 1490 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; 1491 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst; 1492 if (l3_mask->ip4dst) 1493 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; 1494 list_add_tail(&spec_l3->list, list_h); 1495 1496 return 0; 1497 1498 free_spec: 1499 kfree(spec_l2); 1500 kfree(spec_l3); 1501 return err; 1502 } 1503 1504 static int add_tcp_udp_rule(struct mlx4_en_priv *priv, 1505 struct ethtool_rxnfc *cmd, 1506 struct list_head *list_h, int proto) 1507 { 1508 int err; 1509 struct mlx4_spec_list *spec_l2 = NULL; 1510 struct mlx4_spec_list *spec_l3 = NULL; 1511 struct mlx4_spec_list *spec_l4 = NULL; 1512 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec; 1513 1514 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1515 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); 1516 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL); 1517 if (!spec_l2 || !spec_l3 || !spec_l4) { 1518 err = -ENOMEM; 1519 goto free_spec; 1520 } 1521 1522 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; 1523 1524 if (proto == TCP_V4_FLOW) { 1525 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, 1526 spec_l2, 1527 cmd->fs.h_u. 1528 tcp_ip4_spec.ip4dst); 1529 if (err) 1530 goto free_spec; 1531 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP; 1532 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src; 1533 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst; 1534 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc; 1535 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst; 1536 } else { 1537 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, 1538 spec_l2, 1539 cmd->fs.h_u. 1540 udp_ip4_spec.ip4dst); 1541 if (err) 1542 goto free_spec; 1543 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP; 1544 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src; 1545 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst; 1546 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc; 1547 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst; 1548 } 1549 1550 if (l4_mask->ip4src) 1551 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; 1552 if (l4_mask->ip4dst) 1553 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; 1554 1555 if (l4_mask->psrc) 1556 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK; 1557 if (l4_mask->pdst) 1558 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK; 1559 1560 list_add_tail(&spec_l3->list, list_h); 1561 list_add_tail(&spec_l4->list, list_h); 1562 1563 return 0; 1564 1565 free_spec: 1566 kfree(spec_l2); 1567 kfree(spec_l3); 1568 kfree(spec_l4); 1569 return err; 1570 } 1571 1572 static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev, 1573 struct ethtool_rxnfc *cmd, 1574 struct list_head *rule_list_h) 1575 { 1576 int err; 1577 struct ethhdr *eth_spec; 1578 struct mlx4_spec_list *spec_l2; 1579 struct mlx4_en_priv *priv = netdev_priv(dev); 1580 1581 err = mlx4_en_validate_flow(dev, cmd); 1582 if (err) 1583 return err; 1584 1585 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1586 case ETHER_FLOW: 1587 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1588 if (!spec_l2) 1589 return -ENOMEM; 1590 1591 eth_spec = &cmd->fs.h_u.ether_spec; 1592 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, 1593 ð_spec->h_dest[0]); 1594 spec_l2->eth.ether_type = eth_spec->h_proto; 1595 if (eth_spec->h_proto) 1596 spec_l2->eth.ether_type_enable = 1; 1597 break; 1598 case IP_USER_FLOW: 1599 err = add_ip_rule(priv, cmd, rule_list_h); 1600 break; 1601 case TCP_V4_FLOW: 1602 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW); 1603 break; 1604 case UDP_V4_FLOW: 1605 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW); 1606 break; 1607 } 1608 1609 return err; 1610 } 1611 1612 static int mlx4_en_flow_replace(struct net_device *dev, 1613 struct ethtool_rxnfc *cmd) 1614 { 1615 int err; 1616 struct mlx4_en_priv *priv = netdev_priv(dev); 1617 struct ethtool_flow_id *loc_rule; 1618 struct mlx4_spec_list *spec, *tmp_spec; 1619 u32 qpn; 1620 u64 reg_id; 1621 1622 struct mlx4_net_trans_rule rule = { 1623 .queue_mode = MLX4_NET_TRANS_Q_FIFO, 1624 .exclusive = 0, 1625 .allow_loopback = 1, 1626 .promisc_mode = MLX4_FS_REGULAR, 1627 }; 1628 1629 rule.port = priv->port; 1630 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location; 1631 INIT_LIST_HEAD(&rule.list); 1632 1633 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */ 1634 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC) 1635 qpn = priv->drop_qp.qpn; 1636 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) { 1637 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1); 1638 } else { 1639 if (cmd->fs.ring_cookie >= priv->rx_ring_num) { 1640 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n", 1641 cmd->fs.ring_cookie); 1642 return -EINVAL; 1643 } 1644 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn; 1645 if (!qpn) { 1646 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n", 1647 cmd->fs.ring_cookie); 1648 return -EINVAL; 1649 } 1650 } 1651 rule.qpn = qpn; 1652 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list); 1653 if (err) 1654 goto out_free_list; 1655 1656 loc_rule = &priv->ethtool_rules[cmd->fs.location]; 1657 if (loc_rule->id) { 1658 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id); 1659 if (err) { 1660 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n", 1661 cmd->fs.location, loc_rule->id); 1662 goto out_free_list; 1663 } 1664 loc_rule->id = 0; 1665 memset(&loc_rule->flow_spec, 0, 1666 sizeof(struct ethtool_rx_flow_spec)); 1667 list_del(&loc_rule->list); 1668 } 1669 err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id); 1670 if (err) { 1671 en_err(priv, "Fail to attach network rule at location %d\n", 1672 cmd->fs.location); 1673 goto out_free_list; 1674 } 1675 loc_rule->id = reg_id; 1676 memcpy(&loc_rule->flow_spec, &cmd->fs, 1677 sizeof(struct ethtool_rx_flow_spec)); 1678 list_add_tail(&loc_rule->list, &priv->ethtool_list); 1679 1680 out_free_list: 1681 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) { 1682 list_del(&spec->list); 1683 kfree(spec); 1684 } 1685 return err; 1686 } 1687 1688 static int mlx4_en_flow_detach(struct net_device *dev, 1689 struct ethtool_rxnfc *cmd) 1690 { 1691 int err = 0; 1692 struct ethtool_flow_id *rule; 1693 struct mlx4_en_priv *priv = netdev_priv(dev); 1694 1695 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1696 return -EINVAL; 1697 1698 rule = &priv->ethtool_rules[cmd->fs.location]; 1699 if (!rule->id) { 1700 err = -ENOENT; 1701 goto out; 1702 } 1703 1704 err = mlx4_flow_detach(priv->mdev->dev, rule->id); 1705 if (err) { 1706 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n", 1707 cmd->fs.location, rule->id); 1708 goto out; 1709 } 1710 rule->id = 0; 1711 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec)); 1712 list_del(&rule->list); 1713 out: 1714 return err; 1715 1716 } 1717 1718 static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1719 int loc) 1720 { 1721 int err = 0; 1722 struct ethtool_flow_id *rule; 1723 struct mlx4_en_priv *priv = netdev_priv(dev); 1724 1725 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1726 return -EINVAL; 1727 1728 rule = &priv->ethtool_rules[loc]; 1729 if (rule->id) 1730 memcpy(&cmd->fs, &rule->flow_spec, 1731 sizeof(struct ethtool_rx_flow_spec)); 1732 else 1733 err = -ENOENT; 1734 1735 return err; 1736 } 1737 1738 static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv) 1739 { 1740 1741 int i, res = 0; 1742 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 1743 if (priv->ethtool_rules[i].id) 1744 res++; 1745 } 1746 return res; 1747 1748 } 1749 1750 static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1751 u32 *rule_locs) 1752 { 1753 struct mlx4_en_priv *priv = netdev_priv(dev); 1754 struct mlx4_en_dev *mdev = priv->mdev; 1755 int err = 0; 1756 int i = 0, priority = 0; 1757 1758 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT || 1759 cmd->cmd == ETHTOOL_GRXCLSRULE || 1760 cmd->cmd == ETHTOOL_GRXCLSRLALL) && 1761 (mdev->dev->caps.steering_mode != 1762 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)) 1763 return -EINVAL; 1764 1765 switch (cmd->cmd) { 1766 case ETHTOOL_GRXRINGS: 1767 cmd->data = priv->rx_ring_num; 1768 break; 1769 case ETHTOOL_GRXCLSRLCNT: 1770 cmd->rule_cnt = mlx4_en_get_num_flows(priv); 1771 break; 1772 case ETHTOOL_GRXCLSRULE: 1773 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location); 1774 break; 1775 case ETHTOOL_GRXCLSRLALL: 1776 cmd->data = MAX_NUM_OF_FS_RULES; 1777 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) { 1778 err = mlx4_en_get_flow(dev, cmd, i); 1779 if (!err) 1780 rule_locs[priority++] = i; 1781 i++; 1782 } 1783 err = 0; 1784 break; 1785 default: 1786 err = -EOPNOTSUPP; 1787 break; 1788 } 1789 1790 return err; 1791 } 1792 1793 static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1794 { 1795 int err = 0; 1796 struct mlx4_en_priv *priv = netdev_priv(dev); 1797 struct mlx4_en_dev *mdev = priv->mdev; 1798 1799 if (mdev->dev->caps.steering_mode != 1800 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up) 1801 return -EINVAL; 1802 1803 switch (cmd->cmd) { 1804 case ETHTOOL_SRXCLSRLINS: 1805 err = mlx4_en_flow_replace(dev, cmd); 1806 break; 1807 case ETHTOOL_SRXCLSRLDEL: 1808 err = mlx4_en_flow_detach(dev, cmd); 1809 break; 1810 default: 1811 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd); 1812 return -EINVAL; 1813 } 1814 1815 return err; 1816 } 1817 1818 static int mlx4_en_get_max_num_rx_rings(struct net_device *dev) 1819 { 1820 return min_t(int, num_online_cpus(), MAX_RX_RINGS); 1821 } 1822 1823 static void mlx4_en_get_channels(struct net_device *dev, 1824 struct ethtool_channels *channel) 1825 { 1826 struct mlx4_en_priv *priv = netdev_priv(dev); 1827 1828 channel->max_rx = mlx4_en_get_max_num_rx_rings(dev); 1829 channel->max_tx = priv->mdev->profile.max_num_tx_rings_p_up; 1830 1831 channel->rx_count = priv->rx_ring_num; 1832 channel->tx_count = priv->tx_ring_num[TX] / 1833 priv->prof->num_up; 1834 } 1835 1836 static int mlx4_en_set_channels(struct net_device *dev, 1837 struct ethtool_channels *channel) 1838 { 1839 struct mlx4_en_priv *priv = netdev_priv(dev); 1840 struct mlx4_en_dev *mdev = priv->mdev; 1841 struct mlx4_en_port_profile new_prof; 1842 struct mlx4_en_priv *tmp; 1843 int total_tx_count; 1844 int port_up = 0; 1845 int xdp_count; 1846 int err = 0; 1847 u8 up; 1848 1849 if (!channel->tx_count || !channel->rx_count) 1850 return -EINVAL; 1851 1852 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 1853 if (!tmp) 1854 return -ENOMEM; 1855 1856 mutex_lock(&mdev->state_lock); 1857 xdp_count = priv->tx_ring_num[TX_XDP] ? channel->rx_count : 0; 1858 total_tx_count = channel->tx_count * priv->prof->num_up + xdp_count; 1859 if (total_tx_count > MAX_TX_RINGS) { 1860 err = -EINVAL; 1861 en_err(priv, 1862 "Total number of TX and XDP rings (%d) exceeds the maximum supported (%d)\n", 1863 total_tx_count, MAX_TX_RINGS); 1864 goto out; 1865 } 1866 1867 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile)); 1868 new_prof.num_tx_rings_p_up = channel->tx_count; 1869 new_prof.tx_ring_num[TX] = channel->tx_count * priv->prof->num_up; 1870 new_prof.tx_ring_num[TX_XDP] = xdp_count; 1871 new_prof.rx_ring_num = channel->rx_count; 1872 1873 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true); 1874 if (err) 1875 goto out; 1876 1877 if (priv->port_up) { 1878 port_up = 1; 1879 mlx4_en_stop_port(dev, 1); 1880 } 1881 1882 mlx4_en_safe_replace_resources(priv, tmp); 1883 1884 netif_set_real_num_rx_queues(dev, priv->rx_ring_num); 1885 1886 up = (priv->prof->num_up == MLX4_EN_NUM_UP_LOW) ? 1887 0 : priv->prof->num_up; 1888 mlx4_en_setup_tc(dev, up); 1889 1890 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num[TX]); 1891 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num); 1892 1893 if (port_up) { 1894 err = mlx4_en_start_port(dev); 1895 if (err) 1896 en_err(priv, "Failed starting port\n"); 1897 } 1898 1899 err = mlx4_en_moderation_update(priv); 1900 out: 1901 mutex_unlock(&mdev->state_lock); 1902 kfree(tmp); 1903 return err; 1904 } 1905 1906 static int mlx4_en_get_ts_info(struct net_device *dev, 1907 struct ethtool_ts_info *info) 1908 { 1909 struct mlx4_en_priv *priv = netdev_priv(dev); 1910 struct mlx4_en_dev *mdev = priv->mdev; 1911 int ret; 1912 1913 ret = ethtool_op_get_ts_info(dev, info); 1914 if (ret) 1915 return ret; 1916 1917 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 1918 info->so_timestamping |= 1919 SOF_TIMESTAMPING_TX_HARDWARE | 1920 SOF_TIMESTAMPING_RX_HARDWARE | 1921 SOF_TIMESTAMPING_RAW_HARDWARE; 1922 1923 info->tx_types = 1924 (1 << HWTSTAMP_TX_OFF) | 1925 (1 << HWTSTAMP_TX_ON); 1926 1927 info->rx_filters = 1928 (1 << HWTSTAMP_FILTER_NONE) | 1929 (1 << HWTSTAMP_FILTER_ALL); 1930 1931 if (mdev->ptp_clock) 1932 info->phc_index = ptp_clock_index(mdev->ptp_clock); 1933 } 1934 1935 return ret; 1936 } 1937 1938 static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags) 1939 { 1940 struct mlx4_en_priv *priv = netdev_priv(dev); 1941 struct mlx4_en_dev *mdev = priv->mdev; 1942 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); 1943 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); 1944 bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV); 1945 bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV); 1946 int i; 1947 int ret = 0; 1948 1949 if (bf_enabled_new != bf_enabled_old) { 1950 int t; 1951 1952 if (bf_enabled_new) { 1953 bool bf_supported = true; 1954 1955 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) 1956 for (i = 0; i < priv->tx_ring_num[t]; i++) 1957 bf_supported &= 1958 priv->tx_ring[t][i]->bf_alloced; 1959 1960 if (!bf_supported) { 1961 en_err(priv, "BlueFlame is not supported\n"); 1962 return -EINVAL; 1963 } 1964 1965 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME; 1966 } else { 1967 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 1968 } 1969 1970 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) 1971 for (i = 0; i < priv->tx_ring_num[t]; i++) 1972 priv->tx_ring[t][i]->bf_enabled = 1973 bf_enabled_new; 1974 1975 en_info(priv, "BlueFlame %s\n", 1976 bf_enabled_new ? "Enabled" : "Disabled"); 1977 } 1978 1979 if (phv_enabled_new != phv_enabled_old) { 1980 ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new); 1981 if (ret) 1982 return ret; 1983 else if (phv_enabled_new) 1984 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV; 1985 else 1986 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV; 1987 en_info(priv, "PHV bit %s\n", 1988 phv_enabled_new ? "Enabled" : "Disabled"); 1989 } 1990 return 0; 1991 } 1992 1993 static u32 mlx4_en_get_priv_flags(struct net_device *dev) 1994 { 1995 struct mlx4_en_priv *priv = netdev_priv(dev); 1996 1997 return priv->pflags; 1998 } 1999 2000 static int mlx4_en_get_tunable(struct net_device *dev, 2001 const struct ethtool_tunable *tuna, 2002 void *data) 2003 { 2004 const struct mlx4_en_priv *priv = netdev_priv(dev); 2005 int ret = 0; 2006 2007 switch (tuna->id) { 2008 case ETHTOOL_TX_COPYBREAK: 2009 *(u32 *)data = priv->prof->inline_thold; 2010 break; 2011 default: 2012 ret = -EINVAL; 2013 break; 2014 } 2015 2016 return ret; 2017 } 2018 2019 static int mlx4_en_set_tunable(struct net_device *dev, 2020 const struct ethtool_tunable *tuna, 2021 const void *data) 2022 { 2023 struct mlx4_en_priv *priv = netdev_priv(dev); 2024 int val, ret = 0; 2025 2026 switch (tuna->id) { 2027 case ETHTOOL_TX_COPYBREAK: 2028 val = *(u32 *)data; 2029 if (val < MIN_PKT_LEN || val > MAX_INLINE) 2030 ret = -EINVAL; 2031 else 2032 priv->prof->inline_thold = val; 2033 break; 2034 default: 2035 ret = -EINVAL; 2036 break; 2037 } 2038 2039 return ret; 2040 } 2041 2042 static int mlx4_en_get_module_info(struct net_device *dev, 2043 struct ethtool_modinfo *modinfo) 2044 { 2045 struct mlx4_en_priv *priv = netdev_priv(dev); 2046 struct mlx4_en_dev *mdev = priv->mdev; 2047 int ret; 2048 u8 data[4]; 2049 2050 /* Read first 2 bytes to get Module & REV ID */ 2051 ret = mlx4_get_module_info(mdev->dev, priv->port, 2052 0/*offset*/, 2/*size*/, data); 2053 if (ret < 2) 2054 return -EIO; 2055 2056 switch (data[0] /* identifier */) { 2057 case MLX4_MODULE_ID_QSFP: 2058 modinfo->type = ETH_MODULE_SFF_8436; 2059 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2060 break; 2061 case MLX4_MODULE_ID_QSFP_PLUS: 2062 if (data[1] >= 0x3) { /* revision id */ 2063 modinfo->type = ETH_MODULE_SFF_8636; 2064 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2065 } else { 2066 modinfo->type = ETH_MODULE_SFF_8436; 2067 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2068 } 2069 break; 2070 case MLX4_MODULE_ID_QSFP28: 2071 modinfo->type = ETH_MODULE_SFF_8636; 2072 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2073 break; 2074 case MLX4_MODULE_ID_SFP: 2075 modinfo->type = ETH_MODULE_SFF_8472; 2076 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2077 break; 2078 default: 2079 return -EINVAL; 2080 } 2081 2082 return 0; 2083 } 2084 2085 static int mlx4_en_get_module_eeprom(struct net_device *dev, 2086 struct ethtool_eeprom *ee, 2087 u8 *data) 2088 { 2089 struct mlx4_en_priv *priv = netdev_priv(dev); 2090 struct mlx4_en_dev *mdev = priv->mdev; 2091 int offset = ee->offset; 2092 int i = 0, ret; 2093 2094 if (ee->len == 0) 2095 return -EINVAL; 2096 2097 memset(data, 0, ee->len); 2098 2099 while (i < ee->len) { 2100 en_dbg(DRV, priv, 2101 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n", 2102 i, offset, ee->len - i); 2103 2104 ret = mlx4_get_module_info(mdev->dev, priv->port, 2105 offset, ee->len - i, data + i); 2106 2107 if (!ret) /* Done reading */ 2108 return 0; 2109 2110 if (ret < 0) { 2111 en_err(priv, 2112 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n", 2113 i, offset, ee->len - i, ret); 2114 return 0; 2115 } 2116 2117 i += ret; 2118 offset += ret; 2119 } 2120 return 0; 2121 } 2122 2123 static int mlx4_en_set_phys_id(struct net_device *dev, 2124 enum ethtool_phys_id_state state) 2125 { 2126 int err; 2127 u16 beacon_duration; 2128 struct mlx4_en_priv *priv = netdev_priv(dev); 2129 struct mlx4_en_dev *mdev = priv->mdev; 2130 2131 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON)) 2132 return -EOPNOTSUPP; 2133 2134 switch (state) { 2135 case ETHTOOL_ID_ACTIVE: 2136 beacon_duration = PORT_BEACON_MAX_LIMIT; 2137 break; 2138 case ETHTOOL_ID_INACTIVE: 2139 beacon_duration = 0; 2140 break; 2141 default: 2142 return -EOPNOTSUPP; 2143 } 2144 2145 err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration); 2146 return err; 2147 } 2148 2149 const struct ethtool_ops mlx4_en_ethtool_ops = { 2150 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2151 ETHTOOL_COALESCE_MAX_FRAMES | 2152 ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ | 2153 ETHTOOL_COALESCE_PKT_RATE_RX_USECS, 2154 .get_drvinfo = mlx4_en_get_drvinfo, 2155 .get_link_ksettings = mlx4_en_get_link_ksettings, 2156 .set_link_ksettings = mlx4_en_set_link_ksettings, 2157 .get_link = ethtool_op_get_link, 2158 .get_strings = mlx4_en_get_strings, 2159 .get_sset_count = mlx4_en_get_sset_count, 2160 .get_ethtool_stats = mlx4_en_get_ethtool_stats, 2161 .self_test = mlx4_en_self_test, 2162 .set_phys_id = mlx4_en_set_phys_id, 2163 .get_wol = mlx4_en_get_wol, 2164 .set_wol = mlx4_en_set_wol, 2165 .get_msglevel = mlx4_en_get_msglevel, 2166 .set_msglevel = mlx4_en_set_msglevel, 2167 .get_coalesce = mlx4_en_get_coalesce, 2168 .set_coalesce = mlx4_en_set_coalesce, 2169 .get_pause_stats = mlx4_en_get_pause_stats, 2170 .get_pauseparam = mlx4_en_get_pauseparam, 2171 .set_pauseparam = mlx4_en_set_pauseparam, 2172 .get_ringparam = mlx4_en_get_ringparam, 2173 .set_ringparam = mlx4_en_set_ringparam, 2174 .get_rxnfc = mlx4_en_get_rxnfc, 2175 .set_rxnfc = mlx4_en_set_rxnfc, 2176 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size, 2177 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size, 2178 .get_rxfh = mlx4_en_get_rxfh, 2179 .set_rxfh = mlx4_en_set_rxfh, 2180 .get_channels = mlx4_en_get_channels, 2181 .set_channels = mlx4_en_set_channels, 2182 .get_ts_info = mlx4_en_get_ts_info, 2183 .set_priv_flags = mlx4_en_set_priv_flags, 2184 .get_priv_flags = mlx4_en_get_priv_flags, 2185 .get_tunable = mlx4_en_get_tunable, 2186 .set_tunable = mlx4_en_set_tunable, 2187 .get_module_info = mlx4_en_get_module_info, 2188 .get_module_eeprom = mlx4_en_get_module_eeprom 2189 }; 2190 2191 2192 2193 2194 2195