1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <linux/kernel.h> 35 #include <linux/ethtool.h> 36 #include <linux/netdevice.h> 37 #include <linux/mlx4/driver.h> 38 #include <linux/mlx4/device.h> 39 #include <linux/in.h> 40 #include <net/ip.h> 41 42 #include "mlx4_en.h" 43 #include "en_port.h" 44 45 #define EN_ETHTOOL_QP_ATTACH (1ull << 63) 46 #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff) 47 #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff) 48 49 static int mlx4_en_moderation_update(struct mlx4_en_priv *priv) 50 { 51 int i; 52 int err = 0; 53 54 for (i = 0; i < priv->tx_ring_num; i++) { 55 priv->tx_cq[i]->moder_cnt = priv->tx_frames; 56 priv->tx_cq[i]->moder_time = priv->tx_usecs; 57 if (priv->port_up) { 58 err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]); 59 if (err) 60 return err; 61 } 62 } 63 64 if (priv->adaptive_rx_coal) 65 return 0; 66 67 for (i = 0; i < priv->rx_ring_num; i++) { 68 priv->rx_cq[i]->moder_cnt = priv->rx_frames; 69 priv->rx_cq[i]->moder_time = priv->rx_usecs; 70 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; 71 if (priv->port_up) { 72 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]); 73 if (err) 74 return err; 75 } 76 } 77 78 return err; 79 } 80 81 static void 82 mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) 83 { 84 struct mlx4_en_priv *priv = netdev_priv(dev); 85 struct mlx4_en_dev *mdev = priv->mdev; 86 87 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); 88 strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")", 89 sizeof(drvinfo->version)); 90 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 91 "%d.%d.%d", 92 (u16) (mdev->dev->caps.fw_ver >> 32), 93 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff), 94 (u16) (mdev->dev->caps.fw_ver & 0xffff)); 95 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->pdev), 96 sizeof(drvinfo->bus_info)); 97 drvinfo->n_stats = 0; 98 drvinfo->regdump_len = 0; 99 drvinfo->eedump_len = 0; 100 } 101 102 static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = { 103 "blueflame", 104 }; 105 106 static const char main_strings[][ETH_GSTRING_LEN] = { 107 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", 108 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", 109 "rx_length_errors", "rx_over_errors", "rx_crc_errors", 110 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", 111 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", 112 "tx_heartbeat_errors", "tx_window_errors", 113 114 /* port statistics */ 115 "tso_packets", 116 "xmit_more", 117 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed", 118 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload", 119 120 /* packet statistics */ 121 "broadcast", "rx_prio_0", "rx_prio_1", "rx_prio_2", "rx_prio_3", 122 "rx_prio_4", "rx_prio_5", "rx_prio_6", "rx_prio_7", "tx_prio_0", 123 "tx_prio_1", "tx_prio_2", "tx_prio_3", "tx_prio_4", "tx_prio_5", 124 "tx_prio_6", "tx_prio_7", 125 }; 126 #define NUM_MAIN_STATS 21 127 #define NUM_ALL_STATS (NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PKT_STATS + NUM_PERF_STATS) 128 129 static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= { 130 "Interrupt Test", 131 "Link Test", 132 "Speed Test", 133 "Register Test", 134 "Loopback Test", 135 }; 136 137 static u32 mlx4_en_get_msglevel(struct net_device *dev) 138 { 139 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable; 140 } 141 142 static void mlx4_en_set_msglevel(struct net_device *dev, u32 val) 143 { 144 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val; 145 } 146 147 static void mlx4_en_get_wol(struct net_device *netdev, 148 struct ethtool_wolinfo *wol) 149 { 150 struct mlx4_en_priv *priv = netdev_priv(netdev); 151 int err = 0; 152 u64 config = 0; 153 u64 mask; 154 155 if ((priv->port < 1) || (priv->port > 2)) { 156 en_err(priv, "Failed to get WoL information\n"); 157 return; 158 } 159 160 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : 161 MLX4_DEV_CAP_FLAG_WOL_PORT2; 162 163 if (!(priv->mdev->dev->caps.flags & mask)) { 164 wol->supported = 0; 165 wol->wolopts = 0; 166 return; 167 } 168 169 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); 170 if (err) { 171 en_err(priv, "Failed to get WoL information\n"); 172 return; 173 } 174 175 if (config & MLX4_EN_WOL_MAGIC) 176 wol->supported = WAKE_MAGIC; 177 else 178 wol->supported = 0; 179 180 if (config & MLX4_EN_WOL_ENABLED) 181 wol->wolopts = WAKE_MAGIC; 182 else 183 wol->wolopts = 0; 184 } 185 186 static int mlx4_en_set_wol(struct net_device *netdev, 187 struct ethtool_wolinfo *wol) 188 { 189 struct mlx4_en_priv *priv = netdev_priv(netdev); 190 u64 config = 0; 191 int err = 0; 192 u64 mask; 193 194 if ((priv->port < 1) || (priv->port > 2)) 195 return -EOPNOTSUPP; 196 197 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : 198 MLX4_DEV_CAP_FLAG_WOL_PORT2; 199 200 if (!(priv->mdev->dev->caps.flags & mask)) 201 return -EOPNOTSUPP; 202 203 if (wol->supported & ~WAKE_MAGIC) 204 return -EINVAL; 205 206 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); 207 if (err) { 208 en_err(priv, "Failed to get WoL info, unable to modify\n"); 209 return err; 210 } 211 212 if (wol->wolopts & WAKE_MAGIC) { 213 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED | 214 MLX4_EN_WOL_MAGIC; 215 } else { 216 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC); 217 config |= MLX4_EN_WOL_DO_MODIFY; 218 } 219 220 err = mlx4_wol_write(priv->mdev->dev, config, priv->port); 221 if (err) 222 en_err(priv, "Failed to set WoL information\n"); 223 224 return err; 225 } 226 227 static int mlx4_en_get_sset_count(struct net_device *dev, int sset) 228 { 229 struct mlx4_en_priv *priv = netdev_priv(dev); 230 int bit_count = hweight64(priv->stats_bitmap); 231 232 switch (sset) { 233 case ETH_SS_STATS: 234 return (priv->stats_bitmap ? bit_count : NUM_ALL_STATS) + 235 (priv->tx_ring_num * 2) + 236 #ifdef CONFIG_NET_RX_BUSY_POLL 237 (priv->rx_ring_num * 5); 238 #else 239 (priv->rx_ring_num * 2); 240 #endif 241 case ETH_SS_TEST: 242 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags 243 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2; 244 case ETH_SS_PRIV_FLAGS: 245 return ARRAY_SIZE(mlx4_en_priv_flags); 246 default: 247 return -EOPNOTSUPP; 248 } 249 } 250 251 static void mlx4_en_get_ethtool_stats(struct net_device *dev, 252 struct ethtool_stats *stats, uint64_t *data) 253 { 254 struct mlx4_en_priv *priv = netdev_priv(dev); 255 int index = 0; 256 int i, j = 0; 257 258 spin_lock_bh(&priv->stats_lock); 259 260 if (!(priv->stats_bitmap)) { 261 for (i = 0; i < NUM_MAIN_STATS; i++) 262 data[index++] = 263 ((unsigned long *) &priv->stats)[i]; 264 for (i = 0; i < NUM_PORT_STATS; i++) 265 data[index++] = 266 ((unsigned long *) &priv->port_stats)[i]; 267 for (i = 0; i < NUM_PKT_STATS; i++) 268 data[index++] = 269 ((unsigned long *) &priv->pkstats)[i]; 270 } else { 271 for (i = 0; i < NUM_MAIN_STATS; i++) { 272 if ((priv->stats_bitmap >> j) & 1) 273 data[index++] = 274 ((unsigned long *) &priv->stats)[i]; 275 j++; 276 } 277 for (i = 0; i < NUM_PORT_STATS; i++) { 278 if ((priv->stats_bitmap >> j) & 1) 279 data[index++] = 280 ((unsigned long *) &priv->port_stats)[i]; 281 j++; 282 } 283 } 284 for (i = 0; i < priv->tx_ring_num; i++) { 285 data[index++] = priv->tx_ring[i]->packets; 286 data[index++] = priv->tx_ring[i]->bytes; 287 } 288 for (i = 0; i < priv->rx_ring_num; i++) { 289 data[index++] = priv->rx_ring[i]->packets; 290 data[index++] = priv->rx_ring[i]->bytes; 291 #ifdef CONFIG_NET_RX_BUSY_POLL 292 data[index++] = priv->rx_ring[i]->yields; 293 data[index++] = priv->rx_ring[i]->misses; 294 data[index++] = priv->rx_ring[i]->cleaned; 295 #endif 296 } 297 spin_unlock_bh(&priv->stats_lock); 298 299 } 300 301 static void mlx4_en_self_test(struct net_device *dev, 302 struct ethtool_test *etest, u64 *buf) 303 { 304 mlx4_en_ex_selftest(dev, &etest->flags, buf); 305 } 306 307 static void mlx4_en_get_strings(struct net_device *dev, 308 uint32_t stringset, uint8_t *data) 309 { 310 struct mlx4_en_priv *priv = netdev_priv(dev); 311 int index = 0; 312 int i; 313 314 switch (stringset) { 315 case ETH_SS_TEST: 316 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++) 317 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); 318 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) 319 for (; i < MLX4_EN_NUM_SELF_TEST; i++) 320 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); 321 break; 322 323 case ETH_SS_STATS: 324 /* Add main counters */ 325 if (!priv->stats_bitmap) { 326 for (i = 0; i < NUM_MAIN_STATS; i++) 327 strcpy(data + (index++) * ETH_GSTRING_LEN, 328 main_strings[i]); 329 for (i = 0; i < NUM_PORT_STATS; i++) 330 strcpy(data + (index++) * ETH_GSTRING_LEN, 331 main_strings[i + 332 NUM_MAIN_STATS]); 333 for (i = 0; i < NUM_PKT_STATS; i++) 334 strcpy(data + (index++) * ETH_GSTRING_LEN, 335 main_strings[i + 336 NUM_MAIN_STATS + 337 NUM_PORT_STATS]); 338 } else 339 for (i = 0; i < NUM_MAIN_STATS + NUM_PORT_STATS; i++) { 340 if ((priv->stats_bitmap >> i) & 1) { 341 strcpy(data + 342 (index++) * ETH_GSTRING_LEN, 343 main_strings[i]); 344 } 345 if (!(priv->stats_bitmap >> i)) 346 break; 347 } 348 for (i = 0; i < priv->tx_ring_num; i++) { 349 sprintf(data + (index++) * ETH_GSTRING_LEN, 350 "tx%d_packets", i); 351 sprintf(data + (index++) * ETH_GSTRING_LEN, 352 "tx%d_bytes", i); 353 } 354 for (i = 0; i < priv->rx_ring_num; i++) { 355 sprintf(data + (index++) * ETH_GSTRING_LEN, 356 "rx%d_packets", i); 357 sprintf(data + (index++) * ETH_GSTRING_LEN, 358 "rx%d_bytes", i); 359 #ifdef CONFIG_NET_RX_BUSY_POLL 360 sprintf(data + (index++) * ETH_GSTRING_LEN, 361 "rx%d_napi_yield", i); 362 sprintf(data + (index++) * ETH_GSTRING_LEN, 363 "rx%d_misses", i); 364 sprintf(data + (index++) * ETH_GSTRING_LEN, 365 "rx%d_cleaned", i); 366 #endif 367 } 368 break; 369 case ETH_SS_PRIV_FLAGS: 370 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++) 371 strcpy(data + i * ETH_GSTRING_LEN, 372 mlx4_en_priv_flags[i]); 373 break; 374 375 } 376 } 377 378 static u32 mlx4_en_autoneg_get(struct net_device *dev) 379 { 380 struct mlx4_en_priv *priv = netdev_priv(dev); 381 struct mlx4_en_dev *mdev = priv->mdev; 382 u32 autoneg = AUTONEG_DISABLE; 383 384 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) && 385 (priv->port_state.flags & MLX4_EN_PORT_ANE)) 386 autoneg = AUTONEG_ENABLE; 387 388 return autoneg; 389 } 390 391 static u32 ptys_get_supported_port(struct mlx4_ptys_reg *ptys_reg) 392 { 393 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); 394 395 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) 396 | MLX4_PROT_MASK(MLX4_1000BASE_T) 397 | MLX4_PROT_MASK(MLX4_100BASE_TX))) { 398 return SUPPORTED_TP; 399 } 400 401 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) 402 | MLX4_PROT_MASK(MLX4_10GBASE_SR) 403 | MLX4_PROT_MASK(MLX4_56GBASE_SR4) 404 | MLX4_PROT_MASK(MLX4_40GBASE_CR4) 405 | MLX4_PROT_MASK(MLX4_40GBASE_SR4) 406 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { 407 return SUPPORTED_FIBRE; 408 } 409 410 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) 411 | MLX4_PROT_MASK(MLX4_40GBASE_KR4) 412 | MLX4_PROT_MASK(MLX4_20GBASE_KR2) 413 | MLX4_PROT_MASK(MLX4_10GBASE_KR) 414 | MLX4_PROT_MASK(MLX4_10GBASE_KX4) 415 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { 416 return SUPPORTED_Backplane; 417 } 418 return 0; 419 } 420 421 static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg) 422 { 423 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper); 424 425 if (!eth_proto) /* link down */ 426 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); 427 428 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) 429 | MLX4_PROT_MASK(MLX4_1000BASE_T) 430 | MLX4_PROT_MASK(MLX4_100BASE_TX))) { 431 return PORT_TP; 432 } 433 434 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR) 435 | MLX4_PROT_MASK(MLX4_56GBASE_SR4) 436 | MLX4_PROT_MASK(MLX4_40GBASE_SR4) 437 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { 438 return PORT_FIBRE; 439 } 440 441 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) 442 | MLX4_PROT_MASK(MLX4_56GBASE_CR4) 443 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) { 444 return PORT_DA; 445 } 446 447 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) 448 | MLX4_PROT_MASK(MLX4_40GBASE_KR4) 449 | MLX4_PROT_MASK(MLX4_20GBASE_KR2) 450 | MLX4_PROT_MASK(MLX4_10GBASE_KR) 451 | MLX4_PROT_MASK(MLX4_10GBASE_KX4) 452 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { 453 return PORT_NONE; 454 } 455 return PORT_OTHER; 456 } 457 458 #define MLX4_LINK_MODES_SZ \ 459 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8) 460 461 enum ethtool_report { 462 SUPPORTED = 0, 463 ADVERTISED = 1, 464 SPEED = 2 465 }; 466 467 /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */ 468 static u32 ptys2ethtool_map[MLX4_LINK_MODES_SZ][3] = { 469 [MLX4_100BASE_TX] = { 470 SUPPORTED_100baseT_Full, 471 ADVERTISED_100baseT_Full, 472 SPEED_100 473 }, 474 475 [MLX4_1000BASE_T] = { 476 SUPPORTED_1000baseT_Full, 477 ADVERTISED_1000baseT_Full, 478 SPEED_1000 479 }, 480 [MLX4_1000BASE_CX_SGMII] = { 481 SUPPORTED_1000baseKX_Full, 482 ADVERTISED_1000baseKX_Full, 483 SPEED_1000 484 }, 485 [MLX4_1000BASE_KX] = { 486 SUPPORTED_1000baseKX_Full, 487 ADVERTISED_1000baseKX_Full, 488 SPEED_1000 489 }, 490 491 [MLX4_10GBASE_T] = { 492 SUPPORTED_10000baseT_Full, 493 ADVERTISED_10000baseT_Full, 494 SPEED_10000 495 }, 496 [MLX4_10GBASE_CX4] = { 497 SUPPORTED_10000baseKX4_Full, 498 ADVERTISED_10000baseKX4_Full, 499 SPEED_10000 500 }, 501 [MLX4_10GBASE_KX4] = { 502 SUPPORTED_10000baseKX4_Full, 503 ADVERTISED_10000baseKX4_Full, 504 SPEED_10000 505 }, 506 [MLX4_10GBASE_KR] = { 507 SUPPORTED_10000baseKR_Full, 508 ADVERTISED_10000baseKR_Full, 509 SPEED_10000 510 }, 511 [MLX4_10GBASE_CR] = { 512 SUPPORTED_10000baseKR_Full, 513 ADVERTISED_10000baseKR_Full, 514 SPEED_10000 515 }, 516 [MLX4_10GBASE_SR] = { 517 SUPPORTED_10000baseKR_Full, 518 ADVERTISED_10000baseKR_Full, 519 SPEED_10000 520 }, 521 522 [MLX4_20GBASE_KR2] = { 523 SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full, 524 ADVERTISED_20000baseMLD2_Full | ADVERTISED_20000baseKR2_Full, 525 SPEED_20000 526 }, 527 528 [MLX4_40GBASE_CR4] = { 529 SUPPORTED_40000baseCR4_Full, 530 ADVERTISED_40000baseCR4_Full, 531 SPEED_40000 532 }, 533 [MLX4_40GBASE_KR4] = { 534 SUPPORTED_40000baseKR4_Full, 535 ADVERTISED_40000baseKR4_Full, 536 SPEED_40000 537 }, 538 [MLX4_40GBASE_SR4] = { 539 SUPPORTED_40000baseSR4_Full, 540 ADVERTISED_40000baseSR4_Full, 541 SPEED_40000 542 }, 543 544 [MLX4_56GBASE_KR4] = { 545 SUPPORTED_56000baseKR4_Full, 546 ADVERTISED_56000baseKR4_Full, 547 SPEED_56000 548 }, 549 [MLX4_56GBASE_CR4] = { 550 SUPPORTED_56000baseCR4_Full, 551 ADVERTISED_56000baseCR4_Full, 552 SPEED_56000 553 }, 554 [MLX4_56GBASE_SR4] = { 555 SUPPORTED_56000baseSR4_Full, 556 ADVERTISED_56000baseSR4_Full, 557 SPEED_56000 558 }, 559 }; 560 561 static u32 ptys2ethtool_link_modes(u32 eth_proto, enum ethtool_report report) 562 { 563 int i; 564 u32 link_modes = 0; 565 566 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 567 if (eth_proto & MLX4_PROT_MASK(i)) 568 link_modes |= ptys2ethtool_map[i][report]; 569 } 570 return link_modes; 571 } 572 573 static u32 ethtool2ptys_link_modes(u32 link_modes, enum ethtool_report report) 574 { 575 int i; 576 u32 ptys_modes = 0; 577 578 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 579 if (ptys2ethtool_map[i][report] & link_modes) 580 ptys_modes |= 1 << i; 581 } 582 return ptys_modes; 583 } 584 585 /* Convert actual speed (SPEED_XXX) to ptys link modes */ 586 static u32 speed2ptys_link_modes(u32 speed) 587 { 588 int i; 589 u32 ptys_modes = 0; 590 591 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 592 if (ptys2ethtool_map[i][SPEED] == speed) 593 ptys_modes |= 1 << i; 594 } 595 return ptys_modes; 596 } 597 598 static int ethtool_get_ptys_settings(struct net_device *dev, 599 struct ethtool_cmd *cmd) 600 { 601 struct mlx4_en_priv *priv = netdev_priv(dev); 602 struct mlx4_ptys_reg ptys_reg; 603 u32 eth_proto; 604 int ret; 605 606 memset(&ptys_reg, 0, sizeof(ptys_reg)); 607 ptys_reg.local_port = priv->port; 608 ptys_reg.proto_mask = MLX4_PTYS_EN; 609 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, 610 MLX4_ACCESS_REG_QUERY, &ptys_reg); 611 if (ret) { 612 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)", 613 ret); 614 return ret; 615 } 616 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n", 617 ptys_reg.proto_mask); 618 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n", 619 be32_to_cpu(ptys_reg.eth_proto_cap)); 620 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n", 621 be32_to_cpu(ptys_reg.eth_proto_admin)); 622 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n", 623 be32_to_cpu(ptys_reg.eth_proto_oper)); 624 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n", 625 be32_to_cpu(ptys_reg.eth_proto_lp_adv)); 626 627 cmd->supported = 0; 628 cmd->advertising = 0; 629 630 cmd->supported |= ptys_get_supported_port(&ptys_reg); 631 632 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap); 633 cmd->supported |= ptys2ethtool_link_modes(eth_proto, SUPPORTED); 634 635 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin); 636 cmd->advertising |= ptys2ethtool_link_modes(eth_proto, ADVERTISED); 637 638 cmd->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 639 cmd->advertising |= (priv->prof->tx_pause) ? ADVERTISED_Pause : 0; 640 641 cmd->advertising |= (priv->prof->tx_pause ^ priv->prof->rx_pause) ? 642 ADVERTISED_Asym_Pause : 0; 643 644 cmd->port = ptys_get_active_port(&ptys_reg); 645 cmd->transceiver = (SUPPORTED_TP & cmd->supported) ? 646 XCVR_EXTERNAL : XCVR_INTERNAL; 647 648 if (mlx4_en_autoneg_get(dev)) { 649 cmd->supported |= SUPPORTED_Autoneg; 650 cmd->advertising |= ADVERTISED_Autoneg; 651 } 652 653 cmd->autoneg = (priv->port_state.flags & MLX4_EN_PORT_ANC) ? 654 AUTONEG_ENABLE : AUTONEG_DISABLE; 655 656 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv); 657 cmd->lp_advertising = ptys2ethtool_link_modes(eth_proto, ADVERTISED); 658 659 cmd->lp_advertising |= (priv->port_state.flags & MLX4_EN_PORT_ANC) ? 660 ADVERTISED_Autoneg : 0; 661 662 cmd->phy_address = 0; 663 cmd->mdio_support = 0; 664 cmd->maxtxpkt = 0; 665 cmd->maxrxpkt = 0; 666 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID; 667 cmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 668 669 return ret; 670 } 671 672 static void ethtool_get_default_settings(struct net_device *dev, 673 struct ethtool_cmd *cmd) 674 { 675 struct mlx4_en_priv *priv = netdev_priv(dev); 676 int trans_type; 677 678 cmd->autoneg = AUTONEG_DISABLE; 679 cmd->supported = SUPPORTED_10000baseT_Full; 680 cmd->advertising = ADVERTISED_10000baseT_Full; 681 trans_type = priv->port_state.transceiver; 682 683 if (trans_type > 0 && trans_type <= 0xC) { 684 cmd->port = PORT_FIBRE; 685 cmd->transceiver = XCVR_EXTERNAL; 686 cmd->supported |= SUPPORTED_FIBRE; 687 cmd->advertising |= ADVERTISED_FIBRE; 688 } else if (trans_type == 0x80 || trans_type == 0) { 689 cmd->port = PORT_TP; 690 cmd->transceiver = XCVR_INTERNAL; 691 cmd->supported |= SUPPORTED_TP; 692 cmd->advertising |= ADVERTISED_TP; 693 } else { 694 cmd->port = -1; 695 cmd->transceiver = -1; 696 } 697 } 698 699 static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 700 { 701 struct mlx4_en_priv *priv = netdev_priv(dev); 702 int ret = -EINVAL; 703 704 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port)) 705 return -ENOMEM; 706 707 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n", 708 priv->port_state.flags & MLX4_EN_PORT_ANC, 709 priv->port_state.flags & MLX4_EN_PORT_ANE); 710 711 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) 712 ret = ethtool_get_ptys_settings(dev, cmd); 713 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */ 714 ethtool_get_default_settings(dev, cmd); 715 716 if (netif_carrier_ok(dev)) { 717 ethtool_cmd_speed_set(cmd, priv->port_state.link_speed); 718 cmd->duplex = DUPLEX_FULL; 719 } else { 720 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 721 cmd->duplex = DUPLEX_UNKNOWN; 722 } 723 return 0; 724 } 725 726 /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */ 727 static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed, 728 __be32 proto_cap) 729 { 730 __be32 proto_admin = 0; 731 732 if (!speed) { /* Speed = 0 ==> Reset Link modes */ 733 proto_admin = proto_cap; 734 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n", 735 be32_to_cpu(proto_cap)); 736 } else { 737 u32 ptys_link_modes = speed2ptys_link_modes(speed); 738 739 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap; 740 en_info(priv, "Setting Speed to %d\n", speed); 741 } 742 return proto_admin; 743 } 744 745 static int mlx4_en_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 746 { 747 struct mlx4_en_priv *priv = netdev_priv(dev); 748 struct mlx4_ptys_reg ptys_reg; 749 __be32 proto_admin; 750 int ret; 751 752 u32 ptys_adv = ethtool2ptys_link_modes(cmd->advertising, ADVERTISED); 753 int speed = ethtool_cmd_speed(cmd); 754 755 en_dbg(DRV, priv, "Set Speed=%d adv=0x%x autoneg=%d duplex=%d\n", 756 speed, cmd->advertising, cmd->autoneg, cmd->duplex); 757 758 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) || 759 (cmd->duplex == DUPLEX_HALF)) 760 return -EINVAL; 761 762 memset(&ptys_reg, 0, sizeof(ptys_reg)); 763 ptys_reg.local_port = priv->port; 764 ptys_reg.proto_mask = MLX4_PTYS_EN; 765 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, 766 MLX4_ACCESS_REG_QUERY, &ptys_reg); 767 if (ret) { 768 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n", 769 ret); 770 return 0; 771 } 772 773 proto_admin = cpu_to_be32(ptys_adv); 774 if (speed >= 0 && speed != priv->port_state.link_speed) 775 /* If speed was set then speed decides :-) */ 776 proto_admin = speed_set_ptys_admin(priv, speed, 777 ptys_reg.eth_proto_cap); 778 779 proto_admin &= ptys_reg.eth_proto_cap; 780 781 if (proto_admin == ptys_reg.eth_proto_admin) 782 return 0; /* Nothing to change */ 783 784 if (!proto_admin) { 785 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n"); 786 return -EINVAL; /* nothing to change due to bad input */ 787 } 788 789 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n", 790 be32_to_cpu(proto_admin)); 791 792 ptys_reg.eth_proto_admin = proto_admin; 793 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE, 794 &ptys_reg); 795 if (ret) { 796 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)", 797 be32_to_cpu(ptys_reg.eth_proto_admin), ret); 798 return ret; 799 } 800 801 en_warn(priv, "Port link mode changed, restarting port...\n"); 802 mutex_lock(&priv->mdev->state_lock); 803 if (priv->port_up) { 804 mlx4_en_stop_port(dev, 1); 805 if (mlx4_en_start_port(dev)) 806 en_err(priv, "Failed restarting port %d\n", priv->port); 807 } 808 mutex_unlock(&priv->mdev->state_lock); 809 return 0; 810 } 811 812 static int mlx4_en_get_coalesce(struct net_device *dev, 813 struct ethtool_coalesce *coal) 814 { 815 struct mlx4_en_priv *priv = netdev_priv(dev); 816 817 coal->tx_coalesce_usecs = priv->tx_usecs; 818 coal->tx_max_coalesced_frames = priv->tx_frames; 819 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit; 820 821 coal->rx_coalesce_usecs = priv->rx_usecs; 822 coal->rx_max_coalesced_frames = priv->rx_frames; 823 824 coal->pkt_rate_low = priv->pkt_rate_low; 825 coal->rx_coalesce_usecs_low = priv->rx_usecs_low; 826 coal->pkt_rate_high = priv->pkt_rate_high; 827 coal->rx_coalesce_usecs_high = priv->rx_usecs_high; 828 coal->rate_sample_interval = priv->sample_interval; 829 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal; 830 831 return 0; 832 } 833 834 static int mlx4_en_set_coalesce(struct net_device *dev, 835 struct ethtool_coalesce *coal) 836 { 837 struct mlx4_en_priv *priv = netdev_priv(dev); 838 839 if (!coal->tx_max_coalesced_frames_irq) 840 return -EINVAL; 841 842 priv->rx_frames = (coal->rx_max_coalesced_frames == 843 MLX4_EN_AUTO_CONF) ? 844 MLX4_EN_RX_COAL_TARGET : 845 coal->rx_max_coalesced_frames; 846 priv->rx_usecs = (coal->rx_coalesce_usecs == 847 MLX4_EN_AUTO_CONF) ? 848 MLX4_EN_RX_COAL_TIME : 849 coal->rx_coalesce_usecs; 850 851 /* Setting TX coalescing parameters */ 852 if (coal->tx_coalesce_usecs != priv->tx_usecs || 853 coal->tx_max_coalesced_frames != priv->tx_frames) { 854 priv->tx_usecs = coal->tx_coalesce_usecs; 855 priv->tx_frames = coal->tx_max_coalesced_frames; 856 } 857 858 /* Set adaptive coalescing params */ 859 priv->pkt_rate_low = coal->pkt_rate_low; 860 priv->rx_usecs_low = coal->rx_coalesce_usecs_low; 861 priv->pkt_rate_high = coal->pkt_rate_high; 862 priv->rx_usecs_high = coal->rx_coalesce_usecs_high; 863 priv->sample_interval = coal->rate_sample_interval; 864 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce; 865 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq; 866 867 return mlx4_en_moderation_update(priv); 868 } 869 870 static int mlx4_en_set_pauseparam(struct net_device *dev, 871 struct ethtool_pauseparam *pause) 872 { 873 struct mlx4_en_priv *priv = netdev_priv(dev); 874 struct mlx4_en_dev *mdev = priv->mdev; 875 int err; 876 877 if (pause->autoneg) 878 return -EINVAL; 879 880 priv->prof->tx_pause = pause->tx_pause != 0; 881 priv->prof->rx_pause = pause->rx_pause != 0; 882 err = mlx4_SET_PORT_general(mdev->dev, priv->port, 883 priv->rx_skb_size + ETH_FCS_LEN, 884 priv->prof->tx_pause, 885 priv->prof->tx_ppp, 886 priv->prof->rx_pause, 887 priv->prof->rx_ppp); 888 if (err) 889 en_err(priv, "Failed setting pause params\n"); 890 891 return err; 892 } 893 894 static void mlx4_en_get_pauseparam(struct net_device *dev, 895 struct ethtool_pauseparam *pause) 896 { 897 struct mlx4_en_priv *priv = netdev_priv(dev); 898 899 pause->tx_pause = priv->prof->tx_pause; 900 pause->rx_pause = priv->prof->rx_pause; 901 } 902 903 static int mlx4_en_set_ringparam(struct net_device *dev, 904 struct ethtool_ringparam *param) 905 { 906 struct mlx4_en_priv *priv = netdev_priv(dev); 907 struct mlx4_en_dev *mdev = priv->mdev; 908 u32 rx_size, tx_size; 909 int port_up = 0; 910 int err = 0; 911 912 if (param->rx_jumbo_pending || param->rx_mini_pending) 913 return -EINVAL; 914 915 rx_size = roundup_pow_of_two(param->rx_pending); 916 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE); 917 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE); 918 tx_size = roundup_pow_of_two(param->tx_pending); 919 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE); 920 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE); 921 922 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size : 923 priv->rx_ring[0]->size) && 924 tx_size == priv->tx_ring[0]->size) 925 return 0; 926 927 mutex_lock(&mdev->state_lock); 928 if (priv->port_up) { 929 port_up = 1; 930 mlx4_en_stop_port(dev, 1); 931 } 932 933 mlx4_en_free_resources(priv); 934 935 priv->prof->tx_ring_size = tx_size; 936 priv->prof->rx_ring_size = rx_size; 937 938 err = mlx4_en_alloc_resources(priv); 939 if (err) { 940 en_err(priv, "Failed reallocating port resources\n"); 941 goto out; 942 } 943 if (port_up) { 944 err = mlx4_en_start_port(dev); 945 if (err) 946 en_err(priv, "Failed starting port\n"); 947 } 948 949 err = mlx4_en_moderation_update(priv); 950 951 out: 952 mutex_unlock(&mdev->state_lock); 953 return err; 954 } 955 956 static void mlx4_en_get_ringparam(struct net_device *dev, 957 struct ethtool_ringparam *param) 958 { 959 struct mlx4_en_priv *priv = netdev_priv(dev); 960 961 memset(param, 0, sizeof(*param)); 962 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE; 963 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE; 964 param->rx_pending = priv->port_up ? 965 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size; 966 param->tx_pending = priv->tx_ring[0]->size; 967 } 968 969 static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev) 970 { 971 struct mlx4_en_priv *priv = netdev_priv(dev); 972 973 return priv->rx_ring_num; 974 } 975 976 static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev) 977 { 978 return MLX4_EN_RSS_KEY_SIZE; 979 } 980 981 static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc) 982 { 983 struct mlx4_en_priv *priv = netdev_priv(dev); 984 985 /* check if requested function is supported by the device */ 986 if ((hfunc == ETH_RSS_HASH_TOP && 987 !(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) || 988 (hfunc == ETH_RSS_HASH_XOR && 989 !(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR))) 990 return -EINVAL; 991 992 priv->rss_hash_fn = hfunc; 993 if (hfunc == ETH_RSS_HASH_TOP && !(dev->features & NETIF_F_RXHASH)) 994 en_warn(priv, 995 "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n"); 996 if (hfunc == ETH_RSS_HASH_XOR && (dev->features & NETIF_F_RXHASH)) 997 en_warn(priv, 998 "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n"); 999 return 0; 1000 } 1001 1002 static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key, 1003 u8 *hfunc) 1004 { 1005 struct mlx4_en_priv *priv = netdev_priv(dev); 1006 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1007 int rss_rings; 1008 size_t n = priv->rx_ring_num; 1009 int err = 0; 1010 1011 rss_rings = priv->prof->rss_rings ?: priv->rx_ring_num; 1012 rss_rings = 1 << ilog2(rss_rings); 1013 1014 while (n--) { 1015 if (!ring_index) 1016 break; 1017 ring_index[n] = rss_map->qps[n % rss_rings].qpn - 1018 rss_map->base_qpn; 1019 } 1020 if (key) 1021 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE); 1022 if (hfunc) 1023 *hfunc = priv->rss_hash_fn; 1024 return err; 1025 } 1026 1027 static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index, 1028 const u8 *key, const u8 hfunc) 1029 { 1030 struct mlx4_en_priv *priv = netdev_priv(dev); 1031 struct mlx4_en_dev *mdev = priv->mdev; 1032 int port_up = 0; 1033 int err = 0; 1034 int i; 1035 int rss_rings = 0; 1036 1037 /* Calculate RSS table size and make sure flows are spread evenly 1038 * between rings 1039 */ 1040 for (i = 0; i < priv->rx_ring_num; i++) { 1041 if (!ring_index) 1042 continue; 1043 if (i > 0 && !ring_index[i] && !rss_rings) 1044 rss_rings = i; 1045 1046 if (ring_index[i] != (i % (rss_rings ?: priv->rx_ring_num))) 1047 return -EINVAL; 1048 } 1049 1050 if (!rss_rings) 1051 rss_rings = priv->rx_ring_num; 1052 1053 /* RSS table size must be an order of 2 */ 1054 if (!is_power_of_2(rss_rings)) 1055 return -EINVAL; 1056 1057 if (hfunc != ETH_RSS_HASH_NO_CHANGE) { 1058 err = mlx4_en_check_rxfh_func(dev, hfunc); 1059 if (err) 1060 return err; 1061 } 1062 1063 mutex_lock(&mdev->state_lock); 1064 if (priv->port_up) { 1065 port_up = 1; 1066 mlx4_en_stop_port(dev, 1); 1067 } 1068 1069 if (ring_index) 1070 priv->prof->rss_rings = rss_rings; 1071 if (key) 1072 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE); 1073 1074 if (port_up) { 1075 err = mlx4_en_start_port(dev); 1076 if (err) 1077 en_err(priv, "Failed starting port\n"); 1078 } 1079 1080 mutex_unlock(&mdev->state_lock); 1081 return err; 1082 } 1083 1084 #define all_zeros_or_all_ones(field) \ 1085 ((field) == 0 || (field) == (__force typeof(field))-1) 1086 1087 static int mlx4_en_validate_flow(struct net_device *dev, 1088 struct ethtool_rxnfc *cmd) 1089 { 1090 struct ethtool_usrip4_spec *l3_mask; 1091 struct ethtool_tcpip4_spec *l4_mask; 1092 struct ethhdr *eth_mask; 1093 1094 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1095 return -EINVAL; 1096 1097 if (cmd->fs.flow_type & FLOW_MAC_EXT) { 1098 /* dest mac mask must be ff:ff:ff:ff:ff:ff */ 1099 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest)) 1100 return -EINVAL; 1101 } 1102 1103 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1104 case TCP_V4_FLOW: 1105 case UDP_V4_FLOW: 1106 if (cmd->fs.m_u.tcp_ip4_spec.tos) 1107 return -EINVAL; 1108 l4_mask = &cmd->fs.m_u.tcp_ip4_spec; 1109 /* don't allow mask which isn't all 0 or 1 */ 1110 if (!all_zeros_or_all_ones(l4_mask->ip4src) || 1111 !all_zeros_or_all_ones(l4_mask->ip4dst) || 1112 !all_zeros_or_all_ones(l4_mask->psrc) || 1113 !all_zeros_or_all_ones(l4_mask->pdst)) 1114 return -EINVAL; 1115 break; 1116 case IP_USER_FLOW: 1117 l3_mask = &cmd->fs.m_u.usr_ip4_spec; 1118 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto || 1119 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 || 1120 (!l3_mask->ip4src && !l3_mask->ip4dst) || 1121 !all_zeros_or_all_ones(l3_mask->ip4src) || 1122 !all_zeros_or_all_ones(l3_mask->ip4dst)) 1123 return -EINVAL; 1124 break; 1125 case ETHER_FLOW: 1126 eth_mask = &cmd->fs.m_u.ether_spec; 1127 /* source mac mask must not be set */ 1128 if (!is_zero_ether_addr(eth_mask->h_source)) 1129 return -EINVAL; 1130 1131 /* dest mac mask must be ff:ff:ff:ff:ff:ff */ 1132 if (!is_broadcast_ether_addr(eth_mask->h_dest)) 1133 return -EINVAL; 1134 1135 if (!all_zeros_or_all_ones(eth_mask->h_proto)) 1136 return -EINVAL; 1137 break; 1138 default: 1139 return -EINVAL; 1140 } 1141 1142 if ((cmd->fs.flow_type & FLOW_EXT)) { 1143 if (cmd->fs.m_ext.vlan_etype || 1144 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == 1145 0 || 1146 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == 1147 cpu_to_be16(VLAN_VID_MASK))) 1148 return -EINVAL; 1149 1150 if (cmd->fs.m_ext.vlan_tci) { 1151 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID) 1152 return -EINVAL; 1153 1154 } 1155 } 1156 1157 return 0; 1158 } 1159 1160 static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd, 1161 struct list_head *rule_list_h, 1162 struct mlx4_spec_list *spec_l2, 1163 unsigned char *mac) 1164 { 1165 int err = 0; 1166 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16); 1167 1168 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH; 1169 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN); 1170 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN); 1171 1172 if ((cmd->fs.flow_type & FLOW_EXT) && 1173 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) { 1174 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci; 1175 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK); 1176 } 1177 1178 list_add_tail(&spec_l2->list, rule_list_h); 1179 1180 return err; 1181 } 1182 1183 static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv, 1184 struct ethtool_rxnfc *cmd, 1185 struct list_head *rule_list_h, 1186 struct mlx4_spec_list *spec_l2, 1187 __be32 ipv4_dst) 1188 { 1189 #ifdef CONFIG_INET 1190 unsigned char mac[ETH_ALEN]; 1191 1192 if (!ipv4_is_multicast(ipv4_dst)) { 1193 if (cmd->fs.flow_type & FLOW_MAC_EXT) 1194 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN); 1195 else 1196 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN); 1197 } else { 1198 ip_eth_mc_map(ipv4_dst, mac); 1199 } 1200 1201 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]); 1202 #else 1203 return -EINVAL; 1204 #endif 1205 } 1206 1207 static int add_ip_rule(struct mlx4_en_priv *priv, 1208 struct ethtool_rxnfc *cmd, 1209 struct list_head *list_h) 1210 { 1211 int err; 1212 struct mlx4_spec_list *spec_l2 = NULL; 1213 struct mlx4_spec_list *spec_l3 = NULL; 1214 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec; 1215 1216 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); 1217 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1218 if (!spec_l2 || !spec_l3) { 1219 err = -ENOMEM; 1220 goto free_spec; 1221 } 1222 1223 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2, 1224 cmd->fs.h_u. 1225 usr_ip4_spec.ip4dst); 1226 if (err) 1227 goto free_spec; 1228 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; 1229 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src; 1230 if (l3_mask->ip4src) 1231 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; 1232 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst; 1233 if (l3_mask->ip4dst) 1234 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; 1235 list_add_tail(&spec_l3->list, list_h); 1236 1237 return 0; 1238 1239 free_spec: 1240 kfree(spec_l2); 1241 kfree(spec_l3); 1242 return err; 1243 } 1244 1245 static int add_tcp_udp_rule(struct mlx4_en_priv *priv, 1246 struct ethtool_rxnfc *cmd, 1247 struct list_head *list_h, int proto) 1248 { 1249 int err; 1250 struct mlx4_spec_list *spec_l2 = NULL; 1251 struct mlx4_spec_list *spec_l3 = NULL; 1252 struct mlx4_spec_list *spec_l4 = NULL; 1253 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec; 1254 1255 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1256 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); 1257 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL); 1258 if (!spec_l2 || !spec_l3 || !spec_l4) { 1259 err = -ENOMEM; 1260 goto free_spec; 1261 } 1262 1263 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; 1264 1265 if (proto == TCP_V4_FLOW) { 1266 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, 1267 spec_l2, 1268 cmd->fs.h_u. 1269 tcp_ip4_spec.ip4dst); 1270 if (err) 1271 goto free_spec; 1272 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP; 1273 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src; 1274 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst; 1275 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc; 1276 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst; 1277 } else { 1278 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, 1279 spec_l2, 1280 cmd->fs.h_u. 1281 udp_ip4_spec.ip4dst); 1282 if (err) 1283 goto free_spec; 1284 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP; 1285 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src; 1286 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst; 1287 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc; 1288 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst; 1289 } 1290 1291 if (l4_mask->ip4src) 1292 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; 1293 if (l4_mask->ip4dst) 1294 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; 1295 1296 if (l4_mask->psrc) 1297 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK; 1298 if (l4_mask->pdst) 1299 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK; 1300 1301 list_add_tail(&spec_l3->list, list_h); 1302 list_add_tail(&spec_l4->list, list_h); 1303 1304 return 0; 1305 1306 free_spec: 1307 kfree(spec_l2); 1308 kfree(spec_l3); 1309 kfree(spec_l4); 1310 return err; 1311 } 1312 1313 static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev, 1314 struct ethtool_rxnfc *cmd, 1315 struct list_head *rule_list_h) 1316 { 1317 int err; 1318 struct ethhdr *eth_spec; 1319 struct mlx4_spec_list *spec_l2; 1320 struct mlx4_en_priv *priv = netdev_priv(dev); 1321 1322 err = mlx4_en_validate_flow(dev, cmd); 1323 if (err) 1324 return err; 1325 1326 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1327 case ETHER_FLOW: 1328 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1329 if (!spec_l2) 1330 return -ENOMEM; 1331 1332 eth_spec = &cmd->fs.h_u.ether_spec; 1333 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, 1334 ð_spec->h_dest[0]); 1335 spec_l2->eth.ether_type = eth_spec->h_proto; 1336 if (eth_spec->h_proto) 1337 spec_l2->eth.ether_type_enable = 1; 1338 break; 1339 case IP_USER_FLOW: 1340 err = add_ip_rule(priv, cmd, rule_list_h); 1341 break; 1342 case TCP_V4_FLOW: 1343 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW); 1344 break; 1345 case UDP_V4_FLOW: 1346 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW); 1347 break; 1348 } 1349 1350 return err; 1351 } 1352 1353 static int mlx4_en_flow_replace(struct net_device *dev, 1354 struct ethtool_rxnfc *cmd) 1355 { 1356 int err; 1357 struct mlx4_en_priv *priv = netdev_priv(dev); 1358 struct ethtool_flow_id *loc_rule; 1359 struct mlx4_spec_list *spec, *tmp_spec; 1360 u32 qpn; 1361 u64 reg_id; 1362 1363 struct mlx4_net_trans_rule rule = { 1364 .queue_mode = MLX4_NET_TRANS_Q_FIFO, 1365 .exclusive = 0, 1366 .allow_loopback = 1, 1367 .promisc_mode = MLX4_FS_REGULAR, 1368 }; 1369 1370 rule.port = priv->port; 1371 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location; 1372 INIT_LIST_HEAD(&rule.list); 1373 1374 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */ 1375 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC) 1376 qpn = priv->drop_qp.qpn; 1377 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) { 1378 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1); 1379 } else { 1380 if (cmd->fs.ring_cookie >= priv->rx_ring_num) { 1381 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n", 1382 cmd->fs.ring_cookie); 1383 return -EINVAL; 1384 } 1385 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn; 1386 if (!qpn) { 1387 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n", 1388 cmd->fs.ring_cookie); 1389 return -EINVAL; 1390 } 1391 } 1392 rule.qpn = qpn; 1393 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list); 1394 if (err) 1395 goto out_free_list; 1396 1397 loc_rule = &priv->ethtool_rules[cmd->fs.location]; 1398 if (loc_rule->id) { 1399 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id); 1400 if (err) { 1401 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n", 1402 cmd->fs.location, loc_rule->id); 1403 goto out_free_list; 1404 } 1405 loc_rule->id = 0; 1406 memset(&loc_rule->flow_spec, 0, 1407 sizeof(struct ethtool_rx_flow_spec)); 1408 list_del(&loc_rule->list); 1409 } 1410 err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id); 1411 if (err) { 1412 en_err(priv, "Fail to attach network rule at location %d\n", 1413 cmd->fs.location); 1414 goto out_free_list; 1415 } 1416 loc_rule->id = reg_id; 1417 memcpy(&loc_rule->flow_spec, &cmd->fs, 1418 sizeof(struct ethtool_rx_flow_spec)); 1419 list_add_tail(&loc_rule->list, &priv->ethtool_list); 1420 1421 out_free_list: 1422 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) { 1423 list_del(&spec->list); 1424 kfree(spec); 1425 } 1426 return err; 1427 } 1428 1429 static int mlx4_en_flow_detach(struct net_device *dev, 1430 struct ethtool_rxnfc *cmd) 1431 { 1432 int err = 0; 1433 struct ethtool_flow_id *rule; 1434 struct mlx4_en_priv *priv = netdev_priv(dev); 1435 1436 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1437 return -EINVAL; 1438 1439 rule = &priv->ethtool_rules[cmd->fs.location]; 1440 if (!rule->id) { 1441 err = -ENOENT; 1442 goto out; 1443 } 1444 1445 err = mlx4_flow_detach(priv->mdev->dev, rule->id); 1446 if (err) { 1447 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n", 1448 cmd->fs.location, rule->id); 1449 goto out; 1450 } 1451 rule->id = 0; 1452 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec)); 1453 list_del(&rule->list); 1454 out: 1455 return err; 1456 1457 } 1458 1459 static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1460 int loc) 1461 { 1462 int err = 0; 1463 struct ethtool_flow_id *rule; 1464 struct mlx4_en_priv *priv = netdev_priv(dev); 1465 1466 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1467 return -EINVAL; 1468 1469 rule = &priv->ethtool_rules[loc]; 1470 if (rule->id) 1471 memcpy(&cmd->fs, &rule->flow_spec, 1472 sizeof(struct ethtool_rx_flow_spec)); 1473 else 1474 err = -ENOENT; 1475 1476 return err; 1477 } 1478 1479 static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv) 1480 { 1481 1482 int i, res = 0; 1483 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 1484 if (priv->ethtool_rules[i].id) 1485 res++; 1486 } 1487 return res; 1488 1489 } 1490 1491 static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1492 u32 *rule_locs) 1493 { 1494 struct mlx4_en_priv *priv = netdev_priv(dev); 1495 struct mlx4_en_dev *mdev = priv->mdev; 1496 int err = 0; 1497 int i = 0, priority = 0; 1498 1499 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT || 1500 cmd->cmd == ETHTOOL_GRXCLSRULE || 1501 cmd->cmd == ETHTOOL_GRXCLSRLALL) && 1502 (mdev->dev->caps.steering_mode != 1503 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)) 1504 return -EINVAL; 1505 1506 switch (cmd->cmd) { 1507 case ETHTOOL_GRXRINGS: 1508 cmd->data = priv->rx_ring_num; 1509 break; 1510 case ETHTOOL_GRXCLSRLCNT: 1511 cmd->rule_cnt = mlx4_en_get_num_flows(priv); 1512 break; 1513 case ETHTOOL_GRXCLSRULE: 1514 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location); 1515 break; 1516 case ETHTOOL_GRXCLSRLALL: 1517 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) { 1518 err = mlx4_en_get_flow(dev, cmd, i); 1519 if (!err) 1520 rule_locs[priority++] = i; 1521 i++; 1522 } 1523 err = 0; 1524 break; 1525 default: 1526 err = -EOPNOTSUPP; 1527 break; 1528 } 1529 1530 return err; 1531 } 1532 1533 static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1534 { 1535 int err = 0; 1536 struct mlx4_en_priv *priv = netdev_priv(dev); 1537 struct mlx4_en_dev *mdev = priv->mdev; 1538 1539 if (mdev->dev->caps.steering_mode != 1540 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up) 1541 return -EINVAL; 1542 1543 switch (cmd->cmd) { 1544 case ETHTOOL_SRXCLSRLINS: 1545 err = mlx4_en_flow_replace(dev, cmd); 1546 break; 1547 case ETHTOOL_SRXCLSRLDEL: 1548 err = mlx4_en_flow_detach(dev, cmd); 1549 break; 1550 default: 1551 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd); 1552 return -EINVAL; 1553 } 1554 1555 return err; 1556 } 1557 1558 static void mlx4_en_get_channels(struct net_device *dev, 1559 struct ethtool_channels *channel) 1560 { 1561 struct mlx4_en_priv *priv = netdev_priv(dev); 1562 1563 memset(channel, 0, sizeof(*channel)); 1564 1565 channel->max_rx = MAX_RX_RINGS; 1566 channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP; 1567 1568 channel->rx_count = priv->rx_ring_num; 1569 channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP; 1570 } 1571 1572 static int mlx4_en_set_channels(struct net_device *dev, 1573 struct ethtool_channels *channel) 1574 { 1575 struct mlx4_en_priv *priv = netdev_priv(dev); 1576 struct mlx4_en_dev *mdev = priv->mdev; 1577 int port_up = 0; 1578 int err = 0; 1579 1580 if (channel->other_count || channel->combined_count || 1581 channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP || 1582 channel->rx_count > MAX_RX_RINGS || 1583 !channel->tx_count || !channel->rx_count) 1584 return -EINVAL; 1585 1586 mutex_lock(&mdev->state_lock); 1587 if (priv->port_up) { 1588 port_up = 1; 1589 mlx4_en_stop_port(dev, 1); 1590 } 1591 1592 mlx4_en_free_resources(priv); 1593 1594 priv->num_tx_rings_p_up = channel->tx_count; 1595 priv->tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP; 1596 priv->rx_ring_num = channel->rx_count; 1597 1598 err = mlx4_en_alloc_resources(priv); 1599 if (err) { 1600 en_err(priv, "Failed reallocating port resources\n"); 1601 goto out; 1602 } 1603 1604 netif_set_real_num_tx_queues(dev, priv->tx_ring_num); 1605 netif_set_real_num_rx_queues(dev, priv->rx_ring_num); 1606 1607 if (dev->num_tc) 1608 mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP); 1609 1610 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num); 1611 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num); 1612 1613 if (port_up) { 1614 err = mlx4_en_start_port(dev); 1615 if (err) 1616 en_err(priv, "Failed starting port\n"); 1617 } 1618 1619 err = mlx4_en_moderation_update(priv); 1620 1621 out: 1622 mutex_unlock(&mdev->state_lock); 1623 return err; 1624 } 1625 1626 static int mlx4_en_get_ts_info(struct net_device *dev, 1627 struct ethtool_ts_info *info) 1628 { 1629 struct mlx4_en_priv *priv = netdev_priv(dev); 1630 struct mlx4_en_dev *mdev = priv->mdev; 1631 int ret; 1632 1633 ret = ethtool_op_get_ts_info(dev, info); 1634 if (ret) 1635 return ret; 1636 1637 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 1638 info->so_timestamping |= 1639 SOF_TIMESTAMPING_TX_HARDWARE | 1640 SOF_TIMESTAMPING_RX_HARDWARE | 1641 SOF_TIMESTAMPING_RAW_HARDWARE; 1642 1643 info->tx_types = 1644 (1 << HWTSTAMP_TX_OFF) | 1645 (1 << HWTSTAMP_TX_ON); 1646 1647 info->rx_filters = 1648 (1 << HWTSTAMP_FILTER_NONE) | 1649 (1 << HWTSTAMP_FILTER_ALL); 1650 1651 if (mdev->ptp_clock) 1652 info->phc_index = ptp_clock_index(mdev->ptp_clock); 1653 } 1654 1655 return ret; 1656 } 1657 1658 static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags) 1659 { 1660 struct mlx4_en_priv *priv = netdev_priv(dev); 1661 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); 1662 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); 1663 int i; 1664 1665 if (bf_enabled_new == bf_enabled_old) 1666 return 0; /* Nothing to do */ 1667 1668 if (bf_enabled_new) { 1669 bool bf_supported = true; 1670 1671 for (i = 0; i < priv->tx_ring_num; i++) 1672 bf_supported &= priv->tx_ring[i]->bf_alloced; 1673 1674 if (!bf_supported) { 1675 en_err(priv, "BlueFlame is not supported\n"); 1676 return -EINVAL; 1677 } 1678 1679 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME; 1680 } else { 1681 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 1682 } 1683 1684 for (i = 0; i < priv->tx_ring_num; i++) 1685 priv->tx_ring[i]->bf_enabled = bf_enabled_new; 1686 1687 en_info(priv, "BlueFlame %s\n", 1688 bf_enabled_new ? "Enabled" : "Disabled"); 1689 1690 return 0; 1691 } 1692 1693 static u32 mlx4_en_get_priv_flags(struct net_device *dev) 1694 { 1695 struct mlx4_en_priv *priv = netdev_priv(dev); 1696 1697 return priv->pflags; 1698 } 1699 1700 static int mlx4_en_get_tunable(struct net_device *dev, 1701 const struct ethtool_tunable *tuna, 1702 void *data) 1703 { 1704 const struct mlx4_en_priv *priv = netdev_priv(dev); 1705 int ret = 0; 1706 1707 switch (tuna->id) { 1708 case ETHTOOL_TX_COPYBREAK: 1709 *(u32 *)data = priv->prof->inline_thold; 1710 break; 1711 default: 1712 ret = -EINVAL; 1713 break; 1714 } 1715 1716 return ret; 1717 } 1718 1719 static int mlx4_en_set_tunable(struct net_device *dev, 1720 const struct ethtool_tunable *tuna, 1721 const void *data) 1722 { 1723 struct mlx4_en_priv *priv = netdev_priv(dev); 1724 int val, ret = 0; 1725 1726 switch (tuna->id) { 1727 case ETHTOOL_TX_COPYBREAK: 1728 val = *(u32 *)data; 1729 if (val < MIN_PKT_LEN || val > MAX_INLINE) 1730 ret = -EINVAL; 1731 else 1732 priv->prof->inline_thold = val; 1733 break; 1734 default: 1735 ret = -EINVAL; 1736 break; 1737 } 1738 1739 return ret; 1740 } 1741 1742 static int mlx4_en_get_module_info(struct net_device *dev, 1743 struct ethtool_modinfo *modinfo) 1744 { 1745 struct mlx4_en_priv *priv = netdev_priv(dev); 1746 struct mlx4_en_dev *mdev = priv->mdev; 1747 int ret; 1748 u8 data[4]; 1749 1750 /* Read first 2 bytes to get Module & REV ID */ 1751 ret = mlx4_get_module_info(mdev->dev, priv->port, 1752 0/*offset*/, 2/*size*/, data); 1753 if (ret < 2) 1754 return -EIO; 1755 1756 switch (data[0] /* identifier */) { 1757 case MLX4_MODULE_ID_QSFP: 1758 modinfo->type = ETH_MODULE_SFF_8436; 1759 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 1760 break; 1761 case MLX4_MODULE_ID_QSFP_PLUS: 1762 if (data[1] >= 0x3) { /* revision id */ 1763 modinfo->type = ETH_MODULE_SFF_8636; 1764 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 1765 } else { 1766 modinfo->type = ETH_MODULE_SFF_8436; 1767 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 1768 } 1769 break; 1770 case MLX4_MODULE_ID_QSFP28: 1771 modinfo->type = ETH_MODULE_SFF_8636; 1772 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 1773 break; 1774 case MLX4_MODULE_ID_SFP: 1775 modinfo->type = ETH_MODULE_SFF_8472; 1776 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1777 break; 1778 default: 1779 return -ENOSYS; 1780 } 1781 1782 return 0; 1783 } 1784 1785 static int mlx4_en_get_module_eeprom(struct net_device *dev, 1786 struct ethtool_eeprom *ee, 1787 u8 *data) 1788 { 1789 struct mlx4_en_priv *priv = netdev_priv(dev); 1790 struct mlx4_en_dev *mdev = priv->mdev; 1791 int offset = ee->offset; 1792 int i = 0, ret; 1793 1794 if (ee->len == 0) 1795 return -EINVAL; 1796 1797 memset(data, 0, ee->len); 1798 1799 while (i < ee->len) { 1800 en_dbg(DRV, priv, 1801 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n", 1802 i, offset, ee->len - i); 1803 1804 ret = mlx4_get_module_info(mdev->dev, priv->port, 1805 offset, ee->len - i, data + i); 1806 1807 if (!ret) /* Done reading */ 1808 return 0; 1809 1810 if (ret < 0) { 1811 en_err(priv, 1812 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n", 1813 i, offset, ee->len - i, ret); 1814 return 0; 1815 } 1816 1817 i += ret; 1818 offset += ret; 1819 } 1820 return 0; 1821 } 1822 1823 const struct ethtool_ops mlx4_en_ethtool_ops = { 1824 .get_drvinfo = mlx4_en_get_drvinfo, 1825 .get_settings = mlx4_en_get_settings, 1826 .set_settings = mlx4_en_set_settings, 1827 .get_link = ethtool_op_get_link, 1828 .get_strings = mlx4_en_get_strings, 1829 .get_sset_count = mlx4_en_get_sset_count, 1830 .get_ethtool_stats = mlx4_en_get_ethtool_stats, 1831 .self_test = mlx4_en_self_test, 1832 .get_wol = mlx4_en_get_wol, 1833 .set_wol = mlx4_en_set_wol, 1834 .get_msglevel = mlx4_en_get_msglevel, 1835 .set_msglevel = mlx4_en_set_msglevel, 1836 .get_coalesce = mlx4_en_get_coalesce, 1837 .set_coalesce = mlx4_en_set_coalesce, 1838 .get_pauseparam = mlx4_en_get_pauseparam, 1839 .set_pauseparam = mlx4_en_set_pauseparam, 1840 .get_ringparam = mlx4_en_get_ringparam, 1841 .set_ringparam = mlx4_en_set_ringparam, 1842 .get_rxnfc = mlx4_en_get_rxnfc, 1843 .set_rxnfc = mlx4_en_set_rxnfc, 1844 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size, 1845 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size, 1846 .get_rxfh = mlx4_en_get_rxfh, 1847 .set_rxfh = mlx4_en_set_rxfh, 1848 .get_channels = mlx4_en_get_channels, 1849 .set_channels = mlx4_en_set_channels, 1850 .get_ts_info = mlx4_en_get_ts_info, 1851 .set_priv_flags = mlx4_en_set_priv_flags, 1852 .get_priv_flags = mlx4_en_get_priv_flags, 1853 .get_tunable = mlx4_en_get_tunable, 1854 .set_tunable = mlx4_en_set_tunable, 1855 .get_module_info = mlx4_en_get_module_info, 1856 .get_module_eeprom = mlx4_en_get_module_eeprom 1857 }; 1858 1859 1860 1861 1862 1863