1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <linux/kernel.h> 35 #include <linux/ethtool.h> 36 #include <linux/netdevice.h> 37 #include <linux/mlx4/driver.h> 38 #include <linux/mlx4/device.h> 39 #include <linux/in.h> 40 #include <net/ip.h> 41 #include <linux/bitmap.h> 42 43 #include "mlx4_en.h" 44 #include "en_port.h" 45 46 #define EN_ETHTOOL_QP_ATTACH (1ull << 63) 47 #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff) 48 #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff) 49 50 static int mlx4_en_moderation_update(struct mlx4_en_priv *priv) 51 { 52 int i; 53 int err = 0; 54 55 for (i = 0; i < priv->tx_ring_num; i++) { 56 priv->tx_cq[i]->moder_cnt = priv->tx_frames; 57 priv->tx_cq[i]->moder_time = priv->tx_usecs; 58 if (priv->port_up) { 59 err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]); 60 if (err) 61 return err; 62 } 63 } 64 65 if (priv->adaptive_rx_coal) 66 return 0; 67 68 for (i = 0; i < priv->rx_ring_num; i++) { 69 priv->rx_cq[i]->moder_cnt = priv->rx_frames; 70 priv->rx_cq[i]->moder_time = priv->rx_usecs; 71 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; 72 if (priv->port_up) { 73 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]); 74 if (err) 75 return err; 76 } 77 } 78 79 return err; 80 } 81 82 static void 83 mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) 84 { 85 struct mlx4_en_priv *priv = netdev_priv(dev); 86 struct mlx4_en_dev *mdev = priv->mdev; 87 88 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); 89 strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")", 90 sizeof(drvinfo->version)); 91 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 92 "%d.%d.%d", 93 (u16) (mdev->dev->caps.fw_ver >> 32), 94 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff), 95 (u16) (mdev->dev->caps.fw_ver & 0xffff)); 96 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev), 97 sizeof(drvinfo->bus_info)); 98 } 99 100 static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = { 101 "blueflame", 102 "phv-bit" 103 }; 104 105 static const char main_strings[][ETH_GSTRING_LEN] = { 106 /* main statistics */ 107 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", 108 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", 109 "rx_length_errors", "rx_over_errors", "rx_crc_errors", 110 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", 111 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", 112 "tx_heartbeat_errors", "tx_window_errors", 113 114 /* port statistics */ 115 "tso_packets", 116 "xmit_more", 117 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed", 118 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload", 119 120 /* pf statistics */ 121 "pf_rx_packets", 122 "pf_rx_bytes", 123 "pf_tx_packets", 124 "pf_tx_bytes", 125 126 /* priority flow control statistics rx */ 127 "rx_pause_prio_0", "rx_pause_duration_prio_0", 128 "rx_pause_transition_prio_0", 129 "rx_pause_prio_1", "rx_pause_duration_prio_1", 130 "rx_pause_transition_prio_1", 131 "rx_pause_prio_2", "rx_pause_duration_prio_2", 132 "rx_pause_transition_prio_2", 133 "rx_pause_prio_3", "rx_pause_duration_prio_3", 134 "rx_pause_transition_prio_3", 135 "rx_pause_prio_4", "rx_pause_duration_prio_4", 136 "rx_pause_transition_prio_4", 137 "rx_pause_prio_5", "rx_pause_duration_prio_5", 138 "rx_pause_transition_prio_5", 139 "rx_pause_prio_6", "rx_pause_duration_prio_6", 140 "rx_pause_transition_prio_6", 141 "rx_pause_prio_7", "rx_pause_duration_prio_7", 142 "rx_pause_transition_prio_7", 143 144 /* flow control statistics rx */ 145 "rx_pause", "rx_pause_duration", "rx_pause_transition", 146 147 /* priority flow control statistics tx */ 148 "tx_pause_prio_0", "tx_pause_duration_prio_0", 149 "tx_pause_transition_prio_0", 150 "tx_pause_prio_1", "tx_pause_duration_prio_1", 151 "tx_pause_transition_prio_1", 152 "tx_pause_prio_2", "tx_pause_duration_prio_2", 153 "tx_pause_transition_prio_2", 154 "tx_pause_prio_3", "tx_pause_duration_prio_3", 155 "tx_pause_transition_prio_3", 156 "tx_pause_prio_4", "tx_pause_duration_prio_4", 157 "tx_pause_transition_prio_4", 158 "tx_pause_prio_5", "tx_pause_duration_prio_5", 159 "tx_pause_transition_prio_5", 160 "tx_pause_prio_6", "tx_pause_duration_prio_6", 161 "tx_pause_transition_prio_6", 162 "tx_pause_prio_7", "tx_pause_duration_prio_7", 163 "tx_pause_transition_prio_7", 164 165 /* flow control statistics tx */ 166 "tx_pause", "tx_pause_duration", "tx_pause_transition", 167 168 /* packet statistics */ 169 "rx_multicast_packets", 170 "rx_broadcast_packets", 171 "rx_jabbers", 172 "rx_in_range_length_error", 173 "rx_out_range_length_error", 174 "tx_multicast_packets", 175 "tx_broadcast_packets", 176 "rx_prio_0_packets", "rx_prio_0_bytes", 177 "rx_prio_1_packets", "rx_prio_1_bytes", 178 "rx_prio_2_packets", "rx_prio_2_bytes", 179 "rx_prio_3_packets", "rx_prio_3_bytes", 180 "rx_prio_4_packets", "rx_prio_4_bytes", 181 "rx_prio_5_packets", "rx_prio_5_bytes", 182 "rx_prio_6_packets", "rx_prio_6_bytes", 183 "rx_prio_7_packets", "rx_prio_7_bytes", 184 "rx_novlan_packets", "rx_novlan_bytes", 185 "tx_prio_0_packets", "tx_prio_0_bytes", 186 "tx_prio_1_packets", "tx_prio_1_bytes", 187 "tx_prio_2_packets", "tx_prio_2_bytes", 188 "tx_prio_3_packets", "tx_prio_3_bytes", 189 "tx_prio_4_packets", "tx_prio_4_bytes", 190 "tx_prio_5_packets", "tx_prio_5_bytes", 191 "tx_prio_6_packets", "tx_prio_6_bytes", 192 "tx_prio_7_packets", "tx_prio_7_bytes", 193 "tx_novlan_packets", "tx_novlan_bytes", 194 195 }; 196 197 static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= { 198 "Interrupt Test", 199 "Link Test", 200 "Speed Test", 201 "Register Test", 202 "Loopback Test", 203 }; 204 205 static u32 mlx4_en_get_msglevel(struct net_device *dev) 206 { 207 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable; 208 } 209 210 static void mlx4_en_set_msglevel(struct net_device *dev, u32 val) 211 { 212 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val; 213 } 214 215 static void mlx4_en_get_wol(struct net_device *netdev, 216 struct ethtool_wolinfo *wol) 217 { 218 struct mlx4_en_priv *priv = netdev_priv(netdev); 219 int err = 0; 220 u64 config = 0; 221 u64 mask; 222 223 if ((priv->port < 1) || (priv->port > 2)) { 224 en_err(priv, "Failed to get WoL information\n"); 225 return; 226 } 227 228 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : 229 MLX4_DEV_CAP_FLAG_WOL_PORT2; 230 231 if (!(priv->mdev->dev->caps.flags & mask)) { 232 wol->supported = 0; 233 wol->wolopts = 0; 234 return; 235 } 236 237 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); 238 if (err) { 239 en_err(priv, "Failed to get WoL information\n"); 240 return; 241 } 242 243 if (config & MLX4_EN_WOL_MAGIC) 244 wol->supported = WAKE_MAGIC; 245 else 246 wol->supported = 0; 247 248 if (config & MLX4_EN_WOL_ENABLED) 249 wol->wolopts = WAKE_MAGIC; 250 else 251 wol->wolopts = 0; 252 } 253 254 static int mlx4_en_set_wol(struct net_device *netdev, 255 struct ethtool_wolinfo *wol) 256 { 257 struct mlx4_en_priv *priv = netdev_priv(netdev); 258 u64 config = 0; 259 int err = 0; 260 u64 mask; 261 262 if ((priv->port < 1) || (priv->port > 2)) 263 return -EOPNOTSUPP; 264 265 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : 266 MLX4_DEV_CAP_FLAG_WOL_PORT2; 267 268 if (!(priv->mdev->dev->caps.flags & mask)) 269 return -EOPNOTSUPP; 270 271 if (wol->supported & ~WAKE_MAGIC) 272 return -EINVAL; 273 274 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); 275 if (err) { 276 en_err(priv, "Failed to get WoL info, unable to modify\n"); 277 return err; 278 } 279 280 if (wol->wolopts & WAKE_MAGIC) { 281 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED | 282 MLX4_EN_WOL_MAGIC; 283 } else { 284 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC); 285 config |= MLX4_EN_WOL_DO_MODIFY; 286 } 287 288 err = mlx4_wol_write(priv->mdev->dev, config, priv->port); 289 if (err) 290 en_err(priv, "Failed to set WoL information\n"); 291 292 return err; 293 } 294 295 struct bitmap_iterator { 296 unsigned long *stats_bitmap; 297 unsigned int count; 298 unsigned int iterator; 299 bool advance_array; /* if set, force no increments */ 300 }; 301 302 static inline void bitmap_iterator_init(struct bitmap_iterator *h, 303 unsigned long *stats_bitmap, 304 int count) 305 { 306 h->iterator = 0; 307 h->advance_array = !bitmap_empty(stats_bitmap, count); 308 h->count = h->advance_array ? bitmap_weight(stats_bitmap, count) 309 : count; 310 h->stats_bitmap = stats_bitmap; 311 } 312 313 static inline int bitmap_iterator_test(struct bitmap_iterator *h) 314 { 315 return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap); 316 } 317 318 static inline int bitmap_iterator_inc(struct bitmap_iterator *h) 319 { 320 return h->iterator++; 321 } 322 323 static inline unsigned int 324 bitmap_iterator_count(struct bitmap_iterator *h) 325 { 326 return h->count; 327 } 328 329 static int mlx4_en_get_sset_count(struct net_device *dev, int sset) 330 { 331 struct mlx4_en_priv *priv = netdev_priv(dev); 332 struct bitmap_iterator it; 333 334 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 335 336 switch (sset) { 337 case ETH_SS_STATS: 338 return bitmap_iterator_count(&it) + 339 (priv->tx_ring_num * 2) + 340 (priv->rx_ring_num * 2); 341 case ETH_SS_TEST: 342 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags 343 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2; 344 case ETH_SS_PRIV_FLAGS: 345 return ARRAY_SIZE(mlx4_en_priv_flags); 346 default: 347 return -EOPNOTSUPP; 348 } 349 } 350 351 static void mlx4_en_get_ethtool_stats(struct net_device *dev, 352 struct ethtool_stats *stats, uint64_t *data) 353 { 354 struct mlx4_en_priv *priv = netdev_priv(dev); 355 int index = 0; 356 int i; 357 struct bitmap_iterator it; 358 359 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 360 361 spin_lock_bh(&priv->stats_lock); 362 363 for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it)) 364 if (bitmap_iterator_test(&it)) 365 data[index++] = ((unsigned long *)&priv->stats)[i]; 366 367 for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it)) 368 if (bitmap_iterator_test(&it)) 369 data[index++] = ((unsigned long *)&priv->port_stats)[i]; 370 371 for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it)) 372 if (bitmap_iterator_test(&it)) 373 data[index++] = 374 ((unsigned long *)&priv->pf_stats)[i]; 375 376 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX; 377 i++, bitmap_iterator_inc(&it)) 378 if (bitmap_iterator_test(&it)) 379 data[index++] = 380 ((u64 *)&priv->rx_priority_flowstats)[i]; 381 382 for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it)) 383 if (bitmap_iterator_test(&it)) 384 data[index++] = ((u64 *)&priv->rx_flowstats)[i]; 385 386 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX; 387 i++, bitmap_iterator_inc(&it)) 388 if (bitmap_iterator_test(&it)) 389 data[index++] = 390 ((u64 *)&priv->tx_priority_flowstats)[i]; 391 392 for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it)) 393 if (bitmap_iterator_test(&it)) 394 data[index++] = ((u64 *)&priv->tx_flowstats)[i]; 395 396 for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it)) 397 if (bitmap_iterator_test(&it)) 398 data[index++] = ((unsigned long *)&priv->pkstats)[i]; 399 400 for (i = 0; i < priv->tx_ring_num; i++) { 401 data[index++] = priv->tx_ring[i]->packets; 402 data[index++] = priv->tx_ring[i]->bytes; 403 } 404 for (i = 0; i < priv->rx_ring_num; i++) { 405 data[index++] = priv->rx_ring[i]->packets; 406 data[index++] = priv->rx_ring[i]->bytes; 407 } 408 spin_unlock_bh(&priv->stats_lock); 409 410 } 411 412 static void mlx4_en_self_test(struct net_device *dev, 413 struct ethtool_test *etest, u64 *buf) 414 { 415 mlx4_en_ex_selftest(dev, &etest->flags, buf); 416 } 417 418 static void mlx4_en_get_strings(struct net_device *dev, 419 uint32_t stringset, uint8_t *data) 420 { 421 struct mlx4_en_priv *priv = netdev_priv(dev); 422 int index = 0; 423 int i, strings = 0; 424 struct bitmap_iterator it; 425 426 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); 427 428 switch (stringset) { 429 case ETH_SS_TEST: 430 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++) 431 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); 432 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) 433 for (; i < MLX4_EN_NUM_SELF_TEST; i++) 434 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); 435 break; 436 437 case ETH_SS_STATS: 438 /* Add main counters */ 439 for (i = 0; i < NUM_MAIN_STATS; i++, strings++, 440 bitmap_iterator_inc(&it)) 441 if (bitmap_iterator_test(&it)) 442 strcpy(data + (index++) * ETH_GSTRING_LEN, 443 main_strings[strings]); 444 445 for (i = 0; i < NUM_PORT_STATS; i++, strings++, 446 bitmap_iterator_inc(&it)) 447 if (bitmap_iterator_test(&it)) 448 strcpy(data + (index++) * ETH_GSTRING_LEN, 449 main_strings[strings]); 450 451 for (i = 0; i < NUM_PF_STATS; i++, strings++, 452 bitmap_iterator_inc(&it)) 453 if (bitmap_iterator_test(&it)) 454 strcpy(data + (index++) * ETH_GSTRING_LEN, 455 main_strings[strings]); 456 457 for (i = 0; i < NUM_FLOW_STATS; i++, strings++, 458 bitmap_iterator_inc(&it)) 459 if (bitmap_iterator_test(&it)) 460 strcpy(data + (index++) * ETH_GSTRING_LEN, 461 main_strings[strings]); 462 463 for (i = 0; i < NUM_PKT_STATS; i++, strings++, 464 bitmap_iterator_inc(&it)) 465 if (bitmap_iterator_test(&it)) 466 strcpy(data + (index++) * ETH_GSTRING_LEN, 467 main_strings[strings]); 468 469 for (i = 0; i < priv->tx_ring_num; i++) { 470 sprintf(data + (index++) * ETH_GSTRING_LEN, 471 "tx%d_packets", i); 472 sprintf(data + (index++) * ETH_GSTRING_LEN, 473 "tx%d_bytes", i); 474 } 475 for (i = 0; i < priv->rx_ring_num; i++) { 476 sprintf(data + (index++) * ETH_GSTRING_LEN, 477 "rx%d_packets", i); 478 sprintf(data + (index++) * ETH_GSTRING_LEN, 479 "rx%d_bytes", i); 480 } 481 break; 482 case ETH_SS_PRIV_FLAGS: 483 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++) 484 strcpy(data + i * ETH_GSTRING_LEN, 485 mlx4_en_priv_flags[i]); 486 break; 487 488 } 489 } 490 491 static u32 mlx4_en_autoneg_get(struct net_device *dev) 492 { 493 struct mlx4_en_priv *priv = netdev_priv(dev); 494 struct mlx4_en_dev *mdev = priv->mdev; 495 u32 autoneg = AUTONEG_DISABLE; 496 497 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) && 498 (priv->port_state.flags & MLX4_EN_PORT_ANE)) 499 autoneg = AUTONEG_ENABLE; 500 501 return autoneg; 502 } 503 504 static u32 ptys_get_supported_port(struct mlx4_ptys_reg *ptys_reg) 505 { 506 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); 507 508 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) 509 | MLX4_PROT_MASK(MLX4_1000BASE_T) 510 | MLX4_PROT_MASK(MLX4_100BASE_TX))) { 511 return SUPPORTED_TP; 512 } 513 514 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) 515 | MLX4_PROT_MASK(MLX4_10GBASE_SR) 516 | MLX4_PROT_MASK(MLX4_56GBASE_SR4) 517 | MLX4_PROT_MASK(MLX4_40GBASE_CR4) 518 | MLX4_PROT_MASK(MLX4_40GBASE_SR4) 519 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { 520 return SUPPORTED_FIBRE; 521 } 522 523 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) 524 | MLX4_PROT_MASK(MLX4_40GBASE_KR4) 525 | MLX4_PROT_MASK(MLX4_20GBASE_KR2) 526 | MLX4_PROT_MASK(MLX4_10GBASE_KR) 527 | MLX4_PROT_MASK(MLX4_10GBASE_KX4) 528 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { 529 return SUPPORTED_Backplane; 530 } 531 return 0; 532 } 533 534 static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg) 535 { 536 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper); 537 538 if (!eth_proto) /* link down */ 539 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); 540 541 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) 542 | MLX4_PROT_MASK(MLX4_1000BASE_T) 543 | MLX4_PROT_MASK(MLX4_100BASE_TX))) { 544 return PORT_TP; 545 } 546 547 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR) 548 | MLX4_PROT_MASK(MLX4_56GBASE_SR4) 549 | MLX4_PROT_MASK(MLX4_40GBASE_SR4) 550 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { 551 return PORT_FIBRE; 552 } 553 554 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) 555 | MLX4_PROT_MASK(MLX4_56GBASE_CR4) 556 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) { 557 return PORT_DA; 558 } 559 560 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) 561 | MLX4_PROT_MASK(MLX4_40GBASE_KR4) 562 | MLX4_PROT_MASK(MLX4_20GBASE_KR2) 563 | MLX4_PROT_MASK(MLX4_10GBASE_KR) 564 | MLX4_PROT_MASK(MLX4_10GBASE_KX4) 565 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { 566 return PORT_NONE; 567 } 568 return PORT_OTHER; 569 } 570 571 #define MLX4_LINK_MODES_SZ \ 572 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8) 573 574 enum ethtool_report { 575 SUPPORTED = 0, 576 ADVERTISED = 1, 577 SPEED = 2 578 }; 579 580 /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */ 581 static u32 ptys2ethtool_map[MLX4_LINK_MODES_SZ][3] = { 582 [MLX4_100BASE_TX] = { 583 SUPPORTED_100baseT_Full, 584 ADVERTISED_100baseT_Full, 585 SPEED_100 586 }, 587 588 [MLX4_1000BASE_T] = { 589 SUPPORTED_1000baseT_Full, 590 ADVERTISED_1000baseT_Full, 591 SPEED_1000 592 }, 593 [MLX4_1000BASE_CX_SGMII] = { 594 SUPPORTED_1000baseKX_Full, 595 ADVERTISED_1000baseKX_Full, 596 SPEED_1000 597 }, 598 [MLX4_1000BASE_KX] = { 599 SUPPORTED_1000baseKX_Full, 600 ADVERTISED_1000baseKX_Full, 601 SPEED_1000 602 }, 603 604 [MLX4_10GBASE_T] = { 605 SUPPORTED_10000baseT_Full, 606 ADVERTISED_10000baseT_Full, 607 SPEED_10000 608 }, 609 [MLX4_10GBASE_CX4] = { 610 SUPPORTED_10000baseKX4_Full, 611 ADVERTISED_10000baseKX4_Full, 612 SPEED_10000 613 }, 614 [MLX4_10GBASE_KX4] = { 615 SUPPORTED_10000baseKX4_Full, 616 ADVERTISED_10000baseKX4_Full, 617 SPEED_10000 618 }, 619 [MLX4_10GBASE_KR] = { 620 SUPPORTED_10000baseKR_Full, 621 ADVERTISED_10000baseKR_Full, 622 SPEED_10000 623 }, 624 [MLX4_10GBASE_CR] = { 625 SUPPORTED_10000baseKR_Full, 626 ADVERTISED_10000baseKR_Full, 627 SPEED_10000 628 }, 629 [MLX4_10GBASE_SR] = { 630 SUPPORTED_10000baseKR_Full, 631 ADVERTISED_10000baseKR_Full, 632 SPEED_10000 633 }, 634 635 [MLX4_20GBASE_KR2] = { 636 SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full, 637 ADVERTISED_20000baseMLD2_Full | ADVERTISED_20000baseKR2_Full, 638 SPEED_20000 639 }, 640 641 [MLX4_40GBASE_CR4] = { 642 SUPPORTED_40000baseCR4_Full, 643 ADVERTISED_40000baseCR4_Full, 644 SPEED_40000 645 }, 646 [MLX4_40GBASE_KR4] = { 647 SUPPORTED_40000baseKR4_Full, 648 ADVERTISED_40000baseKR4_Full, 649 SPEED_40000 650 }, 651 [MLX4_40GBASE_SR4] = { 652 SUPPORTED_40000baseSR4_Full, 653 ADVERTISED_40000baseSR4_Full, 654 SPEED_40000 655 }, 656 657 [MLX4_56GBASE_KR4] = { 658 SUPPORTED_56000baseKR4_Full, 659 ADVERTISED_56000baseKR4_Full, 660 SPEED_56000 661 }, 662 [MLX4_56GBASE_CR4] = { 663 SUPPORTED_56000baseCR4_Full, 664 ADVERTISED_56000baseCR4_Full, 665 SPEED_56000 666 }, 667 [MLX4_56GBASE_SR4] = { 668 SUPPORTED_56000baseSR4_Full, 669 ADVERTISED_56000baseSR4_Full, 670 SPEED_56000 671 }, 672 }; 673 674 static u32 ptys2ethtool_link_modes(u32 eth_proto, enum ethtool_report report) 675 { 676 int i; 677 u32 link_modes = 0; 678 679 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 680 if (eth_proto & MLX4_PROT_MASK(i)) 681 link_modes |= ptys2ethtool_map[i][report]; 682 } 683 return link_modes; 684 } 685 686 static u32 ethtool2ptys_link_modes(u32 link_modes, enum ethtool_report report) 687 { 688 int i; 689 u32 ptys_modes = 0; 690 691 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 692 if (ptys2ethtool_map[i][report] & link_modes) 693 ptys_modes |= 1 << i; 694 } 695 return ptys_modes; 696 } 697 698 /* Convert actual speed (SPEED_XXX) to ptys link modes */ 699 static u32 speed2ptys_link_modes(u32 speed) 700 { 701 int i; 702 u32 ptys_modes = 0; 703 704 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { 705 if (ptys2ethtool_map[i][SPEED] == speed) 706 ptys_modes |= 1 << i; 707 } 708 return ptys_modes; 709 } 710 711 static int ethtool_get_ptys_settings(struct net_device *dev, 712 struct ethtool_cmd *cmd) 713 { 714 struct mlx4_en_priv *priv = netdev_priv(dev); 715 struct mlx4_ptys_reg ptys_reg; 716 u32 eth_proto; 717 int ret; 718 719 memset(&ptys_reg, 0, sizeof(ptys_reg)); 720 ptys_reg.local_port = priv->port; 721 ptys_reg.proto_mask = MLX4_PTYS_EN; 722 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, 723 MLX4_ACCESS_REG_QUERY, &ptys_reg); 724 if (ret) { 725 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)", 726 ret); 727 return ret; 728 } 729 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n", 730 ptys_reg.proto_mask); 731 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n", 732 be32_to_cpu(ptys_reg.eth_proto_cap)); 733 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n", 734 be32_to_cpu(ptys_reg.eth_proto_admin)); 735 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n", 736 be32_to_cpu(ptys_reg.eth_proto_oper)); 737 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n", 738 be32_to_cpu(ptys_reg.eth_proto_lp_adv)); 739 740 cmd->supported = 0; 741 cmd->advertising = 0; 742 743 cmd->supported |= ptys_get_supported_port(&ptys_reg); 744 745 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap); 746 cmd->supported |= ptys2ethtool_link_modes(eth_proto, SUPPORTED); 747 748 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin); 749 cmd->advertising |= ptys2ethtool_link_modes(eth_proto, ADVERTISED); 750 751 cmd->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 752 cmd->advertising |= (priv->prof->tx_pause) ? ADVERTISED_Pause : 0; 753 754 cmd->advertising |= (priv->prof->tx_pause ^ priv->prof->rx_pause) ? 755 ADVERTISED_Asym_Pause : 0; 756 757 cmd->port = ptys_get_active_port(&ptys_reg); 758 cmd->transceiver = (SUPPORTED_TP & cmd->supported) ? 759 XCVR_EXTERNAL : XCVR_INTERNAL; 760 761 if (mlx4_en_autoneg_get(dev)) { 762 cmd->supported |= SUPPORTED_Autoneg; 763 cmd->advertising |= ADVERTISED_Autoneg; 764 } 765 766 cmd->autoneg = (priv->port_state.flags & MLX4_EN_PORT_ANC) ? 767 AUTONEG_ENABLE : AUTONEG_DISABLE; 768 769 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv); 770 cmd->lp_advertising = ptys2ethtool_link_modes(eth_proto, ADVERTISED); 771 772 cmd->lp_advertising |= (priv->port_state.flags & MLX4_EN_PORT_ANC) ? 773 ADVERTISED_Autoneg : 0; 774 775 cmd->phy_address = 0; 776 cmd->mdio_support = 0; 777 cmd->maxtxpkt = 0; 778 cmd->maxrxpkt = 0; 779 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID; 780 cmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 781 782 return ret; 783 } 784 785 static void ethtool_get_default_settings(struct net_device *dev, 786 struct ethtool_cmd *cmd) 787 { 788 struct mlx4_en_priv *priv = netdev_priv(dev); 789 int trans_type; 790 791 cmd->autoneg = AUTONEG_DISABLE; 792 cmd->supported = SUPPORTED_10000baseT_Full; 793 cmd->advertising = ADVERTISED_10000baseT_Full; 794 trans_type = priv->port_state.transceiver; 795 796 if (trans_type > 0 && trans_type <= 0xC) { 797 cmd->port = PORT_FIBRE; 798 cmd->transceiver = XCVR_EXTERNAL; 799 cmd->supported |= SUPPORTED_FIBRE; 800 cmd->advertising |= ADVERTISED_FIBRE; 801 } else if (trans_type == 0x80 || trans_type == 0) { 802 cmd->port = PORT_TP; 803 cmd->transceiver = XCVR_INTERNAL; 804 cmd->supported |= SUPPORTED_TP; 805 cmd->advertising |= ADVERTISED_TP; 806 } else { 807 cmd->port = -1; 808 cmd->transceiver = -1; 809 } 810 } 811 812 static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 813 { 814 struct mlx4_en_priv *priv = netdev_priv(dev); 815 int ret = -EINVAL; 816 817 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port)) 818 return -ENOMEM; 819 820 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n", 821 priv->port_state.flags & MLX4_EN_PORT_ANC, 822 priv->port_state.flags & MLX4_EN_PORT_ANE); 823 824 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) 825 ret = ethtool_get_ptys_settings(dev, cmd); 826 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */ 827 ethtool_get_default_settings(dev, cmd); 828 829 if (netif_carrier_ok(dev)) { 830 ethtool_cmd_speed_set(cmd, priv->port_state.link_speed); 831 cmd->duplex = DUPLEX_FULL; 832 } else { 833 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 834 cmd->duplex = DUPLEX_UNKNOWN; 835 } 836 return 0; 837 } 838 839 /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */ 840 static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed, 841 __be32 proto_cap) 842 { 843 __be32 proto_admin = 0; 844 845 if (!speed) { /* Speed = 0 ==> Reset Link modes */ 846 proto_admin = proto_cap; 847 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n", 848 be32_to_cpu(proto_cap)); 849 } else { 850 u32 ptys_link_modes = speed2ptys_link_modes(speed); 851 852 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap; 853 en_info(priv, "Setting Speed to %d\n", speed); 854 } 855 return proto_admin; 856 } 857 858 static int mlx4_en_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 859 { 860 struct mlx4_en_priv *priv = netdev_priv(dev); 861 struct mlx4_ptys_reg ptys_reg; 862 __be32 proto_admin; 863 int ret; 864 865 u32 ptys_adv = ethtool2ptys_link_modes(cmd->advertising, ADVERTISED); 866 int speed = ethtool_cmd_speed(cmd); 867 868 en_dbg(DRV, priv, "Set Speed=%d adv=0x%x autoneg=%d duplex=%d\n", 869 speed, cmd->advertising, cmd->autoneg, cmd->duplex); 870 871 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) || 872 (cmd->duplex == DUPLEX_HALF)) 873 return -EINVAL; 874 875 memset(&ptys_reg, 0, sizeof(ptys_reg)); 876 ptys_reg.local_port = priv->port; 877 ptys_reg.proto_mask = MLX4_PTYS_EN; 878 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, 879 MLX4_ACCESS_REG_QUERY, &ptys_reg); 880 if (ret) { 881 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n", 882 ret); 883 return 0; 884 } 885 886 proto_admin = cmd->autoneg == AUTONEG_ENABLE ? 887 cpu_to_be32(ptys_adv) : 888 speed_set_ptys_admin(priv, speed, 889 ptys_reg.eth_proto_cap); 890 891 proto_admin &= ptys_reg.eth_proto_cap; 892 if (!proto_admin) { 893 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n"); 894 return -EINVAL; /* nothing to change due to bad input */ 895 } 896 897 if (proto_admin == ptys_reg.eth_proto_admin) 898 return 0; /* Nothing to change */ 899 900 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n", 901 be32_to_cpu(proto_admin)); 902 903 ptys_reg.eth_proto_admin = proto_admin; 904 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE, 905 &ptys_reg); 906 if (ret) { 907 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)", 908 be32_to_cpu(ptys_reg.eth_proto_admin), ret); 909 return ret; 910 } 911 912 mutex_lock(&priv->mdev->state_lock); 913 if (priv->port_up) { 914 en_warn(priv, "Port link mode changed, restarting port...\n"); 915 mlx4_en_stop_port(dev, 1); 916 if (mlx4_en_start_port(dev)) 917 en_err(priv, "Failed restarting port %d\n", priv->port); 918 } 919 mutex_unlock(&priv->mdev->state_lock); 920 return 0; 921 } 922 923 static int mlx4_en_get_coalesce(struct net_device *dev, 924 struct ethtool_coalesce *coal) 925 { 926 struct mlx4_en_priv *priv = netdev_priv(dev); 927 928 coal->tx_coalesce_usecs = priv->tx_usecs; 929 coal->tx_max_coalesced_frames = priv->tx_frames; 930 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit; 931 932 coal->rx_coalesce_usecs = priv->rx_usecs; 933 coal->rx_max_coalesced_frames = priv->rx_frames; 934 935 coal->pkt_rate_low = priv->pkt_rate_low; 936 coal->rx_coalesce_usecs_low = priv->rx_usecs_low; 937 coal->pkt_rate_high = priv->pkt_rate_high; 938 coal->rx_coalesce_usecs_high = priv->rx_usecs_high; 939 coal->rate_sample_interval = priv->sample_interval; 940 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal; 941 942 return 0; 943 } 944 945 static int mlx4_en_set_coalesce(struct net_device *dev, 946 struct ethtool_coalesce *coal) 947 { 948 struct mlx4_en_priv *priv = netdev_priv(dev); 949 950 if (!coal->tx_max_coalesced_frames_irq) 951 return -EINVAL; 952 953 priv->rx_frames = (coal->rx_max_coalesced_frames == 954 MLX4_EN_AUTO_CONF) ? 955 MLX4_EN_RX_COAL_TARGET : 956 coal->rx_max_coalesced_frames; 957 priv->rx_usecs = (coal->rx_coalesce_usecs == 958 MLX4_EN_AUTO_CONF) ? 959 MLX4_EN_RX_COAL_TIME : 960 coal->rx_coalesce_usecs; 961 962 /* Setting TX coalescing parameters */ 963 if (coal->tx_coalesce_usecs != priv->tx_usecs || 964 coal->tx_max_coalesced_frames != priv->tx_frames) { 965 priv->tx_usecs = coal->tx_coalesce_usecs; 966 priv->tx_frames = coal->tx_max_coalesced_frames; 967 } 968 969 /* Set adaptive coalescing params */ 970 priv->pkt_rate_low = coal->pkt_rate_low; 971 priv->rx_usecs_low = coal->rx_coalesce_usecs_low; 972 priv->pkt_rate_high = coal->pkt_rate_high; 973 priv->rx_usecs_high = coal->rx_coalesce_usecs_high; 974 priv->sample_interval = coal->rate_sample_interval; 975 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce; 976 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq; 977 978 return mlx4_en_moderation_update(priv); 979 } 980 981 static int mlx4_en_set_pauseparam(struct net_device *dev, 982 struct ethtool_pauseparam *pause) 983 { 984 struct mlx4_en_priv *priv = netdev_priv(dev); 985 struct mlx4_en_dev *mdev = priv->mdev; 986 int err; 987 988 if (pause->autoneg) 989 return -EINVAL; 990 991 priv->prof->tx_pause = pause->tx_pause != 0; 992 priv->prof->rx_pause = pause->rx_pause != 0; 993 err = mlx4_SET_PORT_general(mdev->dev, priv->port, 994 priv->rx_skb_size + ETH_FCS_LEN, 995 priv->prof->tx_pause, 996 priv->prof->tx_ppp, 997 priv->prof->rx_pause, 998 priv->prof->rx_ppp); 999 if (err) 1000 en_err(priv, "Failed setting pause params\n"); 1001 else 1002 mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap, 1003 priv->prof->rx_ppp, 1004 priv->prof->rx_pause, 1005 priv->prof->tx_ppp, 1006 priv->prof->tx_pause); 1007 1008 return err; 1009 } 1010 1011 static void mlx4_en_get_pauseparam(struct net_device *dev, 1012 struct ethtool_pauseparam *pause) 1013 { 1014 struct mlx4_en_priv *priv = netdev_priv(dev); 1015 1016 pause->tx_pause = priv->prof->tx_pause; 1017 pause->rx_pause = priv->prof->rx_pause; 1018 } 1019 1020 static int mlx4_en_set_ringparam(struct net_device *dev, 1021 struct ethtool_ringparam *param) 1022 { 1023 struct mlx4_en_priv *priv = netdev_priv(dev); 1024 struct mlx4_en_dev *mdev = priv->mdev; 1025 u32 rx_size, tx_size; 1026 int port_up = 0; 1027 int err = 0; 1028 1029 if (param->rx_jumbo_pending || param->rx_mini_pending) 1030 return -EINVAL; 1031 1032 rx_size = roundup_pow_of_two(param->rx_pending); 1033 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE); 1034 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE); 1035 tx_size = roundup_pow_of_two(param->tx_pending); 1036 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE); 1037 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE); 1038 1039 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size : 1040 priv->rx_ring[0]->size) && 1041 tx_size == priv->tx_ring[0]->size) 1042 return 0; 1043 1044 mutex_lock(&mdev->state_lock); 1045 if (priv->port_up) { 1046 port_up = 1; 1047 mlx4_en_stop_port(dev, 1); 1048 } 1049 1050 mlx4_en_free_resources(priv); 1051 1052 priv->prof->tx_ring_size = tx_size; 1053 priv->prof->rx_ring_size = rx_size; 1054 1055 err = mlx4_en_alloc_resources(priv); 1056 if (err) { 1057 en_err(priv, "Failed reallocating port resources\n"); 1058 goto out; 1059 } 1060 if (port_up) { 1061 err = mlx4_en_start_port(dev); 1062 if (err) 1063 en_err(priv, "Failed starting port\n"); 1064 } 1065 1066 err = mlx4_en_moderation_update(priv); 1067 1068 out: 1069 mutex_unlock(&mdev->state_lock); 1070 return err; 1071 } 1072 1073 static void mlx4_en_get_ringparam(struct net_device *dev, 1074 struct ethtool_ringparam *param) 1075 { 1076 struct mlx4_en_priv *priv = netdev_priv(dev); 1077 1078 memset(param, 0, sizeof(*param)); 1079 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE; 1080 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE; 1081 param->rx_pending = priv->port_up ? 1082 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size; 1083 param->tx_pending = priv->tx_ring[0]->size; 1084 } 1085 1086 static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev) 1087 { 1088 struct mlx4_en_priv *priv = netdev_priv(dev); 1089 1090 return priv->rx_ring_num; 1091 } 1092 1093 static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev) 1094 { 1095 return MLX4_EN_RSS_KEY_SIZE; 1096 } 1097 1098 static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc) 1099 { 1100 struct mlx4_en_priv *priv = netdev_priv(dev); 1101 1102 /* check if requested function is supported by the device */ 1103 if (hfunc == ETH_RSS_HASH_TOP) { 1104 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) 1105 return -EINVAL; 1106 if (!(dev->features & NETIF_F_RXHASH)) 1107 en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n"); 1108 return 0; 1109 } else if (hfunc == ETH_RSS_HASH_XOR) { 1110 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR)) 1111 return -EINVAL; 1112 if (dev->features & NETIF_F_RXHASH) 1113 en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n"); 1114 return 0; 1115 } 1116 1117 return -EINVAL; 1118 } 1119 1120 static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key, 1121 u8 *hfunc) 1122 { 1123 struct mlx4_en_priv *priv = netdev_priv(dev); 1124 struct mlx4_en_rss_map *rss_map = &priv->rss_map; 1125 int rss_rings; 1126 size_t n = priv->rx_ring_num; 1127 int err = 0; 1128 1129 rss_rings = priv->prof->rss_rings ?: priv->rx_ring_num; 1130 rss_rings = 1 << ilog2(rss_rings); 1131 1132 while (n--) { 1133 if (!ring_index) 1134 break; 1135 ring_index[n] = rss_map->qps[n % rss_rings].qpn - 1136 rss_map->base_qpn; 1137 } 1138 if (key) 1139 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE); 1140 if (hfunc) 1141 *hfunc = priv->rss_hash_fn; 1142 return err; 1143 } 1144 1145 static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index, 1146 const u8 *key, const u8 hfunc) 1147 { 1148 struct mlx4_en_priv *priv = netdev_priv(dev); 1149 struct mlx4_en_dev *mdev = priv->mdev; 1150 int port_up = 0; 1151 int err = 0; 1152 int i; 1153 int rss_rings = 0; 1154 1155 /* Calculate RSS table size and make sure flows are spread evenly 1156 * between rings 1157 */ 1158 for (i = 0; i < priv->rx_ring_num; i++) { 1159 if (!ring_index) 1160 continue; 1161 if (i > 0 && !ring_index[i] && !rss_rings) 1162 rss_rings = i; 1163 1164 if (ring_index[i] != (i % (rss_rings ?: priv->rx_ring_num))) 1165 return -EINVAL; 1166 } 1167 1168 if (!rss_rings) 1169 rss_rings = priv->rx_ring_num; 1170 1171 /* RSS table size must be an order of 2 */ 1172 if (!is_power_of_2(rss_rings)) 1173 return -EINVAL; 1174 1175 if (hfunc != ETH_RSS_HASH_NO_CHANGE) { 1176 err = mlx4_en_check_rxfh_func(dev, hfunc); 1177 if (err) 1178 return err; 1179 } 1180 1181 mutex_lock(&mdev->state_lock); 1182 if (priv->port_up) { 1183 port_up = 1; 1184 mlx4_en_stop_port(dev, 1); 1185 } 1186 1187 if (ring_index) 1188 priv->prof->rss_rings = rss_rings; 1189 if (key) 1190 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE); 1191 if (hfunc != ETH_RSS_HASH_NO_CHANGE) 1192 priv->rss_hash_fn = hfunc; 1193 1194 if (port_up) { 1195 err = mlx4_en_start_port(dev); 1196 if (err) 1197 en_err(priv, "Failed starting port\n"); 1198 } 1199 1200 mutex_unlock(&mdev->state_lock); 1201 return err; 1202 } 1203 1204 #define all_zeros_or_all_ones(field) \ 1205 ((field) == 0 || (field) == (__force typeof(field))-1) 1206 1207 static int mlx4_en_validate_flow(struct net_device *dev, 1208 struct ethtool_rxnfc *cmd) 1209 { 1210 struct ethtool_usrip4_spec *l3_mask; 1211 struct ethtool_tcpip4_spec *l4_mask; 1212 struct ethhdr *eth_mask; 1213 1214 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1215 return -EINVAL; 1216 1217 if (cmd->fs.flow_type & FLOW_MAC_EXT) { 1218 /* dest mac mask must be ff:ff:ff:ff:ff:ff */ 1219 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest)) 1220 return -EINVAL; 1221 } 1222 1223 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1224 case TCP_V4_FLOW: 1225 case UDP_V4_FLOW: 1226 if (cmd->fs.m_u.tcp_ip4_spec.tos) 1227 return -EINVAL; 1228 l4_mask = &cmd->fs.m_u.tcp_ip4_spec; 1229 /* don't allow mask which isn't all 0 or 1 */ 1230 if (!all_zeros_or_all_ones(l4_mask->ip4src) || 1231 !all_zeros_or_all_ones(l4_mask->ip4dst) || 1232 !all_zeros_or_all_ones(l4_mask->psrc) || 1233 !all_zeros_or_all_ones(l4_mask->pdst)) 1234 return -EINVAL; 1235 break; 1236 case IP_USER_FLOW: 1237 l3_mask = &cmd->fs.m_u.usr_ip4_spec; 1238 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto || 1239 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 || 1240 (!l3_mask->ip4src && !l3_mask->ip4dst) || 1241 !all_zeros_or_all_ones(l3_mask->ip4src) || 1242 !all_zeros_or_all_ones(l3_mask->ip4dst)) 1243 return -EINVAL; 1244 break; 1245 case ETHER_FLOW: 1246 eth_mask = &cmd->fs.m_u.ether_spec; 1247 /* source mac mask must not be set */ 1248 if (!is_zero_ether_addr(eth_mask->h_source)) 1249 return -EINVAL; 1250 1251 /* dest mac mask must be ff:ff:ff:ff:ff:ff */ 1252 if (!is_broadcast_ether_addr(eth_mask->h_dest)) 1253 return -EINVAL; 1254 1255 if (!all_zeros_or_all_ones(eth_mask->h_proto)) 1256 return -EINVAL; 1257 break; 1258 default: 1259 return -EINVAL; 1260 } 1261 1262 if ((cmd->fs.flow_type & FLOW_EXT)) { 1263 if (cmd->fs.m_ext.vlan_etype || 1264 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == 1265 0 || 1266 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == 1267 cpu_to_be16(VLAN_VID_MASK))) 1268 return -EINVAL; 1269 1270 if (cmd->fs.m_ext.vlan_tci) { 1271 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID) 1272 return -EINVAL; 1273 1274 } 1275 } 1276 1277 return 0; 1278 } 1279 1280 static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd, 1281 struct list_head *rule_list_h, 1282 struct mlx4_spec_list *spec_l2, 1283 unsigned char *mac) 1284 { 1285 int err = 0; 1286 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16); 1287 1288 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH; 1289 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN); 1290 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN); 1291 1292 if ((cmd->fs.flow_type & FLOW_EXT) && 1293 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) { 1294 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci; 1295 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK); 1296 } 1297 1298 list_add_tail(&spec_l2->list, rule_list_h); 1299 1300 return err; 1301 } 1302 1303 static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv, 1304 struct ethtool_rxnfc *cmd, 1305 struct list_head *rule_list_h, 1306 struct mlx4_spec_list *spec_l2, 1307 __be32 ipv4_dst) 1308 { 1309 #ifdef CONFIG_INET 1310 unsigned char mac[ETH_ALEN]; 1311 1312 if (!ipv4_is_multicast(ipv4_dst)) { 1313 if (cmd->fs.flow_type & FLOW_MAC_EXT) 1314 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN); 1315 else 1316 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN); 1317 } else { 1318 ip_eth_mc_map(ipv4_dst, mac); 1319 } 1320 1321 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]); 1322 #else 1323 return -EINVAL; 1324 #endif 1325 } 1326 1327 static int add_ip_rule(struct mlx4_en_priv *priv, 1328 struct ethtool_rxnfc *cmd, 1329 struct list_head *list_h) 1330 { 1331 int err; 1332 struct mlx4_spec_list *spec_l2 = NULL; 1333 struct mlx4_spec_list *spec_l3 = NULL; 1334 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec; 1335 1336 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); 1337 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1338 if (!spec_l2 || !spec_l3) { 1339 err = -ENOMEM; 1340 goto free_spec; 1341 } 1342 1343 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2, 1344 cmd->fs.h_u. 1345 usr_ip4_spec.ip4dst); 1346 if (err) 1347 goto free_spec; 1348 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; 1349 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src; 1350 if (l3_mask->ip4src) 1351 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; 1352 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst; 1353 if (l3_mask->ip4dst) 1354 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; 1355 list_add_tail(&spec_l3->list, list_h); 1356 1357 return 0; 1358 1359 free_spec: 1360 kfree(spec_l2); 1361 kfree(spec_l3); 1362 return err; 1363 } 1364 1365 static int add_tcp_udp_rule(struct mlx4_en_priv *priv, 1366 struct ethtool_rxnfc *cmd, 1367 struct list_head *list_h, int proto) 1368 { 1369 int err; 1370 struct mlx4_spec_list *spec_l2 = NULL; 1371 struct mlx4_spec_list *spec_l3 = NULL; 1372 struct mlx4_spec_list *spec_l4 = NULL; 1373 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec; 1374 1375 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1376 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); 1377 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL); 1378 if (!spec_l2 || !spec_l3 || !spec_l4) { 1379 err = -ENOMEM; 1380 goto free_spec; 1381 } 1382 1383 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; 1384 1385 if (proto == TCP_V4_FLOW) { 1386 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, 1387 spec_l2, 1388 cmd->fs.h_u. 1389 tcp_ip4_spec.ip4dst); 1390 if (err) 1391 goto free_spec; 1392 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP; 1393 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src; 1394 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst; 1395 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc; 1396 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst; 1397 } else { 1398 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, 1399 spec_l2, 1400 cmd->fs.h_u. 1401 udp_ip4_spec.ip4dst); 1402 if (err) 1403 goto free_spec; 1404 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP; 1405 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src; 1406 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst; 1407 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc; 1408 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst; 1409 } 1410 1411 if (l4_mask->ip4src) 1412 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; 1413 if (l4_mask->ip4dst) 1414 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; 1415 1416 if (l4_mask->psrc) 1417 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK; 1418 if (l4_mask->pdst) 1419 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK; 1420 1421 list_add_tail(&spec_l3->list, list_h); 1422 list_add_tail(&spec_l4->list, list_h); 1423 1424 return 0; 1425 1426 free_spec: 1427 kfree(spec_l2); 1428 kfree(spec_l3); 1429 kfree(spec_l4); 1430 return err; 1431 } 1432 1433 static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev, 1434 struct ethtool_rxnfc *cmd, 1435 struct list_head *rule_list_h) 1436 { 1437 int err; 1438 struct ethhdr *eth_spec; 1439 struct mlx4_spec_list *spec_l2; 1440 struct mlx4_en_priv *priv = netdev_priv(dev); 1441 1442 err = mlx4_en_validate_flow(dev, cmd); 1443 if (err) 1444 return err; 1445 1446 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1447 case ETHER_FLOW: 1448 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); 1449 if (!spec_l2) 1450 return -ENOMEM; 1451 1452 eth_spec = &cmd->fs.h_u.ether_spec; 1453 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, 1454 ð_spec->h_dest[0]); 1455 spec_l2->eth.ether_type = eth_spec->h_proto; 1456 if (eth_spec->h_proto) 1457 spec_l2->eth.ether_type_enable = 1; 1458 break; 1459 case IP_USER_FLOW: 1460 err = add_ip_rule(priv, cmd, rule_list_h); 1461 break; 1462 case TCP_V4_FLOW: 1463 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW); 1464 break; 1465 case UDP_V4_FLOW: 1466 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW); 1467 break; 1468 } 1469 1470 return err; 1471 } 1472 1473 static int mlx4_en_flow_replace(struct net_device *dev, 1474 struct ethtool_rxnfc *cmd) 1475 { 1476 int err; 1477 struct mlx4_en_priv *priv = netdev_priv(dev); 1478 struct ethtool_flow_id *loc_rule; 1479 struct mlx4_spec_list *spec, *tmp_spec; 1480 u32 qpn; 1481 u64 reg_id; 1482 1483 struct mlx4_net_trans_rule rule = { 1484 .queue_mode = MLX4_NET_TRANS_Q_FIFO, 1485 .exclusive = 0, 1486 .allow_loopback = 1, 1487 .promisc_mode = MLX4_FS_REGULAR, 1488 }; 1489 1490 rule.port = priv->port; 1491 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location; 1492 INIT_LIST_HEAD(&rule.list); 1493 1494 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */ 1495 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC) 1496 qpn = priv->drop_qp.qpn; 1497 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) { 1498 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1); 1499 } else { 1500 if (cmd->fs.ring_cookie >= priv->rx_ring_num) { 1501 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n", 1502 cmd->fs.ring_cookie); 1503 return -EINVAL; 1504 } 1505 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn; 1506 if (!qpn) { 1507 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n", 1508 cmd->fs.ring_cookie); 1509 return -EINVAL; 1510 } 1511 } 1512 rule.qpn = qpn; 1513 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list); 1514 if (err) 1515 goto out_free_list; 1516 1517 loc_rule = &priv->ethtool_rules[cmd->fs.location]; 1518 if (loc_rule->id) { 1519 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id); 1520 if (err) { 1521 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n", 1522 cmd->fs.location, loc_rule->id); 1523 goto out_free_list; 1524 } 1525 loc_rule->id = 0; 1526 memset(&loc_rule->flow_spec, 0, 1527 sizeof(struct ethtool_rx_flow_spec)); 1528 list_del(&loc_rule->list); 1529 } 1530 err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id); 1531 if (err) { 1532 en_err(priv, "Fail to attach network rule at location %d\n", 1533 cmd->fs.location); 1534 goto out_free_list; 1535 } 1536 loc_rule->id = reg_id; 1537 memcpy(&loc_rule->flow_spec, &cmd->fs, 1538 sizeof(struct ethtool_rx_flow_spec)); 1539 list_add_tail(&loc_rule->list, &priv->ethtool_list); 1540 1541 out_free_list: 1542 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) { 1543 list_del(&spec->list); 1544 kfree(spec); 1545 } 1546 return err; 1547 } 1548 1549 static int mlx4_en_flow_detach(struct net_device *dev, 1550 struct ethtool_rxnfc *cmd) 1551 { 1552 int err = 0; 1553 struct ethtool_flow_id *rule; 1554 struct mlx4_en_priv *priv = netdev_priv(dev); 1555 1556 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1557 return -EINVAL; 1558 1559 rule = &priv->ethtool_rules[cmd->fs.location]; 1560 if (!rule->id) { 1561 err = -ENOENT; 1562 goto out; 1563 } 1564 1565 err = mlx4_flow_detach(priv->mdev->dev, rule->id); 1566 if (err) { 1567 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n", 1568 cmd->fs.location, rule->id); 1569 goto out; 1570 } 1571 rule->id = 0; 1572 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec)); 1573 list_del(&rule->list); 1574 out: 1575 return err; 1576 1577 } 1578 1579 static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1580 int loc) 1581 { 1582 int err = 0; 1583 struct ethtool_flow_id *rule; 1584 struct mlx4_en_priv *priv = netdev_priv(dev); 1585 1586 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1587 return -EINVAL; 1588 1589 rule = &priv->ethtool_rules[loc]; 1590 if (rule->id) 1591 memcpy(&cmd->fs, &rule->flow_spec, 1592 sizeof(struct ethtool_rx_flow_spec)); 1593 else 1594 err = -ENOENT; 1595 1596 return err; 1597 } 1598 1599 static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv) 1600 { 1601 1602 int i, res = 0; 1603 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 1604 if (priv->ethtool_rules[i].id) 1605 res++; 1606 } 1607 return res; 1608 1609 } 1610 1611 static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1612 u32 *rule_locs) 1613 { 1614 struct mlx4_en_priv *priv = netdev_priv(dev); 1615 struct mlx4_en_dev *mdev = priv->mdev; 1616 int err = 0; 1617 int i = 0, priority = 0; 1618 1619 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT || 1620 cmd->cmd == ETHTOOL_GRXCLSRULE || 1621 cmd->cmd == ETHTOOL_GRXCLSRLALL) && 1622 (mdev->dev->caps.steering_mode != 1623 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)) 1624 return -EINVAL; 1625 1626 switch (cmd->cmd) { 1627 case ETHTOOL_GRXRINGS: 1628 cmd->data = priv->rx_ring_num; 1629 break; 1630 case ETHTOOL_GRXCLSRLCNT: 1631 cmd->rule_cnt = mlx4_en_get_num_flows(priv); 1632 break; 1633 case ETHTOOL_GRXCLSRULE: 1634 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location); 1635 break; 1636 case ETHTOOL_GRXCLSRLALL: 1637 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) { 1638 err = mlx4_en_get_flow(dev, cmd, i); 1639 if (!err) 1640 rule_locs[priority++] = i; 1641 i++; 1642 } 1643 err = 0; 1644 break; 1645 default: 1646 err = -EOPNOTSUPP; 1647 break; 1648 } 1649 1650 return err; 1651 } 1652 1653 static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1654 { 1655 int err = 0; 1656 struct mlx4_en_priv *priv = netdev_priv(dev); 1657 struct mlx4_en_dev *mdev = priv->mdev; 1658 1659 if (mdev->dev->caps.steering_mode != 1660 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up) 1661 return -EINVAL; 1662 1663 switch (cmd->cmd) { 1664 case ETHTOOL_SRXCLSRLINS: 1665 err = mlx4_en_flow_replace(dev, cmd); 1666 break; 1667 case ETHTOOL_SRXCLSRLDEL: 1668 err = mlx4_en_flow_detach(dev, cmd); 1669 break; 1670 default: 1671 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd); 1672 return -EINVAL; 1673 } 1674 1675 return err; 1676 } 1677 1678 static void mlx4_en_get_channels(struct net_device *dev, 1679 struct ethtool_channels *channel) 1680 { 1681 struct mlx4_en_priv *priv = netdev_priv(dev); 1682 1683 memset(channel, 0, sizeof(*channel)); 1684 1685 channel->max_rx = MAX_RX_RINGS; 1686 channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP; 1687 1688 channel->rx_count = priv->rx_ring_num; 1689 channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP; 1690 } 1691 1692 static int mlx4_en_set_channels(struct net_device *dev, 1693 struct ethtool_channels *channel) 1694 { 1695 struct mlx4_en_priv *priv = netdev_priv(dev); 1696 struct mlx4_en_dev *mdev = priv->mdev; 1697 int port_up = 0; 1698 int err = 0; 1699 1700 if (channel->other_count || channel->combined_count || 1701 channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP || 1702 channel->rx_count > MAX_RX_RINGS || 1703 !channel->tx_count || !channel->rx_count) 1704 return -EINVAL; 1705 1706 mutex_lock(&mdev->state_lock); 1707 if (priv->port_up) { 1708 port_up = 1; 1709 mlx4_en_stop_port(dev, 1); 1710 } 1711 1712 mlx4_en_free_resources(priv); 1713 1714 priv->num_tx_rings_p_up = channel->tx_count; 1715 priv->tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP; 1716 priv->rx_ring_num = channel->rx_count; 1717 1718 err = mlx4_en_alloc_resources(priv); 1719 if (err) { 1720 en_err(priv, "Failed reallocating port resources\n"); 1721 goto out; 1722 } 1723 1724 netif_set_real_num_tx_queues(dev, priv->tx_ring_num); 1725 netif_set_real_num_rx_queues(dev, priv->rx_ring_num); 1726 1727 if (dev->num_tc) 1728 mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP); 1729 1730 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num); 1731 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num); 1732 1733 if (port_up) { 1734 err = mlx4_en_start_port(dev); 1735 if (err) 1736 en_err(priv, "Failed starting port\n"); 1737 } 1738 1739 err = mlx4_en_moderation_update(priv); 1740 1741 out: 1742 mutex_unlock(&mdev->state_lock); 1743 return err; 1744 } 1745 1746 static int mlx4_en_get_ts_info(struct net_device *dev, 1747 struct ethtool_ts_info *info) 1748 { 1749 struct mlx4_en_priv *priv = netdev_priv(dev); 1750 struct mlx4_en_dev *mdev = priv->mdev; 1751 int ret; 1752 1753 ret = ethtool_op_get_ts_info(dev, info); 1754 if (ret) 1755 return ret; 1756 1757 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 1758 info->so_timestamping |= 1759 SOF_TIMESTAMPING_TX_HARDWARE | 1760 SOF_TIMESTAMPING_RX_HARDWARE | 1761 SOF_TIMESTAMPING_RAW_HARDWARE; 1762 1763 info->tx_types = 1764 (1 << HWTSTAMP_TX_OFF) | 1765 (1 << HWTSTAMP_TX_ON); 1766 1767 info->rx_filters = 1768 (1 << HWTSTAMP_FILTER_NONE) | 1769 (1 << HWTSTAMP_FILTER_ALL); 1770 1771 if (mdev->ptp_clock) 1772 info->phc_index = ptp_clock_index(mdev->ptp_clock); 1773 } 1774 1775 return ret; 1776 } 1777 1778 static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags) 1779 { 1780 struct mlx4_en_priv *priv = netdev_priv(dev); 1781 struct mlx4_en_dev *mdev = priv->mdev; 1782 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); 1783 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); 1784 bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV); 1785 bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV); 1786 int i; 1787 int ret = 0; 1788 1789 if (bf_enabled_new != bf_enabled_old) { 1790 if (bf_enabled_new) { 1791 bool bf_supported = true; 1792 1793 for (i = 0; i < priv->tx_ring_num; i++) 1794 bf_supported &= priv->tx_ring[i]->bf_alloced; 1795 1796 if (!bf_supported) { 1797 en_err(priv, "BlueFlame is not supported\n"); 1798 return -EINVAL; 1799 } 1800 1801 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME; 1802 } else { 1803 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; 1804 } 1805 1806 for (i = 0; i < priv->tx_ring_num; i++) 1807 priv->tx_ring[i]->bf_enabled = bf_enabled_new; 1808 1809 en_info(priv, "BlueFlame %s\n", 1810 bf_enabled_new ? "Enabled" : "Disabled"); 1811 } 1812 1813 if (phv_enabled_new != phv_enabled_old) { 1814 ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new); 1815 if (ret) 1816 return ret; 1817 else if (phv_enabled_new) 1818 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV; 1819 else 1820 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV; 1821 en_info(priv, "PHV bit %s\n", 1822 phv_enabled_new ? "Enabled" : "Disabled"); 1823 } 1824 return 0; 1825 } 1826 1827 static u32 mlx4_en_get_priv_flags(struct net_device *dev) 1828 { 1829 struct mlx4_en_priv *priv = netdev_priv(dev); 1830 1831 return priv->pflags; 1832 } 1833 1834 static int mlx4_en_get_tunable(struct net_device *dev, 1835 const struct ethtool_tunable *tuna, 1836 void *data) 1837 { 1838 const struct mlx4_en_priv *priv = netdev_priv(dev); 1839 int ret = 0; 1840 1841 switch (tuna->id) { 1842 case ETHTOOL_TX_COPYBREAK: 1843 *(u32 *)data = priv->prof->inline_thold; 1844 break; 1845 default: 1846 ret = -EINVAL; 1847 break; 1848 } 1849 1850 return ret; 1851 } 1852 1853 static int mlx4_en_set_tunable(struct net_device *dev, 1854 const struct ethtool_tunable *tuna, 1855 const void *data) 1856 { 1857 struct mlx4_en_priv *priv = netdev_priv(dev); 1858 int val, ret = 0; 1859 1860 switch (tuna->id) { 1861 case ETHTOOL_TX_COPYBREAK: 1862 val = *(u32 *)data; 1863 if (val < MIN_PKT_LEN || val > MAX_INLINE) 1864 ret = -EINVAL; 1865 else 1866 priv->prof->inline_thold = val; 1867 break; 1868 default: 1869 ret = -EINVAL; 1870 break; 1871 } 1872 1873 return ret; 1874 } 1875 1876 static int mlx4_en_get_module_info(struct net_device *dev, 1877 struct ethtool_modinfo *modinfo) 1878 { 1879 struct mlx4_en_priv *priv = netdev_priv(dev); 1880 struct mlx4_en_dev *mdev = priv->mdev; 1881 int ret; 1882 u8 data[4]; 1883 1884 /* Read first 2 bytes to get Module & REV ID */ 1885 ret = mlx4_get_module_info(mdev->dev, priv->port, 1886 0/*offset*/, 2/*size*/, data); 1887 if (ret < 2) 1888 return -EIO; 1889 1890 switch (data[0] /* identifier */) { 1891 case MLX4_MODULE_ID_QSFP: 1892 modinfo->type = ETH_MODULE_SFF_8436; 1893 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 1894 break; 1895 case MLX4_MODULE_ID_QSFP_PLUS: 1896 if (data[1] >= 0x3) { /* revision id */ 1897 modinfo->type = ETH_MODULE_SFF_8636; 1898 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 1899 } else { 1900 modinfo->type = ETH_MODULE_SFF_8436; 1901 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 1902 } 1903 break; 1904 case MLX4_MODULE_ID_QSFP28: 1905 modinfo->type = ETH_MODULE_SFF_8636; 1906 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 1907 break; 1908 case MLX4_MODULE_ID_SFP: 1909 modinfo->type = ETH_MODULE_SFF_8472; 1910 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1911 break; 1912 default: 1913 return -ENOSYS; 1914 } 1915 1916 return 0; 1917 } 1918 1919 static int mlx4_en_get_module_eeprom(struct net_device *dev, 1920 struct ethtool_eeprom *ee, 1921 u8 *data) 1922 { 1923 struct mlx4_en_priv *priv = netdev_priv(dev); 1924 struct mlx4_en_dev *mdev = priv->mdev; 1925 int offset = ee->offset; 1926 int i = 0, ret; 1927 1928 if (ee->len == 0) 1929 return -EINVAL; 1930 1931 memset(data, 0, ee->len); 1932 1933 while (i < ee->len) { 1934 en_dbg(DRV, priv, 1935 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n", 1936 i, offset, ee->len - i); 1937 1938 ret = mlx4_get_module_info(mdev->dev, priv->port, 1939 offset, ee->len - i, data + i); 1940 1941 if (!ret) /* Done reading */ 1942 return 0; 1943 1944 if (ret < 0) { 1945 en_err(priv, 1946 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n", 1947 i, offset, ee->len - i, ret); 1948 return 0; 1949 } 1950 1951 i += ret; 1952 offset += ret; 1953 } 1954 return 0; 1955 } 1956 1957 static int mlx4_en_set_phys_id(struct net_device *dev, 1958 enum ethtool_phys_id_state state) 1959 { 1960 int err; 1961 u16 beacon_duration; 1962 struct mlx4_en_priv *priv = netdev_priv(dev); 1963 struct mlx4_en_dev *mdev = priv->mdev; 1964 1965 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON)) 1966 return -EOPNOTSUPP; 1967 1968 switch (state) { 1969 case ETHTOOL_ID_ACTIVE: 1970 beacon_duration = PORT_BEACON_MAX_LIMIT; 1971 break; 1972 case ETHTOOL_ID_INACTIVE: 1973 beacon_duration = 0; 1974 break; 1975 default: 1976 return -EOPNOTSUPP; 1977 } 1978 1979 err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration); 1980 return err; 1981 } 1982 1983 const struct ethtool_ops mlx4_en_ethtool_ops = { 1984 .get_drvinfo = mlx4_en_get_drvinfo, 1985 .get_settings = mlx4_en_get_settings, 1986 .set_settings = mlx4_en_set_settings, 1987 .get_link = ethtool_op_get_link, 1988 .get_strings = mlx4_en_get_strings, 1989 .get_sset_count = mlx4_en_get_sset_count, 1990 .get_ethtool_stats = mlx4_en_get_ethtool_stats, 1991 .self_test = mlx4_en_self_test, 1992 .set_phys_id = mlx4_en_set_phys_id, 1993 .get_wol = mlx4_en_get_wol, 1994 .set_wol = mlx4_en_set_wol, 1995 .get_msglevel = mlx4_en_get_msglevel, 1996 .set_msglevel = mlx4_en_set_msglevel, 1997 .get_coalesce = mlx4_en_get_coalesce, 1998 .set_coalesce = mlx4_en_set_coalesce, 1999 .get_pauseparam = mlx4_en_get_pauseparam, 2000 .set_pauseparam = mlx4_en_set_pauseparam, 2001 .get_ringparam = mlx4_en_get_ringparam, 2002 .set_ringparam = mlx4_en_set_ringparam, 2003 .get_rxnfc = mlx4_en_get_rxnfc, 2004 .set_rxnfc = mlx4_en_set_rxnfc, 2005 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size, 2006 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size, 2007 .get_rxfh = mlx4_en_get_rxfh, 2008 .set_rxfh = mlx4_en_set_rxfh, 2009 .get_channels = mlx4_en_get_channels, 2010 .set_channels = mlx4_en_set_channels, 2011 .get_ts_info = mlx4_en_get_ts_info, 2012 .set_priv_flags = mlx4_en_set_priv_flags, 2013 .get_priv_flags = mlx4_en_get_priv_flags, 2014 .get_tunable = mlx4_en_get_tunable, 2015 .set_tunable = mlx4_en_set_tunable, 2016 .get_module_info = mlx4_en_get_module_info, 2017 .get_module_eeprom = mlx4_en_get_module_eeprom 2018 }; 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