1 /* 2 * Copyright (c) 2012 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #include <linux/mlx4/device.h> 35 36 #include "mlx4_en.h" 37 38 int mlx4_en_timestamp_config(struct net_device *dev, int tx_type, int rx_filter) 39 { 40 struct mlx4_en_priv *priv = netdev_priv(dev); 41 struct mlx4_en_dev *mdev = priv->mdev; 42 int port_up = 0; 43 int err = 0; 44 45 if (priv->hwtstamp_config.tx_type == tx_type && 46 priv->hwtstamp_config.rx_filter == rx_filter) 47 return 0; 48 49 mutex_lock(&mdev->state_lock); 50 if (priv->port_up) { 51 port_up = 1; 52 mlx4_en_stop_port(dev, 1); 53 } 54 55 mlx4_en_free_resources(priv); 56 57 en_warn(priv, "Changing Time Stamp configuration\n"); 58 59 priv->hwtstamp_config.tx_type = tx_type; 60 priv->hwtstamp_config.rx_filter = rx_filter; 61 62 if (rx_filter != HWTSTAMP_FILTER_NONE) 63 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX; 64 else 65 dev->features |= NETIF_F_HW_VLAN_CTAG_RX; 66 67 err = mlx4_en_alloc_resources(priv); 68 if (err) { 69 en_err(priv, "Failed reallocating port resources\n"); 70 goto out; 71 } 72 if (port_up) { 73 err = mlx4_en_start_port(dev); 74 if (err) 75 en_err(priv, "Failed starting port\n"); 76 } 77 78 out: 79 mutex_unlock(&mdev->state_lock); 80 netdev_features_change(dev); 81 return err; 82 } 83 84 /* mlx4_en_read_clock - read raw cycle counter (to be used by time counter) 85 */ 86 static cycle_t mlx4_en_read_clock(const struct cyclecounter *tc) 87 { 88 struct mlx4_en_dev *mdev = 89 container_of(tc, struct mlx4_en_dev, cycles); 90 struct mlx4_dev *dev = mdev->dev; 91 92 return mlx4_read_clock(dev) & tc->mask; 93 } 94 95 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe) 96 { 97 u64 hi, lo; 98 struct mlx4_ts_cqe *ts_cqe = (struct mlx4_ts_cqe *)cqe; 99 100 lo = (u64)be16_to_cpu(ts_cqe->timestamp_lo); 101 hi = ((u64)be32_to_cpu(ts_cqe->timestamp_hi) + !lo) << 16; 102 103 return hi | lo; 104 } 105 106 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 107 struct skb_shared_hwtstamps *hwts, 108 u64 timestamp) 109 { 110 unsigned long flags; 111 u64 nsec; 112 113 read_lock_irqsave(&mdev->clock_lock, flags); 114 nsec = timecounter_cyc2time(&mdev->clock, timestamp); 115 read_unlock_irqrestore(&mdev->clock_lock, flags); 116 117 memset(hwts, 0, sizeof(struct skb_shared_hwtstamps)); 118 hwts->hwtstamp = ns_to_ktime(nsec); 119 } 120 121 /** 122 * mlx4_en_remove_timestamp - disable PTP device 123 * @mdev: board private structure 124 * 125 * Stop the PTP support. 126 **/ 127 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev) 128 { 129 if (mdev->ptp_clock) { 130 ptp_clock_unregister(mdev->ptp_clock); 131 mdev->ptp_clock = NULL; 132 mlx4_info(mdev, "removed PHC\n"); 133 } 134 } 135 136 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev) 137 { 138 bool timeout = time_is_before_jiffies(mdev->last_overflow_check + 139 mdev->overflow_period); 140 unsigned long flags; 141 142 if (timeout) { 143 write_lock_irqsave(&mdev->clock_lock, flags); 144 timecounter_read(&mdev->clock); 145 write_unlock_irqrestore(&mdev->clock_lock, flags); 146 mdev->last_overflow_check = jiffies; 147 } 148 } 149 150 /** 151 * mlx4_en_phc_adjfreq - adjust the frequency of the hardware clock 152 * @ptp: ptp clock structure 153 * @delta: Desired frequency change in parts per billion 154 * 155 * Adjust the frequency of the PHC cycle counter by the indicated delta from 156 * the base frequency. 157 **/ 158 static int mlx4_en_phc_adjfreq(struct ptp_clock_info *ptp, s32 delta) 159 { 160 u64 adj; 161 u32 diff, mult; 162 int neg_adj = 0; 163 unsigned long flags; 164 struct mlx4_en_dev *mdev = container_of(ptp, struct mlx4_en_dev, 165 ptp_clock_info); 166 167 if (delta < 0) { 168 neg_adj = 1; 169 delta = -delta; 170 } 171 mult = mdev->nominal_c_mult; 172 adj = mult; 173 adj *= delta; 174 diff = div_u64(adj, 1000000000ULL); 175 176 write_lock_irqsave(&mdev->clock_lock, flags); 177 timecounter_read(&mdev->clock); 178 mdev->cycles.mult = neg_adj ? mult - diff : mult + diff; 179 write_unlock_irqrestore(&mdev->clock_lock, flags); 180 181 return 0; 182 } 183 184 /** 185 * mlx4_en_phc_adjtime - Shift the time of the hardware clock 186 * @ptp: ptp clock structure 187 * @delta: Desired change in nanoseconds 188 * 189 * Adjust the timer by resetting the timecounter structure. 190 **/ 191 static int mlx4_en_phc_adjtime(struct ptp_clock_info *ptp, s64 delta) 192 { 193 struct mlx4_en_dev *mdev = container_of(ptp, struct mlx4_en_dev, 194 ptp_clock_info); 195 unsigned long flags; 196 s64 now; 197 198 write_lock_irqsave(&mdev->clock_lock, flags); 199 now = timecounter_read(&mdev->clock); 200 now += delta; 201 timecounter_init(&mdev->clock, &mdev->cycles, now); 202 write_unlock_irqrestore(&mdev->clock_lock, flags); 203 204 return 0; 205 } 206 207 /** 208 * mlx4_en_phc_gettime - Reads the current time from the hardware clock 209 * @ptp: ptp clock structure 210 * @ts: timespec structure to hold the current time value 211 * 212 * Read the timecounter and return the correct value in ns after converting 213 * it into a struct timespec. 214 **/ 215 static int mlx4_en_phc_gettime(struct ptp_clock_info *ptp, struct timespec *ts) 216 { 217 struct mlx4_en_dev *mdev = container_of(ptp, struct mlx4_en_dev, 218 ptp_clock_info); 219 unsigned long flags; 220 u32 remainder; 221 u64 ns; 222 223 write_lock_irqsave(&mdev->clock_lock, flags); 224 ns = timecounter_read(&mdev->clock); 225 write_unlock_irqrestore(&mdev->clock_lock, flags); 226 227 ts->tv_sec = div_u64_rem(ns, NSEC_PER_SEC, &remainder); 228 ts->tv_nsec = remainder; 229 230 return 0; 231 } 232 233 /** 234 * mlx4_en_phc_settime - Set the current time on the hardware clock 235 * @ptp: ptp clock structure 236 * @ts: timespec containing the new time for the cycle counter 237 * 238 * Reset the timecounter to use a new base value instead of the kernel 239 * wall timer value. 240 **/ 241 static int mlx4_en_phc_settime(struct ptp_clock_info *ptp, 242 const struct timespec *ts) 243 { 244 struct mlx4_en_dev *mdev = container_of(ptp, struct mlx4_en_dev, 245 ptp_clock_info); 246 u64 ns = timespec_to_ns(ts); 247 unsigned long flags; 248 249 /* reset the timecounter */ 250 write_lock_irqsave(&mdev->clock_lock, flags); 251 timecounter_init(&mdev->clock, &mdev->cycles, ns); 252 write_unlock_irqrestore(&mdev->clock_lock, flags); 253 254 return 0; 255 } 256 257 /** 258 * mlx4_en_phc_enable - enable or disable an ancillary feature 259 * @ptp: ptp clock structure 260 * @request: Desired resource to enable or disable 261 * @on: Caller passes one to enable or zero to disable 262 * 263 * Enable (or disable) ancillary features of the PHC subsystem. 264 * Currently, no ancillary features are supported. 265 **/ 266 static int mlx4_en_phc_enable(struct ptp_clock_info __always_unused *ptp, 267 struct ptp_clock_request __always_unused *request, 268 int __always_unused on) 269 { 270 return -EOPNOTSUPP; 271 } 272 273 static const struct ptp_clock_info mlx4_en_ptp_clock_info = { 274 .owner = THIS_MODULE, 275 .max_adj = 100000000, 276 .n_alarm = 0, 277 .n_ext_ts = 0, 278 .n_per_out = 0, 279 .n_pins = 0, 280 .pps = 0, 281 .adjfreq = mlx4_en_phc_adjfreq, 282 .adjtime = mlx4_en_phc_adjtime, 283 .gettime = mlx4_en_phc_gettime, 284 .settime = mlx4_en_phc_settime, 285 .enable = mlx4_en_phc_enable, 286 }; 287 288 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev) 289 { 290 struct mlx4_dev *dev = mdev->dev; 291 unsigned long flags; 292 u64 ns; 293 294 rwlock_init(&mdev->clock_lock); 295 296 memset(&mdev->cycles, 0, sizeof(mdev->cycles)); 297 mdev->cycles.read = mlx4_en_read_clock; 298 mdev->cycles.mask = CLOCKSOURCE_MASK(48); 299 /* Using shift to make calculation more accurate. Since current HW 300 * clock frequency is 427 MHz, and cycles are given using a 48 bits 301 * register, the biggest shift when calculating using u64, is 14 302 * (max_cycles * multiplier < 2^64) 303 */ 304 mdev->cycles.shift = 14; 305 mdev->cycles.mult = 306 clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift); 307 mdev->nominal_c_mult = mdev->cycles.mult; 308 309 write_lock_irqsave(&mdev->clock_lock, flags); 310 timecounter_init(&mdev->clock, &mdev->cycles, 311 ktime_to_ns(ktime_get_real())); 312 write_unlock_irqrestore(&mdev->clock_lock, flags); 313 314 /* Calculate period in seconds to call the overflow watchdog - to make 315 * sure counter is checked at least once every wrap around. 316 */ 317 ns = cyclecounter_cyc2ns(&mdev->cycles, mdev->cycles.mask); 318 do_div(ns, NSEC_PER_SEC / 2 / HZ); 319 mdev->overflow_period = ns; 320 321 /* Configure the PHC */ 322 mdev->ptp_clock_info = mlx4_en_ptp_clock_info; 323 snprintf(mdev->ptp_clock_info.name, 16, "mlx4 ptp"); 324 325 mdev->ptp_clock = ptp_clock_register(&mdev->ptp_clock_info, 326 &mdev->pdev->dev); 327 if (IS_ERR(mdev->ptp_clock)) { 328 mdev->ptp_clock = NULL; 329 mlx4_err(mdev, "ptp_clock_register failed\n"); 330 } else { 331 mlx4_info(mdev, "registered PHC clock\n"); 332 } 333 334 } 335