1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/sched.h> 36 #include <linux/slab.h> 37 #include <linux/export.h> 38 #include <linux/pci.h> 39 #include <linux/errno.h> 40 41 #include <linux/mlx4/cmd.h> 42 #include <linux/mlx4/device.h> 43 #include <linux/semaphore.h> 44 #include <rdma/ib_smi.h> 45 46 #include <asm/io.h> 47 48 #include "mlx4.h" 49 #include "fw.h" 50 51 #define CMD_POLL_TOKEN 0xffff 52 #define INBOX_MASK 0xffffffffffffff00ULL 53 54 #define CMD_CHAN_VER 1 55 #define CMD_CHAN_IF_REV 1 56 57 enum { 58 /* command completed successfully: */ 59 CMD_STAT_OK = 0x00, 60 /* Internal error (such as a bus error) occurred while processing command: */ 61 CMD_STAT_INTERNAL_ERR = 0x01, 62 /* Operation/command not supported or opcode modifier not supported: */ 63 CMD_STAT_BAD_OP = 0x02, 64 /* Parameter not supported or parameter out of range: */ 65 CMD_STAT_BAD_PARAM = 0x03, 66 /* System not enabled or bad system state: */ 67 CMD_STAT_BAD_SYS_STATE = 0x04, 68 /* Attempt to access reserved or unallocaterd resource: */ 69 CMD_STAT_BAD_RESOURCE = 0x05, 70 /* Requested resource is currently executing a command, or is otherwise busy: */ 71 CMD_STAT_RESOURCE_BUSY = 0x06, 72 /* Required capability exceeds device limits: */ 73 CMD_STAT_EXCEED_LIM = 0x08, 74 /* Resource is not in the appropriate state or ownership: */ 75 CMD_STAT_BAD_RES_STATE = 0x09, 76 /* Index out of range: */ 77 CMD_STAT_BAD_INDEX = 0x0a, 78 /* FW image corrupted: */ 79 CMD_STAT_BAD_NVMEM = 0x0b, 80 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */ 81 CMD_STAT_ICM_ERROR = 0x0c, 82 /* Attempt to modify a QP/EE which is not in the presumed state: */ 83 CMD_STAT_BAD_QP_STATE = 0x10, 84 /* Bad segment parameters (Address/Size): */ 85 CMD_STAT_BAD_SEG_PARAM = 0x20, 86 /* Memory Region has Memory Windows bound to: */ 87 CMD_STAT_REG_BOUND = 0x21, 88 /* HCA local attached memory not present: */ 89 CMD_STAT_LAM_NOT_PRE = 0x22, 90 /* Bad management packet (silently discarded): */ 91 CMD_STAT_BAD_PKT = 0x30, 92 /* More outstanding CQEs in CQ than new CQ size: */ 93 CMD_STAT_BAD_SIZE = 0x40, 94 /* Multi Function device support required: */ 95 CMD_STAT_MULTI_FUNC_REQ = 0x50, 96 }; 97 98 enum { 99 HCR_IN_PARAM_OFFSET = 0x00, 100 HCR_IN_MODIFIER_OFFSET = 0x08, 101 HCR_OUT_PARAM_OFFSET = 0x0c, 102 HCR_TOKEN_OFFSET = 0x14, 103 HCR_STATUS_OFFSET = 0x18, 104 105 HCR_OPMOD_SHIFT = 12, 106 HCR_T_BIT = 21, 107 HCR_E_BIT = 22, 108 HCR_GO_BIT = 23 109 }; 110 111 enum { 112 GO_BIT_TIMEOUT_MSECS = 10000 113 }; 114 115 enum mlx4_vlan_transition { 116 MLX4_VLAN_TRANSITION_VST_VST = 0, 117 MLX4_VLAN_TRANSITION_VST_VGT = 1, 118 MLX4_VLAN_TRANSITION_VGT_VST = 2, 119 MLX4_VLAN_TRANSITION_VGT_VGT = 3, 120 }; 121 122 123 struct mlx4_cmd_context { 124 struct completion done; 125 int result; 126 int next; 127 u64 out_param; 128 u16 token; 129 u8 fw_status; 130 }; 131 132 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave, 133 struct mlx4_vhcr_cmd *in_vhcr); 134 135 static int mlx4_status_to_errno(u8 status) 136 { 137 static const int trans_table[] = { 138 [CMD_STAT_INTERNAL_ERR] = -EIO, 139 [CMD_STAT_BAD_OP] = -EPERM, 140 [CMD_STAT_BAD_PARAM] = -EINVAL, 141 [CMD_STAT_BAD_SYS_STATE] = -ENXIO, 142 [CMD_STAT_BAD_RESOURCE] = -EBADF, 143 [CMD_STAT_RESOURCE_BUSY] = -EBUSY, 144 [CMD_STAT_EXCEED_LIM] = -ENOMEM, 145 [CMD_STAT_BAD_RES_STATE] = -EBADF, 146 [CMD_STAT_BAD_INDEX] = -EBADF, 147 [CMD_STAT_BAD_NVMEM] = -EFAULT, 148 [CMD_STAT_ICM_ERROR] = -ENFILE, 149 [CMD_STAT_BAD_QP_STATE] = -EINVAL, 150 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT, 151 [CMD_STAT_REG_BOUND] = -EBUSY, 152 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN, 153 [CMD_STAT_BAD_PKT] = -EINVAL, 154 [CMD_STAT_BAD_SIZE] = -ENOMEM, 155 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES, 156 }; 157 158 if (status >= ARRAY_SIZE(trans_table) || 159 (status != CMD_STAT_OK && trans_table[status] == 0)) 160 return -EIO; 161 162 return trans_table[status]; 163 } 164 165 static u8 mlx4_errno_to_status(int errno) 166 { 167 switch (errno) { 168 case -EPERM: 169 return CMD_STAT_BAD_OP; 170 case -EINVAL: 171 return CMD_STAT_BAD_PARAM; 172 case -ENXIO: 173 return CMD_STAT_BAD_SYS_STATE; 174 case -EBUSY: 175 return CMD_STAT_RESOURCE_BUSY; 176 case -ENOMEM: 177 return CMD_STAT_EXCEED_LIM; 178 case -ENFILE: 179 return CMD_STAT_ICM_ERROR; 180 default: 181 return CMD_STAT_INTERNAL_ERR; 182 } 183 } 184 185 static int comm_pending(struct mlx4_dev *dev) 186 { 187 struct mlx4_priv *priv = mlx4_priv(dev); 188 u32 status = readl(&priv->mfunc.comm->slave_read); 189 190 return (swab32(status) >> 31) != priv->cmd.comm_toggle; 191 } 192 193 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param) 194 { 195 struct mlx4_priv *priv = mlx4_priv(dev); 196 u32 val; 197 198 priv->cmd.comm_toggle ^= 1; 199 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31); 200 __raw_writel((__force u32) cpu_to_be32(val), 201 &priv->mfunc.comm->slave_write); 202 mmiowb(); 203 } 204 205 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param, 206 unsigned long timeout) 207 { 208 struct mlx4_priv *priv = mlx4_priv(dev); 209 unsigned long end; 210 int err = 0; 211 int ret_from_pending = 0; 212 213 /* First, verify that the master reports correct status */ 214 if (comm_pending(dev)) { 215 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n", 216 priv->cmd.comm_toggle, cmd); 217 return -EAGAIN; 218 } 219 220 /* Write command */ 221 down(&priv->cmd.poll_sem); 222 mlx4_comm_cmd_post(dev, cmd, param); 223 224 end = msecs_to_jiffies(timeout) + jiffies; 225 while (comm_pending(dev) && time_before(jiffies, end)) 226 cond_resched(); 227 ret_from_pending = comm_pending(dev); 228 if (ret_from_pending) { 229 /* check if the slave is trying to boot in the middle of 230 * FLR process. The only non-zero result in the RESET command 231 * is MLX4_DELAY_RESET_SLAVE*/ 232 if ((MLX4_COMM_CMD_RESET == cmd)) { 233 err = MLX4_DELAY_RESET_SLAVE; 234 } else { 235 mlx4_warn(dev, "Communication channel timed out\n"); 236 err = -ETIMEDOUT; 237 } 238 } 239 240 up(&priv->cmd.poll_sem); 241 return err; 242 } 243 244 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op, 245 u16 param, unsigned long timeout) 246 { 247 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 248 struct mlx4_cmd_context *context; 249 unsigned long end; 250 int err = 0; 251 252 down(&cmd->event_sem); 253 254 spin_lock(&cmd->context_lock); 255 BUG_ON(cmd->free_head < 0); 256 context = &cmd->context[cmd->free_head]; 257 context->token += cmd->token_mask + 1; 258 cmd->free_head = context->next; 259 spin_unlock(&cmd->context_lock); 260 261 init_completion(&context->done); 262 263 mlx4_comm_cmd_post(dev, op, param); 264 265 if (!wait_for_completion_timeout(&context->done, 266 msecs_to_jiffies(timeout))) { 267 mlx4_warn(dev, "communication channel command 0x%x timed out\n", 268 op); 269 err = -EBUSY; 270 goto out; 271 } 272 273 err = context->result; 274 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) { 275 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n", 276 op, context->fw_status); 277 goto out; 278 } 279 280 out: 281 /* wait for comm channel ready 282 * this is necessary for prevention the race 283 * when switching between event to polling mode 284 */ 285 end = msecs_to_jiffies(timeout) + jiffies; 286 while (comm_pending(dev) && time_before(jiffies, end)) 287 cond_resched(); 288 289 spin_lock(&cmd->context_lock); 290 context->next = cmd->free_head; 291 cmd->free_head = context - cmd->context; 292 spin_unlock(&cmd->context_lock); 293 294 up(&cmd->event_sem); 295 return err; 296 } 297 298 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 299 unsigned long timeout) 300 { 301 if (mlx4_priv(dev)->cmd.use_events) 302 return mlx4_comm_cmd_wait(dev, cmd, param, timeout); 303 return mlx4_comm_cmd_poll(dev, cmd, param, timeout); 304 } 305 306 static int cmd_pending(struct mlx4_dev *dev) 307 { 308 u32 status; 309 310 if (pci_channel_offline(dev->pdev)) 311 return -EIO; 312 313 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET); 314 315 return (status & swab32(1 << HCR_GO_BIT)) || 316 (mlx4_priv(dev)->cmd.toggle == 317 !!(status & swab32(1 << HCR_T_BIT))); 318 } 319 320 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param, 321 u32 in_modifier, u8 op_modifier, u16 op, u16 token, 322 int event) 323 { 324 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 325 u32 __iomem *hcr = cmd->hcr; 326 int ret = -EAGAIN; 327 unsigned long end; 328 329 mutex_lock(&cmd->hcr_mutex); 330 331 if (pci_channel_offline(dev->pdev)) { 332 /* 333 * Device is going through error recovery 334 * and cannot accept commands. 335 */ 336 ret = -EIO; 337 goto out; 338 } 339 340 end = jiffies; 341 if (event) 342 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS); 343 344 while (cmd_pending(dev)) { 345 if (pci_channel_offline(dev->pdev)) { 346 /* 347 * Device is going through error recovery 348 * and cannot accept commands. 349 */ 350 ret = -EIO; 351 goto out; 352 } 353 354 if (time_after_eq(jiffies, end)) { 355 mlx4_err(dev, "%s:cmd_pending failed\n", __func__); 356 goto out; 357 } 358 cond_resched(); 359 } 360 361 /* 362 * We use writel (instead of something like memcpy_toio) 363 * because writes of less than 32 bits to the HCR don't work 364 * (and some architectures such as ia64 implement memcpy_toio 365 * in terms of writeb). 366 */ 367 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0); 368 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1); 369 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2); 370 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3); 371 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4); 372 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5); 373 374 /* __raw_writel may not order writes. */ 375 wmb(); 376 377 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | 378 (cmd->toggle << HCR_T_BIT) | 379 (event ? (1 << HCR_E_BIT) : 0) | 380 (op_modifier << HCR_OPMOD_SHIFT) | 381 op), hcr + 6); 382 383 /* 384 * Make sure that our HCR writes don't get mixed in with 385 * writes from another CPU starting a FW command. 386 */ 387 mmiowb(); 388 389 cmd->toggle = cmd->toggle ^ 1; 390 391 ret = 0; 392 393 out: 394 mutex_unlock(&cmd->hcr_mutex); 395 return ret; 396 } 397 398 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 399 int out_is_imm, u32 in_modifier, u8 op_modifier, 400 u16 op, unsigned long timeout) 401 { 402 struct mlx4_priv *priv = mlx4_priv(dev); 403 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr; 404 int ret; 405 406 mutex_lock(&priv->cmd.slave_cmd_mutex); 407 408 vhcr->in_param = cpu_to_be64(in_param); 409 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0; 410 vhcr->in_modifier = cpu_to_be32(in_modifier); 411 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff)); 412 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN); 413 vhcr->status = 0; 414 vhcr->flags = !!(priv->cmd.use_events) << 6; 415 416 if (mlx4_is_master(dev)) { 417 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr); 418 if (!ret) { 419 if (out_is_imm) { 420 if (out_param) 421 *out_param = 422 be64_to_cpu(vhcr->out_param); 423 else { 424 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n", 425 op); 426 vhcr->status = CMD_STAT_BAD_PARAM; 427 } 428 } 429 ret = mlx4_status_to_errno(vhcr->status); 430 } 431 } else { 432 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, 433 MLX4_COMM_TIME + timeout); 434 if (!ret) { 435 if (out_is_imm) { 436 if (out_param) 437 *out_param = 438 be64_to_cpu(vhcr->out_param); 439 else { 440 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n", 441 op); 442 vhcr->status = CMD_STAT_BAD_PARAM; 443 } 444 } 445 ret = mlx4_status_to_errno(vhcr->status); 446 } else 447 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n", 448 op); 449 } 450 451 mutex_unlock(&priv->cmd.slave_cmd_mutex); 452 return ret; 453 } 454 455 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 456 int out_is_imm, u32 in_modifier, u8 op_modifier, 457 u16 op, unsigned long timeout) 458 { 459 struct mlx4_priv *priv = mlx4_priv(dev); 460 void __iomem *hcr = priv->cmd.hcr; 461 int err = 0; 462 unsigned long end; 463 u32 stat; 464 465 down(&priv->cmd.poll_sem); 466 467 if (pci_channel_offline(dev->pdev)) { 468 /* 469 * Device is going through error recovery 470 * and cannot accept commands. 471 */ 472 err = -EIO; 473 goto out; 474 } 475 476 if (out_is_imm && !out_param) { 477 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n", 478 op); 479 err = -EINVAL; 480 goto out; 481 } 482 483 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0, 484 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0); 485 if (err) 486 goto out; 487 488 end = msecs_to_jiffies(timeout) + jiffies; 489 while (cmd_pending(dev) && time_before(jiffies, end)) { 490 if (pci_channel_offline(dev->pdev)) { 491 /* 492 * Device is going through error recovery 493 * and cannot accept commands. 494 */ 495 err = -EIO; 496 goto out; 497 } 498 499 cond_resched(); 500 } 501 502 if (cmd_pending(dev)) { 503 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n", 504 op); 505 err = -ETIMEDOUT; 506 goto out; 507 } 508 509 if (out_is_imm) 510 *out_param = 511 (u64) be32_to_cpu((__force __be32) 512 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 | 513 (u64) be32_to_cpu((__force __be32) 514 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4)); 515 stat = be32_to_cpu((__force __be32) 516 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24; 517 err = mlx4_status_to_errno(stat); 518 if (err) 519 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n", 520 op, stat); 521 522 out: 523 up(&priv->cmd.poll_sem); 524 return err; 525 } 526 527 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param) 528 { 529 struct mlx4_priv *priv = mlx4_priv(dev); 530 struct mlx4_cmd_context *context = 531 &priv->cmd.context[token & priv->cmd.token_mask]; 532 533 /* previously timed out command completing at long last */ 534 if (token != context->token) 535 return; 536 537 context->fw_status = status; 538 context->result = mlx4_status_to_errno(status); 539 context->out_param = out_param; 540 541 complete(&context->done); 542 } 543 544 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 545 int out_is_imm, u32 in_modifier, u8 op_modifier, 546 u16 op, unsigned long timeout) 547 { 548 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 549 struct mlx4_cmd_context *context; 550 int err = 0; 551 552 down(&cmd->event_sem); 553 554 spin_lock(&cmd->context_lock); 555 BUG_ON(cmd->free_head < 0); 556 context = &cmd->context[cmd->free_head]; 557 context->token += cmd->token_mask + 1; 558 cmd->free_head = context->next; 559 spin_unlock(&cmd->context_lock); 560 561 if (out_is_imm && !out_param) { 562 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n", 563 op); 564 err = -EINVAL; 565 goto out; 566 } 567 568 init_completion(&context->done); 569 570 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0, 571 in_modifier, op_modifier, op, context->token, 1); 572 573 if (!wait_for_completion_timeout(&context->done, 574 msecs_to_jiffies(timeout))) { 575 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n", 576 op); 577 err = -EBUSY; 578 goto out; 579 } 580 581 err = context->result; 582 if (err) { 583 /* Since we do not want to have this error message always 584 * displayed at driver start when there are ConnectX2 HCAs 585 * on the host, we deprecate the error message for this 586 * specific command/input_mod/opcode_mod/fw-status to be debug. 587 */ 588 if (op == MLX4_CMD_SET_PORT && in_modifier == 1 && 589 op_modifier == 0 && context->fw_status == CMD_STAT_BAD_SIZE) 590 mlx4_dbg(dev, "command 0x%x failed: fw status = 0x%x\n", 591 op, context->fw_status); 592 else 593 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n", 594 op, context->fw_status); 595 goto out; 596 } 597 598 if (out_is_imm) 599 *out_param = context->out_param; 600 601 out: 602 spin_lock(&cmd->context_lock); 603 context->next = cmd->free_head; 604 cmd->free_head = context - cmd->context; 605 spin_unlock(&cmd->context_lock); 606 607 up(&cmd->event_sem); 608 return err; 609 } 610 611 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 612 int out_is_imm, u32 in_modifier, u8 op_modifier, 613 u16 op, unsigned long timeout, int native) 614 { 615 if (pci_channel_offline(dev->pdev)) 616 return -EIO; 617 618 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) { 619 if (mlx4_priv(dev)->cmd.use_events) 620 return mlx4_cmd_wait(dev, in_param, out_param, 621 out_is_imm, in_modifier, 622 op_modifier, op, timeout); 623 else 624 return mlx4_cmd_poll(dev, in_param, out_param, 625 out_is_imm, in_modifier, 626 op_modifier, op, timeout); 627 } 628 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm, 629 in_modifier, op_modifier, op, timeout); 630 } 631 EXPORT_SYMBOL_GPL(__mlx4_cmd); 632 633 634 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev) 635 { 636 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL, 637 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 638 } 639 640 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr, 641 int slave, u64 slave_addr, 642 int size, int is_read) 643 { 644 u64 in_param; 645 u64 out_param; 646 647 if ((slave_addr & 0xfff) | (master_addr & 0xfff) | 648 (slave & ~0x7f) | (size & 0xff)) { 649 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n", 650 slave_addr, master_addr, slave, size); 651 return -EINVAL; 652 } 653 654 if (is_read) { 655 in_param = (u64) slave | slave_addr; 656 out_param = (u64) dev->caps.function | master_addr; 657 } else { 658 in_param = (u64) dev->caps.function | master_addr; 659 out_param = (u64) slave | slave_addr; 660 } 661 662 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0, 663 MLX4_CMD_ACCESS_MEM, 664 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 665 } 666 667 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey, 668 struct mlx4_cmd_mailbox *inbox, 669 struct mlx4_cmd_mailbox *outbox) 670 { 671 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf); 672 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf); 673 int err; 674 int i; 675 676 if (index & 0x1f) 677 return -EINVAL; 678 679 in_mad->attr_mod = cpu_to_be32(index / 32); 680 681 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3, 682 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C, 683 MLX4_CMD_NATIVE); 684 if (err) 685 return err; 686 687 for (i = 0; i < 32; ++i) 688 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]); 689 690 return err; 691 } 692 693 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table, 694 struct mlx4_cmd_mailbox *inbox, 695 struct mlx4_cmd_mailbox *outbox) 696 { 697 int i; 698 int err; 699 700 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) { 701 err = query_pkey_block(dev, port, i, table + i, inbox, outbox); 702 if (err) 703 return err; 704 } 705 706 return 0; 707 } 708 #define PORT_CAPABILITY_LOCATION_IN_SMP 20 709 #define PORT_STATE_OFFSET 32 710 711 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf) 712 { 713 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP) 714 return IB_PORT_ACTIVE; 715 else 716 return IB_PORT_DOWN; 717 } 718 719 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave, 720 struct mlx4_vhcr *vhcr, 721 struct mlx4_cmd_mailbox *inbox, 722 struct mlx4_cmd_mailbox *outbox, 723 struct mlx4_cmd_info *cmd) 724 { 725 struct ib_smp *smp = inbox->buf; 726 u32 index; 727 u8 port; 728 u8 opcode_modifier; 729 u16 *table; 730 int err; 731 int vidx, pidx; 732 int network_view; 733 struct mlx4_priv *priv = mlx4_priv(dev); 734 struct ib_smp *outsmp = outbox->buf; 735 __be16 *outtab = (__be16 *)(outsmp->data); 736 __be32 slave_cap_mask; 737 __be64 slave_node_guid; 738 739 port = vhcr->in_modifier; 740 741 /* network-view bit is for driver use only, and should not be passed to FW */ 742 opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */ 743 network_view = !!(vhcr->op_modifier & 0x8); 744 745 if (smp->base_version == 1 && 746 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED && 747 smp->class_version == 1) { 748 /* host view is paravirtualized */ 749 if (!network_view && smp->method == IB_MGMT_METHOD_GET) { 750 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) { 751 index = be32_to_cpu(smp->attr_mod); 752 if (port < 1 || port > dev->caps.num_ports) 753 return -EINVAL; 754 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL); 755 if (!table) 756 return -ENOMEM; 757 /* need to get the full pkey table because the paravirtualized 758 * pkeys may be scattered among several pkey blocks. 759 */ 760 err = get_full_pkey_table(dev, port, table, inbox, outbox); 761 if (!err) { 762 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) { 763 pidx = priv->virt2phys_pkey[slave][port - 1][vidx]; 764 outtab[vidx % 32] = cpu_to_be16(table[pidx]); 765 } 766 } 767 kfree(table); 768 return err; 769 } 770 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) { 771 /*get the slave specific caps:*/ 772 /*do the command */ 773 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 774 vhcr->in_modifier, opcode_modifier, 775 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 776 /* modify the response for slaves */ 777 if (!err && slave != mlx4_master_func_num(dev)) { 778 u8 *state = outsmp->data + PORT_STATE_OFFSET; 779 780 *state = (*state & 0xf0) | vf_port_state(dev, port, slave); 781 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port]; 782 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4); 783 } 784 return err; 785 } 786 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) { 787 /* compute slave's gid block */ 788 smp->attr_mod = cpu_to_be32(slave / 8); 789 /* execute cmd */ 790 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 791 vhcr->in_modifier, opcode_modifier, 792 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 793 if (!err) { 794 /* if needed, move slave gid to index 0 */ 795 if (slave % 8) 796 memcpy(outsmp->data, 797 outsmp->data + (slave % 8) * 8, 8); 798 /* delete all other gids */ 799 memset(outsmp->data + 8, 0, 56); 800 } 801 return err; 802 } 803 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) { 804 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 805 vhcr->in_modifier, opcode_modifier, 806 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 807 if (!err) { 808 slave_node_guid = mlx4_get_slave_node_guid(dev, slave); 809 memcpy(outsmp->data + 12, &slave_node_guid, 8); 810 } 811 return err; 812 } 813 } 814 } 815 816 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs. 817 * These are the MADs used by ib verbs (such as ib_query_gids). 818 */ 819 if (slave != mlx4_master_func_num(dev) && 820 !mlx4_vf_smi_enabled(dev, slave, port)) { 821 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED && 822 smp->method == IB_MGMT_METHOD_GET) || network_view) { 823 mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n", 824 slave, smp->method, smp->mgmt_class, 825 network_view ? "Network" : "Host", 826 be16_to_cpu(smp->attr_id)); 827 return -EPERM; 828 } 829 } 830 831 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, 832 vhcr->in_modifier, opcode_modifier, 833 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 834 } 835 836 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave, 837 struct mlx4_vhcr *vhcr, 838 struct mlx4_cmd_mailbox *inbox, 839 struct mlx4_cmd_mailbox *outbox, 840 struct mlx4_cmd_info *cmd) 841 { 842 return -EPERM; 843 } 844 845 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 846 struct mlx4_vhcr *vhcr, 847 struct mlx4_cmd_mailbox *inbox, 848 struct mlx4_cmd_mailbox *outbox, 849 struct mlx4_cmd_info *cmd) 850 { 851 u64 in_param; 852 u64 out_param; 853 int err; 854 855 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param; 856 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param; 857 if (cmd->encode_slave_id) { 858 in_param &= 0xffffffffffffff00ll; 859 in_param |= slave; 860 } 861 862 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm, 863 vhcr->in_modifier, vhcr->op_modifier, vhcr->op, 864 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 865 866 if (cmd->out_is_imm) 867 vhcr->out_param = out_param; 868 869 return err; 870 } 871 872 static struct mlx4_cmd_info cmd_info[] = { 873 { 874 .opcode = MLX4_CMD_QUERY_FW, 875 .has_inbox = false, 876 .has_outbox = true, 877 .out_is_imm = false, 878 .encode_slave_id = false, 879 .verify = NULL, 880 .wrapper = mlx4_QUERY_FW_wrapper 881 }, 882 { 883 .opcode = MLX4_CMD_QUERY_HCA, 884 .has_inbox = false, 885 .has_outbox = true, 886 .out_is_imm = false, 887 .encode_slave_id = false, 888 .verify = NULL, 889 .wrapper = NULL 890 }, 891 { 892 .opcode = MLX4_CMD_QUERY_DEV_CAP, 893 .has_inbox = false, 894 .has_outbox = true, 895 .out_is_imm = false, 896 .encode_slave_id = false, 897 .verify = NULL, 898 .wrapper = mlx4_QUERY_DEV_CAP_wrapper 899 }, 900 { 901 .opcode = MLX4_CMD_QUERY_FUNC_CAP, 902 .has_inbox = false, 903 .has_outbox = true, 904 .out_is_imm = false, 905 .encode_slave_id = false, 906 .verify = NULL, 907 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper 908 }, 909 { 910 .opcode = MLX4_CMD_QUERY_ADAPTER, 911 .has_inbox = false, 912 .has_outbox = true, 913 .out_is_imm = false, 914 .encode_slave_id = false, 915 .verify = NULL, 916 .wrapper = NULL 917 }, 918 { 919 .opcode = MLX4_CMD_INIT_PORT, 920 .has_inbox = false, 921 .has_outbox = false, 922 .out_is_imm = false, 923 .encode_slave_id = false, 924 .verify = NULL, 925 .wrapper = mlx4_INIT_PORT_wrapper 926 }, 927 { 928 .opcode = MLX4_CMD_CLOSE_PORT, 929 .has_inbox = false, 930 .has_outbox = false, 931 .out_is_imm = false, 932 .encode_slave_id = false, 933 .verify = NULL, 934 .wrapper = mlx4_CLOSE_PORT_wrapper 935 }, 936 { 937 .opcode = MLX4_CMD_QUERY_PORT, 938 .has_inbox = false, 939 .has_outbox = true, 940 .out_is_imm = false, 941 .encode_slave_id = false, 942 .verify = NULL, 943 .wrapper = mlx4_QUERY_PORT_wrapper 944 }, 945 { 946 .opcode = MLX4_CMD_SET_PORT, 947 .has_inbox = true, 948 .has_outbox = false, 949 .out_is_imm = false, 950 .encode_slave_id = false, 951 .verify = NULL, 952 .wrapper = mlx4_SET_PORT_wrapper 953 }, 954 { 955 .opcode = MLX4_CMD_MAP_EQ, 956 .has_inbox = false, 957 .has_outbox = false, 958 .out_is_imm = false, 959 .encode_slave_id = false, 960 .verify = NULL, 961 .wrapper = mlx4_MAP_EQ_wrapper 962 }, 963 { 964 .opcode = MLX4_CMD_SW2HW_EQ, 965 .has_inbox = true, 966 .has_outbox = false, 967 .out_is_imm = false, 968 .encode_slave_id = true, 969 .verify = NULL, 970 .wrapper = mlx4_SW2HW_EQ_wrapper 971 }, 972 { 973 .opcode = MLX4_CMD_HW_HEALTH_CHECK, 974 .has_inbox = false, 975 .has_outbox = false, 976 .out_is_imm = false, 977 .encode_slave_id = false, 978 .verify = NULL, 979 .wrapper = NULL 980 }, 981 { 982 .opcode = MLX4_CMD_NOP, 983 .has_inbox = false, 984 .has_outbox = false, 985 .out_is_imm = false, 986 .encode_slave_id = false, 987 .verify = NULL, 988 .wrapper = NULL 989 }, 990 { 991 .opcode = MLX4_CMD_CONFIG_DEV, 992 .has_inbox = false, 993 .has_outbox = true, 994 .out_is_imm = false, 995 .encode_slave_id = false, 996 .verify = NULL, 997 .wrapper = mlx4_CONFIG_DEV_wrapper 998 }, 999 { 1000 .opcode = MLX4_CMD_ALLOC_RES, 1001 .has_inbox = false, 1002 .has_outbox = false, 1003 .out_is_imm = true, 1004 .encode_slave_id = false, 1005 .verify = NULL, 1006 .wrapper = mlx4_ALLOC_RES_wrapper 1007 }, 1008 { 1009 .opcode = MLX4_CMD_FREE_RES, 1010 .has_inbox = false, 1011 .has_outbox = false, 1012 .out_is_imm = false, 1013 .encode_slave_id = false, 1014 .verify = NULL, 1015 .wrapper = mlx4_FREE_RES_wrapper 1016 }, 1017 { 1018 .opcode = MLX4_CMD_SW2HW_MPT, 1019 .has_inbox = true, 1020 .has_outbox = false, 1021 .out_is_imm = false, 1022 .encode_slave_id = true, 1023 .verify = NULL, 1024 .wrapper = mlx4_SW2HW_MPT_wrapper 1025 }, 1026 { 1027 .opcode = MLX4_CMD_QUERY_MPT, 1028 .has_inbox = false, 1029 .has_outbox = true, 1030 .out_is_imm = false, 1031 .encode_slave_id = false, 1032 .verify = NULL, 1033 .wrapper = mlx4_QUERY_MPT_wrapper 1034 }, 1035 { 1036 .opcode = MLX4_CMD_HW2SW_MPT, 1037 .has_inbox = false, 1038 .has_outbox = false, 1039 .out_is_imm = false, 1040 .encode_slave_id = false, 1041 .verify = NULL, 1042 .wrapper = mlx4_HW2SW_MPT_wrapper 1043 }, 1044 { 1045 .opcode = MLX4_CMD_READ_MTT, 1046 .has_inbox = false, 1047 .has_outbox = true, 1048 .out_is_imm = false, 1049 .encode_slave_id = false, 1050 .verify = NULL, 1051 .wrapper = NULL 1052 }, 1053 { 1054 .opcode = MLX4_CMD_WRITE_MTT, 1055 .has_inbox = true, 1056 .has_outbox = false, 1057 .out_is_imm = false, 1058 .encode_slave_id = false, 1059 .verify = NULL, 1060 .wrapper = mlx4_WRITE_MTT_wrapper 1061 }, 1062 { 1063 .opcode = MLX4_CMD_SYNC_TPT, 1064 .has_inbox = true, 1065 .has_outbox = false, 1066 .out_is_imm = false, 1067 .encode_slave_id = false, 1068 .verify = NULL, 1069 .wrapper = NULL 1070 }, 1071 { 1072 .opcode = MLX4_CMD_HW2SW_EQ, 1073 .has_inbox = false, 1074 .has_outbox = true, 1075 .out_is_imm = false, 1076 .encode_slave_id = true, 1077 .verify = NULL, 1078 .wrapper = mlx4_HW2SW_EQ_wrapper 1079 }, 1080 { 1081 .opcode = MLX4_CMD_QUERY_EQ, 1082 .has_inbox = false, 1083 .has_outbox = true, 1084 .out_is_imm = false, 1085 .encode_slave_id = true, 1086 .verify = NULL, 1087 .wrapper = mlx4_QUERY_EQ_wrapper 1088 }, 1089 { 1090 .opcode = MLX4_CMD_SW2HW_CQ, 1091 .has_inbox = true, 1092 .has_outbox = false, 1093 .out_is_imm = false, 1094 .encode_slave_id = true, 1095 .verify = NULL, 1096 .wrapper = mlx4_SW2HW_CQ_wrapper 1097 }, 1098 { 1099 .opcode = MLX4_CMD_HW2SW_CQ, 1100 .has_inbox = false, 1101 .has_outbox = false, 1102 .out_is_imm = false, 1103 .encode_slave_id = false, 1104 .verify = NULL, 1105 .wrapper = mlx4_HW2SW_CQ_wrapper 1106 }, 1107 { 1108 .opcode = MLX4_CMD_QUERY_CQ, 1109 .has_inbox = false, 1110 .has_outbox = true, 1111 .out_is_imm = false, 1112 .encode_slave_id = false, 1113 .verify = NULL, 1114 .wrapper = mlx4_QUERY_CQ_wrapper 1115 }, 1116 { 1117 .opcode = MLX4_CMD_MODIFY_CQ, 1118 .has_inbox = true, 1119 .has_outbox = false, 1120 .out_is_imm = true, 1121 .encode_slave_id = false, 1122 .verify = NULL, 1123 .wrapper = mlx4_MODIFY_CQ_wrapper 1124 }, 1125 { 1126 .opcode = MLX4_CMD_SW2HW_SRQ, 1127 .has_inbox = true, 1128 .has_outbox = false, 1129 .out_is_imm = false, 1130 .encode_slave_id = true, 1131 .verify = NULL, 1132 .wrapper = mlx4_SW2HW_SRQ_wrapper 1133 }, 1134 { 1135 .opcode = MLX4_CMD_HW2SW_SRQ, 1136 .has_inbox = false, 1137 .has_outbox = false, 1138 .out_is_imm = false, 1139 .encode_slave_id = false, 1140 .verify = NULL, 1141 .wrapper = mlx4_HW2SW_SRQ_wrapper 1142 }, 1143 { 1144 .opcode = MLX4_CMD_QUERY_SRQ, 1145 .has_inbox = false, 1146 .has_outbox = true, 1147 .out_is_imm = false, 1148 .encode_slave_id = false, 1149 .verify = NULL, 1150 .wrapper = mlx4_QUERY_SRQ_wrapper 1151 }, 1152 { 1153 .opcode = MLX4_CMD_ARM_SRQ, 1154 .has_inbox = false, 1155 .has_outbox = false, 1156 .out_is_imm = false, 1157 .encode_slave_id = false, 1158 .verify = NULL, 1159 .wrapper = mlx4_ARM_SRQ_wrapper 1160 }, 1161 { 1162 .opcode = MLX4_CMD_RST2INIT_QP, 1163 .has_inbox = true, 1164 .has_outbox = false, 1165 .out_is_imm = false, 1166 .encode_slave_id = true, 1167 .verify = NULL, 1168 .wrapper = mlx4_RST2INIT_QP_wrapper 1169 }, 1170 { 1171 .opcode = MLX4_CMD_INIT2INIT_QP, 1172 .has_inbox = true, 1173 .has_outbox = false, 1174 .out_is_imm = false, 1175 .encode_slave_id = false, 1176 .verify = NULL, 1177 .wrapper = mlx4_INIT2INIT_QP_wrapper 1178 }, 1179 { 1180 .opcode = MLX4_CMD_INIT2RTR_QP, 1181 .has_inbox = true, 1182 .has_outbox = false, 1183 .out_is_imm = false, 1184 .encode_slave_id = false, 1185 .verify = NULL, 1186 .wrapper = mlx4_INIT2RTR_QP_wrapper 1187 }, 1188 { 1189 .opcode = MLX4_CMD_RTR2RTS_QP, 1190 .has_inbox = true, 1191 .has_outbox = false, 1192 .out_is_imm = false, 1193 .encode_slave_id = false, 1194 .verify = NULL, 1195 .wrapper = mlx4_RTR2RTS_QP_wrapper 1196 }, 1197 { 1198 .opcode = MLX4_CMD_RTS2RTS_QP, 1199 .has_inbox = true, 1200 .has_outbox = false, 1201 .out_is_imm = false, 1202 .encode_slave_id = false, 1203 .verify = NULL, 1204 .wrapper = mlx4_RTS2RTS_QP_wrapper 1205 }, 1206 { 1207 .opcode = MLX4_CMD_SQERR2RTS_QP, 1208 .has_inbox = true, 1209 .has_outbox = false, 1210 .out_is_imm = false, 1211 .encode_slave_id = false, 1212 .verify = NULL, 1213 .wrapper = mlx4_SQERR2RTS_QP_wrapper 1214 }, 1215 { 1216 .opcode = MLX4_CMD_2ERR_QP, 1217 .has_inbox = false, 1218 .has_outbox = false, 1219 .out_is_imm = false, 1220 .encode_slave_id = false, 1221 .verify = NULL, 1222 .wrapper = mlx4_GEN_QP_wrapper 1223 }, 1224 { 1225 .opcode = MLX4_CMD_RTS2SQD_QP, 1226 .has_inbox = false, 1227 .has_outbox = false, 1228 .out_is_imm = false, 1229 .encode_slave_id = false, 1230 .verify = NULL, 1231 .wrapper = mlx4_GEN_QP_wrapper 1232 }, 1233 { 1234 .opcode = MLX4_CMD_SQD2SQD_QP, 1235 .has_inbox = true, 1236 .has_outbox = false, 1237 .out_is_imm = false, 1238 .encode_slave_id = false, 1239 .verify = NULL, 1240 .wrapper = mlx4_SQD2SQD_QP_wrapper 1241 }, 1242 { 1243 .opcode = MLX4_CMD_SQD2RTS_QP, 1244 .has_inbox = true, 1245 .has_outbox = false, 1246 .out_is_imm = false, 1247 .encode_slave_id = false, 1248 .verify = NULL, 1249 .wrapper = mlx4_SQD2RTS_QP_wrapper 1250 }, 1251 { 1252 .opcode = MLX4_CMD_2RST_QP, 1253 .has_inbox = false, 1254 .has_outbox = false, 1255 .out_is_imm = false, 1256 .encode_slave_id = false, 1257 .verify = NULL, 1258 .wrapper = mlx4_2RST_QP_wrapper 1259 }, 1260 { 1261 .opcode = MLX4_CMD_QUERY_QP, 1262 .has_inbox = false, 1263 .has_outbox = true, 1264 .out_is_imm = false, 1265 .encode_slave_id = false, 1266 .verify = NULL, 1267 .wrapper = mlx4_GEN_QP_wrapper 1268 }, 1269 { 1270 .opcode = MLX4_CMD_SUSPEND_QP, 1271 .has_inbox = false, 1272 .has_outbox = false, 1273 .out_is_imm = false, 1274 .encode_slave_id = false, 1275 .verify = NULL, 1276 .wrapper = mlx4_GEN_QP_wrapper 1277 }, 1278 { 1279 .opcode = MLX4_CMD_UNSUSPEND_QP, 1280 .has_inbox = false, 1281 .has_outbox = false, 1282 .out_is_imm = false, 1283 .encode_slave_id = false, 1284 .verify = NULL, 1285 .wrapper = mlx4_GEN_QP_wrapper 1286 }, 1287 { 1288 .opcode = MLX4_CMD_UPDATE_QP, 1289 .has_inbox = true, 1290 .has_outbox = false, 1291 .out_is_imm = false, 1292 .encode_slave_id = false, 1293 .verify = NULL, 1294 .wrapper = mlx4_UPDATE_QP_wrapper 1295 }, 1296 { 1297 .opcode = MLX4_CMD_GET_OP_REQ, 1298 .has_inbox = false, 1299 .has_outbox = false, 1300 .out_is_imm = false, 1301 .encode_slave_id = false, 1302 .verify = NULL, 1303 .wrapper = mlx4_CMD_EPERM_wrapper, 1304 }, 1305 { 1306 .opcode = MLX4_CMD_CONF_SPECIAL_QP, 1307 .has_inbox = false, 1308 .has_outbox = false, 1309 .out_is_imm = false, 1310 .encode_slave_id = false, 1311 .verify = NULL, /* XXX verify: only demux can do this */ 1312 .wrapper = NULL 1313 }, 1314 { 1315 .opcode = MLX4_CMD_MAD_IFC, 1316 .has_inbox = true, 1317 .has_outbox = true, 1318 .out_is_imm = false, 1319 .encode_slave_id = false, 1320 .verify = NULL, 1321 .wrapper = mlx4_MAD_IFC_wrapper 1322 }, 1323 { 1324 .opcode = MLX4_CMD_MAD_DEMUX, 1325 .has_inbox = false, 1326 .has_outbox = false, 1327 .out_is_imm = false, 1328 .encode_slave_id = false, 1329 .verify = NULL, 1330 .wrapper = mlx4_CMD_EPERM_wrapper 1331 }, 1332 { 1333 .opcode = MLX4_CMD_QUERY_IF_STAT, 1334 .has_inbox = false, 1335 .has_outbox = true, 1336 .out_is_imm = false, 1337 .encode_slave_id = false, 1338 .verify = NULL, 1339 .wrapper = mlx4_QUERY_IF_STAT_wrapper 1340 }, 1341 { 1342 .opcode = MLX4_CMD_ACCESS_REG, 1343 .has_inbox = true, 1344 .has_outbox = true, 1345 .out_is_imm = false, 1346 .encode_slave_id = false, 1347 .verify = NULL, 1348 .wrapper = mlx4_ACCESS_REG_wrapper, 1349 }, 1350 /* Native multicast commands are not available for guests */ 1351 { 1352 .opcode = MLX4_CMD_QP_ATTACH, 1353 .has_inbox = true, 1354 .has_outbox = false, 1355 .out_is_imm = false, 1356 .encode_slave_id = false, 1357 .verify = NULL, 1358 .wrapper = mlx4_QP_ATTACH_wrapper 1359 }, 1360 { 1361 .opcode = MLX4_CMD_PROMISC, 1362 .has_inbox = false, 1363 .has_outbox = false, 1364 .out_is_imm = false, 1365 .encode_slave_id = false, 1366 .verify = NULL, 1367 .wrapper = mlx4_PROMISC_wrapper 1368 }, 1369 /* Ethernet specific commands */ 1370 { 1371 .opcode = MLX4_CMD_SET_VLAN_FLTR, 1372 .has_inbox = true, 1373 .has_outbox = false, 1374 .out_is_imm = false, 1375 .encode_slave_id = false, 1376 .verify = NULL, 1377 .wrapper = mlx4_SET_VLAN_FLTR_wrapper 1378 }, 1379 { 1380 .opcode = MLX4_CMD_SET_MCAST_FLTR, 1381 .has_inbox = false, 1382 .has_outbox = false, 1383 .out_is_imm = false, 1384 .encode_slave_id = false, 1385 .verify = NULL, 1386 .wrapper = mlx4_SET_MCAST_FLTR_wrapper 1387 }, 1388 { 1389 .opcode = MLX4_CMD_DUMP_ETH_STATS, 1390 .has_inbox = false, 1391 .has_outbox = true, 1392 .out_is_imm = false, 1393 .encode_slave_id = false, 1394 .verify = NULL, 1395 .wrapper = mlx4_DUMP_ETH_STATS_wrapper 1396 }, 1397 { 1398 .opcode = MLX4_CMD_INFORM_FLR_DONE, 1399 .has_inbox = false, 1400 .has_outbox = false, 1401 .out_is_imm = false, 1402 .encode_slave_id = false, 1403 .verify = NULL, 1404 .wrapper = NULL 1405 }, 1406 /* flow steering commands */ 1407 { 1408 .opcode = MLX4_QP_FLOW_STEERING_ATTACH, 1409 .has_inbox = true, 1410 .has_outbox = false, 1411 .out_is_imm = true, 1412 .encode_slave_id = false, 1413 .verify = NULL, 1414 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper 1415 }, 1416 { 1417 .opcode = MLX4_QP_FLOW_STEERING_DETACH, 1418 .has_inbox = false, 1419 .has_outbox = false, 1420 .out_is_imm = false, 1421 .encode_slave_id = false, 1422 .verify = NULL, 1423 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper 1424 }, 1425 { 1426 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE, 1427 .has_inbox = false, 1428 .has_outbox = false, 1429 .out_is_imm = false, 1430 .encode_slave_id = false, 1431 .verify = NULL, 1432 .wrapper = mlx4_CMD_EPERM_wrapper 1433 }, 1434 }; 1435 1436 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave, 1437 struct mlx4_vhcr_cmd *in_vhcr) 1438 { 1439 struct mlx4_priv *priv = mlx4_priv(dev); 1440 struct mlx4_cmd_info *cmd = NULL; 1441 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr; 1442 struct mlx4_vhcr *vhcr; 1443 struct mlx4_cmd_mailbox *inbox = NULL; 1444 struct mlx4_cmd_mailbox *outbox = NULL; 1445 u64 in_param; 1446 u64 out_param; 1447 int ret = 0; 1448 int i; 1449 int err = 0; 1450 1451 /* Create sw representation of Virtual HCR */ 1452 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL); 1453 if (!vhcr) 1454 return -ENOMEM; 1455 1456 /* DMA in the vHCR */ 1457 if (!in_vhcr) { 1458 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave, 1459 priv->mfunc.master.slave_state[slave].vhcr_dma, 1460 ALIGN(sizeof(struct mlx4_vhcr_cmd), 1461 MLX4_ACCESS_MEM_ALIGN), 1); 1462 if (ret) { 1463 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n", 1464 __func__, ret); 1465 kfree(vhcr); 1466 return ret; 1467 } 1468 } 1469 1470 /* Fill SW VHCR fields */ 1471 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param); 1472 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param); 1473 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier); 1474 vhcr->token = be16_to_cpu(vhcr_cmd->token); 1475 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff; 1476 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12); 1477 vhcr->e_bit = vhcr_cmd->flags & (1 << 6); 1478 1479 /* Lookup command */ 1480 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) { 1481 if (vhcr->op == cmd_info[i].opcode) { 1482 cmd = &cmd_info[i]; 1483 break; 1484 } 1485 } 1486 if (!cmd) { 1487 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n", 1488 vhcr->op, slave); 1489 vhcr_cmd->status = CMD_STAT_BAD_PARAM; 1490 goto out_status; 1491 } 1492 1493 /* Read inbox */ 1494 if (cmd->has_inbox) { 1495 vhcr->in_param &= INBOX_MASK; 1496 inbox = mlx4_alloc_cmd_mailbox(dev); 1497 if (IS_ERR(inbox)) { 1498 vhcr_cmd->status = CMD_STAT_BAD_SIZE; 1499 inbox = NULL; 1500 goto out_status; 1501 } 1502 1503 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave, 1504 vhcr->in_param, 1505 MLX4_MAILBOX_SIZE, 1)) { 1506 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n", 1507 __func__, cmd->opcode); 1508 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR; 1509 goto out_status; 1510 } 1511 } 1512 1513 /* Apply permission and bound checks if applicable */ 1514 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) { 1515 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n", 1516 vhcr->op, slave, vhcr->in_modifier); 1517 vhcr_cmd->status = CMD_STAT_BAD_OP; 1518 goto out_status; 1519 } 1520 1521 /* Allocate outbox */ 1522 if (cmd->has_outbox) { 1523 outbox = mlx4_alloc_cmd_mailbox(dev); 1524 if (IS_ERR(outbox)) { 1525 vhcr_cmd->status = CMD_STAT_BAD_SIZE; 1526 outbox = NULL; 1527 goto out_status; 1528 } 1529 } 1530 1531 /* Execute the command! */ 1532 if (cmd->wrapper) { 1533 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox, 1534 cmd); 1535 if (cmd->out_is_imm) 1536 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param); 1537 } else { 1538 in_param = cmd->has_inbox ? (u64) inbox->dma : 1539 vhcr->in_param; 1540 out_param = cmd->has_outbox ? (u64) outbox->dma : 1541 vhcr->out_param; 1542 err = __mlx4_cmd(dev, in_param, &out_param, 1543 cmd->out_is_imm, vhcr->in_modifier, 1544 vhcr->op_modifier, vhcr->op, 1545 MLX4_CMD_TIME_CLASS_A, 1546 MLX4_CMD_NATIVE); 1547 1548 if (cmd->out_is_imm) { 1549 vhcr->out_param = out_param; 1550 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param); 1551 } 1552 } 1553 1554 if (err) { 1555 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n", 1556 vhcr->op, slave, vhcr->errno, err); 1557 vhcr_cmd->status = mlx4_errno_to_status(err); 1558 goto out_status; 1559 } 1560 1561 1562 /* Write outbox if command completed successfully */ 1563 if (cmd->has_outbox && !vhcr_cmd->status) { 1564 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave, 1565 vhcr->out_param, 1566 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED); 1567 if (ret) { 1568 /* If we failed to write back the outbox after the 1569 *command was successfully executed, we must fail this 1570 * slave, as it is now in undefined state */ 1571 mlx4_err(dev, "%s:Failed writing outbox\n", __func__); 1572 goto out; 1573 } 1574 } 1575 1576 out_status: 1577 /* DMA back vhcr result */ 1578 if (!in_vhcr) { 1579 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave, 1580 priv->mfunc.master.slave_state[slave].vhcr_dma, 1581 ALIGN(sizeof(struct mlx4_vhcr), 1582 MLX4_ACCESS_MEM_ALIGN), 1583 MLX4_CMD_WRAPPED); 1584 if (ret) 1585 mlx4_err(dev, "%s:Failed writing vhcr result\n", 1586 __func__); 1587 else if (vhcr->e_bit && 1588 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe)) 1589 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n", 1590 slave); 1591 } 1592 1593 out: 1594 kfree(vhcr); 1595 mlx4_free_cmd_mailbox(dev, inbox); 1596 mlx4_free_cmd_mailbox(dev, outbox); 1597 return ret; 1598 } 1599 1600 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv, 1601 int slave, int port) 1602 { 1603 struct mlx4_vport_oper_state *vp_oper; 1604 struct mlx4_vport_state *vp_admin; 1605 struct mlx4_vf_immed_vlan_work *work; 1606 struct mlx4_dev *dev = &(priv->dev); 1607 int err; 1608 int admin_vlan_ix = NO_INDX; 1609 1610 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; 1611 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; 1612 1613 if (vp_oper->state.default_vlan == vp_admin->default_vlan && 1614 vp_oper->state.default_qos == vp_admin->default_qos && 1615 vp_oper->state.link_state == vp_admin->link_state) 1616 return 0; 1617 1618 if (!(priv->mfunc.master.slave_state[slave].active && 1619 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) { 1620 /* even if the UPDATE_QP command isn't supported, we still want 1621 * to set this VF link according to the admin directive 1622 */ 1623 vp_oper->state.link_state = vp_admin->link_state; 1624 return -1; 1625 } 1626 1627 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n", 1628 slave, port); 1629 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n", 1630 vp_admin->default_vlan, vp_admin->default_qos, 1631 vp_admin->link_state); 1632 1633 work = kzalloc(sizeof(*work), GFP_KERNEL); 1634 if (!work) 1635 return -ENOMEM; 1636 1637 if (vp_oper->state.default_vlan != vp_admin->default_vlan) { 1638 if (MLX4_VGT != vp_admin->default_vlan) { 1639 err = __mlx4_register_vlan(&priv->dev, port, 1640 vp_admin->default_vlan, 1641 &admin_vlan_ix); 1642 if (err) { 1643 kfree(work); 1644 mlx4_warn(&priv->dev, 1645 "No vlan resources slave %d, port %d\n", 1646 slave, port); 1647 return err; 1648 } 1649 } else { 1650 admin_vlan_ix = NO_INDX; 1651 } 1652 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN; 1653 mlx4_dbg(&priv->dev, 1654 "alloc vlan %d idx %d slave %d port %d\n", 1655 (int)(vp_admin->default_vlan), 1656 admin_vlan_ix, slave, port); 1657 } 1658 1659 /* save original vlan ix and vlan id */ 1660 work->orig_vlan_id = vp_oper->state.default_vlan; 1661 work->orig_vlan_ix = vp_oper->vlan_idx; 1662 1663 /* handle new qos */ 1664 if (vp_oper->state.default_qos != vp_admin->default_qos) 1665 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS; 1666 1667 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN) 1668 vp_oper->vlan_idx = admin_vlan_ix; 1669 1670 vp_oper->state.default_vlan = vp_admin->default_vlan; 1671 vp_oper->state.default_qos = vp_admin->default_qos; 1672 vp_oper->state.link_state = vp_admin->link_state; 1673 1674 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE) 1675 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE; 1676 1677 /* iterate over QPs owned by this slave, using UPDATE_QP */ 1678 work->port = port; 1679 work->slave = slave; 1680 work->qos = vp_oper->state.default_qos; 1681 work->vlan_id = vp_oper->state.default_vlan; 1682 work->vlan_ix = vp_oper->vlan_idx; 1683 work->priv = priv; 1684 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler); 1685 queue_work(priv->mfunc.master.comm_wq, &work->work); 1686 1687 return 0; 1688 } 1689 1690 1691 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave) 1692 { 1693 int port, err; 1694 struct mlx4_vport_state *vp_admin; 1695 struct mlx4_vport_oper_state *vp_oper; 1696 struct mlx4_active_ports actv_ports = mlx4_get_active_ports( 1697 &priv->dev, slave); 1698 int min_port = find_first_bit(actv_ports.ports, 1699 priv->dev.caps.num_ports) + 1; 1700 int max_port = min_port - 1 + 1701 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports); 1702 1703 for (port = min_port; port <= max_port; port++) { 1704 if (!test_bit(port - 1, actv_ports.ports)) 1705 continue; 1706 priv->mfunc.master.vf_oper[slave].smi_enabled[port] = 1707 priv->mfunc.master.vf_admin[slave].enable_smi[port]; 1708 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; 1709 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; 1710 vp_oper->state = *vp_admin; 1711 if (MLX4_VGT != vp_admin->default_vlan) { 1712 err = __mlx4_register_vlan(&priv->dev, port, 1713 vp_admin->default_vlan, &(vp_oper->vlan_idx)); 1714 if (err) { 1715 vp_oper->vlan_idx = NO_INDX; 1716 mlx4_warn(&priv->dev, 1717 "No vlan resources slave %d, port %d\n", 1718 slave, port); 1719 return err; 1720 } 1721 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n", 1722 (int)(vp_oper->state.default_vlan), 1723 vp_oper->vlan_idx, slave, port); 1724 } 1725 if (vp_admin->spoofchk) { 1726 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev, 1727 port, 1728 vp_admin->mac); 1729 if (0 > vp_oper->mac_idx) { 1730 err = vp_oper->mac_idx; 1731 vp_oper->mac_idx = NO_INDX; 1732 mlx4_warn(&priv->dev, 1733 "No mac resources slave %d, port %d\n", 1734 slave, port); 1735 return err; 1736 } 1737 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n", 1738 vp_oper->state.mac, vp_oper->mac_idx, slave, port); 1739 } 1740 } 1741 return 0; 1742 } 1743 1744 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave) 1745 { 1746 int port; 1747 struct mlx4_vport_oper_state *vp_oper; 1748 struct mlx4_active_ports actv_ports = mlx4_get_active_ports( 1749 &priv->dev, slave); 1750 int min_port = find_first_bit(actv_ports.ports, 1751 priv->dev.caps.num_ports) + 1; 1752 int max_port = min_port - 1 + 1753 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports); 1754 1755 1756 for (port = min_port; port <= max_port; port++) { 1757 if (!test_bit(port - 1, actv_ports.ports)) 1758 continue; 1759 priv->mfunc.master.vf_oper[slave].smi_enabled[port] = 1760 MLX4_VF_SMI_DISABLED; 1761 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; 1762 if (NO_INDX != vp_oper->vlan_idx) { 1763 __mlx4_unregister_vlan(&priv->dev, 1764 port, vp_oper->state.default_vlan); 1765 vp_oper->vlan_idx = NO_INDX; 1766 } 1767 if (NO_INDX != vp_oper->mac_idx) { 1768 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac); 1769 vp_oper->mac_idx = NO_INDX; 1770 } 1771 } 1772 return; 1773 } 1774 1775 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd, 1776 u16 param, u8 toggle) 1777 { 1778 struct mlx4_priv *priv = mlx4_priv(dev); 1779 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; 1780 u32 reply; 1781 u8 is_going_down = 0; 1782 int i; 1783 unsigned long flags; 1784 1785 slave_state[slave].comm_toggle ^= 1; 1786 reply = (u32) slave_state[slave].comm_toggle << 31; 1787 if (toggle != slave_state[slave].comm_toggle) { 1788 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n", 1789 toggle, slave); 1790 goto reset_slave; 1791 } 1792 if (cmd == MLX4_COMM_CMD_RESET) { 1793 mlx4_warn(dev, "Received reset from slave:%d\n", slave); 1794 slave_state[slave].active = false; 1795 slave_state[slave].old_vlan_api = false; 1796 mlx4_master_deactivate_admin_state(priv, slave); 1797 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) { 1798 slave_state[slave].event_eq[i].eqn = -1; 1799 slave_state[slave].event_eq[i].token = 0; 1800 } 1801 /*check if we are in the middle of FLR process, 1802 if so return "retry" status to the slave*/ 1803 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) 1804 goto inform_slave_state; 1805 1806 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave); 1807 1808 /* write the version in the event field */ 1809 reply |= mlx4_comm_get_version(); 1810 1811 goto reset_slave; 1812 } 1813 /*command from slave in the middle of FLR*/ 1814 if (cmd != MLX4_COMM_CMD_RESET && 1815 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) { 1816 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n", 1817 slave, cmd); 1818 return; 1819 } 1820 1821 switch (cmd) { 1822 case MLX4_COMM_CMD_VHCR0: 1823 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET) 1824 goto reset_slave; 1825 slave_state[slave].vhcr_dma = ((u64) param) << 48; 1826 priv->mfunc.master.slave_state[slave].cookie = 0; 1827 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]); 1828 break; 1829 case MLX4_COMM_CMD_VHCR1: 1830 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0) 1831 goto reset_slave; 1832 slave_state[slave].vhcr_dma |= ((u64) param) << 32; 1833 break; 1834 case MLX4_COMM_CMD_VHCR2: 1835 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1) 1836 goto reset_slave; 1837 slave_state[slave].vhcr_dma |= ((u64) param) << 16; 1838 break; 1839 case MLX4_COMM_CMD_VHCR_EN: 1840 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2) 1841 goto reset_slave; 1842 slave_state[slave].vhcr_dma |= param; 1843 if (mlx4_master_activate_admin_state(priv, slave)) 1844 goto reset_slave; 1845 slave_state[slave].active = true; 1846 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave); 1847 break; 1848 case MLX4_COMM_CMD_VHCR_POST: 1849 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) && 1850 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST)) 1851 goto reset_slave; 1852 1853 mutex_lock(&priv->cmd.slave_cmd_mutex); 1854 if (mlx4_master_process_vhcr(dev, slave, NULL)) { 1855 mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n", 1856 slave); 1857 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1858 goto reset_slave; 1859 } 1860 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1861 break; 1862 default: 1863 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave); 1864 goto reset_slave; 1865 } 1866 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 1867 if (!slave_state[slave].is_slave_going_down) 1868 slave_state[slave].last_cmd = cmd; 1869 else 1870 is_going_down = 1; 1871 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 1872 if (is_going_down) { 1873 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n", 1874 cmd, slave); 1875 return; 1876 } 1877 __raw_writel((__force u32) cpu_to_be32(reply), 1878 &priv->mfunc.comm[slave].slave_read); 1879 mmiowb(); 1880 1881 return; 1882 1883 reset_slave: 1884 /* cleanup any slave resources */ 1885 mlx4_delete_all_resources_for_slave(dev, slave); 1886 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 1887 if (!slave_state[slave].is_slave_going_down) 1888 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET; 1889 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 1890 /*with slave in the middle of flr, no need to clean resources again.*/ 1891 inform_slave_state: 1892 memset(&slave_state[slave].event_eq, 0, 1893 sizeof(struct mlx4_slave_event_eq_info)); 1894 __raw_writel((__force u32) cpu_to_be32(reply), 1895 &priv->mfunc.comm[slave].slave_read); 1896 wmb(); 1897 } 1898 1899 /* master command processing */ 1900 void mlx4_master_comm_channel(struct work_struct *work) 1901 { 1902 struct mlx4_mfunc_master_ctx *master = 1903 container_of(work, 1904 struct mlx4_mfunc_master_ctx, 1905 comm_work); 1906 struct mlx4_mfunc *mfunc = 1907 container_of(master, struct mlx4_mfunc, master); 1908 struct mlx4_priv *priv = 1909 container_of(mfunc, struct mlx4_priv, mfunc); 1910 struct mlx4_dev *dev = &priv->dev; 1911 __be32 *bit_vec; 1912 u32 comm_cmd; 1913 u32 vec; 1914 int i, j, slave; 1915 int toggle; 1916 int served = 0; 1917 int reported = 0; 1918 u32 slt; 1919 1920 bit_vec = master->comm_arm_bit_vector; 1921 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) { 1922 vec = be32_to_cpu(bit_vec[i]); 1923 for (j = 0; j < 32; j++) { 1924 if (!(vec & (1 << j))) 1925 continue; 1926 ++reported; 1927 slave = (i * 32) + j; 1928 comm_cmd = swab32(readl( 1929 &mfunc->comm[slave].slave_write)); 1930 slt = swab32(readl(&mfunc->comm[slave].slave_read)) 1931 >> 31; 1932 toggle = comm_cmd >> 31; 1933 if (toggle != slt) { 1934 if (master->slave_state[slave].comm_toggle 1935 != slt) { 1936 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n", 1937 slave, slt, 1938 master->slave_state[slave].comm_toggle); 1939 master->slave_state[slave].comm_toggle = 1940 slt; 1941 } 1942 mlx4_master_do_cmd(dev, slave, 1943 comm_cmd >> 16 & 0xff, 1944 comm_cmd & 0xffff, toggle); 1945 ++served; 1946 } 1947 } 1948 } 1949 1950 if (reported && reported != served) 1951 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n", 1952 reported, served); 1953 1954 if (mlx4_ARM_COMM_CHANNEL(dev)) 1955 mlx4_warn(dev, "Failed to arm comm channel events\n"); 1956 } 1957 1958 static int sync_toggles(struct mlx4_dev *dev) 1959 { 1960 struct mlx4_priv *priv = mlx4_priv(dev); 1961 int wr_toggle; 1962 int rd_toggle; 1963 unsigned long end; 1964 1965 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31; 1966 end = jiffies + msecs_to_jiffies(5000); 1967 1968 while (time_before(jiffies, end)) { 1969 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31; 1970 if (rd_toggle == wr_toggle) { 1971 priv->cmd.comm_toggle = rd_toggle; 1972 return 0; 1973 } 1974 1975 cond_resched(); 1976 } 1977 1978 /* 1979 * we could reach here if for example the previous VM using this 1980 * function misbehaved and left the channel with unsynced state. We 1981 * should fix this here and give this VM a chance to use a properly 1982 * synced channel 1983 */ 1984 mlx4_warn(dev, "recovering from previously mis-behaved VM\n"); 1985 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read); 1986 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write); 1987 priv->cmd.comm_toggle = 0; 1988 1989 return 0; 1990 } 1991 1992 int mlx4_multi_func_init(struct mlx4_dev *dev) 1993 { 1994 struct mlx4_priv *priv = mlx4_priv(dev); 1995 struct mlx4_slave_state *s_state; 1996 int i, j, err, port; 1997 1998 if (mlx4_is_master(dev)) 1999 priv->mfunc.comm = 2000 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) + 2001 priv->fw.comm_base, MLX4_COMM_PAGESIZE); 2002 else 2003 priv->mfunc.comm = 2004 ioremap(pci_resource_start(dev->pdev, 2) + 2005 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE); 2006 if (!priv->mfunc.comm) { 2007 mlx4_err(dev, "Couldn't map communication vector\n"); 2008 goto err_vhcr; 2009 } 2010 2011 if (mlx4_is_master(dev)) { 2012 priv->mfunc.master.slave_state = 2013 kzalloc(dev->num_slaves * 2014 sizeof(struct mlx4_slave_state), GFP_KERNEL); 2015 if (!priv->mfunc.master.slave_state) 2016 goto err_comm; 2017 2018 priv->mfunc.master.vf_admin = 2019 kzalloc(dev->num_slaves * 2020 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL); 2021 if (!priv->mfunc.master.vf_admin) 2022 goto err_comm_admin; 2023 2024 priv->mfunc.master.vf_oper = 2025 kzalloc(dev->num_slaves * 2026 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL); 2027 if (!priv->mfunc.master.vf_oper) 2028 goto err_comm_oper; 2029 2030 for (i = 0; i < dev->num_slaves; ++i) { 2031 s_state = &priv->mfunc.master.slave_state[i]; 2032 s_state->last_cmd = MLX4_COMM_CMD_RESET; 2033 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j) 2034 s_state->event_eq[j].eqn = -1; 2035 __raw_writel((__force u32) 0, 2036 &priv->mfunc.comm[i].slave_write); 2037 __raw_writel((__force u32) 0, 2038 &priv->mfunc.comm[i].slave_read); 2039 mmiowb(); 2040 for (port = 1; port <= MLX4_MAX_PORTS; port++) { 2041 s_state->vlan_filter[port] = 2042 kzalloc(sizeof(struct mlx4_vlan_fltr), 2043 GFP_KERNEL); 2044 if (!s_state->vlan_filter[port]) { 2045 if (--port) 2046 kfree(s_state->vlan_filter[port]); 2047 goto err_slaves; 2048 } 2049 INIT_LIST_HEAD(&s_state->mcast_filters[port]); 2050 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT; 2051 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT; 2052 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX; 2053 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX; 2054 } 2055 spin_lock_init(&s_state->lock); 2056 } 2057 2058 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size); 2059 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD; 2060 INIT_WORK(&priv->mfunc.master.comm_work, 2061 mlx4_master_comm_channel); 2062 INIT_WORK(&priv->mfunc.master.slave_event_work, 2063 mlx4_gen_slave_eqe); 2064 INIT_WORK(&priv->mfunc.master.slave_flr_event_work, 2065 mlx4_master_handle_slave_flr); 2066 spin_lock_init(&priv->mfunc.master.slave_state_lock); 2067 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock); 2068 priv->mfunc.master.comm_wq = 2069 create_singlethread_workqueue("mlx4_comm"); 2070 if (!priv->mfunc.master.comm_wq) 2071 goto err_slaves; 2072 2073 if (mlx4_init_resource_tracker(dev)) 2074 goto err_thread; 2075 2076 err = mlx4_ARM_COMM_CHANNEL(dev); 2077 if (err) { 2078 mlx4_err(dev, " Failed to arm comm channel eq: %x\n", 2079 err); 2080 goto err_resource; 2081 } 2082 2083 } else { 2084 err = sync_toggles(dev); 2085 if (err) { 2086 mlx4_err(dev, "Couldn't sync toggles\n"); 2087 goto err_comm; 2088 } 2089 } 2090 return 0; 2091 2092 err_resource: 2093 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL); 2094 err_thread: 2095 flush_workqueue(priv->mfunc.master.comm_wq); 2096 destroy_workqueue(priv->mfunc.master.comm_wq); 2097 err_slaves: 2098 while (--i) { 2099 for (port = 1; port <= MLX4_MAX_PORTS; port++) 2100 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]); 2101 } 2102 kfree(priv->mfunc.master.vf_oper); 2103 err_comm_oper: 2104 kfree(priv->mfunc.master.vf_admin); 2105 err_comm_admin: 2106 kfree(priv->mfunc.master.slave_state); 2107 err_comm: 2108 iounmap(priv->mfunc.comm); 2109 err_vhcr: 2110 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE, 2111 priv->mfunc.vhcr, 2112 priv->mfunc.vhcr_dma); 2113 priv->mfunc.vhcr = NULL; 2114 return -ENOMEM; 2115 } 2116 2117 int mlx4_cmd_init(struct mlx4_dev *dev) 2118 { 2119 struct mlx4_priv *priv = mlx4_priv(dev); 2120 int flags = 0; 2121 2122 if (!priv->cmd.initialized) { 2123 mutex_init(&priv->cmd.hcr_mutex); 2124 mutex_init(&priv->cmd.slave_cmd_mutex); 2125 sema_init(&priv->cmd.poll_sem, 1); 2126 priv->cmd.use_events = 0; 2127 priv->cmd.toggle = 1; 2128 priv->cmd.initialized = 1; 2129 flags |= MLX4_CMD_CLEANUP_STRUCT; 2130 } 2131 2132 if (!mlx4_is_slave(dev) && !priv->cmd.hcr) { 2133 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) + 2134 MLX4_HCR_BASE, MLX4_HCR_SIZE); 2135 if (!priv->cmd.hcr) { 2136 mlx4_err(dev, "Couldn't map command register\n"); 2137 goto err; 2138 } 2139 flags |= MLX4_CMD_CLEANUP_HCR; 2140 } 2141 2142 if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) { 2143 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE, 2144 &priv->mfunc.vhcr_dma, 2145 GFP_KERNEL); 2146 if (!priv->mfunc.vhcr) 2147 goto err; 2148 2149 flags |= MLX4_CMD_CLEANUP_VHCR; 2150 } 2151 2152 if (!priv->cmd.pool) { 2153 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev, 2154 MLX4_MAILBOX_SIZE, 2155 MLX4_MAILBOX_SIZE, 0); 2156 if (!priv->cmd.pool) 2157 goto err; 2158 2159 flags |= MLX4_CMD_CLEANUP_POOL; 2160 } 2161 2162 return 0; 2163 2164 err: 2165 mlx4_cmd_cleanup(dev, flags); 2166 return -ENOMEM; 2167 } 2168 2169 void mlx4_multi_func_cleanup(struct mlx4_dev *dev) 2170 { 2171 struct mlx4_priv *priv = mlx4_priv(dev); 2172 int i, port; 2173 2174 if (mlx4_is_master(dev)) { 2175 flush_workqueue(priv->mfunc.master.comm_wq); 2176 destroy_workqueue(priv->mfunc.master.comm_wq); 2177 for (i = 0; i < dev->num_slaves; i++) { 2178 for (port = 1; port <= MLX4_MAX_PORTS; port++) 2179 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]); 2180 } 2181 kfree(priv->mfunc.master.slave_state); 2182 kfree(priv->mfunc.master.vf_admin); 2183 kfree(priv->mfunc.master.vf_oper); 2184 } 2185 2186 iounmap(priv->mfunc.comm); 2187 } 2188 2189 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask) 2190 { 2191 struct mlx4_priv *priv = mlx4_priv(dev); 2192 2193 if (priv->cmd.pool && (cleanup_mask & MLX4_CMD_CLEANUP_POOL)) { 2194 pci_pool_destroy(priv->cmd.pool); 2195 priv->cmd.pool = NULL; 2196 } 2197 2198 if (!mlx4_is_slave(dev) && priv->cmd.hcr && 2199 (cleanup_mask & MLX4_CMD_CLEANUP_HCR)) { 2200 iounmap(priv->cmd.hcr); 2201 priv->cmd.hcr = NULL; 2202 } 2203 if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr && 2204 (cleanup_mask & MLX4_CMD_CLEANUP_VHCR)) { 2205 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE, 2206 priv->mfunc.vhcr, priv->mfunc.vhcr_dma); 2207 priv->mfunc.vhcr = NULL; 2208 } 2209 if (priv->cmd.initialized && (cleanup_mask & MLX4_CMD_CLEANUP_STRUCT)) 2210 priv->cmd.initialized = 0; 2211 } 2212 2213 /* 2214 * Switch to using events to issue FW commands (can only be called 2215 * after event queue for command events has been initialized). 2216 */ 2217 int mlx4_cmd_use_events(struct mlx4_dev *dev) 2218 { 2219 struct mlx4_priv *priv = mlx4_priv(dev); 2220 int i; 2221 int err = 0; 2222 2223 priv->cmd.context = kmalloc(priv->cmd.max_cmds * 2224 sizeof (struct mlx4_cmd_context), 2225 GFP_KERNEL); 2226 if (!priv->cmd.context) 2227 return -ENOMEM; 2228 2229 for (i = 0; i < priv->cmd.max_cmds; ++i) { 2230 priv->cmd.context[i].token = i; 2231 priv->cmd.context[i].next = i + 1; 2232 } 2233 2234 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1; 2235 priv->cmd.free_head = 0; 2236 2237 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds); 2238 spin_lock_init(&priv->cmd.context_lock); 2239 2240 for (priv->cmd.token_mask = 1; 2241 priv->cmd.token_mask < priv->cmd.max_cmds; 2242 priv->cmd.token_mask <<= 1) 2243 ; /* nothing */ 2244 --priv->cmd.token_mask; 2245 2246 down(&priv->cmd.poll_sem); 2247 priv->cmd.use_events = 1; 2248 2249 return err; 2250 } 2251 2252 /* 2253 * Switch back to polling (used when shutting down the device) 2254 */ 2255 void mlx4_cmd_use_polling(struct mlx4_dev *dev) 2256 { 2257 struct mlx4_priv *priv = mlx4_priv(dev); 2258 int i; 2259 2260 priv->cmd.use_events = 0; 2261 2262 for (i = 0; i < priv->cmd.max_cmds; ++i) 2263 down(&priv->cmd.event_sem); 2264 2265 kfree(priv->cmd.context); 2266 2267 up(&priv->cmd.poll_sem); 2268 } 2269 2270 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev) 2271 { 2272 struct mlx4_cmd_mailbox *mailbox; 2273 2274 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL); 2275 if (!mailbox) 2276 return ERR_PTR(-ENOMEM); 2277 2278 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL, 2279 &mailbox->dma); 2280 if (!mailbox->buf) { 2281 kfree(mailbox); 2282 return ERR_PTR(-ENOMEM); 2283 } 2284 2285 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); 2286 2287 return mailbox; 2288 } 2289 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox); 2290 2291 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, 2292 struct mlx4_cmd_mailbox *mailbox) 2293 { 2294 if (!mailbox) 2295 return; 2296 2297 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma); 2298 kfree(mailbox); 2299 } 2300 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox); 2301 2302 u32 mlx4_comm_get_version(void) 2303 { 2304 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER; 2305 } 2306 2307 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf) 2308 { 2309 if ((vf < 0) || (vf >= dev->num_vfs)) { 2310 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs); 2311 return -EINVAL; 2312 } 2313 2314 return vf+1; 2315 } 2316 2317 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave) 2318 { 2319 if (slave < 1 || slave > dev->num_vfs) { 2320 mlx4_err(dev, 2321 "Bad slave number:%d (number of activated slaves: %lu)\n", 2322 slave, dev->num_slaves); 2323 return -EINVAL; 2324 } 2325 return slave - 1; 2326 } 2327 2328 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave) 2329 { 2330 struct mlx4_active_ports actv_ports; 2331 int vf; 2332 2333 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS); 2334 2335 if (slave == 0) { 2336 bitmap_fill(actv_ports.ports, dev->caps.num_ports); 2337 return actv_ports; 2338 } 2339 2340 vf = mlx4_get_vf_indx(dev, slave); 2341 if (vf < 0) 2342 return actv_ports; 2343 2344 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1, 2345 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports, 2346 dev->caps.num_ports)); 2347 2348 return actv_ports; 2349 } 2350 EXPORT_SYMBOL_GPL(mlx4_get_active_ports); 2351 2352 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port) 2353 { 2354 unsigned n; 2355 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 2356 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports); 2357 2358 if (port <= 0 || port > m) 2359 return -EINVAL; 2360 2361 n = find_first_bit(actv_ports.ports, dev->caps.num_ports); 2362 if (port <= n) 2363 port = n + 1; 2364 2365 return port; 2366 } 2367 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port); 2368 2369 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port) 2370 { 2371 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 2372 if (test_bit(port - 1, actv_ports.ports)) 2373 return port - 2374 find_first_bit(actv_ports.ports, dev->caps.num_ports); 2375 2376 return -1; 2377 } 2378 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port); 2379 2380 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 2381 int port) 2382 { 2383 unsigned i; 2384 struct mlx4_slaves_pport slaves_pport; 2385 2386 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX); 2387 2388 if (port <= 0 || port > dev->caps.num_ports) 2389 return slaves_pport; 2390 2391 for (i = 0; i < dev->num_vfs + 1; i++) { 2392 struct mlx4_active_ports actv_ports = 2393 mlx4_get_active_ports(dev, i); 2394 if (test_bit(port - 1, actv_ports.ports)) 2395 set_bit(i, slaves_pport.slaves); 2396 } 2397 2398 return slaves_pport; 2399 } 2400 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport); 2401 2402 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 2403 struct mlx4_dev *dev, 2404 const struct mlx4_active_ports *crit_ports) 2405 { 2406 unsigned i; 2407 struct mlx4_slaves_pport slaves_pport; 2408 2409 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX); 2410 2411 for (i = 0; i < dev->num_vfs + 1; i++) { 2412 struct mlx4_active_ports actv_ports = 2413 mlx4_get_active_ports(dev, i); 2414 if (bitmap_equal(crit_ports->ports, actv_ports.ports, 2415 dev->caps.num_ports)) 2416 set_bit(i, slaves_pport.slaves); 2417 } 2418 2419 return slaves_pport; 2420 } 2421 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv); 2422 2423 static int mlx4_slaves_closest_port(struct mlx4_dev *dev, int slave, int port) 2424 { 2425 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 2426 int min_port = find_first_bit(actv_ports.ports, dev->caps.num_ports) 2427 + 1; 2428 int max_port = min_port + 2429 bitmap_weight(actv_ports.ports, dev->caps.num_ports); 2430 2431 if (port < min_port) 2432 port = min_port; 2433 else if (port >= max_port) 2434 port = max_port - 1; 2435 2436 return port; 2437 } 2438 2439 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac) 2440 { 2441 struct mlx4_priv *priv = mlx4_priv(dev); 2442 struct mlx4_vport_state *s_info; 2443 int slave; 2444 2445 if (!mlx4_is_master(dev)) 2446 return -EPROTONOSUPPORT; 2447 2448 slave = mlx4_get_slave_indx(dev, vf); 2449 if (slave < 0) 2450 return -EINVAL; 2451 2452 port = mlx4_slaves_closest_port(dev, slave, port); 2453 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; 2454 s_info->mac = mac; 2455 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n", 2456 vf, port, s_info->mac); 2457 return 0; 2458 } 2459 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac); 2460 2461 2462 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos) 2463 { 2464 struct mlx4_priv *priv = mlx4_priv(dev); 2465 struct mlx4_vport_state *vf_admin; 2466 int slave; 2467 2468 if ((!mlx4_is_master(dev)) || 2469 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL)) 2470 return -EPROTONOSUPPORT; 2471 2472 if ((vlan > 4095) || (qos > 7)) 2473 return -EINVAL; 2474 2475 slave = mlx4_get_slave_indx(dev, vf); 2476 if (slave < 0) 2477 return -EINVAL; 2478 2479 port = mlx4_slaves_closest_port(dev, slave, port); 2480 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; 2481 2482 if ((0 == vlan) && (0 == qos)) 2483 vf_admin->default_vlan = MLX4_VGT; 2484 else 2485 vf_admin->default_vlan = vlan; 2486 vf_admin->default_qos = qos; 2487 2488 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port)) 2489 mlx4_info(dev, 2490 "updating vf %d port %d config will take effect on next VF restart\n", 2491 vf, port); 2492 return 0; 2493 } 2494 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan); 2495 2496 /* mlx4_get_slave_default_vlan - 2497 * return true if VST ( default vlan) 2498 * if VST, will return vlan & qos (if not NULL) 2499 */ 2500 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave, 2501 u16 *vlan, u8 *qos) 2502 { 2503 struct mlx4_vport_oper_state *vp_oper; 2504 struct mlx4_priv *priv; 2505 2506 priv = mlx4_priv(dev); 2507 port = mlx4_slaves_closest_port(dev, slave, port); 2508 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; 2509 2510 if (MLX4_VGT != vp_oper->state.default_vlan) { 2511 if (vlan) 2512 *vlan = vp_oper->state.default_vlan; 2513 if (qos) 2514 *qos = vp_oper->state.default_qos; 2515 return true; 2516 } 2517 return false; 2518 } 2519 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan); 2520 2521 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting) 2522 { 2523 struct mlx4_priv *priv = mlx4_priv(dev); 2524 struct mlx4_vport_state *s_info; 2525 int slave; 2526 2527 if ((!mlx4_is_master(dev)) || 2528 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM)) 2529 return -EPROTONOSUPPORT; 2530 2531 slave = mlx4_get_slave_indx(dev, vf); 2532 if (slave < 0) 2533 return -EINVAL; 2534 2535 port = mlx4_slaves_closest_port(dev, slave, port); 2536 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; 2537 s_info->spoofchk = setting; 2538 2539 return 0; 2540 } 2541 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk); 2542 2543 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf) 2544 { 2545 struct mlx4_priv *priv = mlx4_priv(dev); 2546 struct mlx4_vport_state *s_info; 2547 int slave; 2548 2549 if (!mlx4_is_master(dev)) 2550 return -EPROTONOSUPPORT; 2551 2552 slave = mlx4_get_slave_indx(dev, vf); 2553 if (slave < 0) 2554 return -EINVAL; 2555 2556 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; 2557 ivf->vf = vf; 2558 2559 /* need to convert it to a func */ 2560 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff); 2561 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff); 2562 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff); 2563 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff); 2564 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff); 2565 ivf->mac[5] = ((s_info->mac) & 0xff); 2566 2567 ivf->vlan = s_info->default_vlan; 2568 ivf->qos = s_info->default_qos; 2569 ivf->max_tx_rate = s_info->tx_rate; 2570 ivf->min_tx_rate = 0; 2571 ivf->spoofchk = s_info->spoofchk; 2572 ivf->linkstate = s_info->link_state; 2573 2574 return 0; 2575 } 2576 EXPORT_SYMBOL_GPL(mlx4_get_vf_config); 2577 2578 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state) 2579 { 2580 struct mlx4_priv *priv = mlx4_priv(dev); 2581 struct mlx4_vport_state *s_info; 2582 int slave; 2583 u8 link_stat_event; 2584 2585 slave = mlx4_get_slave_indx(dev, vf); 2586 if (slave < 0) 2587 return -EINVAL; 2588 2589 port = mlx4_slaves_closest_port(dev, slave, port); 2590 switch (link_state) { 2591 case IFLA_VF_LINK_STATE_AUTO: 2592 /* get current link state */ 2593 if (!priv->sense.do_sense_port[port]) 2594 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE; 2595 else 2596 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN; 2597 break; 2598 2599 case IFLA_VF_LINK_STATE_ENABLE: 2600 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE; 2601 break; 2602 2603 case IFLA_VF_LINK_STATE_DISABLE: 2604 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN; 2605 break; 2606 2607 default: 2608 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n", 2609 link_state, slave, port); 2610 return -EINVAL; 2611 }; 2612 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; 2613 s_info->link_state = link_state; 2614 2615 /* send event */ 2616 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event); 2617 2618 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port)) 2619 mlx4_dbg(dev, 2620 "updating vf %d port %d no link state HW enforcment\n", 2621 vf, port); 2622 return 0; 2623 } 2624 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state); 2625 2626 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port) 2627 { 2628 struct mlx4_priv *priv = mlx4_priv(dev); 2629 2630 if (slave < 1 || slave >= dev->num_slaves || 2631 port < 1 || port > MLX4_MAX_PORTS) 2632 return 0; 2633 2634 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] == 2635 MLX4_VF_SMI_ENABLED; 2636 } 2637 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled); 2638 2639 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port) 2640 { 2641 struct mlx4_priv *priv = mlx4_priv(dev); 2642 2643 if (slave == mlx4_master_func_num(dev)) 2644 return 1; 2645 2646 if (slave < 1 || slave >= dev->num_slaves || 2647 port < 1 || port > MLX4_MAX_PORTS) 2648 return 0; 2649 2650 return priv->mfunc.master.vf_admin[slave].enable_smi[port] == 2651 MLX4_VF_SMI_ENABLED; 2652 } 2653 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin); 2654 2655 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 2656 int enabled) 2657 { 2658 struct mlx4_priv *priv = mlx4_priv(dev); 2659 2660 if (slave == mlx4_master_func_num(dev)) 2661 return 0; 2662 2663 if (slave < 1 || slave >= dev->num_slaves || 2664 port < 1 || port > MLX4_MAX_PORTS || 2665 enabled < 0 || enabled > 1) 2666 return -EINVAL; 2667 2668 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled; 2669 return 0; 2670 } 2671 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin); 2672