1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2022 Lorenzo Bianconi <lorenzo@kernel.org>  */
3 
4 #ifndef __MTK_WED_WO_H
5 #define __MTK_WED_WO_H
6 
7 #include <linux/skbuff.h>
8 #include <linux/netdevice.h>
9 
10 struct mtk_wed_hw;
11 
12 struct mtk_wed_mcu_hdr {
13 	/* DW0 */
14 	u8 version;
15 	u8 cmd;
16 	__le16 length;
17 
18 	/* DW1 */
19 	__le16 seq;
20 	__le16 flag;
21 
22 	/* DW2 */
23 	__le32 status;
24 
25 	/* DW3 */
26 	u8 rsv[20];
27 };
28 
29 struct mtk_wed_wo_log_info {
30 	__le32 sn;
31 	__le32 total;
32 	__le32 rro;
33 	__le32 mod;
34 };
35 
36 enum mtk_wed_wo_event {
37 	MTK_WED_WO_EVT_LOG_DUMP		= 0x1,
38 	MTK_WED_WO_EVT_PROFILING	= 0x2,
39 	MTK_WED_WO_EVT_RXCNT_INFO	= 0x3,
40 };
41 
42 #define MTK_WED_MODULE_ID_WO		1
43 #define MTK_FW_DL_TIMEOUT		4000000 /* us */
44 #define MTK_WOCPU_TIMEOUT		2000000 /* us */
45 
46 enum {
47 	MTK_WED_WARP_CMD_FLAG_RSP		= BIT(0),
48 	MTK_WED_WARP_CMD_FLAG_NEED_RSP		= BIT(1),
49 	MTK_WED_WARP_CMD_FLAG_FROM_TO_WO	= BIT(2),
50 };
51 
52 #define MTK_WED_WO_CPU_MCUSYS_RESET_ADDR	0x15194050
53 #define MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK	0x20
54 #define MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK	0x1
55 
56 enum {
57 	MTK_WED_WO_REGION_EMI,
58 	MTK_WED_WO_REGION_ILM,
59 	MTK_WED_WO_REGION_DATA,
60 	MTK_WED_WO_REGION_BOOT,
61 	__MTK_WED_WO_REGION_MAX,
62 };
63 
64 enum mtk_wed_wo_state {
65 	MTK_WED_WO_STATE_UNDEFINED,
66 	MTK_WED_WO_STATE_INIT,
67 	MTK_WED_WO_STATE_ENABLE,
68 	MTK_WED_WO_STATE_DISABLE,
69 	MTK_WED_WO_STATE_HALT,
70 	MTK_WED_WO_STATE_GATING,
71 	MTK_WED_WO_STATE_SER_RESET,
72 	MTK_WED_WO_STATE_WF_RESET,
73 };
74 
75 enum mtk_wed_wo_done_state {
76 	MTK_WED_WOIF_UNDEFINED,
77 	MTK_WED_WOIF_DISABLE_DONE,
78 	MTK_WED_WOIF_TRIGGER_ENABLE,
79 	MTK_WED_WOIF_ENABLE_DONE,
80 	MTK_WED_WOIF_TRIGGER_GATING,
81 	MTK_WED_WOIF_GATING_DONE,
82 	MTK_WED_WOIF_TRIGGER_HALT,
83 	MTK_WED_WOIF_HALT_DONE,
84 };
85 
86 enum mtk_wed_dummy_cr_idx {
87 	MTK_WED_DUMMY_CR_FWDL,
88 	MTK_WED_DUMMY_CR_WO_STATUS,
89 };
90 
91 #define MT7986_FIRMWARE_WO0	"mediatek/mt7986_wo_0.bin"
92 #define MT7986_FIRMWARE_WO1	"mediatek/mt7986_wo_1.bin"
93 
94 #define MTK_WO_MCU_CFG_LS_BASE				0
95 #define MTK_WO_MCU_CFG_LS_HW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x000)
96 #define MTK_WO_MCU_CFG_LS_FW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x004)
97 #define MTK_WO_MCU_CFG_LS_CFG_DBG1_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x00c)
98 #define MTK_WO_MCU_CFG_LS_CFG_DBG2_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x010)
99 #define MTK_WO_MCU_CFG_LS_WF_MCCR_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x014)
100 #define MTK_WO_MCU_CFG_LS_WF_MCCR_SET_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x018)
101 #define MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x01c)
102 #define MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x050)
103 #define MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x060)
104 #define MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR		(MTK_WO_MCU_CFG_LS_BASE + 0x064)
105 
106 #define MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK	BIT(5)
107 #define MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK	BIT(0)
108 
109 #define MTK_WED_WO_RING_SIZE	256
110 #define MTK_WED_WO_CMD_LEN	1504
111 
112 #define MTK_WED_WO_TXCH_NUM		0
113 #define MTK_WED_WO_RXCH_NUM		1
114 #define MTK_WED_WO_RXCH_WO_EXCEPTION	7
115 
116 #define MTK_WED_WO_TXCH_INT_MASK	BIT(0)
117 #define MTK_WED_WO_RXCH_INT_MASK	BIT(1)
118 #define MTK_WED_WO_EXCEPTION_INT_MASK	BIT(7)
119 #define MTK_WED_WO_ALL_INT_MASK		(MTK_WED_WO_RXCH_INT_MASK | \
120 					 MTK_WED_WO_EXCEPTION_INT_MASK)
121 
122 #define MTK_WED_WO_CCIF_BUSY		0x004
123 #define MTK_WED_WO_CCIF_START		0x008
124 #define MTK_WED_WO_CCIF_TCHNUM		0x00c
125 #define MTK_WED_WO_CCIF_RCHNUM		0x010
126 #define MTK_WED_WO_CCIF_RCHNUM_MASK	GENMASK(7, 0)
127 
128 #define MTK_WED_WO_CCIF_ACK		0x014
129 #define MTK_WED_WO_CCIF_IRQ0_MASK	0x018
130 #define MTK_WED_WO_CCIF_IRQ1_MASK	0x01c
131 #define MTK_WED_WO_CCIF_DUMMY1		0x020
132 #define MTK_WED_WO_CCIF_DUMMY2		0x024
133 #define MTK_WED_WO_CCIF_DUMMY3		0x028
134 #define MTK_WED_WO_CCIF_DUMMY4		0x02c
135 #define MTK_WED_WO_CCIF_SHADOW1		0x030
136 #define MTK_WED_WO_CCIF_SHADOW2		0x034
137 #define MTK_WED_WO_CCIF_SHADOW3		0x038
138 #define MTK_WED_WO_CCIF_SHADOW4		0x03c
139 #define MTK_WED_WO_CCIF_DUMMY5		0x050
140 #define MTK_WED_WO_CCIF_DUMMY6		0x054
141 #define MTK_WED_WO_CCIF_DUMMY7		0x058
142 #define MTK_WED_WO_CCIF_DUMMY8		0x05c
143 #define MTK_WED_WO_CCIF_SHADOW5		0x060
144 #define MTK_WED_WO_CCIF_SHADOW6		0x064
145 #define MTK_WED_WO_CCIF_SHADOW7		0x068
146 #define MTK_WED_WO_CCIF_SHADOW8		0x06c
147 
148 #define MTK_WED_WO_CTL_SD_LEN1		GENMASK(13, 0)
149 #define MTK_WED_WO_CTL_LAST_SEC1	BIT(14)
150 #define MTK_WED_WO_CTL_BURST		BIT(15)
151 #define MTK_WED_WO_CTL_SD_LEN0_SHIFT	16
152 #define MTK_WED_WO_CTL_SD_LEN0		GENMASK(29, 16)
153 #define MTK_WED_WO_CTL_LAST_SEC0	BIT(30)
154 #define MTK_WED_WO_CTL_DMA_DONE		BIT(31)
155 #define MTK_WED_WO_INFO_WINFO		GENMASK(15, 0)
156 
157 struct mtk_wed_wo_memory_region {
158 	const char *name;
159 	void __iomem *addr;
160 	phys_addr_t phy_addr;
161 	u32 size;
162 	bool shared:1;
163 	bool consumed:1;
164 };
165 
166 struct mtk_wed_fw_region {
167 	__le32 decomp_crc;
168 	__le32 decomp_len;
169 	__le32 decomp_blk_sz;
170 	u8 rsv0[4];
171 	__le32 addr;
172 	__le32 len;
173 	u8 feature_set;
174 	u8 rsv1[15];
175 } __packed;
176 
177 struct mtk_wed_fw_trailer {
178 	u8 chip_id;
179 	u8 eco_code;
180 	u8 num_region;
181 	u8 format_ver;
182 	u8 format_flag;
183 	u8 rsv[2];
184 	char fw_ver[10];
185 	char build_date[15];
186 	u32 crc;
187 };
188 
189 struct mtk_wed_wo_queue_regs {
190 	u32 desc_base;
191 	u32 ring_size;
192 	u32 cpu_idx;
193 	u32 dma_idx;
194 };
195 
196 struct mtk_wed_wo_queue_desc {
197 	__le32 buf0;
198 	__le32 ctrl;
199 	__le32 buf1;
200 	__le32 info;
201 	__le32 reserved[4];
202 } __packed __aligned(32);
203 
204 struct mtk_wed_wo_queue_entry {
205 	dma_addr_t addr;
206 	void *buf;
207 	u32 len;
208 };
209 
210 struct mtk_wed_wo_queue {
211 	struct mtk_wed_wo_queue_regs regs;
212 
213 	struct page_frag_cache cache;
214 
215 	struct mtk_wed_wo_queue_desc *desc;
216 	dma_addr_t desc_dma;
217 
218 	struct mtk_wed_wo_queue_entry *entry;
219 
220 	u16 head;
221 	u16 tail;
222 	int n_desc;
223 	int queued;
224 	int buf_size;
225 
226 };
227 
228 struct mtk_wed_wo {
229 	struct mtk_wed_hw *hw;
230 	struct mtk_wed_wo_memory_region boot;
231 
232 	struct mtk_wed_wo_queue q_tx;
233 	struct mtk_wed_wo_queue q_rx;
234 
235 	struct {
236 		struct mutex mutex;
237 		int timeout;
238 		u16 seq;
239 
240 		struct sk_buff_head res_q;
241 		wait_queue_head_t wait;
242 	} mcu;
243 
244 	struct {
245 		struct regmap *regs;
246 
247 		spinlock_t lock;
248 		struct tasklet_struct irq_tasklet;
249 		int irq;
250 		u32 irq_mask;
251 	} mmio;
252 };
253 
254 static inline int
255 mtk_wed_mcu_check_msg(struct mtk_wed_wo *wo, struct sk_buff *skb)
256 {
257 	struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
258 
259 	if (hdr->version)
260 		return -EINVAL;
261 
262 	if (skb->len < sizeof(*hdr) || skb->len != le16_to_cpu(hdr->length))
263 		return -EINVAL;
264 
265 	return 0;
266 }
267 
268 void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb);
269 void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
270 				      struct sk_buff *skb);
271 int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
272 			 const void *data, int len, bool wait_resp);
273 int mtk_wed_mcu_msg_update(struct mtk_wed_device *dev, int id, void *data,
274 			   int len);
275 int mtk_wed_mcu_init(struct mtk_wed_wo *wo);
276 int mtk_wed_wo_init(struct mtk_wed_hw *hw);
277 void mtk_wed_wo_deinit(struct mtk_wed_hw *hw);
278 int mtk_wed_wo_queue_tx_skb(struct mtk_wed_wo *dev, struct mtk_wed_wo_queue *q,
279 			    struct sk_buff *skb);
280 
281 #endif /* __MTK_WED_WO_H */
282