1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
3 
4 #ifndef __MTK_WED_REGS_H
5 #define __MTK_WED_REGS_H
6 
7 #define MTK_WFDMA_DESC_CTRL_TO_HOST		BIT(8)
8 #define MTK_WDMA_DESC_CTRL_LEN1			GENMASK(14, 0)
9 #define MTK_WDMA_DESC_CTRL_LEN1_V2		GENMASK(13, 0)
10 #define MTK_WDMA_DESC_CTRL_LAST_SEG1		BIT(15)
11 #define MTK_WDMA_DESC_CTRL_BURST		BIT(16)
12 #define MTK_WDMA_DESC_CTRL_LEN0			GENMASK(29, 16)
13 #define MTK_WDMA_DESC_CTRL_LAST_SEG0		BIT(30)
14 #define MTK_WDMA_DESC_CTRL_DMA_DONE		BIT(31)
15 
16 struct mtk_wdma_desc {
17 	__le32 buf0;
18 	__le32 ctrl;
19 	__le32 buf1;
20 	__le32 info;
21 } __packed __aligned(4);
22 
23 #define MTK_WED_REV_ID					0x004
24 
25 #define MTK_WED_RESET					0x008
26 #define MTK_WED_RESET_TX_BM				BIT(0)
27 #define MTK_WED_RESET_RX_BM				BIT(1)
28 #define MTK_WED_RESET_TX_FREE_AGENT			BIT(4)
29 #define MTK_WED_RESET_WPDMA_TX_DRV			BIT(8)
30 #define MTK_WED_RESET_WPDMA_RX_DRV			BIT(9)
31 #define MTK_WED_RESET_WPDMA_RX_D_DRV			BIT(10)
32 #define MTK_WED_RESET_WPDMA_INT_AGENT			BIT(11)
33 #define MTK_WED_RESET_WED_TX_DMA			BIT(12)
34 #define MTK_WED_RESET_WED_RX_DMA			BIT(13)
35 #define MTK_WED_RESET_WDMA_TX_DRV			BIT(16)
36 #define MTK_WED_RESET_WDMA_RX_DRV			BIT(17)
37 #define MTK_WED_RESET_WDMA_INT_AGENT			BIT(19)
38 #define MTK_WED_RESET_RX_RRO_QM				BIT(20)
39 #define MTK_WED_RESET_RX_ROUTE_QM			BIT(21)
40 #define MTK_WED_RESET_WED				BIT(31)
41 
42 #define MTK_WED_CTRL					0x00c
43 #define MTK_WED_CTRL_WPDMA_INT_AGENT_EN			BIT(0)
44 #define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY		BIT(1)
45 #define MTK_WED_CTRL_WDMA_INT_AGENT_EN			BIT(2)
46 #define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY		BIT(3)
47 #define MTK_WED_CTRL_WED_TX_BM_EN			BIT(8)
48 #define MTK_WED_CTRL_WED_TX_BM_BUSY			BIT(9)
49 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN		BIT(10)
50 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY		BIT(11)
51 #define MTK_WED_CTRL_WED_RX_BM_EN			BIT(12)
52 #define MTK_WED_CTRL_WED_RX_BM_BUSY			BIT(13)
53 #define MTK_WED_CTRL_RX_RRO_QM_EN			BIT(14)
54 #define MTK_WED_CTRL_RX_RRO_QM_BUSY			BIT(15)
55 #define MTK_WED_CTRL_RX_ROUTE_QM_EN			BIT(16)
56 #define MTK_WED_CTRL_RX_ROUTE_QM_BUSY			BIT(17)
57 #define MTK_WED_CTRL_FINAL_DIDX_READ			BIT(24)
58 #define MTK_WED_CTRL_ETH_DMAD_FMT			BIT(25)
59 #define MTK_WED_CTRL_MIB_READ_CLEAR			BIT(28)
60 
61 #define MTK_WED_EXT_INT_STATUS				0x020
62 #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR		BIT(0)
63 #define MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD		BIT(1)
64 #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID	BIT(4)
65 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH		BIT(8)
66 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH		BIT(9)
67 #define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH		BIT(12)
68 #define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH		BIT(13)
69 #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR	BIT(16)
70 #define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR	BIT(17)
71 #define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT		BIT(18)
72 #define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN	BIT(19)
73 #define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT	BIT(20)
74 #define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR	BIT(21)
75 #define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR	BIT(22)
76 #define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR	BIT(23)
77 #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE	BIT(24)
78 #define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP	BIT(25)
79 #define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR	BIT(26)
80 #define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY		BIT(27)
81 #define MTK_WED_EXT_INT_STATUS_ERROR_MASK		(MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \
82 							 MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \
83 							 MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \
84 							 MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \
85 							 MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \
86 							 MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \
87 							 MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR)
88 
89 #define MTK_WED_EXT_INT_MASK				0x028
90 #define MTK_WED_EXT_INT_MASK1				0x02c
91 #define MTK_WED_EXT_INT_MASK2				0x030
92 
93 #define MTK_WED_STATUS					0x060
94 #define MTK_WED_STATUS_TX				GENMASK(15, 8)
95 
96 #define MTK_WED_TX_BM_CTRL				0x080
97 #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM			GENMASK(6, 0)
98 #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM			GENMASK(22, 16)
99 #define MTK_WED_TX_BM_CTRL_PAUSE			BIT(28)
100 
101 #define MTK_WED_TX_BM_BASE				0x084
102 
103 #define MTK_WED_TX_BM_TKID				0x088
104 #define MTK_WED_TX_BM_TKID_V2				0x0c8
105 #define MTK_WED_TX_BM_TKID_START			GENMASK(15, 0)
106 #define MTK_WED_TX_BM_TKID_END				GENMASK(31, 16)
107 
108 #define MTK_WED_TX_BM_BUF_LEN				0x08c
109 
110 #define MTK_WED_TX_BM_INTF				0x09c
111 #define MTK_WED_TX_BM_INTF_TKID				GENMASK(15, 0)
112 #define MTK_WED_TX_BM_INTF_TKFIFO_FDEP			GENMASK(23, 16)
113 #define MTK_WED_TX_BM_INTF_TKID_VALID			BIT(28)
114 #define MTK_WED_TX_BM_INTF_TKID_READ			BIT(29)
115 
116 #define MTK_WED_TX_BM_DYN_THR				0x0a0
117 #define MTK_WED_TX_BM_DYN_THR_LO			GENMASK(6, 0)
118 #define MTK_WED_TX_BM_DYN_THR_LO_V2			GENMASK(8, 0)
119 #define MTK_WED_TX_BM_DYN_THR_HI			GENMASK(22, 16)
120 #define MTK_WED_TX_BM_DYN_THR_HI_V2			GENMASK(24, 16)
121 
122 #define MTK_WED_TX_TKID_CTRL				0x0c0
123 #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM		GENMASK(6, 0)
124 #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM		GENMASK(22, 16)
125 #define MTK_WED_TX_TKID_CTRL_PAUSE			BIT(28)
126 
127 #define MTK_WED_TX_TKID_DYN_THR				0x0e0
128 #define MTK_WED_TX_TKID_DYN_THR_LO			GENMASK(6, 0)
129 #define MTK_WED_TX_TKID_DYN_THR_HI			GENMASK(22, 16)
130 
131 #define MTK_WED_TXP_DW0					0x120
132 #define MTK_WED_TXP_DW1					0x124
133 #define MTK_WED_WPDMA_WRITE_TXP				GENMASK(31, 16)
134 #define MTK_WED_TXDP_CTRL				0x130
135 #define MTK_WED_TXDP_DW9_OVERWR				BIT(9)
136 #define MTK_WED_RX_BM_TKID_MIB				0x1cc
137 
138 #define MTK_WED_INT_STATUS				0x200
139 #define MTK_WED_INT_MASK				0x204
140 
141 #define MTK_WED_GLO_CFG					0x208
142 #define MTK_WED_GLO_CFG_TX_DMA_EN			BIT(0)
143 #define MTK_WED_GLO_CFG_TX_DMA_BUSY			BIT(1)
144 #define MTK_WED_GLO_CFG_RX_DMA_EN			BIT(2)
145 #define MTK_WED_GLO_CFG_RX_DMA_BUSY			BIT(3)
146 #define MTK_WED_GLO_CFG_RX_BT_SIZE			GENMASK(5, 4)
147 #define MTK_WED_GLO_CFG_TX_WB_DDONE			BIT(6)
148 #define MTK_WED_GLO_CFG_BIG_ENDIAN			BIT(7)
149 #define MTK_WED_GLO_CFG_DIS_BT_SIZE_ALIGN		BIT(8)
150 #define MTK_WED_GLO_CFG_TX_BT_SIZE_LO			BIT(9)
151 #define MTK_WED_GLO_CFG_MULTI_DMA_EN			GENMASK(11, 10)
152 #define MTK_WED_GLO_CFG_FIFO_LITTLE_ENDIAN		BIT(12)
153 #define MTK_WED_GLO_CFG_MI_DEPTH_RD			GENMASK(21, 13)
154 #define MTK_WED_GLO_CFG_TX_BT_SIZE_HI			GENMASK(23, 22)
155 #define MTK_WED_GLO_CFG_SW_RESET			BIT(24)
156 #define MTK_WED_GLO_CFG_FIRST_TOKEN_ONLY		BIT(26)
157 #define MTK_WED_GLO_CFG_OMIT_RX_INFO			BIT(27)
158 #define MTK_WED_GLO_CFG_OMIT_TX_INFO			BIT(28)
159 #define MTK_WED_GLO_CFG_BYTE_SWAP			BIT(29)
160 #define MTK_WED_GLO_CFG_RX_2B_OFFSET			BIT(31)
161 
162 #define MTK_WED_RESET_IDX				0x20c
163 #define MTK_WED_RESET_IDX_TX				GENMASK(3, 0)
164 #define MTK_WED_RESET_IDX_RX				GENMASK(17, 16)
165 #define MTK_WED_RESET_IDX_RX_V2				GENMASK(7, 6)
166 #define MTK_WED_RESET_WPDMA_IDX_RX			GENMASK(31, 30)
167 
168 #define MTK_WED_TX_MIB(_n)				(0x2a0 + (_n) * 4)
169 #define MTK_WED_RX_MIB(_n)				(0x2e0 + (_n) * 4)
170 
171 #define MTK_WED_RING_TX(_n)				(0x300 + (_n) * 0x10)
172 
173 #define MTK_WED_RING_RX(_n)				(0x400 + (_n) * 0x10)
174 #define MTK_WED_RING_RX_DATA(_n)			(0x420 + (_n) * 0x10)
175 
176 #define MTK_WED_SCR0					0x3c0
177 #define MTK_WED_WPDMA_INT_TRIGGER			0x504
178 #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE		BIT(1)
179 #define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE		GENMASK(5, 4)
180 
181 #define MTK_WED_WPDMA_GLO_CFG				0x508
182 #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN			BIT(0)
183 #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY		BIT(1)
184 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN			BIT(2)
185 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY		BIT(3)
186 #define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE		GENMASK(5, 4)
187 #define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE		BIT(6)
188 #define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN		BIT(7)
189 #define MTK_WED_WPDMA_GLO_CFG_DIS_BT_SIZE_ALIGN		BIT(8)
190 #define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_LO		BIT(9)
191 #define MTK_WED_WPDMA_GLO_CFG_MULTI_DMA_EN		GENMASK(11, 10)
192 #define MTK_WED_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN	BIT(12)
193 #define MTK_WED_WPDMA_GLO_CFG_MI_DEPTH_RD		GENMASK(21, 13)
194 #define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_HI		GENMASK(23, 22)
195 #define MTK_WED_WPDMA_GLO_CFG_SW_RESET			BIT(24)
196 #define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY		BIT(26)
197 #define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO		BIT(27)
198 #define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO		BIT(28)
199 #define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP			BIT(29)
200 #define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET		BIT(31)
201 
202 /* CONFIG_MEDIATEK_NETSYS_V2 */
203 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC	BIT(4)
204 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC	BIT(5)
205 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC	BIT(6)
206 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC	BIT(7)
207 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER	GENMASK(18, 16)
208 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT	BIT(19)
209 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UEVENT_PKT_FMT_CHK BIT(20)
210 #define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR		BIT(21)
211 #define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP		BIT(24)
212 #define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV		BIT(28)
213 
214 #define MTK_WED_WPDMA_RESET_IDX				0x50c
215 #define MTK_WED_WPDMA_RESET_IDX_TX			GENMASK(3, 0)
216 #define MTK_WED_WPDMA_RESET_IDX_RX			GENMASK(17, 16)
217 
218 #define MTK_WED_WPDMA_CTRL				0x518
219 #define MTK_WED_WPDMA_CTRL_SDL1_FIXED			BIT(31)
220 
221 #define MTK_WED_WPDMA_INT_CTRL				0x520
222 #define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV		BIT(21)
223 #define MTK_WED_WPDMA_INT_CTRL_SIG_SRC			BIT(22)
224 #define MTK_WED_WPDMA_INT_CTRL_SRC_SEL			GENMASK(17, 16)
225 
226 #define MTK_WED_WPDMA_INT_MASK				0x524
227 
228 #define MTK_WED_WPDMA_INT_CTRL_TX			0x530
229 #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN		BIT(0)
230 #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR		BIT(1)
231 #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG		GENMASK(6, 2)
232 #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN		BIT(8)
233 #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR		BIT(9)
234 #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG		GENMASK(14, 10)
235 
236 #define MTK_WED_WPDMA_INT_CTRL_RX			0x534
237 #define MTK_WED_WPDMA_INT_CTRL_RX0_EN			BIT(0)
238 #define MTK_WED_WPDMA_INT_CTRL_RX0_CLR			BIT(1)
239 #define MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG		GENMASK(6, 2)
240 #define MTK_WED_WPDMA_INT_CTRL_RX1_EN			BIT(8)
241 #define MTK_WED_WPDMA_INT_CTRL_RX1_CLR			BIT(9)
242 #define MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG		GENMASK(14, 10)
243 
244 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE			0x538
245 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN		BIT(0)
246 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR		BIT(1)
247 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG	GENMASK(6, 2)
248 
249 #define MTK_WED_PCIE_CFG_BASE				0x560
250 
251 #define MTK_WED_PCIE_CFG_BASE				0x560
252 #define MTK_WED_PCIE_CFG_INTM				0x564
253 #define MTK_WED_PCIE_CFG_MSIS				0x568
254 #define MTK_WED_PCIE_INT_TRIGGER			0x570
255 #define MTK_WED_PCIE_INT_TRIGGER_STATUS			BIT(16)
256 
257 #define MTK_WED_PCIE_INT_CTRL				0x57c
258 #define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA		BIT(20)
259 #define MTK_WED_PCIE_INT_CTRL_SRC_SEL			GENMASK(17, 16)
260 #define MTK_WED_PCIE_INT_CTRL_POLL_EN			GENMASK(13, 12)
261 
262 #define MTK_WED_WPDMA_CFG_BASE				0x580
263 #define MTK_WED_WPDMA_CFG_INT_MASK			0x584
264 #define MTK_WED_WPDMA_CFG_TX				0x588
265 #define MTK_WED_WPDMA_CFG_TX_FREE			0x58c
266 
267 #define MTK_WED_WPDMA_TX_MIB(_n)			(0x5a0 + (_n) * 4)
268 #define MTK_WED_WPDMA_TX_COHERENT_MIB(_n)		(0x5d0 + (_n) * 4)
269 
270 #define MTK_WED_WPDMA_RING_TX(_n)			(0x600 + (_n) * 0x10)
271 #define MTK_WED_WPDMA_RING_RX(_n)			(0x700 + (_n) * 0x10)
272 #define MTK_WED_WPDMA_RING_RX_DATA(_n)			(0x730 + (_n) * 0x10)
273 
274 #define MTK_WED_WPDMA_RX_D_GLO_CFG			0x75c
275 #define MTK_WED_WPDMA_RX_D_RX_DRV_EN			BIT(0)
276 #define MTK_WED_WPDMA_RX_D_RX_DRV_BUSY			BIT(1)
277 #define MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE		BIT(3)
278 #define MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE		BIT(4)
279 #define MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL		GENMASK(11, 7)
280 #define MTK_WED_WPDMA_RX_D_RXD_READ_LEN			GENMASK(31, 24)
281 
282 #define MTK_WED_WPDMA_RX_D_RST_IDX			0x760
283 #define MTK_WED_WPDMA_RX_D_RST_CRX_IDX			GENMASK(17, 16)
284 #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX			GENMASK(25, 24)
285 
286 #define MTK_WED_WPDMA_RX_GLO_CFG			0x76c
287 #define MTK_WED_WPDMA_RX_RING				0x770
288 
289 #define MTK_WED_WPDMA_RX_D_MIB(_n)			(0x774 + (_n) * 4)
290 #define MTK_WED_WPDMA_RX_D_PROCESSED_MIB(_n)		(0x784 + (_n) * 4)
291 #define MTK_WED_WPDMA_RX_D_COHERENT_MIB			0x78c
292 
293 #define MTK_WED_WDMA_RING_TX				0x800
294 
295 #define MTK_WED_WDMA_TX_MIB				0x810
296 
297 #define MTK_WED_WDMA_RING_RX(_n)			(0x900 + (_n) * 0x10)
298 #define MTK_WED_WDMA_RX_THRES(_n)			(0x940 + (_n) * 0x4)
299 
300 #define MTK_WED_WDMA_GLO_CFG				0xa04
301 #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN			BIT(0)
302 #define MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK		BIT(1)
303 #define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN			BIT(2)
304 #define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY		BIT(3)
305 #define MTK_WED_WDMA_GLO_CFG_BT_SIZE			GENMASK(5, 4)
306 #define MTK_WED_WDMA_GLO_CFG_TX_WB_DDONE		BIT(6)
307 #define MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE	BIT(13)
308 #define MTK_WED_WDMA_GLO_CFG_WCOMPLETE_SEL		BIT(16)
309 #define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_RXDMA_BYPASS	BIT(17)
310 #define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_BYPASS		BIT(18)
311 #define MTK_WED_WDMA_GLO_CFG_FSM_RETURN_IDLE		BIT(19)
312 #define MTK_WED_WDMA_GLO_CFG_WAIT_COHERENT		BIT(20)
313 #define MTK_WED_WDMA_GLO_CFG_AXI_W_AFTER_AW		BIT(21)
314 #define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY_SINGLE_W	BIT(22)
315 #define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY		BIT(23)
316 #define MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP	BIT(24)
317 #define MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE	BIT(25)
318 #define MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE		BIT(26)
319 #define MTK_WED_WDMA_GLO_CFG_RXDRV_CLKGATE_BYPASS	BIT(30)
320 
321 #define MTK_WED_WDMA_RESET_IDX				0xa08
322 #define MTK_WED_WDMA_RESET_IDX_RX			GENMASK(17, 16)
323 #define MTK_WED_WDMA_RESET_IDX_DRV			GENMASK(25, 24)
324 
325 #define MTK_WED_WDMA_INT_CLR				0xa24
326 #define MTK_WED_WDMA_INT_CLR_RX_DONE			GENMASK(17, 16)
327 
328 #define MTK_WED_WDMA_INT_TRIGGER			0xa28
329 #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE		GENMASK(17, 16)
330 
331 #define MTK_WED_WDMA_INT_CTRL				0xa2c
332 #define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL		GENMASK(17, 16)
333 
334 #define MTK_WED_WDMA_CFG_BASE				0xaa0
335 #define MTK_WED_WDMA_OFFSET0				0xaa4
336 #define MTK_WED_WDMA_OFFSET1				0xaa8
337 
338 #define MTK_WED_WDMA_OFST0_GLO_INTS			GENMASK(15, 0)
339 #define MTK_WED_WDMA_OFST0_GLO_CFG			GENMASK(31, 16)
340 #define MTK_WED_WDMA_OFST1_TX_CTRL			GENMASK(15, 0)
341 #define MTK_WED_WDMA_OFST1_RX_CTRL			GENMASK(31, 16)
342 
343 #define MTK_WED_WDMA_RX_MIB(_n)				(0xae0 + (_n) * 4)
344 #define MTK_WED_WDMA_RX_RECYCLE_MIB(_n)			(0xae8 + (_n) * 4)
345 #define MTK_WED_WDMA_RX_PROCESSED_MIB(_n)		(0xaf0 + (_n) * 4)
346 
347 #define MTK_WED_RX_BM_RX_DMAD				0xd80
348 #define MTK_WED_RX_BM_RX_DMAD_SDL0			GENMASK(13, 0)
349 
350 #define MTK_WED_RX_BM_BASE				0xd84
351 #define MTK_WED_RX_BM_INIT_PTR				0xd88
352 #define MTK_WED_RX_BM_SW_TAIL				GENMASK(15, 0)
353 #define MTK_WED_RX_BM_INIT_SW_TAIL			BIT(16)
354 
355 #define MTK_WED_RX_PTR					0xd8c
356 
357 #define MTK_WED_RX_BM_DYN_ALLOC_TH			0xdb4
358 #define MTK_WED_RX_BM_DYN_ALLOC_TH_H			GENMASK(31, 16)
359 #define MTK_WED_RX_BM_DYN_ALLOC_TH_L			GENMASK(15, 0)
360 
361 #define MTK_WED_RING_OFS_BASE				0x00
362 #define MTK_WED_RING_OFS_COUNT				0x04
363 #define MTK_WED_RING_OFS_CPU_IDX			0x08
364 #define MTK_WED_RING_OFS_DMA_IDX			0x0c
365 
366 #define MTK_WDMA_RING_TX(_n)				(0x000 + (_n) * 0x10)
367 #define MTK_WDMA_RING_RX(_n)				(0x100 + (_n) * 0x10)
368 
369 #define MTK_WDMA_GLO_CFG				0x204
370 #define MTK_WDMA_GLO_CFG_TX_DMA_EN			BIT(0)
371 #define MTK_WDMA_GLO_CFG_TX_DMA_BUSY			BIT(1)
372 #define MTK_WDMA_GLO_CFG_RX_DMA_EN			BIT(2)
373 #define MTK_WDMA_GLO_CFG_RX_DMA_BUSY			BIT(3)
374 #define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES		BIT(26)
375 #define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES		BIT(27)
376 #define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES		BIT(28)
377 
378 #define MTK_WDMA_RESET_IDX				0x208
379 #define MTK_WDMA_RESET_IDX_TX				GENMASK(3, 0)
380 #define MTK_WDMA_RESET_IDX_RX				GENMASK(17, 16)
381 
382 #define MTK_WDMA_INT_STATUS				0x220
383 
384 #define MTK_WDMA_INT_MASK				0x228
385 #define MTK_WDMA_INT_MASK_TX_DONE			GENMASK(3, 0)
386 #define MTK_WDMA_INT_MASK_RX_DONE			GENMASK(17, 16)
387 #define MTK_WDMA_INT_MASK_TX_DELAY			BIT(28)
388 #define MTK_WDMA_INT_MASK_TX_COHERENT			BIT(29)
389 #define MTK_WDMA_INT_MASK_RX_DELAY			BIT(30)
390 #define MTK_WDMA_INT_MASK_RX_COHERENT			BIT(31)
391 
392 #define MTK_WDMA_INT_GRP1				0x250
393 #define MTK_WDMA_INT_GRP2				0x254
394 
395 #define MTK_PCIE_MIRROR_MAP(n)				((n) ? 0x4 : 0x0)
396 #define MTK_PCIE_MIRROR_MAP_EN				BIT(0)
397 #define MTK_PCIE_MIRROR_MAP_WED_ID			BIT(1)
398 
399 /* DMA channel mapping */
400 #define HIFSYS_DMA_AG_MAP				0x008
401 
402 #define MTK_WED_RTQM_GLO_CFG				0xb00
403 #define MTK_WED_RTQM_BUSY				BIT(1)
404 #define MTK_WED_RTQM_Q_RST				BIT(2)
405 #define MTK_WED_RTQM_Q_DBG_BYPASS			BIT(5)
406 #define MTK_WED_RTQM_TXDMAD_FPORT			GENMASK(23, 20)
407 
408 #define MTK_WED_RTQM_R2H_MIB(_n)			(0xb70 + (_n) * 0x4)
409 #define MTK_WED_RTQM_R2Q_MIB(_n)			(0xb78 + (_n) * 0x4)
410 #define MTK_WED_RTQM_Q2N_MIB				0xb80
411 #define MTK_WED_RTQM_Q2H_MIB(_n)			(0xb84 + (_n) * 0x4)
412 
413 #define MTK_WED_RTQM_Q2B_MIB				0xb8c
414 #define MTK_WED_RTQM_PFDBK_MIB				0xb90
415 
416 #define MTK_WED_RROQM_GLO_CFG				0xc04
417 #define MTK_WED_RROQM_RST_IDX				0xc08
418 #define MTK_WED_RROQM_RST_IDX_MIOD			BIT(0)
419 #define MTK_WED_RROQM_RST_IDX_FDBK			BIT(4)
420 
421 #define MTK_WED_RROQM_MIOD_CTRL0			0xc40
422 #define MTK_WED_RROQM_MIOD_CTRL1			0xc44
423 #define MTK_WED_RROQM_MIOD_CNT				GENMASK(11, 0)
424 
425 #define MTK_WED_RROQM_MIOD_CTRL2			0xc48
426 #define MTK_WED_RROQM_MIOD_CTRL3			0xc4c
427 
428 #define MTK_WED_RROQM_FDBK_CTRL0			0xc50
429 #define MTK_WED_RROQM_FDBK_CTRL1			0xc54
430 #define MTK_WED_RROQM_FDBK_CNT				GENMASK(11, 0)
431 
432 #define MTK_WED_RROQM_FDBK_CTRL2			0xc58
433 
434 #define MTK_WED_RROQ_BASE_L				0xc80
435 #define MTK_WED_RROQ_BASE_H				0xc84
436 
437 #define MTK_WED_RROQM_MIOD_CFG				0xc8c
438 #define MTK_WED_RROQM_MIOD_MID_DW			GENMASK(5, 0)
439 #define MTK_WED_RROQM_MIOD_MOD_DW			GENMASK(13, 8)
440 #define MTK_WED_RROQM_MIOD_ENTRY_DW			GENMASK(22, 16)
441 
442 #define MTK_WED_RROQM_MID_MIB				0xcc0
443 #define MTK_WED_RROQM_MOD_MIB				0xcc4
444 #define MTK_WED_RROQM_MOD_COHERENT_MIB			0xcc8
445 #define MTK_WED_RROQM_FDBK_MIB				0xcd0
446 #define MTK_WED_RROQM_FDBK_COHERENT_MIB			0xcd4
447 #define MTK_WED_RROQM_FDBK_IND_MIB			0xce0
448 #define MTK_WED_RROQM_FDBK_ENQ_MIB			0xce4
449 #define MTK_WED_RROQM_FDBK_ANC_MIB			0xce8
450 #define MTK_WED_RROQM_FDBK_ANC2H_MIB			0xcec
451 
452 #define MTK_WED_RX_BM_RX_DMAD				0xd80
453 #define MTK_WED_RX_BM_BASE				0xd84
454 #define MTK_WED_RX_BM_INIT_PTR				0xd88
455 #define MTK_WED_RX_BM_PTR				0xd8c
456 #define MTK_WED_RX_BM_PTR_HEAD				GENMASK(32, 16)
457 #define MTK_WED_RX_BM_PTR_TAIL				GENMASK(15, 0)
458 
459 #define MTK_WED_RX_BM_BLEN				0xd90
460 #define MTK_WED_RX_BM_STS				0xd94
461 #define MTK_WED_RX_BM_INTF2				0xd98
462 #define MTK_WED_RX_BM_INTF				0xd9c
463 #define MTK_WED_RX_BM_ERR_STS				0xda8
464 
465 #define MTK_WED_WOCPU_VIEW_MIOD_BASE			0x8000
466 #define MTK_WED_PCIE_INT_MASK				0x0
467 
468 #endif
469