1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */ 3 4 #include <linux/kernel.h> 5 #include <linux/slab.h> 6 #include <linux/module.h> 7 #include <linux/bitfield.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/skbuff.h> 10 #include <linux/of_platform.h> 11 #include <linux/of_address.h> 12 #include <linux/of_reserved_mem.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/debugfs.h> 15 #include <linux/soc/mediatek/mtk_wed.h> 16 #include "mtk_eth_soc.h" 17 #include "mtk_wed_regs.h" 18 #include "mtk_wed.h" 19 #include "mtk_ppe.h" 20 #include "mtk_wed_wo.h" 21 22 #define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000) 23 24 #define MTK_WED_PKT_SIZE 1900 25 #define MTK_WED_BUF_SIZE 2048 26 #define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048) 27 #define MTK_WED_RX_RING_SIZE 1536 28 29 #define MTK_WED_TX_RING_SIZE 2048 30 #define MTK_WED_WDMA_RING_SIZE 1024 31 #define MTK_WED_MAX_GROUP_SIZE 0x100 32 #define MTK_WED_VLD_GROUP_SIZE 0x40 33 #define MTK_WED_PER_GROUP_PKT 128 34 35 #define MTK_WED_FBUF_SIZE 128 36 #define MTK_WED_MIOD_CNT 16 37 #define MTK_WED_FB_CMD_CNT 1024 38 #define MTK_WED_RRO_QUE_CNT 8192 39 #define MTK_WED_MIOD_ENTRY_CNT 128 40 41 static struct mtk_wed_hw *hw_list[2]; 42 static DEFINE_MUTEX(hw_lock); 43 44 static void 45 wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val) 46 { 47 regmap_update_bits(dev->hw->regs, reg, mask | val, val); 48 } 49 50 static void 51 wed_set(struct mtk_wed_device *dev, u32 reg, u32 mask) 52 { 53 return wed_m32(dev, reg, 0, mask); 54 } 55 56 static void 57 wed_clr(struct mtk_wed_device *dev, u32 reg, u32 mask) 58 { 59 return wed_m32(dev, reg, mask, 0); 60 } 61 62 static void 63 wdma_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val) 64 { 65 wdma_w32(dev, reg, (wdma_r32(dev, reg) & ~mask) | val); 66 } 67 68 static void 69 wdma_set(struct mtk_wed_device *dev, u32 reg, u32 mask) 70 { 71 wdma_m32(dev, reg, 0, mask); 72 } 73 74 static void 75 wdma_clr(struct mtk_wed_device *dev, u32 reg, u32 mask) 76 { 77 wdma_m32(dev, reg, mask, 0); 78 } 79 80 static u32 81 wifi_r32(struct mtk_wed_device *dev, u32 reg) 82 { 83 return readl(dev->wlan.base + reg); 84 } 85 86 static void 87 wifi_w32(struct mtk_wed_device *dev, u32 reg, u32 val) 88 { 89 writel(val, dev->wlan.base + reg); 90 } 91 92 static u32 93 mtk_wed_read_reset(struct mtk_wed_device *dev) 94 { 95 return wed_r32(dev, MTK_WED_RESET); 96 } 97 98 static u32 99 mtk_wdma_read_reset(struct mtk_wed_device *dev) 100 { 101 return wdma_r32(dev, MTK_WDMA_GLO_CFG); 102 } 103 104 static int 105 mtk_wdma_rx_reset(struct mtk_wed_device *dev) 106 { 107 u32 status, mask = MTK_WDMA_GLO_CFG_RX_DMA_BUSY; 108 int i, ret; 109 110 wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_DMA_EN); 111 ret = readx_poll_timeout(mtk_wdma_read_reset, dev, status, 112 !(status & mask), 0, 10000); 113 if (ret) 114 dev_err(dev->hw->dev, "rx reset failed\n"); 115 116 wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX); 117 wdma_w32(dev, MTK_WDMA_RESET_IDX, 0); 118 119 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++) { 120 if (dev->rx_wdma[i].desc) 121 continue; 122 123 wdma_w32(dev, 124 MTK_WDMA_RING_RX(i) + MTK_WED_RING_OFS_CPU_IDX, 0); 125 } 126 127 return ret; 128 } 129 130 static void 131 mtk_wdma_tx_reset(struct mtk_wed_device *dev) 132 { 133 u32 status, mask = MTK_WDMA_GLO_CFG_TX_DMA_BUSY; 134 int i; 135 136 wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN); 137 if (readx_poll_timeout(mtk_wdma_read_reset, dev, status, 138 !(status & mask), 0, 10000)) 139 dev_err(dev->hw->dev, "tx reset failed\n"); 140 141 wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX); 142 wdma_w32(dev, MTK_WDMA_RESET_IDX, 0); 143 144 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++) 145 wdma_w32(dev, 146 MTK_WDMA_RING_TX(i) + MTK_WED_RING_OFS_CPU_IDX, 0); 147 } 148 149 static void 150 mtk_wed_reset(struct mtk_wed_device *dev, u32 mask) 151 { 152 u32 status; 153 154 wed_w32(dev, MTK_WED_RESET, mask); 155 if (readx_poll_timeout(mtk_wed_read_reset, dev, status, 156 !(status & mask), 0, 1000)) 157 WARN_ON_ONCE(1); 158 } 159 160 static u32 161 mtk_wed_wo_read_status(struct mtk_wed_device *dev) 162 { 163 return wed_r32(dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_WO_STATUS); 164 } 165 166 static void 167 mtk_wed_wo_reset(struct mtk_wed_device *dev) 168 { 169 struct mtk_wed_wo *wo = dev->hw->wed_wo; 170 u8 state = MTK_WED_WO_STATE_DISABLE; 171 void __iomem *reg; 172 u32 val; 173 174 mtk_wdma_tx_reset(dev); 175 mtk_wed_reset(dev, MTK_WED_RESET_WED); 176 177 if (mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO, 178 MTK_WED_WO_CMD_CHANGE_STATE, &state, 179 sizeof(state), false)) 180 return; 181 182 if (readx_poll_timeout(mtk_wed_wo_read_status, dev, val, 183 val == MTK_WED_WOIF_DISABLE_DONE, 184 100, MTK_WOCPU_TIMEOUT)) 185 dev_err(dev->hw->dev, "failed to disable wed-wo\n"); 186 187 reg = ioremap(MTK_WED_WO_CPU_MCUSYS_RESET_ADDR, 4); 188 189 val = readl(reg); 190 switch (dev->hw->index) { 191 case 0: 192 val |= MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK; 193 writel(val, reg); 194 val &= ~MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK; 195 writel(val, reg); 196 break; 197 case 1: 198 val |= MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK; 199 writel(val, reg); 200 val &= ~MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK; 201 writel(val, reg); 202 break; 203 default: 204 break; 205 } 206 iounmap(reg); 207 } 208 209 void mtk_wed_fe_reset(void) 210 { 211 int i; 212 213 mutex_lock(&hw_lock); 214 215 for (i = 0; i < ARRAY_SIZE(hw_list); i++) { 216 struct mtk_wed_hw *hw = hw_list[i]; 217 struct mtk_wed_device *dev = hw->wed_dev; 218 int err; 219 220 if (!dev || !dev->wlan.reset) 221 continue; 222 223 /* reset callback blocks until WLAN reset is completed */ 224 err = dev->wlan.reset(dev); 225 if (err) 226 dev_err(dev->dev, "wlan reset failed: %d\n", err); 227 } 228 229 mutex_unlock(&hw_lock); 230 } 231 232 void mtk_wed_fe_reset_complete(void) 233 { 234 int i; 235 236 mutex_lock(&hw_lock); 237 238 for (i = 0; i < ARRAY_SIZE(hw_list); i++) { 239 struct mtk_wed_hw *hw = hw_list[i]; 240 struct mtk_wed_device *dev = hw->wed_dev; 241 242 if (!dev || !dev->wlan.reset_complete) 243 continue; 244 245 dev->wlan.reset_complete(dev); 246 } 247 248 mutex_unlock(&hw_lock); 249 } 250 251 static struct mtk_wed_hw * 252 mtk_wed_assign(struct mtk_wed_device *dev) 253 { 254 struct mtk_wed_hw *hw; 255 int i; 256 257 if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) { 258 hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)]; 259 if (!hw) 260 return NULL; 261 262 if (!hw->wed_dev) 263 goto out; 264 265 if (hw->version == 1) 266 return NULL; 267 268 /* MT7986 WED devices do not have any pcie slot restrictions */ 269 } 270 /* MT7986 PCIE or AXI */ 271 for (i = 0; i < ARRAY_SIZE(hw_list); i++) { 272 hw = hw_list[i]; 273 if (hw && !hw->wed_dev) 274 goto out; 275 } 276 277 return NULL; 278 279 out: 280 hw->wed_dev = dev; 281 return hw; 282 } 283 284 static int 285 mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev) 286 { 287 struct mtk_wdma_desc *desc; 288 dma_addr_t desc_phys; 289 void **page_list; 290 int token = dev->wlan.token_start; 291 int ring_size; 292 int n_pages; 293 int i, page_idx; 294 295 ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1); 296 n_pages = ring_size / MTK_WED_BUF_PER_PAGE; 297 298 page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL); 299 if (!page_list) 300 return -ENOMEM; 301 302 dev->tx_buf_ring.size = ring_size; 303 dev->tx_buf_ring.pages = page_list; 304 305 desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc), 306 &desc_phys, GFP_KERNEL); 307 if (!desc) 308 return -ENOMEM; 309 310 dev->tx_buf_ring.desc = desc; 311 dev->tx_buf_ring.desc_phys = desc_phys; 312 313 for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) { 314 dma_addr_t page_phys, buf_phys; 315 struct page *page; 316 void *buf; 317 int s; 318 319 page = __dev_alloc_pages(GFP_KERNEL, 0); 320 if (!page) 321 return -ENOMEM; 322 323 page_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE, 324 DMA_BIDIRECTIONAL); 325 if (dma_mapping_error(dev->hw->dev, page_phys)) { 326 __free_page(page); 327 return -ENOMEM; 328 } 329 330 page_list[page_idx++] = page; 331 dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE, 332 DMA_BIDIRECTIONAL); 333 334 buf = page_to_virt(page); 335 buf_phys = page_phys; 336 337 for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) { 338 u32 txd_size; 339 u32 ctrl; 340 341 txd_size = dev->wlan.init_buf(buf, buf_phys, token++); 342 343 desc->buf0 = cpu_to_le32(buf_phys); 344 desc->buf1 = cpu_to_le32(buf_phys + txd_size); 345 346 if (dev->hw->version == 1) 347 ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) | 348 FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1, 349 MTK_WED_BUF_SIZE - txd_size) | 350 MTK_WDMA_DESC_CTRL_LAST_SEG1; 351 else 352 ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) | 353 FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2, 354 MTK_WED_BUF_SIZE - txd_size) | 355 MTK_WDMA_DESC_CTRL_LAST_SEG0; 356 desc->ctrl = cpu_to_le32(ctrl); 357 desc->info = 0; 358 desc++; 359 360 buf += MTK_WED_BUF_SIZE; 361 buf_phys += MTK_WED_BUF_SIZE; 362 } 363 364 dma_sync_single_for_device(dev->hw->dev, page_phys, PAGE_SIZE, 365 DMA_BIDIRECTIONAL); 366 } 367 368 return 0; 369 } 370 371 static void 372 mtk_wed_free_tx_buffer(struct mtk_wed_device *dev) 373 { 374 struct mtk_wdma_desc *desc = dev->tx_buf_ring.desc; 375 void **page_list = dev->tx_buf_ring.pages; 376 int page_idx; 377 int i; 378 379 if (!page_list) 380 return; 381 382 if (!desc) 383 goto free_pagelist; 384 385 for (i = 0, page_idx = 0; i < dev->tx_buf_ring.size; 386 i += MTK_WED_BUF_PER_PAGE) { 387 void *page = page_list[page_idx++]; 388 dma_addr_t buf_addr; 389 390 if (!page) 391 break; 392 393 buf_addr = le32_to_cpu(desc[i].buf0); 394 dma_unmap_page(dev->hw->dev, buf_addr, PAGE_SIZE, 395 DMA_BIDIRECTIONAL); 396 __free_page(page); 397 } 398 399 dma_free_coherent(dev->hw->dev, dev->tx_buf_ring.size * sizeof(*desc), 400 desc, dev->tx_buf_ring.desc_phys); 401 402 free_pagelist: 403 kfree(page_list); 404 } 405 406 static int 407 mtk_wed_rx_buffer_alloc(struct mtk_wed_device *dev) 408 { 409 struct mtk_rxbm_desc *desc; 410 dma_addr_t desc_phys; 411 412 dev->rx_buf_ring.size = dev->wlan.rx_nbuf; 413 desc = dma_alloc_coherent(dev->hw->dev, 414 dev->wlan.rx_nbuf * sizeof(*desc), 415 &desc_phys, GFP_KERNEL); 416 if (!desc) 417 return -ENOMEM; 418 419 dev->rx_buf_ring.desc = desc; 420 dev->rx_buf_ring.desc_phys = desc_phys; 421 dev->wlan.init_rx_buf(dev, dev->wlan.rx_npkt); 422 423 return 0; 424 } 425 426 static void 427 mtk_wed_free_rx_buffer(struct mtk_wed_device *dev) 428 { 429 struct mtk_rxbm_desc *desc = dev->rx_buf_ring.desc; 430 431 if (!desc) 432 return; 433 434 dev->wlan.release_rx_buf(dev); 435 dma_free_coherent(dev->hw->dev, dev->rx_buf_ring.size * sizeof(*desc), 436 desc, dev->rx_buf_ring.desc_phys); 437 } 438 439 static void 440 mtk_wed_rx_buffer_hw_init(struct mtk_wed_device *dev) 441 { 442 wed_w32(dev, MTK_WED_RX_BM_RX_DMAD, 443 FIELD_PREP(MTK_WED_RX_BM_RX_DMAD_SDL0, dev->wlan.rx_size)); 444 wed_w32(dev, MTK_WED_RX_BM_BASE, dev->rx_buf_ring.desc_phys); 445 wed_w32(dev, MTK_WED_RX_BM_INIT_PTR, MTK_WED_RX_BM_INIT_SW_TAIL | 446 FIELD_PREP(MTK_WED_RX_BM_SW_TAIL, dev->wlan.rx_npkt)); 447 wed_w32(dev, MTK_WED_RX_BM_DYN_ALLOC_TH, 448 FIELD_PREP(MTK_WED_RX_BM_DYN_ALLOC_TH_H, 0xffff)); 449 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN); 450 } 451 452 static void 453 mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring) 454 { 455 if (!ring->desc) 456 return; 457 458 dma_free_coherent(dev->hw->dev, ring->size * ring->desc_size, 459 ring->desc, ring->desc_phys); 460 } 461 462 static void 463 mtk_wed_free_rx_rings(struct mtk_wed_device *dev) 464 { 465 mtk_wed_free_rx_buffer(dev); 466 mtk_wed_free_ring(dev, &dev->rro.ring); 467 } 468 469 static void 470 mtk_wed_free_tx_rings(struct mtk_wed_device *dev) 471 { 472 int i; 473 474 for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) 475 mtk_wed_free_ring(dev, &dev->tx_ring[i]); 476 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++) 477 mtk_wed_free_ring(dev, &dev->rx_wdma[i]); 478 } 479 480 static void 481 mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en) 482 { 483 u32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK; 484 485 if (dev->hw->version == 1) 486 mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR; 487 else 488 mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH | 489 MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH | 490 MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT | 491 MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR; 492 493 if (!dev->hw->num_flows) 494 mask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD; 495 496 wed_w32(dev, MTK_WED_EXT_INT_MASK, en ? mask : 0); 497 wed_r32(dev, MTK_WED_EXT_INT_MASK); 498 } 499 500 static void 501 mtk_wed_set_512_support(struct mtk_wed_device *dev, bool enable) 502 { 503 if (enable) { 504 wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR); 505 wed_w32(dev, MTK_WED_TXP_DW1, 506 FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0103)); 507 } else { 508 wed_w32(dev, MTK_WED_TXP_DW1, 509 FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0100)); 510 wed_clr(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR); 511 } 512 } 513 514 #define MTK_WFMDA_RX_DMA_EN BIT(2) 515 static void 516 mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev, int idx) 517 { 518 u32 val; 519 int i; 520 521 if (!(dev->rx_ring[idx].flags & MTK_WED_RING_CONFIGURED)) 522 return; /* queue is not configured by mt76 */ 523 524 for (i = 0; i < 3; i++) { 525 u32 cur_idx; 526 527 cur_idx = wed_r32(dev, 528 MTK_WED_WPDMA_RING_RX_DATA(idx) + 529 MTK_WED_RING_OFS_CPU_IDX); 530 if (cur_idx == MTK_WED_RX_RING_SIZE - 1) 531 break; 532 533 usleep_range(100000, 200000); 534 } 535 536 if (i == 3) { 537 dev_err(dev->hw->dev, "rx dma enable failed\n"); 538 return; 539 } 540 541 val = wifi_r32(dev, dev->wlan.wpdma_rx_glo - dev->wlan.phy_base) | 542 MTK_WFMDA_RX_DMA_EN; 543 wifi_w32(dev, dev->wlan.wpdma_rx_glo - dev->wlan.phy_base, val); 544 } 545 546 static void 547 mtk_wed_dma_disable(struct mtk_wed_device *dev) 548 { 549 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, 550 MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | 551 MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); 552 553 wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); 554 555 wed_clr(dev, MTK_WED_GLO_CFG, 556 MTK_WED_GLO_CFG_TX_DMA_EN | 557 MTK_WED_GLO_CFG_RX_DMA_EN); 558 559 wdma_clr(dev, MTK_WDMA_GLO_CFG, 560 MTK_WDMA_GLO_CFG_TX_DMA_EN | 561 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES | 562 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES); 563 564 if (dev->hw->version == 1) { 565 regmap_write(dev->hw->mirror, dev->hw->index * 4, 0); 566 wdma_clr(dev, MTK_WDMA_GLO_CFG, 567 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES); 568 } else { 569 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, 570 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC | 571 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC); 572 573 wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, 574 MTK_WED_WPDMA_RX_D_RX_DRV_EN); 575 wed_clr(dev, MTK_WED_WDMA_GLO_CFG, 576 MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK); 577 } 578 579 mtk_wed_set_512_support(dev, false); 580 } 581 582 static void 583 mtk_wed_stop(struct mtk_wed_device *dev) 584 { 585 mtk_wed_set_ext_int(dev, false); 586 587 wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0); 588 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0); 589 wdma_w32(dev, MTK_WDMA_INT_MASK, 0); 590 wdma_w32(dev, MTK_WDMA_INT_GRP2, 0); 591 wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0); 592 593 if (dev->hw->version == 1) 594 return; 595 596 wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0); 597 wed_w32(dev, MTK_WED_EXT_INT_MASK2, 0); 598 } 599 600 static void 601 mtk_wed_deinit(struct mtk_wed_device *dev) 602 { 603 mtk_wed_stop(dev); 604 mtk_wed_dma_disable(dev); 605 606 wed_clr(dev, MTK_WED_CTRL, 607 MTK_WED_CTRL_WDMA_INT_AGENT_EN | 608 MTK_WED_CTRL_WPDMA_INT_AGENT_EN | 609 MTK_WED_CTRL_WED_TX_BM_EN | 610 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); 611 612 if (dev->hw->version == 1) 613 return; 614 615 wed_clr(dev, MTK_WED_CTRL, 616 MTK_WED_CTRL_RX_ROUTE_QM_EN | 617 MTK_WED_CTRL_WED_RX_BM_EN | 618 MTK_WED_CTRL_RX_RRO_QM_EN); 619 } 620 621 static void 622 __mtk_wed_detach(struct mtk_wed_device *dev) 623 { 624 struct mtk_wed_hw *hw = dev->hw; 625 626 mtk_wed_deinit(dev); 627 628 mtk_wdma_rx_reset(dev); 629 mtk_wed_reset(dev, MTK_WED_RESET_WED); 630 mtk_wed_free_tx_buffer(dev); 631 mtk_wed_free_tx_rings(dev); 632 633 if (mtk_wed_get_rx_capa(dev)) { 634 if (hw->wed_wo) 635 mtk_wed_wo_reset(dev); 636 mtk_wed_free_rx_rings(dev); 637 if (hw->wed_wo) 638 mtk_wed_wo_deinit(hw); 639 } 640 641 if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) { 642 struct device_node *wlan_node; 643 644 wlan_node = dev->wlan.pci_dev->dev.of_node; 645 if (of_dma_is_coherent(wlan_node) && hw->hifsys) 646 regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, 647 BIT(hw->index), BIT(hw->index)); 648 } 649 650 if (!hw_list[!hw->index]->wed_dev && 651 hw->eth->dma_dev != hw->eth->dev) 652 mtk_eth_set_dma_device(hw->eth, hw->eth->dev); 653 654 memset(dev, 0, sizeof(*dev)); 655 module_put(THIS_MODULE); 656 657 hw->wed_dev = NULL; 658 } 659 660 static void 661 mtk_wed_detach(struct mtk_wed_device *dev) 662 { 663 mutex_lock(&hw_lock); 664 __mtk_wed_detach(dev); 665 mutex_unlock(&hw_lock); 666 } 667 668 #define PCIE_BASE_ADDR0 0x11280000 669 static void 670 mtk_wed_bus_init(struct mtk_wed_device *dev) 671 { 672 switch (dev->wlan.bus_type) { 673 case MTK_WED_BUS_PCIE: { 674 struct device_node *np = dev->hw->eth->dev->of_node; 675 struct regmap *regs; 676 677 regs = syscon_regmap_lookup_by_phandle(np, 678 "mediatek,wed-pcie"); 679 if (IS_ERR(regs)) 680 break; 681 682 regmap_update_bits(regs, 0, BIT(0), BIT(0)); 683 684 wed_w32(dev, MTK_WED_PCIE_INT_CTRL, 685 FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2)); 686 687 /* pcie interrupt control: pola/source selection */ 688 wed_set(dev, MTK_WED_PCIE_INT_CTRL, 689 MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA | 690 FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1)); 691 wed_r32(dev, MTK_WED_PCIE_INT_CTRL); 692 693 wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180); 694 wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184); 695 696 /* pcie interrupt status trigger register */ 697 wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24)); 698 wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER); 699 700 /* pola setting */ 701 wed_set(dev, MTK_WED_PCIE_INT_CTRL, 702 MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA); 703 break; 704 } 705 case MTK_WED_BUS_AXI: 706 wed_set(dev, MTK_WED_WPDMA_INT_CTRL, 707 MTK_WED_WPDMA_INT_CTRL_SIG_SRC | 708 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_SRC_SEL, 0)); 709 break; 710 default: 711 break; 712 } 713 } 714 715 static void 716 mtk_wed_set_wpdma(struct mtk_wed_device *dev) 717 { 718 if (dev->hw->version == 1) { 719 wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys); 720 } else { 721 mtk_wed_bus_init(dev); 722 723 wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int); 724 wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask); 725 wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx); 726 wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree); 727 wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo); 728 wed_w32(dev, MTK_WED_WPDMA_RX_RING, dev->wlan.wpdma_rx); 729 } 730 } 731 732 static void 733 mtk_wed_hw_init_early(struct mtk_wed_device *dev) 734 { 735 u32 mask, set; 736 737 mtk_wed_deinit(dev); 738 mtk_wed_reset(dev, MTK_WED_RESET_WED); 739 mtk_wed_set_wpdma(dev); 740 741 mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE | 742 MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE | 743 MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE; 744 set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) | 745 MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP | 746 MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY; 747 wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set); 748 749 if (dev->hw->version == 1) { 750 u32 offset = dev->hw->index ? 0x04000400 : 0; 751 752 wdma_set(dev, MTK_WDMA_GLO_CFG, 753 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES | 754 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES | 755 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES); 756 757 wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset); 758 wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset); 759 wed_w32(dev, MTK_WED_PCIE_CFG_BASE, 760 MTK_PCIE_BASE(dev->hw->index)); 761 } else { 762 wed_w32(dev, MTK_WED_WDMA_CFG_BASE, dev->hw->wdma_phy); 763 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_ETH_DMAD_FMT); 764 wed_w32(dev, MTK_WED_WDMA_OFFSET0, 765 FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_INTS, 766 MTK_WDMA_INT_STATUS) | 767 FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_CFG, 768 MTK_WDMA_GLO_CFG)); 769 770 wed_w32(dev, MTK_WED_WDMA_OFFSET1, 771 FIELD_PREP(MTK_WED_WDMA_OFST1_TX_CTRL, 772 MTK_WDMA_RING_TX(0)) | 773 FIELD_PREP(MTK_WED_WDMA_OFST1_RX_CTRL, 774 MTK_WDMA_RING_RX(0))); 775 } 776 } 777 778 static int 779 mtk_wed_rro_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, 780 int size) 781 { 782 ring->desc = dma_alloc_coherent(dev->hw->dev, 783 size * sizeof(*ring->desc), 784 &ring->desc_phys, GFP_KERNEL); 785 if (!ring->desc) 786 return -ENOMEM; 787 788 ring->desc_size = sizeof(*ring->desc); 789 ring->size = size; 790 791 return 0; 792 } 793 794 #define MTK_WED_MIOD_COUNT (MTK_WED_MIOD_ENTRY_CNT * MTK_WED_MIOD_CNT) 795 static int 796 mtk_wed_rro_alloc(struct mtk_wed_device *dev) 797 { 798 struct reserved_mem *rmem; 799 struct device_node *np; 800 int index; 801 802 index = of_property_match_string(dev->hw->node, "memory-region-names", 803 "wo-dlm"); 804 if (index < 0) 805 return index; 806 807 np = of_parse_phandle(dev->hw->node, "memory-region", index); 808 if (!np) 809 return -ENODEV; 810 811 rmem = of_reserved_mem_lookup(np); 812 of_node_put(np); 813 814 if (!rmem) 815 return -ENODEV; 816 817 dev->rro.miod_phys = rmem->base; 818 dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys; 819 820 return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring, 821 MTK_WED_RRO_QUE_CNT); 822 } 823 824 static int 825 mtk_wed_rro_cfg(struct mtk_wed_device *dev) 826 { 827 struct mtk_wed_wo *wo = dev->hw->wed_wo; 828 struct { 829 struct { 830 __le32 base; 831 __le32 cnt; 832 __le32 unit; 833 } ring[2]; 834 __le32 wed; 835 u8 version; 836 } req = { 837 .ring[0] = { 838 .base = cpu_to_le32(MTK_WED_WOCPU_VIEW_MIOD_BASE), 839 .cnt = cpu_to_le32(MTK_WED_MIOD_CNT), 840 .unit = cpu_to_le32(MTK_WED_MIOD_ENTRY_CNT), 841 }, 842 .ring[1] = { 843 .base = cpu_to_le32(MTK_WED_WOCPU_VIEW_MIOD_BASE + 844 MTK_WED_MIOD_COUNT), 845 .cnt = cpu_to_le32(MTK_WED_FB_CMD_CNT), 846 .unit = cpu_to_le32(4), 847 }, 848 }; 849 850 return mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO, 851 MTK_WED_WO_CMD_WED_CFG, 852 &req, sizeof(req), true); 853 } 854 855 static void 856 mtk_wed_rro_hw_init(struct mtk_wed_device *dev) 857 { 858 wed_w32(dev, MTK_WED_RROQM_MIOD_CFG, 859 FIELD_PREP(MTK_WED_RROQM_MIOD_MID_DW, 0x70 >> 2) | 860 FIELD_PREP(MTK_WED_RROQM_MIOD_MOD_DW, 0x10 >> 2) | 861 FIELD_PREP(MTK_WED_RROQM_MIOD_ENTRY_DW, 862 MTK_WED_MIOD_ENTRY_CNT >> 2)); 863 864 wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL0, dev->rro.miod_phys); 865 wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL1, 866 FIELD_PREP(MTK_WED_RROQM_MIOD_CNT, MTK_WED_MIOD_CNT)); 867 wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL0, dev->rro.fdbk_phys); 868 wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL1, 869 FIELD_PREP(MTK_WED_RROQM_FDBK_CNT, MTK_WED_FB_CMD_CNT)); 870 wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL2, 0); 871 wed_w32(dev, MTK_WED_RROQ_BASE_L, dev->rro.ring.desc_phys); 872 873 wed_set(dev, MTK_WED_RROQM_RST_IDX, 874 MTK_WED_RROQM_RST_IDX_MIOD | 875 MTK_WED_RROQM_RST_IDX_FDBK); 876 877 wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0); 878 wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL2, MTK_WED_MIOD_CNT - 1); 879 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_RRO_QM_EN); 880 } 881 882 static void 883 mtk_wed_route_qm_hw_init(struct mtk_wed_device *dev) 884 { 885 wed_w32(dev, MTK_WED_RESET, MTK_WED_RESET_RX_ROUTE_QM); 886 887 for (;;) { 888 usleep_range(100, 200); 889 if (!(wed_r32(dev, MTK_WED_RESET) & MTK_WED_RESET_RX_ROUTE_QM)) 890 break; 891 } 892 893 /* configure RX_ROUTE_QM */ 894 wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST); 895 wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_TXDMAD_FPORT); 896 wed_set(dev, MTK_WED_RTQM_GLO_CFG, 897 FIELD_PREP(MTK_WED_RTQM_TXDMAD_FPORT, 0x3 + dev->hw->index)); 898 wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST); 899 /* enable RX_ROUTE_QM */ 900 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN); 901 } 902 903 static void 904 mtk_wed_hw_init(struct mtk_wed_device *dev) 905 { 906 if (dev->init_done) 907 return; 908 909 dev->init_done = true; 910 mtk_wed_set_ext_int(dev, false); 911 wed_w32(dev, MTK_WED_TX_BM_CTRL, 912 MTK_WED_TX_BM_CTRL_PAUSE | 913 FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, 914 dev->tx_buf_ring.size / 128) | 915 FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, 916 MTK_WED_TX_RING_SIZE / 256)); 917 918 wed_w32(dev, MTK_WED_TX_BM_BASE, dev->tx_buf_ring.desc_phys); 919 920 wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE); 921 922 if (dev->hw->version == 1) { 923 wed_w32(dev, MTK_WED_TX_BM_TKID, 924 FIELD_PREP(MTK_WED_TX_BM_TKID_START, 925 dev->wlan.token_start) | 926 FIELD_PREP(MTK_WED_TX_BM_TKID_END, 927 dev->wlan.token_start + 928 dev->wlan.nbuf - 1)); 929 wed_w32(dev, MTK_WED_TX_BM_DYN_THR, 930 FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) | 931 MTK_WED_TX_BM_DYN_THR_HI); 932 } else { 933 wed_w32(dev, MTK_WED_TX_BM_TKID_V2, 934 FIELD_PREP(MTK_WED_TX_BM_TKID_START, 935 dev->wlan.token_start) | 936 FIELD_PREP(MTK_WED_TX_BM_TKID_END, 937 dev->wlan.token_start + 938 dev->wlan.nbuf - 1)); 939 wed_w32(dev, MTK_WED_TX_BM_DYN_THR, 940 FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) | 941 MTK_WED_TX_BM_DYN_THR_HI_V2); 942 wed_w32(dev, MTK_WED_TX_TKID_CTRL, 943 MTK_WED_TX_TKID_CTRL_PAUSE | 944 FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM, 945 dev->tx_buf_ring.size / 128) | 946 FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM, 947 dev->tx_buf_ring.size / 128)); 948 wed_w32(dev, MTK_WED_TX_TKID_DYN_THR, 949 FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) | 950 MTK_WED_TX_TKID_DYN_THR_HI); 951 } 952 953 mtk_wed_reset(dev, MTK_WED_RESET_TX_BM); 954 955 if (dev->hw->version == 1) { 956 wed_set(dev, MTK_WED_CTRL, 957 MTK_WED_CTRL_WED_TX_BM_EN | 958 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); 959 } else { 960 wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE); 961 /* rx hw init */ 962 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 963 MTK_WED_WPDMA_RX_D_RST_CRX_IDX | 964 MTK_WED_WPDMA_RX_D_RST_DRV_IDX); 965 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0); 966 967 mtk_wed_rx_buffer_hw_init(dev); 968 mtk_wed_rro_hw_init(dev); 969 mtk_wed_route_qm_hw_init(dev); 970 } 971 972 wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE); 973 } 974 975 static void 976 mtk_wed_ring_reset(struct mtk_wed_ring *ring, int size, bool tx) 977 { 978 void *head = (void *)ring->desc; 979 int i; 980 981 for (i = 0; i < size; i++) { 982 struct mtk_wdma_desc *desc; 983 984 desc = (struct mtk_wdma_desc *)(head + i * ring->desc_size); 985 desc->buf0 = 0; 986 if (tx) 987 desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE); 988 else 989 desc->ctrl = cpu_to_le32(MTK_WFDMA_DESC_CTRL_TO_HOST); 990 desc->buf1 = 0; 991 desc->info = 0; 992 } 993 } 994 995 static u32 996 mtk_wed_check_busy(struct mtk_wed_device *dev, u32 reg, u32 mask) 997 { 998 return !!(wed_r32(dev, reg) & mask); 999 } 1000 1001 static int 1002 mtk_wed_poll_busy(struct mtk_wed_device *dev, u32 reg, u32 mask) 1003 { 1004 int sleep = 15000; 1005 int timeout = 100 * sleep; 1006 u32 val; 1007 1008 return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep, 1009 timeout, false, dev, reg, mask); 1010 } 1011 1012 static int 1013 mtk_wed_rx_reset(struct mtk_wed_device *dev) 1014 { 1015 struct mtk_wed_wo *wo = dev->hw->wed_wo; 1016 u8 val = MTK_WED_WO_STATE_SER_RESET; 1017 int i, ret; 1018 1019 ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO, 1020 MTK_WED_WO_CMD_CHANGE_STATE, &val, 1021 sizeof(val), true); 1022 if (ret) 1023 return ret; 1024 1025 wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RX_DRV_EN); 1026 ret = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, 1027 MTK_WED_WPDMA_RX_D_RX_DRV_BUSY); 1028 if (ret) { 1029 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT); 1030 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_D_DRV); 1031 } else { 1032 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 1033 MTK_WED_WPDMA_RX_D_RST_CRX_IDX | 1034 MTK_WED_WPDMA_RX_D_RST_DRV_IDX); 1035 1036 wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, 1037 MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE | 1038 MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE); 1039 wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, 1040 MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE | 1041 MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE); 1042 1043 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0); 1044 } 1045 1046 /* reset rro qm */ 1047 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_RRO_QM_EN); 1048 ret = mtk_wed_poll_busy(dev, MTK_WED_CTRL, 1049 MTK_WED_CTRL_RX_RRO_QM_BUSY); 1050 if (ret) { 1051 mtk_wed_reset(dev, MTK_WED_RESET_RX_RRO_QM); 1052 } else { 1053 wed_set(dev, MTK_WED_RROQM_RST_IDX, 1054 MTK_WED_RROQM_RST_IDX_MIOD | 1055 MTK_WED_RROQM_RST_IDX_FDBK); 1056 wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0); 1057 } 1058 1059 /* reset route qm */ 1060 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN); 1061 ret = mtk_wed_poll_busy(dev, MTK_WED_CTRL, 1062 MTK_WED_CTRL_RX_ROUTE_QM_BUSY); 1063 if (ret) 1064 mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM); 1065 else 1066 wed_set(dev, MTK_WED_RTQM_GLO_CFG, 1067 MTK_WED_RTQM_Q_RST); 1068 1069 /* reset tx wdma */ 1070 mtk_wdma_tx_reset(dev); 1071 1072 /* reset tx wdma drv */ 1073 wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_TX_DRV_EN); 1074 mtk_wed_poll_busy(dev, MTK_WED_CTRL, 1075 MTK_WED_CTRL_WDMA_INT_AGENT_BUSY); 1076 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV); 1077 1078 /* reset wed rx dma */ 1079 ret = mtk_wed_poll_busy(dev, MTK_WED_GLO_CFG, 1080 MTK_WED_GLO_CFG_RX_DMA_BUSY); 1081 wed_clr(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_RX_DMA_EN); 1082 if (ret) { 1083 mtk_wed_reset(dev, MTK_WED_RESET_WED_RX_DMA); 1084 } else { 1085 struct mtk_eth *eth = dev->hw->eth; 1086 1087 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1088 wed_set(dev, MTK_WED_RESET_IDX, 1089 MTK_WED_RESET_IDX_RX_V2); 1090 else 1091 wed_set(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_IDX_RX); 1092 wed_w32(dev, MTK_WED_RESET_IDX, 0); 1093 } 1094 1095 /* reset rx bm */ 1096 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN); 1097 mtk_wed_poll_busy(dev, MTK_WED_CTRL, 1098 MTK_WED_CTRL_WED_RX_BM_BUSY); 1099 mtk_wed_reset(dev, MTK_WED_RESET_RX_BM); 1100 1101 /* wo change to enable state */ 1102 val = MTK_WED_WO_STATE_ENABLE; 1103 ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO, 1104 MTK_WED_WO_CMD_CHANGE_STATE, &val, 1105 sizeof(val), true); 1106 if (ret) 1107 return ret; 1108 1109 /* wed_rx_ring_reset */ 1110 for (i = 0; i < ARRAY_SIZE(dev->rx_ring); i++) { 1111 if (!dev->rx_ring[i].desc) 1112 continue; 1113 1114 mtk_wed_ring_reset(&dev->rx_ring[i], MTK_WED_RX_RING_SIZE, 1115 false); 1116 } 1117 mtk_wed_free_rx_buffer(dev); 1118 1119 return 0; 1120 } 1121 1122 static void 1123 mtk_wed_reset_dma(struct mtk_wed_device *dev) 1124 { 1125 bool busy = false; 1126 u32 val; 1127 int i; 1128 1129 for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) { 1130 if (!dev->tx_ring[i].desc) 1131 continue; 1132 1133 mtk_wed_ring_reset(&dev->tx_ring[i], MTK_WED_TX_RING_SIZE, 1134 true); 1135 } 1136 1137 /* 1. reset WED tx DMA */ 1138 wed_clr(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_TX_DMA_EN); 1139 busy = mtk_wed_poll_busy(dev, MTK_WED_GLO_CFG, 1140 MTK_WED_GLO_CFG_TX_DMA_BUSY); 1141 if (busy) { 1142 mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA); 1143 } else { 1144 wed_w32(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_IDX_TX); 1145 wed_w32(dev, MTK_WED_RESET_IDX, 0); 1146 } 1147 1148 /* 2. reset WDMA rx DMA */ 1149 busy = !!mtk_wdma_rx_reset(dev); 1150 wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); 1151 if (!busy) 1152 busy = mtk_wed_poll_busy(dev, MTK_WED_WDMA_GLO_CFG, 1153 MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY); 1154 1155 if (busy) { 1156 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT); 1157 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV); 1158 } else { 1159 wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 1160 MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV); 1161 wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0); 1162 1163 wed_set(dev, MTK_WED_WDMA_GLO_CFG, 1164 MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE); 1165 1166 wed_clr(dev, MTK_WED_WDMA_GLO_CFG, 1167 MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE); 1168 } 1169 1170 /* 3. reset WED WPDMA tx */ 1171 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); 1172 1173 for (i = 0; i < 100; i++) { 1174 val = wed_r32(dev, MTK_WED_TX_BM_INTF); 1175 if (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40) 1176 break; 1177 } 1178 1179 mtk_wed_reset(dev, MTK_WED_RESET_TX_FREE_AGENT); 1180 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_BM_EN); 1181 mtk_wed_reset(dev, MTK_WED_RESET_TX_BM); 1182 1183 /* 4. reset WED WPDMA tx */ 1184 busy = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_GLO_CFG, 1185 MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY); 1186 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, 1187 MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | 1188 MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); 1189 if (!busy) 1190 busy = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_GLO_CFG, 1191 MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY); 1192 1193 if (busy) { 1194 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT); 1195 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV); 1196 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV); 1197 } else { 1198 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 1199 MTK_WED_WPDMA_RESET_IDX_TX | 1200 MTK_WED_WPDMA_RESET_IDX_RX); 1201 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0); 1202 } 1203 1204 dev->init_done = false; 1205 if (dev->hw->version == 1) 1206 return; 1207 1208 if (!busy) { 1209 wed_w32(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_WPDMA_IDX_RX); 1210 wed_w32(dev, MTK_WED_RESET_IDX, 0); 1211 } 1212 1213 mtk_wed_rx_reset(dev); 1214 } 1215 1216 static int 1217 mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, 1218 int size, u32 desc_size, bool tx) 1219 { 1220 ring->desc = dma_alloc_coherent(dev->hw->dev, size * desc_size, 1221 &ring->desc_phys, GFP_KERNEL); 1222 if (!ring->desc) 1223 return -ENOMEM; 1224 1225 ring->desc_size = desc_size; 1226 ring->size = size; 1227 mtk_wed_ring_reset(ring, size, tx); 1228 1229 return 0; 1230 } 1231 1232 static int 1233 mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size, 1234 bool reset) 1235 { 1236 u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version; 1237 struct mtk_wed_ring *wdma; 1238 1239 if (idx >= ARRAY_SIZE(dev->rx_wdma)) 1240 return -EINVAL; 1241 1242 wdma = &dev->rx_wdma[idx]; 1243 if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE, 1244 desc_size, true)) 1245 return -ENOMEM; 1246 1247 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE, 1248 wdma->desc_phys); 1249 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT, 1250 size); 1251 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0); 1252 1253 wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE, 1254 wdma->desc_phys); 1255 wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT, 1256 size); 1257 1258 return 0; 1259 } 1260 1261 static int 1262 mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size, 1263 bool reset) 1264 { 1265 u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version; 1266 struct mtk_wed_ring *wdma; 1267 1268 if (idx >= ARRAY_SIZE(dev->tx_wdma)) 1269 return -EINVAL; 1270 1271 wdma = &dev->tx_wdma[idx]; 1272 if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE, 1273 desc_size, true)) 1274 return -ENOMEM; 1275 1276 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE, 1277 wdma->desc_phys); 1278 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT, 1279 size); 1280 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0); 1281 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_DMA_IDX, 0); 1282 1283 if (reset) 1284 mtk_wed_ring_reset(wdma, MTK_WED_WDMA_RING_SIZE, true); 1285 1286 if (!idx) { 1287 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_BASE, 1288 wdma->desc_phys); 1289 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_COUNT, 1290 size); 1291 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_CPU_IDX, 1292 0); 1293 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_DMA_IDX, 1294 0); 1295 } 1296 1297 return 0; 1298 } 1299 1300 static void 1301 mtk_wed_ppe_check(struct mtk_wed_device *dev, struct sk_buff *skb, 1302 u32 reason, u32 hash) 1303 { 1304 struct mtk_eth *eth = dev->hw->eth; 1305 struct ethhdr *eh; 1306 1307 if (!skb) 1308 return; 1309 1310 if (reason != MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 1311 return; 1312 1313 skb_set_mac_header(skb, 0); 1314 eh = eth_hdr(skb); 1315 skb->protocol = eh->h_proto; 1316 mtk_ppe_check_skb(eth->ppe[dev->hw->index], skb, hash); 1317 } 1318 1319 static void 1320 mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask) 1321 { 1322 u32 wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0)); 1323 1324 /* wed control cr set */ 1325 wed_set(dev, MTK_WED_CTRL, 1326 MTK_WED_CTRL_WDMA_INT_AGENT_EN | 1327 MTK_WED_CTRL_WPDMA_INT_AGENT_EN | 1328 MTK_WED_CTRL_WED_TX_BM_EN | 1329 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); 1330 1331 if (dev->hw->version == 1) { 1332 wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, 1333 MTK_WED_PCIE_INT_TRIGGER_STATUS); 1334 1335 wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 1336 MTK_WED_WPDMA_INT_TRIGGER_RX_DONE | 1337 MTK_WED_WPDMA_INT_TRIGGER_TX_DONE); 1338 1339 wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask); 1340 } else { 1341 wdma_mask |= FIELD_PREP(MTK_WDMA_INT_MASK_TX_DONE, 1342 GENMASK(1, 0)); 1343 /* initail tx interrupt trigger */ 1344 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX, 1345 MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN | 1346 MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR | 1347 MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN | 1348 MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR | 1349 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG, 1350 dev->wlan.tx_tbit[0]) | 1351 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG, 1352 dev->wlan.tx_tbit[1])); 1353 1354 /* initail txfree interrupt trigger */ 1355 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX_FREE, 1356 MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN | 1357 MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR | 1358 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG, 1359 dev->wlan.txfree_tbit)); 1360 1361 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX, 1362 MTK_WED_WPDMA_INT_CTRL_RX0_EN | 1363 MTK_WED_WPDMA_INT_CTRL_RX0_CLR | 1364 MTK_WED_WPDMA_INT_CTRL_RX1_EN | 1365 MTK_WED_WPDMA_INT_CTRL_RX1_CLR | 1366 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG, 1367 dev->wlan.rx_tbit[0]) | 1368 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG, 1369 dev->wlan.rx_tbit[1])); 1370 1371 wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask); 1372 wed_set(dev, MTK_WED_WDMA_INT_CTRL, 1373 FIELD_PREP(MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL, 1374 dev->wdma_idx)); 1375 } 1376 1377 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask); 1378 1379 wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask); 1380 wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask); 1381 wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask); 1382 wed_w32(dev, MTK_WED_INT_MASK, irq_mask); 1383 } 1384 1385 static void 1386 mtk_wed_dma_enable(struct mtk_wed_device *dev) 1387 { 1388 wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV); 1389 1390 wed_set(dev, MTK_WED_GLO_CFG, 1391 MTK_WED_GLO_CFG_TX_DMA_EN | 1392 MTK_WED_GLO_CFG_RX_DMA_EN); 1393 wed_set(dev, MTK_WED_WPDMA_GLO_CFG, 1394 MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | 1395 MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); 1396 wed_set(dev, MTK_WED_WDMA_GLO_CFG, 1397 MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); 1398 1399 wdma_set(dev, MTK_WDMA_GLO_CFG, 1400 MTK_WDMA_GLO_CFG_TX_DMA_EN | 1401 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES | 1402 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES); 1403 1404 if (dev->hw->version == 1) { 1405 wdma_set(dev, MTK_WDMA_GLO_CFG, 1406 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES); 1407 } else { 1408 int i; 1409 1410 wed_set(dev, MTK_WED_WPDMA_CTRL, 1411 MTK_WED_WPDMA_CTRL_SDL1_FIXED); 1412 1413 wed_set(dev, MTK_WED_WDMA_GLO_CFG, 1414 MTK_WED_WDMA_GLO_CFG_TX_DRV_EN | 1415 MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK); 1416 1417 wed_set(dev, MTK_WED_WPDMA_GLO_CFG, 1418 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC | 1419 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC); 1420 1421 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, 1422 MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP | 1423 MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV); 1424 1425 wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, 1426 MTK_WED_WPDMA_RX_D_RX_DRV_EN | 1427 FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) | 1428 FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL, 1429 0x2)); 1430 1431 for (i = 0; i < MTK_WED_RX_QUEUES; i++) 1432 mtk_wed_check_wfdma_rx_fill(dev, i); 1433 } 1434 } 1435 1436 static void 1437 mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask) 1438 { 1439 int i; 1440 1441 if (mtk_wed_get_rx_capa(dev) && mtk_wed_rx_buffer_alloc(dev)) 1442 return; 1443 1444 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++) 1445 if (!dev->rx_wdma[i].desc) 1446 mtk_wed_wdma_rx_ring_setup(dev, i, 16, false); 1447 1448 mtk_wed_hw_init(dev); 1449 mtk_wed_configure_irq(dev, irq_mask); 1450 1451 mtk_wed_set_ext_int(dev, true); 1452 1453 if (dev->hw->version == 1) { 1454 u32 val = dev->wlan.wpdma_phys | MTK_PCIE_MIRROR_MAP_EN | 1455 FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, 1456 dev->hw->index); 1457 1458 val |= BIT(0) | (BIT(1) * !!dev->hw->index); 1459 regmap_write(dev->hw->mirror, dev->hw->index * 4, val); 1460 } else { 1461 /* driver set mid ready and only once */ 1462 wed_w32(dev, MTK_WED_EXT_INT_MASK1, 1463 MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY); 1464 wed_w32(dev, MTK_WED_EXT_INT_MASK2, 1465 MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY); 1466 1467 wed_r32(dev, MTK_WED_EXT_INT_MASK1); 1468 wed_r32(dev, MTK_WED_EXT_INT_MASK2); 1469 1470 if (mtk_wed_rro_cfg(dev)) 1471 return; 1472 1473 } 1474 1475 mtk_wed_set_512_support(dev, dev->wlan.wcid_512); 1476 1477 mtk_wed_dma_enable(dev); 1478 dev->running = true; 1479 } 1480 1481 static int 1482 mtk_wed_attach(struct mtk_wed_device *dev) 1483 __releases(RCU) 1484 { 1485 struct mtk_wed_hw *hw; 1486 struct device *device; 1487 int ret = 0; 1488 1489 RCU_LOCKDEP_WARN(!rcu_read_lock_held(), 1490 "mtk_wed_attach without holding the RCU read lock"); 1491 1492 if ((dev->wlan.bus_type == MTK_WED_BUS_PCIE && 1493 pci_domain_nr(dev->wlan.pci_dev->bus) > 1) || 1494 !try_module_get(THIS_MODULE)) 1495 ret = -ENODEV; 1496 1497 rcu_read_unlock(); 1498 1499 if (ret) 1500 return ret; 1501 1502 mutex_lock(&hw_lock); 1503 1504 hw = mtk_wed_assign(dev); 1505 if (!hw) { 1506 module_put(THIS_MODULE); 1507 ret = -ENODEV; 1508 goto unlock; 1509 } 1510 1511 device = dev->wlan.bus_type == MTK_WED_BUS_PCIE 1512 ? &dev->wlan.pci_dev->dev 1513 : &dev->wlan.platform_dev->dev; 1514 dev_info(device, "attaching wed device %d version %d\n", 1515 hw->index, hw->version); 1516 1517 dev->hw = hw; 1518 dev->dev = hw->dev; 1519 dev->irq = hw->irq; 1520 dev->wdma_idx = hw->index; 1521 dev->version = hw->version; 1522 1523 if (hw->eth->dma_dev == hw->eth->dev && 1524 of_dma_is_coherent(hw->eth->dev->of_node)) 1525 mtk_eth_set_dma_device(hw->eth, hw->dev); 1526 1527 ret = mtk_wed_tx_buffer_alloc(dev); 1528 if (ret) 1529 goto out; 1530 1531 if (mtk_wed_get_rx_capa(dev)) { 1532 ret = mtk_wed_rro_alloc(dev); 1533 if (ret) 1534 goto out; 1535 } 1536 1537 mtk_wed_hw_init_early(dev); 1538 if (hw->version == 1) { 1539 regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, 1540 BIT(hw->index), 0); 1541 } else { 1542 dev->rev_id = wed_r32(dev, MTK_WED_REV_ID); 1543 ret = mtk_wed_wo_init(hw); 1544 } 1545 out: 1546 if (ret) { 1547 dev_err(dev->hw->dev, "failed to attach wed device\n"); 1548 __mtk_wed_detach(dev); 1549 } 1550 unlock: 1551 mutex_unlock(&hw_lock); 1552 1553 return ret; 1554 } 1555 1556 static int 1557 mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs, 1558 bool reset) 1559 { 1560 struct mtk_wed_ring *ring = &dev->tx_ring[idx]; 1561 1562 /* 1563 * Tx ring redirection: 1564 * Instead of configuring the WLAN PDMA TX ring directly, the WLAN 1565 * driver allocated DMA ring gets configured into WED MTK_WED_RING_TX(n) 1566 * registers. 1567 * 1568 * WED driver posts its own DMA ring as WLAN PDMA TX and configures it 1569 * into MTK_WED_WPDMA_RING_TX(n) registers. 1570 * It gets filled with packets picked up from WED TX ring and from 1571 * WDMA RX. 1572 */ 1573 1574 if (WARN_ON(idx >= ARRAY_SIZE(dev->tx_ring))) 1575 return -EINVAL; 1576 1577 if (!reset && mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE, 1578 sizeof(*ring->desc), true)) 1579 return -ENOMEM; 1580 1581 if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE, 1582 reset)) 1583 return -ENOMEM; 1584 1585 ring->reg_base = MTK_WED_RING_TX(idx); 1586 ring->wpdma = regs; 1587 1588 /* WED -> WPDMA */ 1589 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys); 1590 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE); 1591 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_CPU_IDX, 0); 1592 1593 wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE, 1594 ring->desc_phys); 1595 wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT, 1596 MTK_WED_TX_RING_SIZE); 1597 wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0); 1598 1599 return 0; 1600 } 1601 1602 static int 1603 mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs) 1604 { 1605 struct mtk_wed_ring *ring = &dev->txfree_ring; 1606 int i, index = dev->hw->version == 1; 1607 1608 /* 1609 * For txfree event handling, the same DMA ring is shared between WED 1610 * and WLAN. The WLAN driver accesses the ring index registers through 1611 * WED 1612 */ 1613 ring->reg_base = MTK_WED_RING_RX(index); 1614 ring->wpdma = regs; 1615 1616 for (i = 0; i < 12; i += 4) { 1617 u32 val = readl(regs + i); 1618 1619 wed_w32(dev, MTK_WED_RING_RX(index) + i, val); 1620 wed_w32(dev, MTK_WED_WPDMA_RING_RX(index) + i, val); 1621 } 1622 1623 return 0; 1624 } 1625 1626 static int 1627 mtk_wed_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs, 1628 bool reset) 1629 { 1630 struct mtk_wed_ring *ring = &dev->rx_ring[idx]; 1631 1632 if (WARN_ON(idx >= ARRAY_SIZE(dev->rx_ring))) 1633 return -EINVAL; 1634 1635 if (!reset && mtk_wed_ring_alloc(dev, ring, MTK_WED_RX_RING_SIZE, 1636 sizeof(*ring->desc), false)) 1637 return -ENOMEM; 1638 1639 if (mtk_wed_wdma_tx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE, 1640 reset)) 1641 return -ENOMEM; 1642 1643 ring->reg_base = MTK_WED_RING_RX_DATA(idx); 1644 ring->wpdma = regs; 1645 ring->flags |= MTK_WED_RING_CONFIGURED; 1646 1647 /* WPDMA -> WED */ 1648 wpdma_rx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys); 1649 wpdma_rx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_RX_RING_SIZE); 1650 1651 wed_w32(dev, MTK_WED_WPDMA_RING_RX_DATA(idx) + MTK_WED_RING_OFS_BASE, 1652 ring->desc_phys); 1653 wed_w32(dev, MTK_WED_WPDMA_RING_RX_DATA(idx) + MTK_WED_RING_OFS_COUNT, 1654 MTK_WED_RX_RING_SIZE); 1655 1656 return 0; 1657 } 1658 1659 static u32 1660 mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask) 1661 { 1662 u32 val, ext_mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK; 1663 1664 if (dev->hw->version == 1) 1665 ext_mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR; 1666 else 1667 ext_mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH | 1668 MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH | 1669 MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT | 1670 MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR; 1671 1672 val = wed_r32(dev, MTK_WED_EXT_INT_STATUS); 1673 wed_w32(dev, MTK_WED_EXT_INT_STATUS, val); 1674 val &= ext_mask; 1675 if (!dev->hw->num_flows) 1676 val &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD; 1677 if (val && net_ratelimit()) 1678 pr_err("mtk_wed%d: error status=%08x\n", dev->hw->index, val); 1679 1680 val = wed_r32(dev, MTK_WED_INT_STATUS); 1681 val &= mask; 1682 wed_w32(dev, MTK_WED_INT_STATUS, val); /* ACK */ 1683 1684 return val; 1685 } 1686 1687 static void 1688 mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask) 1689 { 1690 if (!dev->running) 1691 return; 1692 1693 mtk_wed_set_ext_int(dev, !!mask); 1694 wed_w32(dev, MTK_WED_INT_MASK, mask); 1695 } 1696 1697 int mtk_wed_flow_add(int index) 1698 { 1699 struct mtk_wed_hw *hw = hw_list[index]; 1700 int ret; 1701 1702 if (!hw || !hw->wed_dev) 1703 return -ENODEV; 1704 1705 if (hw->num_flows) { 1706 hw->num_flows++; 1707 return 0; 1708 } 1709 1710 mutex_lock(&hw_lock); 1711 if (!hw->wed_dev) { 1712 ret = -ENODEV; 1713 goto out; 1714 } 1715 1716 ret = hw->wed_dev->wlan.offload_enable(hw->wed_dev); 1717 if (!ret) 1718 hw->num_flows++; 1719 mtk_wed_set_ext_int(hw->wed_dev, true); 1720 1721 out: 1722 mutex_unlock(&hw_lock); 1723 1724 return ret; 1725 } 1726 1727 void mtk_wed_flow_remove(int index) 1728 { 1729 struct mtk_wed_hw *hw = hw_list[index]; 1730 1731 if (!hw) 1732 return; 1733 1734 if (--hw->num_flows) 1735 return; 1736 1737 mutex_lock(&hw_lock); 1738 if (!hw->wed_dev) 1739 goto out; 1740 1741 hw->wed_dev->wlan.offload_disable(hw->wed_dev); 1742 mtk_wed_set_ext_int(hw->wed_dev, true); 1743 1744 out: 1745 mutex_unlock(&hw_lock); 1746 } 1747 1748 void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, 1749 void __iomem *wdma, phys_addr_t wdma_phy, 1750 int index) 1751 { 1752 static const struct mtk_wed_ops wed_ops = { 1753 .attach = mtk_wed_attach, 1754 .tx_ring_setup = mtk_wed_tx_ring_setup, 1755 .rx_ring_setup = mtk_wed_rx_ring_setup, 1756 .txfree_ring_setup = mtk_wed_txfree_ring_setup, 1757 .msg_update = mtk_wed_mcu_msg_update, 1758 .start = mtk_wed_start, 1759 .stop = mtk_wed_stop, 1760 .reset_dma = mtk_wed_reset_dma, 1761 .reg_read = wed_r32, 1762 .reg_write = wed_w32, 1763 .irq_get = mtk_wed_irq_get, 1764 .irq_set_mask = mtk_wed_irq_set_mask, 1765 .detach = mtk_wed_detach, 1766 .ppe_check = mtk_wed_ppe_check, 1767 }; 1768 struct device_node *eth_np = eth->dev->of_node; 1769 struct platform_device *pdev; 1770 struct mtk_wed_hw *hw; 1771 struct regmap *regs; 1772 int irq; 1773 1774 if (!np) 1775 return; 1776 1777 pdev = of_find_device_by_node(np); 1778 if (!pdev) 1779 goto err_of_node_put; 1780 1781 get_device(&pdev->dev); 1782 irq = platform_get_irq(pdev, 0); 1783 if (irq < 0) 1784 goto err_put_device; 1785 1786 regs = syscon_regmap_lookup_by_phandle(np, NULL); 1787 if (IS_ERR(regs)) 1788 goto err_put_device; 1789 1790 rcu_assign_pointer(mtk_soc_wed_ops, &wed_ops); 1791 1792 mutex_lock(&hw_lock); 1793 1794 if (WARN_ON(hw_list[index])) 1795 goto unlock; 1796 1797 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 1798 if (!hw) 1799 goto unlock; 1800 1801 hw->node = np; 1802 hw->regs = regs; 1803 hw->eth = eth; 1804 hw->dev = &pdev->dev; 1805 hw->wdma_phy = wdma_phy; 1806 hw->wdma = wdma; 1807 hw->index = index; 1808 hw->irq = irq; 1809 hw->version = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; 1810 1811 if (hw->version == 1) { 1812 hw->mirror = syscon_regmap_lookup_by_phandle(eth_np, 1813 "mediatek,pcie-mirror"); 1814 hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np, 1815 "mediatek,hifsys"); 1816 if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) { 1817 kfree(hw); 1818 goto unlock; 1819 } 1820 1821 if (!index) { 1822 regmap_write(hw->mirror, 0, 0); 1823 regmap_write(hw->mirror, 4, 0); 1824 } 1825 } 1826 1827 mtk_wed_hw_add_debugfs(hw); 1828 1829 hw_list[index] = hw; 1830 1831 mutex_unlock(&hw_lock); 1832 1833 return; 1834 1835 unlock: 1836 mutex_unlock(&hw_lock); 1837 err_put_device: 1838 put_device(&pdev->dev); 1839 err_of_node_put: 1840 of_node_put(np); 1841 } 1842 1843 void mtk_wed_exit(void) 1844 { 1845 int i; 1846 1847 rcu_assign_pointer(mtk_soc_wed_ops, NULL); 1848 1849 synchronize_rcu(); 1850 1851 for (i = 0; i < ARRAY_SIZE(hw_list); i++) { 1852 struct mtk_wed_hw *hw; 1853 1854 hw = hw_list[i]; 1855 if (!hw) 1856 continue; 1857 1858 hw_list[i] = NULL; 1859 debugfs_remove(hw->debugfs_dir); 1860 put_device(hw->dev); 1861 of_node_put(hw->node); 1862 kfree(hw); 1863 } 1864 } 1865