1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #ifndef MTK_ETH_H 16 #define MTK_ETH_H 17 18 #define MTK_QDMA_PAGE_SIZE 2048 19 #define MTK_MAX_RX_LENGTH 1536 20 #define MTK_TX_DMA_BUF_LEN 0x3fff 21 #define MTK_DMA_SIZE 256 22 #define MTK_NAPI_WEIGHT 64 23 #define MTK_MAC_COUNT 2 24 #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 25 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 26 #define MTK_DMA_DUMMY_DESC 0xffffffff 27 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 28 NETIF_MSG_PROBE | \ 29 NETIF_MSG_LINK | \ 30 NETIF_MSG_TIMER | \ 31 NETIF_MSG_IFDOWN | \ 32 NETIF_MSG_IFUP | \ 33 NETIF_MSG_RX_ERR | \ 34 NETIF_MSG_TX_ERR) 35 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 36 NETIF_F_RXCSUM | \ 37 NETIF_F_HW_VLAN_CTAG_TX | \ 38 NETIF_F_HW_VLAN_CTAG_RX | \ 39 NETIF_F_SG | NETIF_F_TSO | \ 40 NETIF_F_TSO6 | \ 41 NETIF_F_IPV6_CSUM) 42 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (MTK_DMA_SIZE - 1)) 43 44 /* Frame Engine Global Reset Register */ 45 #define MTK_RST_GL 0x04 46 #define RST_GL_PSE BIT(0) 47 48 /* Frame Engine Interrupt Status Register */ 49 #define MTK_INT_STATUS2 0x08 50 #define MTK_GDM1_AF BIT(28) 51 #define MTK_GDM2_AF BIT(29) 52 53 /* Frame Engine Interrupt Grouping Register */ 54 #define MTK_FE_INT_GRP 0x20 55 56 /* CDMP Exgress Control Register */ 57 #define MTK_CDMP_EG_CTRL 0x404 58 59 /* GDM Exgress Control Register */ 60 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 61 #define MTK_GDMA_ICS_EN BIT(22) 62 #define MTK_GDMA_TCS_EN BIT(21) 63 #define MTK_GDMA_UCS_EN BIT(20) 64 65 /* Unicast Filter MAC Address Register - Low */ 66 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 67 68 /* Unicast Filter MAC Address Register - High */ 69 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 70 71 /* PDMA RX Base Pointer Register */ 72 #define MTK_PRX_BASE_PTR0 0x900 73 74 /* PDMA RX Maximum Count Register */ 75 #define MTK_PRX_MAX_CNT0 0x904 76 77 /* PDMA RX CPU Pointer Register */ 78 #define MTK_PRX_CRX_IDX0 0x908 79 80 /* PDMA Global Configuration Register */ 81 #define MTK_PDMA_GLO_CFG 0xa04 82 #define MTK_MULTI_EN BIT(10) 83 84 /* PDMA Reset Index Register */ 85 #define MTK_PDMA_RST_IDX 0xa08 86 #define MTK_PST_DRX_IDX0 BIT(16) 87 88 /* PDMA Delay Interrupt Register */ 89 #define MTK_PDMA_DELAY_INT 0xa0c 90 91 /* PDMA Interrupt Status Register */ 92 #define MTK_PDMA_INT_STATUS 0xa20 93 94 /* PDMA Interrupt Mask Register */ 95 #define MTK_PDMA_INT_MASK 0xa28 96 97 /* PDMA Interrupt grouping registers */ 98 #define MTK_PDMA_INT_GRP1 0xa50 99 #define MTK_PDMA_INT_GRP2 0xa54 100 101 /* QDMA TX Queue Configuration Registers */ 102 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 103 #define QDMA_RES_THRES 4 104 105 /* QDMA TX Queue Scheduler Registers */ 106 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 107 108 /* QDMA RX Base Pointer Register */ 109 #define MTK_QRX_BASE_PTR0 0x1900 110 111 /* QDMA RX Maximum Count Register */ 112 #define MTK_QRX_MAX_CNT0 0x1904 113 114 /* QDMA RX CPU Pointer Register */ 115 #define MTK_QRX_CRX_IDX0 0x1908 116 117 /* QDMA RX DMA Pointer Register */ 118 #define MTK_QRX_DRX_IDX0 0x190C 119 120 /* QDMA Global Configuration Register */ 121 #define MTK_QDMA_GLO_CFG 0x1A04 122 #define MTK_RX_2B_OFFSET BIT(31) 123 #define MTK_RX_BT_32DWORDS (3 << 11) 124 #define MTK_NDP_CO_PRO BIT(10) 125 #define MTK_TX_WB_DDONE BIT(6) 126 #define MTK_DMA_SIZE_16DWORDS (2 << 4) 127 #define MTK_RX_DMA_BUSY BIT(3) 128 #define MTK_TX_DMA_BUSY BIT(1) 129 #define MTK_RX_DMA_EN BIT(2) 130 #define MTK_TX_DMA_EN BIT(0) 131 #define MTK_DMA_BUSY_TIMEOUT HZ 132 133 /* QDMA Reset Index Register */ 134 #define MTK_QDMA_RST_IDX 0x1A08 135 #define MTK_PST_DRX_IDX0 BIT(16) 136 137 /* QDMA Delay Interrupt Register */ 138 #define MTK_QDMA_DELAY_INT 0x1A0C 139 140 /* QDMA Flow Control Register */ 141 #define MTK_QDMA_FC_THRES 0x1A10 142 #define FC_THRES_DROP_MODE BIT(20) 143 #define FC_THRES_DROP_EN (7 << 16) 144 #define FC_THRES_MIN 0x4444 145 146 /* QDMA Interrupt Status Register */ 147 #define MTK_QMTK_INT_STATUS 0x1A18 148 #define MTK_RX_DONE_INT3 BIT(19) 149 #define MTK_RX_DONE_INT2 BIT(18) 150 #define MTK_RX_DONE_INT1 BIT(17) 151 #define MTK_RX_DONE_INT0 BIT(16) 152 #define MTK_TX_DONE_INT3 BIT(3) 153 #define MTK_TX_DONE_INT2 BIT(2) 154 #define MTK_TX_DONE_INT1 BIT(1) 155 #define MTK_TX_DONE_INT0 BIT(0) 156 #define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1 | \ 157 MTK_RX_DONE_INT2 | MTK_RX_DONE_INT3) 158 #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 159 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 160 161 /* QDMA Interrupt grouping registers */ 162 #define MTK_QDMA_INT_GRP1 0x1a20 163 #define MTK_QDMA_INT_GRP2 0x1a24 164 #define MTK_RLS_DONE_INT BIT(0) 165 166 /* QDMA Interrupt Status Register */ 167 #define MTK_QDMA_INT_MASK 0x1A1C 168 169 /* QDMA Interrupt Mask Register */ 170 #define MTK_QDMA_HRED2 0x1A44 171 172 /* QDMA TX Forward CPU Pointer Register */ 173 #define MTK_QTX_CTX_PTR 0x1B00 174 175 /* QDMA TX Forward DMA Pointer Register */ 176 #define MTK_QTX_DTX_PTR 0x1B04 177 178 /* QDMA TX Release CPU Pointer Register */ 179 #define MTK_QTX_CRX_PTR 0x1B10 180 181 /* QDMA TX Release DMA Pointer Register */ 182 #define MTK_QTX_DRX_PTR 0x1B14 183 184 /* QDMA FQ Head Pointer Register */ 185 #define MTK_QDMA_FQ_HEAD 0x1B20 186 187 /* QDMA FQ Head Pointer Register */ 188 #define MTK_QDMA_FQ_TAIL 0x1B24 189 190 /* QDMA FQ Free Page Counter Register */ 191 #define MTK_QDMA_FQ_CNT 0x1B28 192 193 /* QDMA FQ Free Page Buffer Length Register */ 194 #define MTK_QDMA_FQ_BLEN 0x1B2C 195 196 /* GMA1 Received Good Byte Count Register */ 197 #define MTK_GDM1_TX_GBCNT 0x2400 198 #define MTK_STAT_OFFSET 0x40 199 200 /* QDMA descriptor txd4 */ 201 #define TX_DMA_CHKSUM (0x7 << 29) 202 #define TX_DMA_TSO BIT(28) 203 #define TX_DMA_FPORT_SHIFT 25 204 #define TX_DMA_FPORT_MASK 0x7 205 #define TX_DMA_INS_VLAN BIT(16) 206 207 /* QDMA descriptor txd3 */ 208 #define TX_DMA_OWNER_CPU BIT(31) 209 #define TX_DMA_LS0 BIT(30) 210 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 211 #define TX_DMA_SWC BIT(14) 212 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 213 214 /* QDMA descriptor rxd2 */ 215 #define RX_DMA_DONE BIT(31) 216 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 217 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 218 219 /* QDMA descriptor rxd3 */ 220 #define RX_DMA_VID(_x) ((_x) & 0xfff) 221 222 /* QDMA descriptor rxd4 */ 223 #define RX_DMA_L4_VALID BIT(24) 224 #define RX_DMA_FPORT_SHIFT 19 225 #define RX_DMA_FPORT_MASK 0x7 226 227 /* PHY Indirect Access Control registers */ 228 #define MTK_PHY_IAC 0x10004 229 #define PHY_IAC_ACCESS BIT(31) 230 #define PHY_IAC_READ BIT(19) 231 #define PHY_IAC_WRITE BIT(18) 232 #define PHY_IAC_START BIT(16) 233 #define PHY_IAC_ADDR_SHIFT 20 234 #define PHY_IAC_REG_SHIFT 25 235 #define PHY_IAC_TIMEOUT HZ 236 237 /* Mac control registers */ 238 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 239 #define MAC_MCR_MAX_RX_1536 BIT(24) 240 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 241 #define MAC_MCR_FORCE_MODE BIT(15) 242 #define MAC_MCR_TX_EN BIT(14) 243 #define MAC_MCR_RX_EN BIT(13) 244 #define MAC_MCR_BACKOFF_EN BIT(9) 245 #define MAC_MCR_BACKPR_EN BIT(8) 246 #define MAC_MCR_FORCE_RX_FC BIT(5) 247 #define MAC_MCR_FORCE_TX_FC BIT(4) 248 #define MAC_MCR_SPEED_1000 BIT(3) 249 #define MAC_MCR_SPEED_100 BIT(2) 250 #define MAC_MCR_FORCE_DPX BIT(1) 251 #define MAC_MCR_FORCE_LINK BIT(0) 252 #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ 253 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ 254 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ 255 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ 256 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ 257 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) 258 259 /* GPIO port control registers for GMAC 2*/ 260 #define GPIO_OD33_CTRL8 0x4c0 261 #define GPIO_BIAS_CTRL 0xed0 262 #define GPIO_DRV_SEL10 0xf00 263 264 /* ethernet subsystem config register */ 265 #define ETHSYS_SYSCFG0 0x14 266 #define SYSCFG0_GE_MASK 0x3 267 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 268 269 /*ethernet reset control register*/ 270 #define ETHSYS_RSTCTRL 0x34 271 #define RSTCTRL_FE BIT(6) 272 #define RSTCTRL_PPE BIT(31) 273 274 struct mtk_rx_dma { 275 unsigned int rxd1; 276 unsigned int rxd2; 277 unsigned int rxd3; 278 unsigned int rxd4; 279 } __packed __aligned(4); 280 281 struct mtk_tx_dma { 282 unsigned int txd1; 283 unsigned int txd2; 284 unsigned int txd3; 285 unsigned int txd4; 286 } __packed __aligned(4); 287 288 struct mtk_eth; 289 struct mtk_mac; 290 291 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 292 * @stats_lock: make sure that stats operations are atomic 293 * @reg_offset: the status register offset of the SoC 294 * @syncp: the refcount 295 * 296 * All of the supported SoCs have hardware counters for traffic statistics. 297 * Whenever the status IRQ triggers we can read the latest stats from these 298 * counters and store them in this struct. 299 */ 300 struct mtk_hw_stats { 301 u64 tx_bytes; 302 u64 tx_packets; 303 u64 tx_skip; 304 u64 tx_collisions; 305 u64 rx_bytes; 306 u64 rx_packets; 307 u64 rx_overflow; 308 u64 rx_fcs_errors; 309 u64 rx_short_errors; 310 u64 rx_long_errors; 311 u64 rx_checksum_errors; 312 u64 rx_flow_control_packets; 313 314 spinlock_t stats_lock; 315 u32 reg_offset; 316 struct u64_stats_sync syncp; 317 }; 318 319 /* PDMA descriptor can point at 1-2 segments. This enum allows us to track how 320 * memory was allocated so that it can be freed properly 321 */ 322 enum mtk_tx_flags { 323 MTK_TX_FLAGS_SINGLE0 = 0x01, 324 MTK_TX_FLAGS_PAGE0 = 0x02, 325 }; 326 327 /* This enum allows us to identify how the clock is defined on the array of the 328 * clock in the order 329 */ 330 enum mtk_clks_map { 331 MTK_CLK_ETHIF, 332 MTK_CLK_ESW, 333 MTK_CLK_GP1, 334 MTK_CLK_GP2, 335 MTK_CLK_MAX 336 }; 337 338 enum mtk_dev_state { 339 MTK_HW_INIT, 340 MTK_RESETTING 341 }; 342 343 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 344 * by the TX descriptor s 345 * @skb: The SKB pointer of the packet being sent 346 * @dma_addr0: The base addr of the first segment 347 * @dma_len0: The length of the first segment 348 * @dma_addr1: The base addr of the second segment 349 * @dma_len1: The length of the second segment 350 */ 351 struct mtk_tx_buf { 352 struct sk_buff *skb; 353 u32 flags; 354 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 355 DEFINE_DMA_UNMAP_LEN(dma_len0); 356 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 357 DEFINE_DMA_UNMAP_LEN(dma_len1); 358 }; 359 360 /* struct mtk_tx_ring - This struct holds info describing a TX ring 361 * @dma: The descriptor ring 362 * @buf: The memory pointed at by the ring 363 * @phys: The physical addr of tx_buf 364 * @next_free: Pointer to the next free descriptor 365 * @last_free: Pointer to the last free descriptor 366 * @thresh: The threshold of minimum amount of free descriptors 367 * @free_count: QDMA uses a linked list. Track how many free descriptors 368 * are present 369 */ 370 struct mtk_tx_ring { 371 struct mtk_tx_dma *dma; 372 struct mtk_tx_buf *buf; 373 dma_addr_t phys; 374 struct mtk_tx_dma *next_free; 375 struct mtk_tx_dma *last_free; 376 u16 thresh; 377 atomic_t free_count; 378 }; 379 380 /* struct mtk_rx_ring - This struct holds info describing a RX ring 381 * @dma: The descriptor ring 382 * @data: The memory pointed at by the ring 383 * @phys: The physical addr of rx_buf 384 * @frag_size: How big can each fragment be 385 * @buf_size: The size of each packet buffer 386 * @calc_idx: The current head of ring 387 */ 388 struct mtk_rx_ring { 389 struct mtk_rx_dma *dma; 390 u8 **data; 391 dma_addr_t phys; 392 u16 frag_size; 393 u16 buf_size; 394 u16 calc_idx; 395 }; 396 397 /* currently no SoC has more than 2 macs */ 398 #define MTK_MAX_DEVS 2 399 400 /* struct mtk_eth - This is the main datasructure for holding the state 401 * of the driver 402 * @dev: The device pointer 403 * @base: The mapped register i/o base 404 * @page_lock: Make sure that register operations are atomic 405 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 406 * dummy for NAPI to work 407 * @netdev: The netdev instances 408 * @mac: Each netdev is linked to a physical MAC 409 * @irq: The IRQ that we are using 410 * @msg_enable: Ethtool msg level 411 * @ethsys: The register map pointing at the range used to setup 412 * MII modes 413 * @pctl: The register map pointing at the range used to setup 414 * GMAC port drive/slew values 415 * @dma_refcnt: track how many netdevs are using the DMA engine 416 * @tx_ring: Pointer to the memore holding info about the TX ring 417 * @rx_ring: Pointer to the memore holding info about the RX ring 418 * @tx_napi: The TX NAPI struct 419 * @rx_napi: The RX NAPI struct 420 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 421 * @phy_scratch_ring: physical address of scratch_ring 422 * @scratch_head: The scratch memory that scratch_ring points to. 423 * @clks: clock array for all clocks required 424 * @mii_bus: If there is a bus we need to create an instance for it 425 * @pending_work: The workqueue used to reset the dma ring 426 * @state Initialization and runtime state of the device. 427 */ 428 429 struct mtk_eth { 430 struct device *dev; 431 void __iomem *base; 432 spinlock_t page_lock; 433 spinlock_t irq_lock; 434 struct net_device dummy_dev; 435 struct net_device *netdev[MTK_MAX_DEVS]; 436 struct mtk_mac *mac[MTK_MAX_DEVS]; 437 int irq[3]; 438 u32 msg_enable; 439 unsigned long sysclk; 440 struct regmap *ethsys; 441 struct regmap *pctl; 442 atomic_t dma_refcnt; 443 struct mtk_tx_ring tx_ring; 444 struct mtk_rx_ring rx_ring; 445 struct napi_struct tx_napi; 446 struct napi_struct rx_napi; 447 struct mtk_tx_dma *scratch_ring; 448 dma_addr_t phy_scratch_ring; 449 void *scratch_head; 450 struct clk *clks[MTK_CLK_MAX]; 451 452 struct mii_bus *mii_bus; 453 struct work_struct pending_work; 454 unsigned long state; 455 }; 456 457 /* struct mtk_mac - the structure that holds the info about the MACs of the 458 * SoC 459 * @id: The number of the MAC 460 * @ge_mode: Interface mode kept for setup restoring 461 * @of_node: Our devicetree node 462 * @hw: Backpointer to our main datastruture 463 * @hw_stats: Packet statistics counter 464 * @phy_dev: The attached PHY if available 465 */ 466 struct mtk_mac { 467 int id; 468 int ge_mode; 469 struct device_node *of_node; 470 struct mtk_eth *hw; 471 struct mtk_hw_stats *hw_stats; 472 struct phy_device *phy_dev; 473 }; 474 475 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 476 extern const struct of_device_id of_mtk_match[]; 477 478 /* read the hardware status register */ 479 void mtk_stats_update_mac(struct mtk_mac *mac); 480 481 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 482 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 483 484 #endif /* MTK_ETH_H */ 485