1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 #include <linux/rhashtable.h> 19 #include <linux/dim.h> 20 #include <linux/bitfield.h> 21 #include "mtk_ppe.h" 22 23 #define MTK_QDMA_PAGE_SIZE 2048 24 #define MTK_MAX_RX_LENGTH 1536 25 #define MTK_MAX_RX_LENGTH_2K 2048 26 #define MTK_TX_DMA_BUF_LEN 0x3fff 27 #define MTK_TX_DMA_BUF_LEN_V2 0xffff 28 #define MTK_DMA_SIZE 512 29 #define MTK_MAC_COUNT 2 30 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 31 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 32 #define MTK_DMA_DUMMY_DESC 0xffffffff 33 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 34 NETIF_MSG_PROBE | \ 35 NETIF_MSG_LINK | \ 36 NETIF_MSG_TIMER | \ 37 NETIF_MSG_IFDOWN | \ 38 NETIF_MSG_IFUP | \ 39 NETIF_MSG_RX_ERR | \ 40 NETIF_MSG_TX_ERR) 41 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 42 NETIF_F_RXCSUM | \ 43 NETIF_F_HW_VLAN_CTAG_TX | \ 44 NETIF_F_HW_VLAN_CTAG_RX | \ 45 NETIF_F_SG | NETIF_F_TSO | \ 46 NETIF_F_TSO6 | \ 47 NETIF_F_IPV6_CSUM |\ 48 NETIF_F_HW_TC) 49 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 50 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 51 52 #define MTK_QRX_OFFSET 0x10 53 54 #define MTK_MAX_RX_RING_NUM 4 55 #define MTK_HW_LRO_DMA_SIZE 8 56 57 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 58 #define MTK_MAX_LRO_IP_CNT 2 59 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 60 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 61 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 62 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 63 #define MTK_HW_LRO_MAX_AGG_CNT 64 64 #define MTK_HW_LRO_BW_THRE 3000 65 #define MTK_HW_LRO_REPLACE_DELTA 1000 66 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 67 68 /* Frame Engine Global Reset Register */ 69 #define MTK_RST_GL 0x04 70 #define RST_GL_PSE BIT(0) 71 72 /* Frame Engine Interrupt Status Register */ 73 #define MTK_INT_STATUS2 0x08 74 #define MTK_GDM1_AF BIT(28) 75 #define MTK_GDM2_AF BIT(29) 76 77 /* PDMA HW LRO Alter Flow Timer Register */ 78 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 79 80 /* Frame Engine Interrupt Grouping Register */ 81 #define MTK_FE_INT_GRP 0x20 82 83 /* CDMP Ingress Control Register */ 84 #define MTK_CDMQ_IG_CTRL 0x1400 85 #define MTK_CDMQ_STAG_EN BIT(0) 86 87 /* CDMP Ingress Control Register */ 88 #define MTK_CDMP_IG_CTRL 0x400 89 #define MTK_CDMP_STAG_EN BIT(0) 90 91 /* CDMP Exgress Control Register */ 92 #define MTK_CDMP_EG_CTRL 0x404 93 94 /* GDM Exgress Control Register */ 95 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 96 #define MTK_GDMA_SPECIAL_TAG BIT(24) 97 #define MTK_GDMA_ICS_EN BIT(22) 98 #define MTK_GDMA_TCS_EN BIT(21) 99 #define MTK_GDMA_UCS_EN BIT(20) 100 #define MTK_GDMA_TO_PDMA 0x0 101 #define MTK_GDMA_TO_PPE 0x4444 102 #define MTK_GDMA_DROP_ALL 0x7777 103 104 /* Unicast Filter MAC Address Register - Low */ 105 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 106 107 /* Unicast Filter MAC Address Register - High */ 108 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 109 110 /* FE global misc reg*/ 111 #define MTK_FE_GLO_MISC 0x124 112 113 /* PSE Free Queue Flow Control */ 114 #define PSE_FQFC_CFG1 0x100 115 #define PSE_FQFC_CFG2 0x104 116 #define PSE_DROP_CFG 0x108 117 118 /* PSE Input Queue Reservation Register*/ 119 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 120 121 /* PSE Output Queue Threshold Register*/ 122 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 123 124 /* GDM and CDM Threshold */ 125 #define MTK_GDM2_THRES 0x1530 126 #define MTK_CDMW0_THRES 0x164c 127 #define MTK_CDMW1_THRES 0x1650 128 #define MTK_CDME0_THRES 0x1654 129 #define MTK_CDME1_THRES 0x1658 130 #define MTK_CDMM_THRES 0x165c 131 132 /* PDMA HW LRO Control Registers */ 133 #define MTK_PDMA_LRO_CTRL_DW0 0x980 134 #define MTK_LRO_EN BIT(0) 135 #define MTK_L3_CKS_UPD_EN BIT(7) 136 #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 137 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 138 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 139 #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 140 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 141 #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 142 143 #define MTK_PDMA_LRO_CTRL_DW1 0x984 144 #define MTK_PDMA_LRO_CTRL_DW2 0x988 145 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 146 #define MTK_ADMA_MODE BIT(15) 147 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 148 149 #define MTK_RX_DMA_LRO_EN BIT(8) 150 #define MTK_MULTI_EN BIT(10) 151 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 152 153 /* PDMA Global Configuration Register */ 154 #define MTK_PDMA_LRO_SDL 0x3000 155 #define MTK_RX_CFG_SDL_OFFSET 16 156 157 /* PDMA Reset Index Register */ 158 #define MTK_PST_DRX_IDX0 BIT(16) 159 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 160 161 /* PDMA Delay Interrupt Register */ 162 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 163 #define MTK_PDMA_DELAY_RX_EN BIT(15) 164 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 165 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 166 167 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 168 #define MTK_PDMA_DELAY_TX_EN BIT(31) 169 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 170 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 171 172 #define MTK_PDMA_DELAY_PINT_MASK 0x7f 173 #define MTK_PDMA_DELAY_PTIME_MASK 0xff 174 175 /* PDMA HW LRO Alter Flow Delta Register */ 176 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 177 178 /* PDMA HW LRO IP Setting Registers */ 179 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 180 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 181 #define MTK_RING_MYIP_VLD BIT(9) 182 183 /* PDMA HW LRO Ring Control Registers */ 184 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 185 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 186 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 187 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 188 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 189 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 190 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 191 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 192 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 193 #define MTK_RING_VLD BIT(8) 194 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 195 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 196 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 197 198 /* QDMA TX Queue Configuration Registers */ 199 #define QDMA_RES_THRES 4 200 201 /* QDMA Global Configuration Register */ 202 #define MTK_RX_2B_OFFSET BIT(31) 203 #define MTK_RX_BT_32DWORDS (3 << 11) 204 #define MTK_NDP_CO_PRO BIT(10) 205 #define MTK_TX_WB_DDONE BIT(6) 206 #define MTK_TX_BT_32DWORDS (3 << 4) 207 #define MTK_RX_DMA_BUSY BIT(3) 208 #define MTK_TX_DMA_BUSY BIT(1) 209 #define MTK_RX_DMA_EN BIT(2) 210 #define MTK_TX_DMA_EN BIT(0) 211 #define MTK_DMA_BUSY_TIMEOUT_US 1000000 212 213 /* QDMA V2 Global Configuration Register */ 214 #define MTK_CHK_DDONE_EN BIT(28) 215 #define MTK_DMAD_WR_WDONE BIT(26) 216 #define MTK_WCOMP_EN BIT(24) 217 #define MTK_RESV_BUF (0x40 << 16) 218 #define MTK_MUTLI_CNT (0x4 << 12) 219 220 /* QDMA Flow Control Register */ 221 #define FC_THRES_DROP_MODE BIT(20) 222 #define FC_THRES_DROP_EN (7 << 16) 223 #define FC_THRES_MIN 0x4444 224 225 /* QDMA Interrupt Status Register */ 226 #define MTK_RX_DONE_DLY BIT(30) 227 #define MTK_TX_DONE_DLY BIT(28) 228 #define MTK_RX_DONE_INT3 BIT(19) 229 #define MTK_RX_DONE_INT2 BIT(18) 230 #define MTK_RX_DONE_INT1 BIT(17) 231 #define MTK_RX_DONE_INT0 BIT(16) 232 #define MTK_TX_DONE_INT3 BIT(3) 233 #define MTK_TX_DONE_INT2 BIT(2) 234 #define MTK_TX_DONE_INT1 BIT(1) 235 #define MTK_TX_DONE_INT0 BIT(0) 236 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 237 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 238 239 #define MTK_RX_DONE_INT_V2 BIT(14) 240 241 /* QDMA Interrupt grouping registers */ 242 #define MTK_RLS_DONE_INT BIT(0) 243 244 #define MTK_STAT_OFFSET 0x40 245 246 /* QDMA TX NUM */ 247 #define MTK_QDMA_TX_NUM 16 248 #define MTK_QDMA_TX_MASK (MTK_QDMA_TX_NUM - 1) 249 #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 250 #define MTK_QDMA_GMAC2_QID 8 251 252 #define MTK_TX_DMA_BUF_SHIFT 8 253 254 /* QDMA V2 descriptor txd6 */ 255 #define TX_DMA_INS_VLAN_V2 BIT(16) 256 /* QDMA V2 descriptor txd5 */ 257 #define TX_DMA_CHKSUM_V2 (0x7 << 28) 258 #define TX_DMA_TSO_V2 BIT(31) 259 260 /* QDMA V2 descriptor txd4 */ 261 #define TX_DMA_FPORT_SHIFT_V2 8 262 #define TX_DMA_FPORT_MASK_V2 0xf 263 #define TX_DMA_SWC_V2 BIT(30) 264 265 #define MTK_WDMA0_BASE 0x2800 266 #define MTK_WDMA1_BASE 0x2c00 267 268 /* QDMA descriptor txd4 */ 269 #define TX_DMA_CHKSUM (0x7 << 29) 270 #define TX_DMA_TSO BIT(28) 271 #define TX_DMA_FPORT_SHIFT 25 272 #define TX_DMA_FPORT_MASK 0x7 273 #define TX_DMA_INS_VLAN BIT(16) 274 275 /* QDMA descriptor txd3 */ 276 #define TX_DMA_OWNER_CPU BIT(31) 277 #define TX_DMA_LS0 BIT(30) 278 #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 279 #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) 280 #define TX_DMA_SWC BIT(14) 281 282 /* PDMA on MT7628 */ 283 #define TX_DMA_DONE BIT(31) 284 #define TX_DMA_LS1 BIT(14) 285 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 286 287 /* QDMA descriptor rxd2 */ 288 #define RX_DMA_DONE BIT(31) 289 #define RX_DMA_LSO BIT(30) 290 #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 291 #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) 292 #define RX_DMA_VTAG BIT(15) 293 294 /* QDMA descriptor rxd3 */ 295 #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 296 #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 297 #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 298 299 /* QDMA descriptor rxd4 */ 300 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 301 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 302 #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 303 #define MTK_RXD4_ALG GENMASK(31, 22) 304 305 /* QDMA descriptor rxd4 */ 306 #define RX_DMA_L4_VALID BIT(24) 307 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 308 #define RX_DMA_SPECIAL_TAG BIT(22) 309 310 #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0xf) 311 #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0x7) 312 313 /* PDMA V2 descriptor rxd3 */ 314 #define RX_DMA_VTAG_V2 BIT(0) 315 #define RX_DMA_L4_VALID_V2 BIT(2) 316 317 /* PHY Indirect Access Control registers */ 318 #define MTK_PHY_IAC 0x10004 319 #define PHY_IAC_ACCESS BIT(31) 320 #define PHY_IAC_REG_MASK GENMASK(29, 25) 321 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 322 #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 323 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 324 #define PHY_IAC_CMD_MASK GENMASK(19, 18) 325 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 326 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 327 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 328 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 329 #define PHY_IAC_START_MASK GENMASK(17, 16) 330 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 331 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 332 #define PHY_IAC_DATA_MASK GENMASK(15, 0) 333 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 334 #define PHY_IAC_TIMEOUT HZ 335 336 #define MTK_MAC_MISC 0x1000c 337 #define MTK_MUX_TO_ESW BIT(0) 338 339 /* Mac control registers */ 340 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 341 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 342 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 343 #define MAC_MCR_MAX_RX_1518 0x0 344 #define MAC_MCR_MAX_RX_1536 0x1 345 #define MAC_MCR_MAX_RX_1552 0x2 346 #define MAC_MCR_MAX_RX_2048 0x3 347 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 348 #define MAC_MCR_FORCE_MODE BIT(15) 349 #define MAC_MCR_TX_EN BIT(14) 350 #define MAC_MCR_RX_EN BIT(13) 351 #define MAC_MCR_BACKOFF_EN BIT(9) 352 #define MAC_MCR_BACKPR_EN BIT(8) 353 #define MAC_MCR_FORCE_RX_FC BIT(5) 354 #define MAC_MCR_FORCE_TX_FC BIT(4) 355 #define MAC_MCR_SPEED_1000 BIT(3) 356 #define MAC_MCR_SPEED_100 BIT(2) 357 #define MAC_MCR_FORCE_DPX BIT(1) 358 #define MAC_MCR_FORCE_LINK BIT(0) 359 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 360 361 /* Mac status registers */ 362 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 363 #define MAC_MSR_EEE1G BIT(7) 364 #define MAC_MSR_EEE100M BIT(6) 365 #define MAC_MSR_RX_FC BIT(5) 366 #define MAC_MSR_TX_FC BIT(4) 367 #define MAC_MSR_SPEED_1000 BIT(3) 368 #define MAC_MSR_SPEED_100 BIT(2) 369 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 370 #define MAC_MSR_DPX BIT(1) 371 #define MAC_MSR_LINK BIT(0) 372 373 /* TRGMII RXC control register */ 374 #define TRGMII_RCK_CTRL 0x10300 375 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 376 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 377 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 378 #define RXC_RST BIT(31) 379 #define RXC_DQSISEL BIT(30) 380 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 381 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 382 383 #define NUM_TRGMII_CTRL 5 384 385 /* TRGMII RXC control register */ 386 #define TRGMII_TCK_CTRL 0x10340 387 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 388 #define TXC_INV BIT(30) 389 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 390 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 391 392 /* TRGMII TX Drive Strength */ 393 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 394 #define TD_DM_DRVP(x) ((x) & 0xf) 395 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 396 397 /* TRGMII Interface mode register */ 398 #define INTF_MODE 0x10390 399 #define TRGMII_INTF_DIS BIT(0) 400 #define TRGMII_MODE BIT(1) 401 #define TRGMII_CENTRAL_ALIGNED BIT(2) 402 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 403 #define INTF_MODE_RGMII_10_100 0 404 405 /* GPIO port control registers for GMAC 2*/ 406 #define GPIO_OD33_CTRL8 0x4c0 407 #define GPIO_BIAS_CTRL 0xed0 408 #define GPIO_DRV_SEL10 0xf00 409 410 /* ethernet subsystem chip id register */ 411 #define ETHSYS_CHIPID0_3 0x0 412 #define ETHSYS_CHIPID4_7 0x4 413 #define MT7623_ETH 7623 414 #define MT7622_ETH 7622 415 #define MT7621_ETH 7621 416 417 /* ethernet system control register */ 418 #define ETHSYS_SYSCFG 0x10 419 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 420 421 /* ethernet subsystem config register */ 422 #define ETHSYS_SYSCFG0 0x14 423 #define SYSCFG0_GE_MASK 0x3 424 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 425 #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 426 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 427 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 428 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 429 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 430 431 432 /* ethernet subsystem clock register */ 433 #define ETHSYS_CLKCFG0 0x2c 434 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 435 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 436 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 437 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 438 439 /* ethernet reset control register */ 440 #define ETHSYS_RSTCTRL 0x34 441 #define RSTCTRL_FE BIT(6) 442 #define RSTCTRL_PPE BIT(31) 443 #define RSTCTRL_PPE1 BIT(30) 444 #define RSTCTRL_ETH BIT(23) 445 446 /* ethernet reset check idle register */ 447 #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 448 449 /* ethernet reset control register */ 450 #define ETHSYS_RSTCTRL 0x34 451 #define RSTCTRL_FE BIT(6) 452 #define RSTCTRL_PPE BIT(31) 453 454 /* ethernet dma channel agent map */ 455 #define ETHSYS_DMA_AG_MAP 0x408 456 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 457 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 458 #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 459 460 /* SGMII subsystem config registers */ 461 /* Register to auto-negotiation restart */ 462 #define SGMSYS_PCS_CONTROL_1 0x0 463 #define SGMII_AN_RESTART BIT(9) 464 #define SGMII_ISOLATE BIT(10) 465 #define SGMII_AN_ENABLE BIT(12) 466 #define SGMII_LINK_STATYS BIT(18) 467 #define SGMII_AN_ABILITY BIT(19) 468 #define SGMII_AN_COMPLETE BIT(21) 469 #define SGMII_PCS_FAULT BIT(23) 470 #define SGMII_AN_EXPANSION_CLR BIT(30) 471 472 /* Register to programmable link timer, the unit in 2 * 8ns */ 473 #define SGMSYS_PCS_LINK_TIMER 0x18 474 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 475 476 /* Register to control remote fault */ 477 #define SGMSYS_SGMII_MODE 0x20 478 #define SGMII_IF_MODE_BIT0 BIT(0) 479 #define SGMII_SPEED_DUPLEX_AN BIT(1) 480 #define SGMII_SPEED_MASK GENMASK(3, 2) 481 #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) 482 #define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) 483 #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) 484 #define SGMII_DUPLEX_FULL BIT(4) 485 #define SGMII_IF_MODE_BIT5 BIT(5) 486 #define SGMII_REMOTE_FAULT_DIS BIT(8) 487 #define SGMII_CODE_SYNC_SET_VAL BIT(9) 488 #define SGMII_CODE_SYNC_SET_EN BIT(10) 489 #define SGMII_SEND_AN_ERROR_EN BIT(11) 490 #define SGMII_IF_MODE_MASK GENMASK(5, 1) 491 492 /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 493 #define SGMSYS_ANA_RG_CS3 0x2028 494 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 495 #define RG_PHY_SPEED_1_25G 0x0 496 #define RG_PHY_SPEED_3_125G BIT(2) 497 498 /* Register to power up QPHY */ 499 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 500 #define SGMII_PHYA_PWD BIT(4) 501 502 /* Infrasys subsystem config registers */ 503 #define INFRA_MISC2 0x70c 504 #define CO_QPHY_SEL BIT(0) 505 #define GEPHY_MAC_SEL BIT(1) 506 507 /* MT7628/88 specific stuff */ 508 #define MT7628_PDMA_OFFSET 0x0800 509 #define MT7628_SDM_OFFSET 0x0c00 510 511 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 512 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 513 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 514 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 515 #define MT7628_PST_DTX_IDX0 BIT(0) 516 517 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 518 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 519 520 /* Counter / stat register */ 521 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 522 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 523 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 524 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 525 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 526 527 struct mtk_rx_dma { 528 unsigned int rxd1; 529 unsigned int rxd2; 530 unsigned int rxd3; 531 unsigned int rxd4; 532 } __packed __aligned(4); 533 534 struct mtk_rx_dma_v2 { 535 unsigned int rxd1; 536 unsigned int rxd2; 537 unsigned int rxd3; 538 unsigned int rxd4; 539 unsigned int rxd5; 540 unsigned int rxd6; 541 unsigned int rxd7; 542 unsigned int rxd8; 543 } __packed __aligned(4); 544 545 struct mtk_tx_dma { 546 unsigned int txd1; 547 unsigned int txd2; 548 unsigned int txd3; 549 unsigned int txd4; 550 } __packed __aligned(4); 551 552 struct mtk_tx_dma_v2 { 553 unsigned int txd1; 554 unsigned int txd2; 555 unsigned int txd3; 556 unsigned int txd4; 557 unsigned int txd5; 558 unsigned int txd6; 559 unsigned int txd7; 560 unsigned int txd8; 561 } __packed __aligned(4); 562 563 struct mtk_eth; 564 struct mtk_mac; 565 566 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 567 * @stats_lock: make sure that stats operations are atomic 568 * @reg_offset: the status register offset of the SoC 569 * @syncp: the refcount 570 * 571 * All of the supported SoCs have hardware counters for traffic statistics. 572 * Whenever the status IRQ triggers we can read the latest stats from these 573 * counters and store them in this struct. 574 */ 575 struct mtk_hw_stats { 576 u64 tx_bytes; 577 u64 tx_packets; 578 u64 tx_skip; 579 u64 tx_collisions; 580 u64 rx_bytes; 581 u64 rx_packets; 582 u64 rx_overflow; 583 u64 rx_fcs_errors; 584 u64 rx_short_errors; 585 u64 rx_long_errors; 586 u64 rx_checksum_errors; 587 u64 rx_flow_control_packets; 588 589 spinlock_t stats_lock; 590 u32 reg_offset; 591 struct u64_stats_sync syncp; 592 }; 593 594 enum mtk_tx_flags { 595 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 596 * track how memory was allocated so that it can be freed properly. 597 */ 598 MTK_TX_FLAGS_SINGLE0 = 0x01, 599 MTK_TX_FLAGS_PAGE0 = 0x02, 600 601 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 602 * SKB out instead of looking up through hardware TX descriptor. 603 */ 604 MTK_TX_FLAGS_FPORT0 = 0x04, 605 MTK_TX_FLAGS_FPORT1 = 0x08, 606 }; 607 608 /* This enum allows us to identify how the clock is defined on the array of the 609 * clock in the order 610 */ 611 enum mtk_clks_map { 612 MTK_CLK_ETHIF, 613 MTK_CLK_SGMIITOP, 614 MTK_CLK_ESW, 615 MTK_CLK_GP0, 616 MTK_CLK_GP1, 617 MTK_CLK_GP2, 618 MTK_CLK_FE, 619 MTK_CLK_TRGPLL, 620 MTK_CLK_SGMII_TX_250M, 621 MTK_CLK_SGMII_RX_250M, 622 MTK_CLK_SGMII_CDR_REF, 623 MTK_CLK_SGMII_CDR_FB, 624 MTK_CLK_SGMII2_TX_250M, 625 MTK_CLK_SGMII2_RX_250M, 626 MTK_CLK_SGMII2_CDR_REF, 627 MTK_CLK_SGMII2_CDR_FB, 628 MTK_CLK_SGMII_CK, 629 MTK_CLK_ETH2PLL, 630 MTK_CLK_WOCPU0, 631 MTK_CLK_WOCPU1, 632 MTK_CLK_NETSYS0, 633 MTK_CLK_NETSYS1, 634 MTK_CLK_MAX 635 }; 636 637 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 638 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 639 BIT(MTK_CLK_TRGPLL)) 640 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 641 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 642 BIT(MTK_CLK_GP2) | \ 643 BIT(MTK_CLK_SGMII_TX_250M) | \ 644 BIT(MTK_CLK_SGMII_RX_250M) | \ 645 BIT(MTK_CLK_SGMII_CDR_REF) | \ 646 BIT(MTK_CLK_SGMII_CDR_FB) | \ 647 BIT(MTK_CLK_SGMII_CK) | \ 648 BIT(MTK_CLK_ETH2PLL)) 649 #define MT7621_CLKS_BITMAP (0) 650 #define MT7628_CLKS_BITMAP (0) 651 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 652 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 653 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 654 BIT(MTK_CLK_SGMII_TX_250M) | \ 655 BIT(MTK_CLK_SGMII_RX_250M) | \ 656 BIT(MTK_CLK_SGMII_CDR_REF) | \ 657 BIT(MTK_CLK_SGMII_CDR_FB) | \ 658 BIT(MTK_CLK_SGMII2_TX_250M) | \ 659 BIT(MTK_CLK_SGMII2_RX_250M) | \ 660 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 661 BIT(MTK_CLK_SGMII2_CDR_FB) | \ 662 BIT(MTK_CLK_SGMII_CK) | \ 663 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 664 #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ 665 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ 666 BIT(MTK_CLK_SGMII_TX_250M) | \ 667 BIT(MTK_CLK_SGMII_RX_250M) | \ 668 BIT(MTK_CLK_SGMII_CDR_REF) | \ 669 BIT(MTK_CLK_SGMII_CDR_FB) | \ 670 BIT(MTK_CLK_SGMII2_TX_250M) | \ 671 BIT(MTK_CLK_SGMII2_RX_250M) | \ 672 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 673 BIT(MTK_CLK_SGMII2_CDR_FB)) 674 675 enum mtk_dev_state { 676 MTK_HW_INIT, 677 MTK_RESETTING 678 }; 679 680 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 681 * by the TX descriptor s 682 * @skb: The SKB pointer of the packet being sent 683 * @dma_addr0: The base addr of the first segment 684 * @dma_len0: The length of the first segment 685 * @dma_addr1: The base addr of the second segment 686 * @dma_len1: The length of the second segment 687 */ 688 struct mtk_tx_buf { 689 struct sk_buff *skb; 690 u32 flags; 691 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 692 DEFINE_DMA_UNMAP_LEN(dma_len0); 693 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 694 DEFINE_DMA_UNMAP_LEN(dma_len1); 695 }; 696 697 /* struct mtk_tx_ring - This struct holds info describing a TX ring 698 * @dma: The descriptor ring 699 * @buf: The memory pointed at by the ring 700 * @phys: The physical addr of tx_buf 701 * @next_free: Pointer to the next free descriptor 702 * @last_free: Pointer to the last free descriptor 703 * @last_free_ptr: Hardware pointer value of the last free descriptor 704 * @thresh: The threshold of minimum amount of free descriptors 705 * @free_count: QDMA uses a linked list. Track how many free descriptors 706 * are present 707 */ 708 struct mtk_tx_ring { 709 void *dma; 710 struct mtk_tx_buf *buf; 711 dma_addr_t phys; 712 struct mtk_tx_dma *next_free; 713 struct mtk_tx_dma *last_free; 714 u32 last_free_ptr; 715 u16 thresh; 716 atomic_t free_count; 717 int dma_size; 718 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 719 dma_addr_t phys_pdma; 720 int cpu_idx; 721 }; 722 723 /* PDMA rx ring mode */ 724 enum mtk_rx_flags { 725 MTK_RX_FLAGS_NORMAL = 0, 726 MTK_RX_FLAGS_HWLRO, 727 MTK_RX_FLAGS_QDMA, 728 }; 729 730 /* struct mtk_rx_ring - This struct holds info describing a RX ring 731 * @dma: The descriptor ring 732 * @data: The memory pointed at by the ring 733 * @phys: The physical addr of rx_buf 734 * @frag_size: How big can each fragment be 735 * @buf_size: The size of each packet buffer 736 * @calc_idx: The current head of ring 737 */ 738 struct mtk_rx_ring { 739 void *dma; 740 u8 **data; 741 dma_addr_t phys; 742 u16 frag_size; 743 u16 buf_size; 744 u16 dma_size; 745 bool calc_idx_update; 746 u16 calc_idx; 747 u32 crx_idx_reg; 748 }; 749 750 enum mkt_eth_capabilities { 751 MTK_RGMII_BIT = 0, 752 MTK_TRGMII_BIT, 753 MTK_SGMII_BIT, 754 MTK_ESW_BIT, 755 MTK_GEPHY_BIT, 756 MTK_MUX_BIT, 757 MTK_INFRA_BIT, 758 MTK_SHARED_SGMII_BIT, 759 MTK_HWLRO_BIT, 760 MTK_SHARED_INT_BIT, 761 MTK_TRGMII_MT7621_CLK_BIT, 762 MTK_QDMA_BIT, 763 MTK_NETSYS_V2_BIT, 764 MTK_SOC_MT7628_BIT, 765 MTK_RSTCTRL_PPE1_BIT, 766 767 /* MUX BITS*/ 768 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 769 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 770 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 771 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 772 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 773 774 /* PATH BITS */ 775 MTK_ETH_PATH_GMAC1_RGMII_BIT, 776 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 777 MTK_ETH_PATH_GMAC1_SGMII_BIT, 778 MTK_ETH_PATH_GMAC2_RGMII_BIT, 779 MTK_ETH_PATH_GMAC2_SGMII_BIT, 780 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 781 MTK_ETH_PATH_GDM1_ESW_BIT, 782 }; 783 784 /* Supported hardware group on SoCs */ 785 #define MTK_RGMII BIT(MTK_RGMII_BIT) 786 #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 787 #define MTK_SGMII BIT(MTK_SGMII_BIT) 788 #define MTK_ESW BIT(MTK_ESW_BIT) 789 #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 790 #define MTK_MUX BIT(MTK_MUX_BIT) 791 #define MTK_INFRA BIT(MTK_INFRA_BIT) 792 #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 793 #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 794 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 795 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 796 #define MTK_QDMA BIT(MTK_QDMA_BIT) 797 #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) 798 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 799 #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) 800 801 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 802 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 803 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 804 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 805 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 806 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 807 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 808 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 809 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 810 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 811 812 /* Supported path present on SoCs */ 813 #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 814 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 815 #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 816 #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 817 #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 818 #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 819 #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 820 821 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 822 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 823 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 824 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 825 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 826 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 827 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 828 829 /* MUXes present on SoCs */ 830 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 831 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 832 833 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 834 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 835 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 836 837 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 838 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 839 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 840 841 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 842 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 843 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 844 MTK_SHARED_SGMII) 845 846 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 847 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 848 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 849 850 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 851 852 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 853 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 854 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 855 856 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 857 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 858 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 859 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 860 861 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 862 MTK_QDMA) 863 864 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 865 866 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 867 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 868 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 869 MTK_MUX_U3_GMAC2_TO_QPHY | \ 870 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 871 872 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 873 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 874 MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) 875 876 struct mtk_tx_dma_desc_info { 877 dma_addr_t addr; 878 u32 size; 879 u16 vlan_tci; 880 u16 qid; 881 u8 gso:1; 882 u8 csum:1; 883 u8 vlan:1; 884 u8 first:1; 885 u8 last:1; 886 }; 887 888 struct mtk_reg_map { 889 u32 tx_irq_mask; 890 u32 tx_irq_status; 891 struct { 892 u32 rx_ptr; /* rx base pointer */ 893 u32 rx_cnt_cfg; /* rx max count configuration */ 894 u32 pcrx_ptr; /* rx cpu pointer */ 895 u32 glo_cfg; /* global configuration */ 896 u32 rst_idx; /* reset index */ 897 u32 delay_irq; /* delay interrupt */ 898 u32 irq_status; /* interrupt status */ 899 u32 irq_mask; /* interrupt mask */ 900 u32 int_grp; 901 } pdma; 902 struct { 903 u32 qtx_cfg; /* tx queue configuration */ 904 u32 rx_ptr; /* rx base pointer */ 905 u32 rx_cnt_cfg; /* rx max count configuration */ 906 u32 qcrx_ptr; /* rx cpu pointer */ 907 u32 glo_cfg; /* global configuration */ 908 u32 rst_idx; /* reset index */ 909 u32 delay_irq; /* delay interrupt */ 910 u32 fc_th; /* flow control */ 911 u32 int_grp; 912 u32 hred; /* interrupt mask */ 913 u32 ctx_ptr; /* tx acquire cpu pointer */ 914 u32 dtx_ptr; /* tx acquire dma pointer */ 915 u32 crx_ptr; /* tx release cpu pointer */ 916 u32 drx_ptr; /* tx release dma pointer */ 917 u32 fq_head; /* fq head pointer */ 918 u32 fq_tail; /* fq tail pointer */ 919 u32 fq_count; /* fq free page count */ 920 u32 fq_blen; /* fq free page buffer length */ 921 } qdma; 922 u32 gdm1_cnt; 923 }; 924 925 /* struct mtk_eth_data - This is the structure holding all differences 926 * among various plaforms 927 * @reg_map Soc register map. 928 * @ana_rgc3: The offset for register ANA_RGC3 related to 929 * sgmiisys syscon 930 * @caps Flags shown the extra capability for the SoC 931 * @hw_features Flags shown HW features 932 * @required_clks Flags shown the bitmap for required clocks on 933 * the target SoC 934 * @required_pctl A bool value to show whether the SoC requires 935 * the extra setup for those pins used by GMAC. 936 * @txd_size Tx DMA descriptor size. 937 * @rxd_size Rx DMA descriptor size. 938 * @rx_irq_done_mask Rx irq done register mask. 939 * @rx_dma_l4_valid Rx DMA valid register mask. 940 * @dma_max_len Max DMA tx/rx buffer length. 941 * @dma_len_offset Tx/Rx DMA length field offset. 942 */ 943 struct mtk_soc_data { 944 const struct mtk_reg_map *reg_map; 945 u32 ana_rgc3; 946 u32 caps; 947 u32 required_clks; 948 bool required_pctl; 949 u8 offload_version; 950 netdev_features_t hw_features; 951 struct { 952 u32 txd_size; 953 u32 rxd_size; 954 u32 rx_irq_done_mask; 955 u32 rx_dma_l4_valid; 956 u32 dma_max_len; 957 u32 dma_len_offset; 958 } txrx; 959 }; 960 961 /* currently no SoC has more than 2 macs */ 962 #define MTK_MAX_DEVS 2 963 964 /* struct mtk_pcs - This structure holds each sgmii regmap and associated 965 * data 966 * @regmap: The register map pointing at the range used to setup 967 * SGMII modes 968 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 969 * @pcs: Phylink PCS structure 970 */ 971 struct mtk_pcs { 972 struct regmap *regmap; 973 u32 ana_rgc3; 974 struct phylink_pcs pcs; 975 }; 976 977 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 978 * characteristics 979 * @pcs Array of individual PCS structures 980 */ 981 struct mtk_sgmii { 982 struct mtk_pcs pcs[MTK_MAX_DEVS]; 983 }; 984 985 /* struct mtk_eth - This is the main datasructure for holding the state 986 * of the driver 987 * @dev: The device pointer 988 * @dev: The device pointer used for dma mapping/alloc 989 * @base: The mapped register i/o base 990 * @page_lock: Make sure that register operations are atomic 991 * @tx_irq__lock: Make sure that IRQ register operations are atomic 992 * @rx_irq__lock: Make sure that IRQ register operations are atomic 993 * @dim_lock: Make sure that Net DIM operations are atomic 994 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 995 * dummy for NAPI to work 996 * @netdev: The netdev instances 997 * @mac: Each netdev is linked to a physical MAC 998 * @irq: The IRQ that we are using 999 * @msg_enable: Ethtool msg level 1000 * @ethsys: The register map pointing at the range used to setup 1001 * MII modes 1002 * @infra: The register map pointing at the range used to setup 1003 * SGMII and GePHY path 1004 * @pctl: The register map pointing at the range used to setup 1005 * GMAC port drive/slew values 1006 * @dma_refcnt: track how many netdevs are using the DMA engine 1007 * @tx_ring: Pointer to the memory holding info about the TX ring 1008 * @rx_ring: Pointer to the memory holding info about the RX ring 1009 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 1010 * @tx_napi: The TX NAPI struct 1011 * @rx_napi: The RX NAPI struct 1012 * @rx_events: Net DIM RX event counter 1013 * @rx_packets: Net DIM RX packet counter 1014 * @rx_bytes: Net DIM RX byte counter 1015 * @rx_dim: Net DIM RX context 1016 * @tx_events: Net DIM TX event counter 1017 * @tx_packets: Net DIM TX packet counter 1018 * @tx_bytes: Net DIM TX byte counter 1019 * @tx_dim: Net DIM TX context 1020 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1021 * @phy_scratch_ring: physical address of scratch_ring 1022 * @scratch_head: The scratch memory that scratch_ring points to. 1023 * @clks: clock array for all clocks required 1024 * @mii_bus: If there is a bus we need to create an instance for it 1025 * @pending_work: The workqueue used to reset the dma ring 1026 * @state: Initialization and runtime state of the device 1027 * @soc: Holding specific data among vaious SoCs 1028 */ 1029 1030 struct mtk_eth { 1031 struct device *dev; 1032 struct device *dma_dev; 1033 void __iomem *base; 1034 spinlock_t page_lock; 1035 spinlock_t tx_irq_lock; 1036 spinlock_t rx_irq_lock; 1037 struct net_device dummy_dev; 1038 struct net_device *netdev[MTK_MAX_DEVS]; 1039 struct mtk_mac *mac[MTK_MAX_DEVS]; 1040 int irq[3]; 1041 u32 msg_enable; 1042 unsigned long sysclk; 1043 struct regmap *ethsys; 1044 struct regmap *infra; 1045 struct mtk_sgmii *sgmii; 1046 struct regmap *pctl; 1047 bool hwlro; 1048 refcount_t dma_refcnt; 1049 struct mtk_tx_ring tx_ring; 1050 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 1051 struct mtk_rx_ring rx_ring_qdma; 1052 struct napi_struct tx_napi; 1053 struct napi_struct rx_napi; 1054 void *scratch_ring; 1055 dma_addr_t phy_scratch_ring; 1056 void *scratch_head; 1057 struct clk *clks[MTK_CLK_MAX]; 1058 1059 struct mii_bus *mii_bus; 1060 struct work_struct pending_work; 1061 unsigned long state; 1062 1063 const struct mtk_soc_data *soc; 1064 1065 spinlock_t dim_lock; 1066 1067 u32 rx_events; 1068 u32 rx_packets; 1069 u32 rx_bytes; 1070 struct dim rx_dim; 1071 1072 u32 tx_events; 1073 u32 tx_packets; 1074 u32 tx_bytes; 1075 struct dim tx_dim; 1076 1077 int ip_align; 1078 1079 struct mtk_ppe *ppe; 1080 struct rhashtable flow_table; 1081 }; 1082 1083 /* struct mtk_mac - the structure that holds the info about the MACs of the 1084 * SoC 1085 * @id: The number of the MAC 1086 * @interface: Interface mode kept for detecting change in hw settings 1087 * @of_node: Our devicetree node 1088 * @hw: Backpointer to our main datastruture 1089 * @hw_stats: Packet statistics counter 1090 */ 1091 struct mtk_mac { 1092 int id; 1093 phy_interface_t interface; 1094 int speed; 1095 struct device_node *of_node; 1096 struct phylink *phylink; 1097 struct phylink_config phylink_config; 1098 struct mtk_eth *hw; 1099 struct mtk_hw_stats *hw_stats; 1100 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1101 int hwlro_ip_cnt; 1102 unsigned int syscfg0; 1103 }; 1104 1105 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1106 extern const struct of_device_id of_mtk_match[]; 1107 1108 /* read the hardware status register */ 1109 void mtk_stats_update_mac(struct mtk_mac *mac); 1110 1111 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1112 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1113 1114 struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id); 1115 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 1116 u32 ana_rgc3); 1117 1118 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 1119 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 1120 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 1121 1122 int mtk_eth_offload_init(struct mtk_eth *eth); 1123 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1124 void *type_data); 1125 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1126 1127 1128 #endif /* MTK_ETH_H */ 1129