1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #ifndef MTK_ETH_H 16 #define MTK_ETH_H 17 18 #include <linux/refcount.h> 19 20 #define MTK_QDMA_PAGE_SIZE 2048 21 #define MTK_MAX_RX_LENGTH 1536 22 #define MTK_TX_DMA_BUF_LEN 0x3fff 23 #define MTK_DMA_SIZE 256 24 #define MTK_NAPI_WEIGHT 64 25 #define MTK_MAC_COUNT 2 26 #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 27 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 28 #define MTK_DMA_DUMMY_DESC 0xffffffff 29 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 30 NETIF_MSG_PROBE | \ 31 NETIF_MSG_LINK | \ 32 NETIF_MSG_TIMER | \ 33 NETIF_MSG_IFDOWN | \ 34 NETIF_MSG_IFUP | \ 35 NETIF_MSG_RX_ERR | \ 36 NETIF_MSG_TX_ERR) 37 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 38 NETIF_F_RXCSUM | \ 39 NETIF_F_HW_VLAN_CTAG_TX | \ 40 NETIF_F_HW_VLAN_CTAG_RX | \ 41 NETIF_F_SG | NETIF_F_TSO | \ 42 NETIF_F_TSO6 | \ 43 NETIF_F_IPV6_CSUM) 44 #define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 45 46 #define MTK_MAX_RX_RING_NUM 4 47 #define MTK_HW_LRO_DMA_SIZE 8 48 49 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 50 #define MTK_MAX_LRO_IP_CNT 2 51 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 52 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 53 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 54 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 55 #define MTK_HW_LRO_MAX_AGG_CNT 64 56 #define MTK_HW_LRO_BW_THRE 3000 57 #define MTK_HW_LRO_REPLACE_DELTA 1000 58 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 59 60 /* Frame Engine Global Reset Register */ 61 #define MTK_RST_GL 0x04 62 #define RST_GL_PSE BIT(0) 63 64 /* Frame Engine Interrupt Status Register */ 65 #define MTK_INT_STATUS2 0x08 66 #define MTK_GDM1_AF BIT(28) 67 #define MTK_GDM2_AF BIT(29) 68 69 /* PDMA HW LRO Alter Flow Timer Register */ 70 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 71 72 /* Frame Engine Interrupt Grouping Register */ 73 #define MTK_FE_INT_GRP 0x20 74 75 /* CDMP Ingress Control Register */ 76 #define MTK_CDMQ_IG_CTRL 0x1400 77 #define MTK_CDMQ_STAG_EN BIT(0) 78 79 /* CDMP Exgress Control Register */ 80 #define MTK_CDMP_EG_CTRL 0x404 81 82 /* GDM Exgress Control Register */ 83 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 84 #define MTK_GDMA_ICS_EN BIT(22) 85 #define MTK_GDMA_TCS_EN BIT(21) 86 #define MTK_GDMA_UCS_EN BIT(20) 87 88 /* Unicast Filter MAC Address Register - Low */ 89 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 90 91 /* Unicast Filter MAC Address Register - High */ 92 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 93 94 /* PDMA RX Base Pointer Register */ 95 #define MTK_PRX_BASE_PTR0 0x900 96 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 97 98 /* PDMA RX Maximum Count Register */ 99 #define MTK_PRX_MAX_CNT0 0x904 100 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 101 102 /* PDMA RX CPU Pointer Register */ 103 #define MTK_PRX_CRX_IDX0 0x908 104 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 105 106 /* PDMA HW LRO Control Registers */ 107 #define MTK_PDMA_LRO_CTRL_DW0 0x980 108 #define MTK_LRO_EN BIT(0) 109 #define MTK_L3_CKS_UPD_EN BIT(7) 110 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 111 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 112 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 113 114 #define MTK_PDMA_LRO_CTRL_DW1 0x984 115 #define MTK_PDMA_LRO_CTRL_DW2 0x988 116 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 117 #define MTK_ADMA_MODE BIT(15) 118 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 119 120 /* PDMA Global Configuration Register */ 121 #define MTK_PDMA_GLO_CFG 0xa04 122 #define MTK_MULTI_EN BIT(10) 123 124 /* PDMA Reset Index Register */ 125 #define MTK_PDMA_RST_IDX 0xa08 126 #define MTK_PST_DRX_IDX0 BIT(16) 127 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 128 129 /* PDMA Delay Interrupt Register */ 130 #define MTK_PDMA_DELAY_INT 0xa0c 131 #define MTK_PDMA_DELAY_RX_EN BIT(15) 132 #define MTK_PDMA_DELAY_RX_PINT 4 133 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 134 #define MTK_PDMA_DELAY_RX_PTIME 4 135 #define MTK_PDMA_DELAY_RX_DELAY \ 136 (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ 137 (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) 138 139 /* PDMA Interrupt Status Register */ 140 #define MTK_PDMA_INT_STATUS 0xa20 141 142 /* PDMA Interrupt Mask Register */ 143 #define MTK_PDMA_INT_MASK 0xa28 144 145 /* PDMA HW LRO Alter Flow Delta Register */ 146 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 147 148 /* PDMA Interrupt grouping registers */ 149 #define MTK_PDMA_INT_GRP1 0xa50 150 #define MTK_PDMA_INT_GRP2 0xa54 151 152 /* PDMA HW LRO IP Setting Registers */ 153 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 154 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 155 #define MTK_RING_MYIP_VLD BIT(9) 156 157 /* PDMA HW LRO Ring Control Registers */ 158 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 159 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 160 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 161 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 162 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 163 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 164 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 165 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 166 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 167 #define MTK_RING_VLD BIT(8) 168 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 169 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 170 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 171 172 /* QDMA TX Queue Configuration Registers */ 173 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 174 #define QDMA_RES_THRES 4 175 176 /* QDMA TX Queue Scheduler Registers */ 177 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 178 179 /* QDMA RX Base Pointer Register */ 180 #define MTK_QRX_BASE_PTR0 0x1900 181 182 /* QDMA RX Maximum Count Register */ 183 #define MTK_QRX_MAX_CNT0 0x1904 184 185 /* QDMA RX CPU Pointer Register */ 186 #define MTK_QRX_CRX_IDX0 0x1908 187 188 /* QDMA RX DMA Pointer Register */ 189 #define MTK_QRX_DRX_IDX0 0x190C 190 191 /* QDMA Global Configuration Register */ 192 #define MTK_QDMA_GLO_CFG 0x1A04 193 #define MTK_RX_2B_OFFSET BIT(31) 194 #define MTK_RX_BT_32DWORDS (3 << 11) 195 #define MTK_NDP_CO_PRO BIT(10) 196 #define MTK_TX_WB_DDONE BIT(6) 197 #define MTK_DMA_SIZE_16DWORDS (2 << 4) 198 #define MTK_RX_DMA_BUSY BIT(3) 199 #define MTK_TX_DMA_BUSY BIT(1) 200 #define MTK_RX_DMA_EN BIT(2) 201 #define MTK_TX_DMA_EN BIT(0) 202 #define MTK_DMA_BUSY_TIMEOUT HZ 203 204 /* QDMA Reset Index Register */ 205 #define MTK_QDMA_RST_IDX 0x1A08 206 207 /* QDMA Delay Interrupt Register */ 208 #define MTK_QDMA_DELAY_INT 0x1A0C 209 210 /* QDMA Flow Control Register */ 211 #define MTK_QDMA_FC_THRES 0x1A10 212 #define FC_THRES_DROP_MODE BIT(20) 213 #define FC_THRES_DROP_EN (7 << 16) 214 #define FC_THRES_MIN 0x4444 215 216 /* QDMA Interrupt Status Register */ 217 #define MTK_QMTK_INT_STATUS 0x1A18 218 #define MTK_RX_DONE_DLY BIT(30) 219 #define MTK_RX_DONE_INT3 BIT(19) 220 #define MTK_RX_DONE_INT2 BIT(18) 221 #define MTK_RX_DONE_INT1 BIT(17) 222 #define MTK_RX_DONE_INT0 BIT(16) 223 #define MTK_TX_DONE_INT3 BIT(3) 224 #define MTK_TX_DONE_INT2 BIT(2) 225 #define MTK_TX_DONE_INT1 BIT(1) 226 #define MTK_TX_DONE_INT0 BIT(0) 227 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 228 #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 229 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 230 231 /* QDMA Interrupt grouping registers */ 232 #define MTK_QDMA_INT_GRP1 0x1a20 233 #define MTK_QDMA_INT_GRP2 0x1a24 234 #define MTK_RLS_DONE_INT BIT(0) 235 236 /* QDMA Interrupt Status Register */ 237 #define MTK_QDMA_INT_MASK 0x1A1C 238 239 /* QDMA Interrupt Mask Register */ 240 #define MTK_QDMA_HRED2 0x1A44 241 242 /* QDMA TX Forward CPU Pointer Register */ 243 #define MTK_QTX_CTX_PTR 0x1B00 244 245 /* QDMA TX Forward DMA Pointer Register */ 246 #define MTK_QTX_DTX_PTR 0x1B04 247 248 /* QDMA TX Release CPU Pointer Register */ 249 #define MTK_QTX_CRX_PTR 0x1B10 250 251 /* QDMA TX Release DMA Pointer Register */ 252 #define MTK_QTX_DRX_PTR 0x1B14 253 254 /* QDMA FQ Head Pointer Register */ 255 #define MTK_QDMA_FQ_HEAD 0x1B20 256 257 /* QDMA FQ Head Pointer Register */ 258 #define MTK_QDMA_FQ_TAIL 0x1B24 259 260 /* QDMA FQ Free Page Counter Register */ 261 #define MTK_QDMA_FQ_CNT 0x1B28 262 263 /* QDMA FQ Free Page Buffer Length Register */ 264 #define MTK_QDMA_FQ_BLEN 0x1B2C 265 266 /* GMA1 Received Good Byte Count Register */ 267 #define MTK_GDM1_TX_GBCNT 0x2400 268 #define MTK_STAT_OFFSET 0x40 269 270 /* QDMA descriptor txd4 */ 271 #define TX_DMA_CHKSUM (0x7 << 29) 272 #define TX_DMA_TSO BIT(28) 273 #define TX_DMA_FPORT_SHIFT 25 274 #define TX_DMA_FPORT_MASK 0x7 275 #define TX_DMA_INS_VLAN BIT(16) 276 277 /* QDMA descriptor txd3 */ 278 #define TX_DMA_OWNER_CPU BIT(31) 279 #define TX_DMA_LS0 BIT(30) 280 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 281 #define TX_DMA_SWC BIT(14) 282 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 283 284 /* QDMA descriptor rxd2 */ 285 #define RX_DMA_DONE BIT(31) 286 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 287 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 288 289 /* QDMA descriptor rxd3 */ 290 #define RX_DMA_VID(_x) ((_x) & 0xfff) 291 292 /* QDMA descriptor rxd4 */ 293 #define RX_DMA_L4_VALID BIT(24) 294 #define RX_DMA_FPORT_SHIFT 19 295 #define RX_DMA_FPORT_MASK 0x7 296 297 /* PHY Indirect Access Control registers */ 298 #define MTK_PHY_IAC 0x10004 299 #define PHY_IAC_ACCESS BIT(31) 300 #define PHY_IAC_READ BIT(19) 301 #define PHY_IAC_WRITE BIT(18) 302 #define PHY_IAC_START BIT(16) 303 #define PHY_IAC_ADDR_SHIFT 20 304 #define PHY_IAC_REG_SHIFT 25 305 #define PHY_IAC_TIMEOUT HZ 306 307 #define MTK_MAC_MISC 0x1000c 308 #define MTK_MUX_TO_ESW BIT(0) 309 310 /* Mac control registers */ 311 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 312 #define MAC_MCR_MAX_RX_1536 BIT(24) 313 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 314 #define MAC_MCR_FORCE_MODE BIT(15) 315 #define MAC_MCR_TX_EN BIT(14) 316 #define MAC_MCR_RX_EN BIT(13) 317 #define MAC_MCR_BACKOFF_EN BIT(9) 318 #define MAC_MCR_BACKPR_EN BIT(8) 319 #define MAC_MCR_FORCE_RX_FC BIT(5) 320 #define MAC_MCR_FORCE_TX_FC BIT(4) 321 #define MAC_MCR_SPEED_1000 BIT(3) 322 #define MAC_MCR_SPEED_100 BIT(2) 323 #define MAC_MCR_FORCE_DPX BIT(1) 324 #define MAC_MCR_FORCE_LINK BIT(0) 325 #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ 326 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ 327 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ 328 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ 329 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ 330 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) 331 332 /* TRGMII RXC control register */ 333 #define TRGMII_RCK_CTRL 0x10300 334 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 335 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 336 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 337 #define RXC_DQSISEL BIT(30) 338 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 339 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 340 341 /* TRGMII RXC control register */ 342 #define TRGMII_TCK_CTRL 0x10340 343 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 344 #define TXC_INV BIT(30) 345 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 346 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 347 348 /* TRGMII Interface mode register */ 349 #define INTF_MODE 0x10390 350 #define TRGMII_INTF_DIS BIT(0) 351 #define TRGMII_MODE BIT(1) 352 #define TRGMII_CENTRAL_ALIGNED BIT(2) 353 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 354 #define INTF_MODE_RGMII_10_100 0 355 356 /* GPIO port control registers for GMAC 2*/ 357 #define GPIO_OD33_CTRL8 0x4c0 358 #define GPIO_BIAS_CTRL 0xed0 359 #define GPIO_DRV_SEL10 0xf00 360 361 /* ethernet subsystem chip id register */ 362 #define ETHSYS_CHIPID0_3 0x0 363 #define ETHSYS_CHIPID4_7 0x4 364 #define MT7623_ETH 7623 365 #define MT7622_ETH 7622 366 367 /* ethernet subsystem config register */ 368 #define ETHSYS_SYSCFG0 0x14 369 #define SYSCFG0_GE_MASK 0x3 370 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 371 #define SYSCFG0_SGMII_MASK (3 << 8) 372 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & GENMASK(9, 8)) 373 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & GENMASK(9, 8)) 374 375 /* ethernet subsystem clock register */ 376 #define ETHSYS_CLKCFG0 0x2c 377 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 378 379 /* ethernet reset control register */ 380 #define ETHSYS_RSTCTRL 0x34 381 #define RSTCTRL_FE BIT(6) 382 #define RSTCTRL_PPE BIT(31) 383 384 /* SGMII subsystem config registers */ 385 /* Register to auto-negotiation restart */ 386 #define SGMSYS_PCS_CONTROL_1 0x0 387 #define SGMII_AN_RESTART BIT(9) 388 389 /* Register to programmable link timer, the unit in 2 * 8ns */ 390 #define SGMSYS_PCS_LINK_TIMER 0x18 391 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 392 393 /* Register to control remote fault */ 394 #define SGMSYS_SGMII_MODE 0x20 395 #define SGMII_REMOTE_FAULT_DIS BIT(8) 396 397 /* Register to power up QPHY */ 398 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 399 #define SGMII_PHYA_PWD BIT(4) 400 401 struct mtk_rx_dma { 402 unsigned int rxd1; 403 unsigned int rxd2; 404 unsigned int rxd3; 405 unsigned int rxd4; 406 } __packed __aligned(4); 407 408 struct mtk_tx_dma { 409 unsigned int txd1; 410 unsigned int txd2; 411 unsigned int txd3; 412 unsigned int txd4; 413 } __packed __aligned(4); 414 415 struct mtk_eth; 416 struct mtk_mac; 417 418 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 419 * @stats_lock: make sure that stats operations are atomic 420 * @reg_offset: the status register offset of the SoC 421 * @syncp: the refcount 422 * 423 * All of the supported SoCs have hardware counters for traffic statistics. 424 * Whenever the status IRQ triggers we can read the latest stats from these 425 * counters and store them in this struct. 426 */ 427 struct mtk_hw_stats { 428 u64 tx_bytes; 429 u64 tx_packets; 430 u64 tx_skip; 431 u64 tx_collisions; 432 u64 rx_bytes; 433 u64 rx_packets; 434 u64 rx_overflow; 435 u64 rx_fcs_errors; 436 u64 rx_short_errors; 437 u64 rx_long_errors; 438 u64 rx_checksum_errors; 439 u64 rx_flow_control_packets; 440 441 spinlock_t stats_lock; 442 u32 reg_offset; 443 struct u64_stats_sync syncp; 444 }; 445 446 enum mtk_tx_flags { 447 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 448 * track how memory was allocated so that it can be freed properly. 449 */ 450 MTK_TX_FLAGS_SINGLE0 = 0x01, 451 MTK_TX_FLAGS_PAGE0 = 0x02, 452 453 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 454 * SKB out instead of looking up through hardware TX descriptor. 455 */ 456 MTK_TX_FLAGS_FPORT0 = 0x04, 457 MTK_TX_FLAGS_FPORT1 = 0x08, 458 }; 459 460 /* This enum allows us to identify how the clock is defined on the array of the 461 * clock in the order 462 */ 463 enum mtk_clks_map { 464 MTK_CLK_ETHIF, 465 MTK_CLK_ESW, 466 MTK_CLK_GP0, 467 MTK_CLK_GP1, 468 MTK_CLK_GP2, 469 MTK_CLK_TRGPLL, 470 MTK_CLK_SGMII_TX_250M, 471 MTK_CLK_SGMII_RX_250M, 472 MTK_CLK_SGMII_CDR_REF, 473 MTK_CLK_SGMII_CDR_FB, 474 MTK_CLK_SGMII_CK, 475 MTK_CLK_ETH2PLL, 476 MTK_CLK_MAX 477 }; 478 479 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 480 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 481 BIT(MTK_CLK_TRGPLL)) 482 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 483 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 484 BIT(MTK_CLK_GP2) | \ 485 BIT(MTK_CLK_SGMII_TX_250M) | \ 486 BIT(MTK_CLK_SGMII_RX_250M) | \ 487 BIT(MTK_CLK_SGMII_CDR_REF) | \ 488 BIT(MTK_CLK_SGMII_CDR_FB) | \ 489 BIT(MTK_CLK_SGMII_CK) | \ 490 BIT(MTK_CLK_ETH2PLL)) 491 enum mtk_dev_state { 492 MTK_HW_INIT, 493 MTK_RESETTING 494 }; 495 496 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 497 * by the TX descriptor s 498 * @skb: The SKB pointer of the packet being sent 499 * @dma_addr0: The base addr of the first segment 500 * @dma_len0: The length of the first segment 501 * @dma_addr1: The base addr of the second segment 502 * @dma_len1: The length of the second segment 503 */ 504 struct mtk_tx_buf { 505 struct sk_buff *skb; 506 u32 flags; 507 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 508 DEFINE_DMA_UNMAP_LEN(dma_len0); 509 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 510 DEFINE_DMA_UNMAP_LEN(dma_len1); 511 }; 512 513 /* struct mtk_tx_ring - This struct holds info describing a TX ring 514 * @dma: The descriptor ring 515 * @buf: The memory pointed at by the ring 516 * @phys: The physical addr of tx_buf 517 * @next_free: Pointer to the next free descriptor 518 * @last_free: Pointer to the last free descriptor 519 * @thresh: The threshold of minimum amount of free descriptors 520 * @free_count: QDMA uses a linked list. Track how many free descriptors 521 * are present 522 */ 523 struct mtk_tx_ring { 524 struct mtk_tx_dma *dma; 525 struct mtk_tx_buf *buf; 526 dma_addr_t phys; 527 struct mtk_tx_dma *next_free; 528 struct mtk_tx_dma *last_free; 529 u16 thresh; 530 atomic_t free_count; 531 }; 532 533 /* PDMA rx ring mode */ 534 enum mtk_rx_flags { 535 MTK_RX_FLAGS_NORMAL = 0, 536 MTK_RX_FLAGS_HWLRO, 537 MTK_RX_FLAGS_QDMA, 538 }; 539 540 /* struct mtk_rx_ring - This struct holds info describing a RX ring 541 * @dma: The descriptor ring 542 * @data: The memory pointed at by the ring 543 * @phys: The physical addr of rx_buf 544 * @frag_size: How big can each fragment be 545 * @buf_size: The size of each packet buffer 546 * @calc_idx: The current head of ring 547 */ 548 struct mtk_rx_ring { 549 struct mtk_rx_dma *dma; 550 u8 **data; 551 dma_addr_t phys; 552 u16 frag_size; 553 u16 buf_size; 554 u16 dma_size; 555 bool calc_idx_update; 556 u16 calc_idx; 557 u32 crx_idx_reg; 558 }; 559 560 #define MTK_TRGMII BIT(0) 561 #define MTK_GMAC1_TRGMII (BIT(1) | MTK_TRGMII) 562 #define MTK_ESW BIT(4) 563 #define MTK_GMAC1_ESW (BIT(5) | MTK_ESW) 564 #define MTK_SGMII BIT(8) 565 #define MTK_GMAC1_SGMII (BIT(9) | MTK_SGMII) 566 #define MTK_GMAC2_SGMII (BIT(10) | MTK_SGMII) 567 #define MTK_DUAL_GMAC_SHARED_SGMII (BIT(11) | MTK_GMAC1_SGMII | \ 568 MTK_GMAC2_SGMII) 569 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 570 571 /* struct mtk_eth_data - This is the structure holding all differences 572 * among various plaforms 573 * @caps Flags shown the extra capability for the SoC 574 * @required_clks Flags shown the bitmap for required clocks on 575 * the target SoC 576 * @required_pctl A bool value to show whether the SoC requires 577 * the extra setup for those pins used by GMAC. 578 */ 579 struct mtk_soc_data { 580 u32 caps; 581 u32 required_clks; 582 bool required_pctl; 583 }; 584 585 /* currently no SoC has more than 2 macs */ 586 #define MTK_MAX_DEVS 2 587 588 /* struct mtk_eth - This is the main datasructure for holding the state 589 * of the driver 590 * @dev: The device pointer 591 * @base: The mapped register i/o base 592 * @page_lock: Make sure that register operations are atomic 593 * @tx_irq__lock: Make sure that IRQ register operations are atomic 594 * @rx_irq__lock: Make sure that IRQ register operations are atomic 595 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 596 * dummy for NAPI to work 597 * @netdev: The netdev instances 598 * @mac: Each netdev is linked to a physical MAC 599 * @irq: The IRQ that we are using 600 * @msg_enable: Ethtool msg level 601 * @ethsys: The register map pointing at the range used to setup 602 * MII modes 603 * @sgmiisys: The register map pointing at the range used to setup 604 * SGMII modes 605 * @pctl: The register map pointing at the range used to setup 606 * GMAC port drive/slew values 607 * @dma_refcnt: track how many netdevs are using the DMA engine 608 * @tx_ring: Pointer to the memory holding info about the TX ring 609 * @rx_ring: Pointer to the memory holding info about the RX ring 610 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 611 * @tx_napi: The TX NAPI struct 612 * @rx_napi: The RX NAPI struct 613 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 614 * @phy_scratch_ring: physical address of scratch_ring 615 * @scratch_head: The scratch memory that scratch_ring points to. 616 * @clks: clock array for all clocks required 617 * @mii_bus: If there is a bus we need to create an instance for it 618 * @pending_work: The workqueue used to reset the dma ring 619 * @state: Initialization and runtime state of the device 620 * @soc: Holding specific data among vaious SoCs 621 */ 622 623 struct mtk_eth { 624 struct device *dev; 625 void __iomem *base; 626 spinlock_t page_lock; 627 spinlock_t tx_irq_lock; 628 spinlock_t rx_irq_lock; 629 struct net_device dummy_dev; 630 struct net_device *netdev[MTK_MAX_DEVS]; 631 struct mtk_mac *mac[MTK_MAX_DEVS]; 632 int irq[3]; 633 u32 msg_enable; 634 unsigned long sysclk; 635 struct regmap *ethsys; 636 struct regmap *sgmiisys; 637 struct regmap *pctl; 638 u32 chip_id; 639 bool hwlro; 640 refcount_t dma_refcnt; 641 struct mtk_tx_ring tx_ring; 642 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 643 struct mtk_rx_ring rx_ring_qdma; 644 struct napi_struct tx_napi; 645 struct napi_struct rx_napi; 646 struct mtk_tx_dma *scratch_ring; 647 dma_addr_t phy_scratch_ring; 648 void *scratch_head; 649 struct clk *clks[MTK_CLK_MAX]; 650 651 struct mii_bus *mii_bus; 652 struct work_struct pending_work; 653 unsigned long state; 654 655 const struct mtk_soc_data *soc; 656 }; 657 658 /* struct mtk_mac - the structure that holds the info about the MACs of the 659 * SoC 660 * @id: The number of the MAC 661 * @ge_mode: Interface mode kept for setup restoring 662 * @of_node: Our devicetree node 663 * @hw: Backpointer to our main datastruture 664 * @hw_stats: Packet statistics counter 665 * @trgmii Indicate if the MAC uses TRGMII connected to internal 666 switch 667 */ 668 struct mtk_mac { 669 int id; 670 int ge_mode; 671 struct device_node *of_node; 672 struct mtk_eth *hw; 673 struct mtk_hw_stats *hw_stats; 674 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 675 int hwlro_ip_cnt; 676 bool trgmii; 677 }; 678 679 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 680 extern const struct of_device_id of_mtk_match[]; 681 682 /* read the hardware status register */ 683 void mtk_stats_update_mac(struct mtk_mac *mac); 684 685 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 686 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 687 688 #endif /* MTK_ETH_H */ 689