1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 #include <linux/rhashtable.h> 19 #include <linux/dim.h> 20 #include <linux/bitfield.h> 21 #include <net/page_pool.h> 22 #include <linux/bpf_trace.h> 23 #include "mtk_ppe.h" 24 25 #define MTK_QDMA_PAGE_SIZE 2048 26 #define MTK_MAX_RX_LENGTH 1536 27 #define MTK_MAX_RX_LENGTH_2K 2048 28 #define MTK_TX_DMA_BUF_LEN 0x3fff 29 #define MTK_TX_DMA_BUF_LEN_V2 0xffff 30 #define MTK_DMA_SIZE 512 31 #define MTK_MAC_COUNT 2 32 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 33 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 34 #define MTK_DMA_DUMMY_DESC 0xffffffff 35 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 36 NETIF_MSG_PROBE | \ 37 NETIF_MSG_LINK | \ 38 NETIF_MSG_TIMER | \ 39 NETIF_MSG_IFDOWN | \ 40 NETIF_MSG_IFUP | \ 41 NETIF_MSG_RX_ERR | \ 42 NETIF_MSG_TX_ERR) 43 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 44 NETIF_F_RXCSUM | \ 45 NETIF_F_HW_VLAN_CTAG_TX | \ 46 NETIF_F_HW_VLAN_CTAG_RX | \ 47 NETIF_F_SG | NETIF_F_TSO | \ 48 NETIF_F_TSO6 | \ 49 NETIF_F_IPV6_CSUM |\ 50 NETIF_F_HW_TC) 51 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 52 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 53 54 #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM 55 #define MTK_PP_PAD (MTK_PP_HEADROOM + \ 56 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 57 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD) 58 59 #define MTK_QRX_OFFSET 0x10 60 61 #define MTK_MAX_RX_RING_NUM 4 62 #define MTK_HW_LRO_DMA_SIZE 8 63 64 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 65 #define MTK_MAX_LRO_IP_CNT 2 66 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 67 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 68 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 69 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 70 #define MTK_HW_LRO_MAX_AGG_CNT 64 71 #define MTK_HW_LRO_BW_THRE 3000 72 #define MTK_HW_LRO_REPLACE_DELTA 1000 73 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 74 75 /* Frame Engine Global Reset Register */ 76 #define MTK_RST_GL 0x04 77 #define RST_GL_PSE BIT(0) 78 79 /* Frame Engine Interrupt Status Register */ 80 #define MTK_INT_STATUS2 0x08 81 #define MTK_GDM1_AF BIT(28) 82 #define MTK_GDM2_AF BIT(29) 83 84 /* PDMA HW LRO Alter Flow Timer Register */ 85 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 86 87 /* Frame Engine Interrupt Grouping Register */ 88 #define MTK_FE_INT_GRP 0x20 89 90 /* CDMP Ingress Control Register */ 91 #define MTK_CDMQ_IG_CTRL 0x1400 92 #define MTK_CDMQ_STAG_EN BIT(0) 93 94 /* CDMP Ingress Control Register */ 95 #define MTK_CDMP_IG_CTRL 0x400 96 #define MTK_CDMP_STAG_EN BIT(0) 97 98 /* CDMP Exgress Control Register */ 99 #define MTK_CDMP_EG_CTRL 0x404 100 101 /* GDM Exgress Control Register */ 102 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 103 #define MTK_GDMA_SPECIAL_TAG BIT(24) 104 #define MTK_GDMA_ICS_EN BIT(22) 105 #define MTK_GDMA_TCS_EN BIT(21) 106 #define MTK_GDMA_UCS_EN BIT(20) 107 #define MTK_GDMA_TO_PDMA 0x0 108 #define MTK_GDMA_DROP_ALL 0x7777 109 110 /* Unicast Filter MAC Address Register - Low */ 111 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 112 113 /* Unicast Filter MAC Address Register - High */ 114 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 115 116 /* FE global misc reg*/ 117 #define MTK_FE_GLO_MISC 0x124 118 119 /* PSE Free Queue Flow Control */ 120 #define PSE_FQFC_CFG1 0x100 121 #define PSE_FQFC_CFG2 0x104 122 #define PSE_DROP_CFG 0x108 123 124 /* PSE Input Queue Reservation Register*/ 125 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 126 127 /* PSE Output Queue Threshold Register*/ 128 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 129 130 /* GDM and CDM Threshold */ 131 #define MTK_GDM2_THRES 0x1530 132 #define MTK_CDMW0_THRES 0x164c 133 #define MTK_CDMW1_THRES 0x1650 134 #define MTK_CDME0_THRES 0x1654 135 #define MTK_CDME1_THRES 0x1658 136 #define MTK_CDMM_THRES 0x165c 137 138 /* PDMA HW LRO Control Registers */ 139 #define MTK_PDMA_LRO_CTRL_DW0 0x980 140 #define MTK_LRO_EN BIT(0) 141 #define MTK_L3_CKS_UPD_EN BIT(7) 142 #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 143 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 144 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 145 #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 146 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 147 #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 148 149 #define MTK_PDMA_LRO_CTRL_DW1 0x984 150 #define MTK_PDMA_LRO_CTRL_DW2 0x988 151 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 152 #define MTK_ADMA_MODE BIT(15) 153 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 154 155 #define MTK_RX_DMA_LRO_EN BIT(8) 156 #define MTK_MULTI_EN BIT(10) 157 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 158 159 /* PDMA Global Configuration Register */ 160 #define MTK_PDMA_LRO_SDL 0x3000 161 #define MTK_RX_CFG_SDL_OFFSET 16 162 163 /* PDMA Reset Index Register */ 164 #define MTK_PST_DRX_IDX0 BIT(16) 165 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 166 167 /* PDMA Delay Interrupt Register */ 168 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 169 #define MTK_PDMA_DELAY_RX_EN BIT(15) 170 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 171 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 172 173 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 174 #define MTK_PDMA_DELAY_TX_EN BIT(31) 175 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 176 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 177 178 #define MTK_PDMA_DELAY_PINT_MASK 0x7f 179 #define MTK_PDMA_DELAY_PTIME_MASK 0xff 180 181 /* PDMA HW LRO Alter Flow Delta Register */ 182 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 183 184 /* PDMA HW LRO IP Setting Registers */ 185 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 186 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 187 #define MTK_RING_MYIP_VLD BIT(9) 188 189 /* PDMA HW LRO Ring Control Registers */ 190 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 191 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 192 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 193 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 194 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 195 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 196 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 197 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 198 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 199 #define MTK_RING_VLD BIT(8) 200 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 201 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 202 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 203 204 /* QDMA TX Queue Configuration Registers */ 205 #define QDMA_RES_THRES 4 206 207 /* QDMA Global Configuration Register */ 208 #define MTK_RX_2B_OFFSET BIT(31) 209 #define MTK_RX_BT_32DWORDS (3 << 11) 210 #define MTK_NDP_CO_PRO BIT(10) 211 #define MTK_TX_WB_DDONE BIT(6) 212 #define MTK_TX_BT_32DWORDS (3 << 4) 213 #define MTK_RX_DMA_BUSY BIT(3) 214 #define MTK_TX_DMA_BUSY BIT(1) 215 #define MTK_RX_DMA_EN BIT(2) 216 #define MTK_TX_DMA_EN BIT(0) 217 #define MTK_DMA_BUSY_TIMEOUT_US 1000000 218 219 /* QDMA V2 Global Configuration Register */ 220 #define MTK_CHK_DDONE_EN BIT(28) 221 #define MTK_DMAD_WR_WDONE BIT(26) 222 #define MTK_WCOMP_EN BIT(24) 223 #define MTK_RESV_BUF (0x40 << 16) 224 #define MTK_MUTLI_CNT (0x4 << 12) 225 226 /* QDMA Flow Control Register */ 227 #define FC_THRES_DROP_MODE BIT(20) 228 #define FC_THRES_DROP_EN (7 << 16) 229 #define FC_THRES_MIN 0x4444 230 231 /* QDMA Interrupt Status Register */ 232 #define MTK_RX_DONE_DLY BIT(30) 233 #define MTK_TX_DONE_DLY BIT(28) 234 #define MTK_RX_DONE_INT3 BIT(19) 235 #define MTK_RX_DONE_INT2 BIT(18) 236 #define MTK_RX_DONE_INT1 BIT(17) 237 #define MTK_RX_DONE_INT0 BIT(16) 238 #define MTK_TX_DONE_INT3 BIT(3) 239 #define MTK_TX_DONE_INT2 BIT(2) 240 #define MTK_TX_DONE_INT1 BIT(1) 241 #define MTK_TX_DONE_INT0 BIT(0) 242 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 243 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 244 245 #define MTK_RX_DONE_INT_V2 BIT(14) 246 247 /* QDMA Interrupt grouping registers */ 248 #define MTK_RLS_DONE_INT BIT(0) 249 250 #define MTK_STAT_OFFSET 0x40 251 252 /* QDMA TX NUM */ 253 #define MTK_QDMA_TX_NUM 16 254 #define MTK_QDMA_TX_MASK (MTK_QDMA_TX_NUM - 1) 255 #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 256 #define MTK_QDMA_GMAC2_QID 8 257 258 #define MTK_TX_DMA_BUF_SHIFT 8 259 260 /* QDMA V2 descriptor txd6 */ 261 #define TX_DMA_INS_VLAN_V2 BIT(16) 262 /* QDMA V2 descriptor txd5 */ 263 #define TX_DMA_CHKSUM_V2 (0x7 << 28) 264 #define TX_DMA_TSO_V2 BIT(31) 265 266 /* QDMA V2 descriptor txd4 */ 267 #define TX_DMA_FPORT_SHIFT_V2 8 268 #define TX_DMA_FPORT_MASK_V2 0xf 269 #define TX_DMA_SWC_V2 BIT(30) 270 271 /* QDMA descriptor txd4 */ 272 #define TX_DMA_CHKSUM (0x7 << 29) 273 #define TX_DMA_TSO BIT(28) 274 #define TX_DMA_FPORT_SHIFT 25 275 #define TX_DMA_FPORT_MASK 0x7 276 #define TX_DMA_INS_VLAN BIT(16) 277 278 /* QDMA descriptor txd3 */ 279 #define TX_DMA_OWNER_CPU BIT(31) 280 #define TX_DMA_LS0 BIT(30) 281 #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 282 #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) 283 #define TX_DMA_SWC BIT(14) 284 285 /* PDMA on MT7628 */ 286 #define TX_DMA_DONE BIT(31) 287 #define TX_DMA_LS1 BIT(14) 288 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 289 290 /* QDMA descriptor rxd2 */ 291 #define RX_DMA_DONE BIT(31) 292 #define RX_DMA_LSO BIT(30) 293 #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 294 #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) 295 #define RX_DMA_VTAG BIT(15) 296 297 /* QDMA descriptor rxd3 */ 298 #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 299 #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 300 #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 301 302 /* QDMA descriptor rxd4 */ 303 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 304 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 305 #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 306 #define MTK_RXD4_ALG GENMASK(31, 22) 307 308 /* QDMA descriptor rxd4 */ 309 #define RX_DMA_L4_VALID BIT(24) 310 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 311 #define RX_DMA_SPECIAL_TAG BIT(22) 312 313 /* PDMA descriptor rxd5 */ 314 #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) 315 #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) 316 #define MTK_RXD5_SRC_PORT GENMASK(29, 26) 317 318 #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7) 319 #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf) 320 321 /* PDMA V2 descriptor rxd3 */ 322 #define RX_DMA_VTAG_V2 BIT(0) 323 #define RX_DMA_L4_VALID_V2 BIT(2) 324 325 /* PHY Indirect Access Control registers */ 326 #define MTK_PHY_IAC 0x10004 327 #define PHY_IAC_ACCESS BIT(31) 328 #define PHY_IAC_REG_MASK GENMASK(29, 25) 329 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 330 #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 331 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 332 #define PHY_IAC_CMD_MASK GENMASK(19, 18) 333 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 334 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 335 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 336 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 337 #define PHY_IAC_START_MASK GENMASK(17, 16) 338 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 339 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 340 #define PHY_IAC_DATA_MASK GENMASK(15, 0) 341 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 342 #define PHY_IAC_TIMEOUT HZ 343 344 #define MTK_MAC_MISC 0x1000c 345 #define MTK_MUX_TO_ESW BIT(0) 346 347 /* Mac control registers */ 348 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 349 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 350 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 351 #define MAC_MCR_MAX_RX_1518 0x0 352 #define MAC_MCR_MAX_RX_1536 0x1 353 #define MAC_MCR_MAX_RX_1552 0x2 354 #define MAC_MCR_MAX_RX_2048 0x3 355 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 356 #define MAC_MCR_FORCE_MODE BIT(15) 357 #define MAC_MCR_TX_EN BIT(14) 358 #define MAC_MCR_RX_EN BIT(13) 359 #define MAC_MCR_BACKOFF_EN BIT(9) 360 #define MAC_MCR_BACKPR_EN BIT(8) 361 #define MAC_MCR_FORCE_RX_FC BIT(5) 362 #define MAC_MCR_FORCE_TX_FC BIT(4) 363 #define MAC_MCR_SPEED_1000 BIT(3) 364 #define MAC_MCR_SPEED_100 BIT(2) 365 #define MAC_MCR_FORCE_DPX BIT(1) 366 #define MAC_MCR_FORCE_LINK BIT(0) 367 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 368 369 /* Mac status registers */ 370 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 371 #define MAC_MSR_EEE1G BIT(7) 372 #define MAC_MSR_EEE100M BIT(6) 373 #define MAC_MSR_RX_FC BIT(5) 374 #define MAC_MSR_TX_FC BIT(4) 375 #define MAC_MSR_SPEED_1000 BIT(3) 376 #define MAC_MSR_SPEED_100 BIT(2) 377 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 378 #define MAC_MSR_DPX BIT(1) 379 #define MAC_MSR_LINK BIT(0) 380 381 /* TRGMII RXC control register */ 382 #define TRGMII_RCK_CTRL 0x10300 383 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 384 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 385 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 386 #define RXC_RST BIT(31) 387 #define RXC_DQSISEL BIT(30) 388 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 389 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 390 391 #define NUM_TRGMII_CTRL 5 392 393 /* TRGMII RXC control register */ 394 #define TRGMII_TCK_CTRL 0x10340 395 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 396 #define TXC_INV BIT(30) 397 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 398 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 399 400 /* TRGMII TX Drive Strength */ 401 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 402 #define TD_DM_DRVP(x) ((x) & 0xf) 403 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 404 405 /* TRGMII Interface mode register */ 406 #define INTF_MODE 0x10390 407 #define TRGMII_INTF_DIS BIT(0) 408 #define TRGMII_MODE BIT(1) 409 #define TRGMII_CENTRAL_ALIGNED BIT(2) 410 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 411 #define INTF_MODE_RGMII_10_100 0 412 413 /* GPIO port control registers for GMAC 2*/ 414 #define GPIO_OD33_CTRL8 0x4c0 415 #define GPIO_BIAS_CTRL 0xed0 416 #define GPIO_DRV_SEL10 0xf00 417 418 /* ethernet subsystem chip id register */ 419 #define ETHSYS_CHIPID0_3 0x0 420 #define ETHSYS_CHIPID4_7 0x4 421 #define MT7623_ETH 7623 422 #define MT7622_ETH 7622 423 #define MT7621_ETH 7621 424 425 /* ethernet system control register */ 426 #define ETHSYS_SYSCFG 0x10 427 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 428 429 /* ethernet subsystem config register */ 430 #define ETHSYS_SYSCFG0 0x14 431 #define SYSCFG0_GE_MASK 0x3 432 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 433 #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 434 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 435 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 436 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 437 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 438 439 440 /* ethernet subsystem clock register */ 441 #define ETHSYS_CLKCFG0 0x2c 442 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 443 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 444 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 445 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 446 447 /* ethernet reset control register */ 448 #define ETHSYS_RSTCTRL 0x34 449 #define RSTCTRL_FE BIT(6) 450 #define RSTCTRL_PPE BIT(31) 451 #define RSTCTRL_PPE1 BIT(30) 452 #define RSTCTRL_ETH BIT(23) 453 454 /* ethernet reset check idle register */ 455 #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 456 457 /* ethernet reset control register */ 458 #define ETHSYS_RSTCTRL 0x34 459 #define RSTCTRL_FE BIT(6) 460 #define RSTCTRL_PPE BIT(31) 461 462 /* ethernet dma channel agent map */ 463 #define ETHSYS_DMA_AG_MAP 0x408 464 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 465 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 466 #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 467 468 /* SGMII subsystem config registers */ 469 /* Register to auto-negotiation restart */ 470 #define SGMSYS_PCS_CONTROL_1 0x0 471 #define SGMII_AN_RESTART BIT(9) 472 #define SGMII_ISOLATE BIT(10) 473 #define SGMII_AN_ENABLE BIT(12) 474 #define SGMII_LINK_STATYS BIT(18) 475 #define SGMII_AN_ABILITY BIT(19) 476 #define SGMII_AN_COMPLETE BIT(21) 477 #define SGMII_PCS_FAULT BIT(23) 478 #define SGMII_AN_EXPANSION_CLR BIT(30) 479 480 /* Register to programmable link timer, the unit in 2 * 8ns */ 481 #define SGMSYS_PCS_LINK_TIMER 0x18 482 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 483 484 /* Register to control remote fault */ 485 #define SGMSYS_SGMII_MODE 0x20 486 #define SGMII_IF_MODE_BIT0 BIT(0) 487 #define SGMII_SPEED_DUPLEX_AN BIT(1) 488 #define SGMII_SPEED_MASK GENMASK(3, 2) 489 #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) 490 #define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) 491 #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) 492 #define SGMII_DUPLEX_FULL BIT(4) 493 #define SGMII_IF_MODE_BIT5 BIT(5) 494 #define SGMII_REMOTE_FAULT_DIS BIT(8) 495 #define SGMII_CODE_SYNC_SET_VAL BIT(9) 496 #define SGMII_CODE_SYNC_SET_EN BIT(10) 497 #define SGMII_SEND_AN_ERROR_EN BIT(11) 498 #define SGMII_IF_MODE_MASK GENMASK(5, 1) 499 500 /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 501 #define SGMSYS_ANA_RG_CS3 0x2028 502 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 503 #define RG_PHY_SPEED_1_25G 0x0 504 #define RG_PHY_SPEED_3_125G BIT(2) 505 506 /* Register to power up QPHY */ 507 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 508 #define SGMII_PHYA_PWD BIT(4) 509 510 /* Infrasys subsystem config registers */ 511 #define INFRA_MISC2 0x70c 512 #define CO_QPHY_SEL BIT(0) 513 #define GEPHY_MAC_SEL BIT(1) 514 515 /* MT7628/88 specific stuff */ 516 #define MT7628_PDMA_OFFSET 0x0800 517 #define MT7628_SDM_OFFSET 0x0c00 518 519 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 520 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 521 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 522 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 523 #define MT7628_PST_DTX_IDX0 BIT(0) 524 525 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 526 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 527 528 /* Counter / stat register */ 529 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 530 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 531 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 532 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 533 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 534 535 struct mtk_rx_dma { 536 unsigned int rxd1; 537 unsigned int rxd2; 538 unsigned int rxd3; 539 unsigned int rxd4; 540 } __packed __aligned(4); 541 542 struct mtk_rx_dma_v2 { 543 unsigned int rxd1; 544 unsigned int rxd2; 545 unsigned int rxd3; 546 unsigned int rxd4; 547 unsigned int rxd5; 548 unsigned int rxd6; 549 unsigned int rxd7; 550 unsigned int rxd8; 551 } __packed __aligned(4); 552 553 struct mtk_tx_dma { 554 unsigned int txd1; 555 unsigned int txd2; 556 unsigned int txd3; 557 unsigned int txd4; 558 } __packed __aligned(4); 559 560 struct mtk_tx_dma_v2 { 561 unsigned int txd1; 562 unsigned int txd2; 563 unsigned int txd3; 564 unsigned int txd4; 565 unsigned int txd5; 566 unsigned int txd6; 567 unsigned int txd7; 568 unsigned int txd8; 569 } __packed __aligned(4); 570 571 struct mtk_eth; 572 struct mtk_mac; 573 574 struct mtk_xdp_stats { 575 u64 rx_xdp_redirect; 576 u64 rx_xdp_pass; 577 u64 rx_xdp_drop; 578 u64 rx_xdp_tx; 579 u64 rx_xdp_tx_errors; 580 u64 tx_xdp_xmit; 581 u64 tx_xdp_xmit_errors; 582 }; 583 584 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 585 * @stats_lock: make sure that stats operations are atomic 586 * @reg_offset: the status register offset of the SoC 587 * @syncp: the refcount 588 * 589 * All of the supported SoCs have hardware counters for traffic statistics. 590 * Whenever the status IRQ triggers we can read the latest stats from these 591 * counters and store them in this struct. 592 */ 593 struct mtk_hw_stats { 594 u64 tx_bytes; 595 u64 tx_packets; 596 u64 tx_skip; 597 u64 tx_collisions; 598 u64 rx_bytes; 599 u64 rx_packets; 600 u64 rx_overflow; 601 u64 rx_fcs_errors; 602 u64 rx_short_errors; 603 u64 rx_long_errors; 604 u64 rx_checksum_errors; 605 u64 rx_flow_control_packets; 606 607 struct mtk_xdp_stats xdp_stats; 608 609 spinlock_t stats_lock; 610 u32 reg_offset; 611 struct u64_stats_sync syncp; 612 }; 613 614 enum mtk_tx_flags { 615 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 616 * track how memory was allocated so that it can be freed properly. 617 */ 618 MTK_TX_FLAGS_SINGLE0 = 0x01, 619 MTK_TX_FLAGS_PAGE0 = 0x02, 620 621 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 622 * SKB out instead of looking up through hardware TX descriptor. 623 */ 624 MTK_TX_FLAGS_FPORT0 = 0x04, 625 MTK_TX_FLAGS_FPORT1 = 0x08, 626 }; 627 628 /* This enum allows us to identify how the clock is defined on the array of the 629 * clock in the order 630 */ 631 enum mtk_clks_map { 632 MTK_CLK_ETHIF, 633 MTK_CLK_SGMIITOP, 634 MTK_CLK_ESW, 635 MTK_CLK_GP0, 636 MTK_CLK_GP1, 637 MTK_CLK_GP2, 638 MTK_CLK_FE, 639 MTK_CLK_TRGPLL, 640 MTK_CLK_SGMII_TX_250M, 641 MTK_CLK_SGMII_RX_250M, 642 MTK_CLK_SGMII_CDR_REF, 643 MTK_CLK_SGMII_CDR_FB, 644 MTK_CLK_SGMII2_TX_250M, 645 MTK_CLK_SGMII2_RX_250M, 646 MTK_CLK_SGMII2_CDR_REF, 647 MTK_CLK_SGMII2_CDR_FB, 648 MTK_CLK_SGMII_CK, 649 MTK_CLK_ETH2PLL, 650 MTK_CLK_WOCPU0, 651 MTK_CLK_WOCPU1, 652 MTK_CLK_NETSYS0, 653 MTK_CLK_NETSYS1, 654 MTK_CLK_MAX 655 }; 656 657 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 658 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 659 BIT(MTK_CLK_TRGPLL)) 660 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 661 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 662 BIT(MTK_CLK_GP2) | \ 663 BIT(MTK_CLK_SGMII_TX_250M) | \ 664 BIT(MTK_CLK_SGMII_RX_250M) | \ 665 BIT(MTK_CLK_SGMII_CDR_REF) | \ 666 BIT(MTK_CLK_SGMII_CDR_FB) | \ 667 BIT(MTK_CLK_SGMII_CK) | \ 668 BIT(MTK_CLK_ETH2PLL)) 669 #define MT7621_CLKS_BITMAP (0) 670 #define MT7628_CLKS_BITMAP (0) 671 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 672 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 673 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 674 BIT(MTK_CLK_SGMII_TX_250M) | \ 675 BIT(MTK_CLK_SGMII_RX_250M) | \ 676 BIT(MTK_CLK_SGMII_CDR_REF) | \ 677 BIT(MTK_CLK_SGMII_CDR_FB) | \ 678 BIT(MTK_CLK_SGMII2_TX_250M) | \ 679 BIT(MTK_CLK_SGMII2_RX_250M) | \ 680 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 681 BIT(MTK_CLK_SGMII2_CDR_FB) | \ 682 BIT(MTK_CLK_SGMII_CK) | \ 683 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 684 #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ 685 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ 686 BIT(MTK_CLK_SGMII_TX_250M) | \ 687 BIT(MTK_CLK_SGMII_RX_250M) | \ 688 BIT(MTK_CLK_SGMII_CDR_REF) | \ 689 BIT(MTK_CLK_SGMII_CDR_FB) | \ 690 BIT(MTK_CLK_SGMII2_TX_250M) | \ 691 BIT(MTK_CLK_SGMII2_RX_250M) | \ 692 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 693 BIT(MTK_CLK_SGMII2_CDR_FB)) 694 695 enum mtk_dev_state { 696 MTK_HW_INIT, 697 MTK_RESETTING 698 }; 699 700 enum mtk_tx_buf_type { 701 MTK_TYPE_SKB, 702 MTK_TYPE_XDP_TX, 703 MTK_TYPE_XDP_NDO, 704 }; 705 706 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 707 * by the TX descriptor s 708 * @skb: The SKB pointer of the packet being sent 709 * @dma_addr0: The base addr of the first segment 710 * @dma_len0: The length of the first segment 711 * @dma_addr1: The base addr of the second segment 712 * @dma_len1: The length of the second segment 713 */ 714 struct mtk_tx_buf { 715 enum mtk_tx_buf_type type; 716 void *data; 717 718 u32 flags; 719 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 720 DEFINE_DMA_UNMAP_LEN(dma_len0); 721 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 722 DEFINE_DMA_UNMAP_LEN(dma_len1); 723 }; 724 725 /* struct mtk_tx_ring - This struct holds info describing a TX ring 726 * @dma: The descriptor ring 727 * @buf: The memory pointed at by the ring 728 * @phys: The physical addr of tx_buf 729 * @next_free: Pointer to the next free descriptor 730 * @last_free: Pointer to the last free descriptor 731 * @last_free_ptr: Hardware pointer value of the last free descriptor 732 * @thresh: The threshold of minimum amount of free descriptors 733 * @free_count: QDMA uses a linked list. Track how many free descriptors 734 * are present 735 */ 736 struct mtk_tx_ring { 737 void *dma; 738 struct mtk_tx_buf *buf; 739 dma_addr_t phys; 740 struct mtk_tx_dma *next_free; 741 struct mtk_tx_dma *last_free; 742 u32 last_free_ptr; 743 u16 thresh; 744 atomic_t free_count; 745 int dma_size; 746 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 747 dma_addr_t phys_pdma; 748 int cpu_idx; 749 }; 750 751 /* PDMA rx ring mode */ 752 enum mtk_rx_flags { 753 MTK_RX_FLAGS_NORMAL = 0, 754 MTK_RX_FLAGS_HWLRO, 755 MTK_RX_FLAGS_QDMA, 756 }; 757 758 /* struct mtk_rx_ring - This struct holds info describing a RX ring 759 * @dma: The descriptor ring 760 * @data: The memory pointed at by the ring 761 * @phys: The physical addr of rx_buf 762 * @frag_size: How big can each fragment be 763 * @buf_size: The size of each packet buffer 764 * @calc_idx: The current head of ring 765 */ 766 struct mtk_rx_ring { 767 void *dma; 768 u8 **data; 769 dma_addr_t phys; 770 u16 frag_size; 771 u16 buf_size; 772 u16 dma_size; 773 bool calc_idx_update; 774 u16 calc_idx; 775 u32 crx_idx_reg; 776 /* page_pool */ 777 struct page_pool *page_pool; 778 struct xdp_rxq_info xdp_q; 779 }; 780 781 enum mkt_eth_capabilities { 782 MTK_RGMII_BIT = 0, 783 MTK_TRGMII_BIT, 784 MTK_SGMII_BIT, 785 MTK_ESW_BIT, 786 MTK_GEPHY_BIT, 787 MTK_MUX_BIT, 788 MTK_INFRA_BIT, 789 MTK_SHARED_SGMII_BIT, 790 MTK_HWLRO_BIT, 791 MTK_SHARED_INT_BIT, 792 MTK_TRGMII_MT7621_CLK_BIT, 793 MTK_QDMA_BIT, 794 MTK_NETSYS_V2_BIT, 795 MTK_SOC_MT7628_BIT, 796 MTK_RSTCTRL_PPE1_BIT, 797 798 /* MUX BITS*/ 799 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 800 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 801 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 802 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 803 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 804 805 /* PATH BITS */ 806 MTK_ETH_PATH_GMAC1_RGMII_BIT, 807 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 808 MTK_ETH_PATH_GMAC1_SGMII_BIT, 809 MTK_ETH_PATH_GMAC2_RGMII_BIT, 810 MTK_ETH_PATH_GMAC2_SGMII_BIT, 811 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 812 MTK_ETH_PATH_GDM1_ESW_BIT, 813 }; 814 815 /* Supported hardware group on SoCs */ 816 #define MTK_RGMII BIT(MTK_RGMII_BIT) 817 #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 818 #define MTK_SGMII BIT(MTK_SGMII_BIT) 819 #define MTK_ESW BIT(MTK_ESW_BIT) 820 #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 821 #define MTK_MUX BIT(MTK_MUX_BIT) 822 #define MTK_INFRA BIT(MTK_INFRA_BIT) 823 #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 824 #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 825 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 826 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 827 #define MTK_QDMA BIT(MTK_QDMA_BIT) 828 #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) 829 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 830 #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) 831 832 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 833 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 834 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 835 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 836 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 837 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 838 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 839 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 840 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 841 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 842 843 /* Supported path present on SoCs */ 844 #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 845 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 846 #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 847 #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 848 #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 849 #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 850 #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 851 852 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 853 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 854 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 855 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 856 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 857 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 858 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 859 860 /* MUXes present on SoCs */ 861 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 862 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 863 864 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 865 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 866 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 867 868 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 869 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 870 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 871 872 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 873 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 874 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 875 MTK_SHARED_SGMII) 876 877 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 878 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 879 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 880 881 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 882 883 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 884 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 885 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 886 887 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 888 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 889 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 890 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 891 892 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 893 MTK_QDMA) 894 895 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 896 897 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 898 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 899 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 900 MTK_MUX_U3_GMAC2_TO_QPHY | \ 901 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 902 903 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 904 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 905 MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) 906 907 struct mtk_tx_dma_desc_info { 908 dma_addr_t addr; 909 u32 size; 910 u16 vlan_tci; 911 u16 qid; 912 u8 gso:1; 913 u8 csum:1; 914 u8 vlan:1; 915 u8 first:1; 916 u8 last:1; 917 }; 918 919 struct mtk_reg_map { 920 u32 tx_irq_mask; 921 u32 tx_irq_status; 922 struct { 923 u32 rx_ptr; /* rx base pointer */ 924 u32 rx_cnt_cfg; /* rx max count configuration */ 925 u32 pcrx_ptr; /* rx cpu pointer */ 926 u32 glo_cfg; /* global configuration */ 927 u32 rst_idx; /* reset index */ 928 u32 delay_irq; /* delay interrupt */ 929 u32 irq_status; /* interrupt status */ 930 u32 irq_mask; /* interrupt mask */ 931 u32 int_grp; 932 } pdma; 933 struct { 934 u32 qtx_cfg; /* tx queue configuration */ 935 u32 rx_ptr; /* rx base pointer */ 936 u32 rx_cnt_cfg; /* rx max count configuration */ 937 u32 qcrx_ptr; /* rx cpu pointer */ 938 u32 glo_cfg; /* global configuration */ 939 u32 rst_idx; /* reset index */ 940 u32 delay_irq; /* delay interrupt */ 941 u32 fc_th; /* flow control */ 942 u32 int_grp; 943 u32 hred; /* interrupt mask */ 944 u32 ctx_ptr; /* tx acquire cpu pointer */ 945 u32 dtx_ptr; /* tx acquire dma pointer */ 946 u32 crx_ptr; /* tx release cpu pointer */ 947 u32 drx_ptr; /* tx release dma pointer */ 948 u32 fq_head; /* fq head pointer */ 949 u32 fq_tail; /* fq tail pointer */ 950 u32 fq_count; /* fq free page count */ 951 u32 fq_blen; /* fq free page buffer length */ 952 } qdma; 953 u32 gdm1_cnt; 954 u32 gdma_to_ppe; 955 u32 ppe_base; 956 u32 wdma_base[2]; 957 }; 958 959 /* struct mtk_eth_data - This is the structure holding all differences 960 * among various plaforms 961 * @reg_map Soc register map. 962 * @ana_rgc3: The offset for register ANA_RGC3 related to 963 * sgmiisys syscon 964 * @caps Flags shown the extra capability for the SoC 965 * @hw_features Flags shown HW features 966 * @required_clks Flags shown the bitmap for required clocks on 967 * the target SoC 968 * @required_pctl A bool value to show whether the SoC requires 969 * the extra setup for those pins used by GMAC. 970 * @hash_offset Flow table hash offset. 971 * @foe_entry_size Foe table entry size. 972 * @txd_size Tx DMA descriptor size. 973 * @rxd_size Rx DMA descriptor size. 974 * @rx_irq_done_mask Rx irq done register mask. 975 * @rx_dma_l4_valid Rx DMA valid register mask. 976 * @dma_max_len Max DMA tx/rx buffer length. 977 * @dma_len_offset Tx/Rx DMA length field offset. 978 */ 979 struct mtk_soc_data { 980 const struct mtk_reg_map *reg_map; 981 u32 ana_rgc3; 982 u32 caps; 983 u32 required_clks; 984 bool required_pctl; 985 u8 offload_version; 986 u8 hash_offset; 987 u16 foe_entry_size; 988 netdev_features_t hw_features; 989 struct { 990 u32 txd_size; 991 u32 rxd_size; 992 u32 rx_irq_done_mask; 993 u32 rx_dma_l4_valid; 994 u32 dma_max_len; 995 u32 dma_len_offset; 996 } txrx; 997 }; 998 999 /* currently no SoC has more than 2 macs */ 1000 #define MTK_MAX_DEVS 2 1001 1002 /* struct mtk_pcs - This structure holds each sgmii regmap and associated 1003 * data 1004 * @regmap: The register map pointing at the range used to setup 1005 * SGMII modes 1006 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 1007 * @pcs: Phylink PCS structure 1008 */ 1009 struct mtk_pcs { 1010 struct regmap *regmap; 1011 u32 ana_rgc3; 1012 struct phylink_pcs pcs; 1013 }; 1014 1015 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 1016 * characteristics 1017 * @pcs Array of individual PCS structures 1018 */ 1019 struct mtk_sgmii { 1020 struct mtk_pcs pcs[MTK_MAX_DEVS]; 1021 }; 1022 1023 /* struct mtk_eth - This is the main datasructure for holding the state 1024 * of the driver 1025 * @dev: The device pointer 1026 * @dev: The device pointer used for dma mapping/alloc 1027 * @base: The mapped register i/o base 1028 * @page_lock: Make sure that register operations are atomic 1029 * @tx_irq__lock: Make sure that IRQ register operations are atomic 1030 * @rx_irq__lock: Make sure that IRQ register operations are atomic 1031 * @dim_lock: Make sure that Net DIM operations are atomic 1032 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 1033 * dummy for NAPI to work 1034 * @netdev: The netdev instances 1035 * @mac: Each netdev is linked to a physical MAC 1036 * @irq: The IRQ that we are using 1037 * @msg_enable: Ethtool msg level 1038 * @ethsys: The register map pointing at the range used to setup 1039 * MII modes 1040 * @infra: The register map pointing at the range used to setup 1041 * SGMII and GePHY path 1042 * @pctl: The register map pointing at the range used to setup 1043 * GMAC port drive/slew values 1044 * @dma_refcnt: track how many netdevs are using the DMA engine 1045 * @tx_ring: Pointer to the memory holding info about the TX ring 1046 * @rx_ring: Pointer to the memory holding info about the RX ring 1047 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 1048 * @tx_napi: The TX NAPI struct 1049 * @rx_napi: The RX NAPI struct 1050 * @rx_events: Net DIM RX event counter 1051 * @rx_packets: Net DIM RX packet counter 1052 * @rx_bytes: Net DIM RX byte counter 1053 * @rx_dim: Net DIM RX context 1054 * @tx_events: Net DIM TX event counter 1055 * @tx_packets: Net DIM TX packet counter 1056 * @tx_bytes: Net DIM TX byte counter 1057 * @tx_dim: Net DIM TX context 1058 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1059 * @phy_scratch_ring: physical address of scratch_ring 1060 * @scratch_head: The scratch memory that scratch_ring points to. 1061 * @clks: clock array for all clocks required 1062 * @mii_bus: If there is a bus we need to create an instance for it 1063 * @pending_work: The workqueue used to reset the dma ring 1064 * @state: Initialization and runtime state of the device 1065 * @soc: Holding specific data among vaious SoCs 1066 */ 1067 1068 struct mtk_eth { 1069 struct device *dev; 1070 struct device *dma_dev; 1071 void __iomem *base; 1072 spinlock_t page_lock; 1073 spinlock_t tx_irq_lock; 1074 spinlock_t rx_irq_lock; 1075 struct net_device dummy_dev; 1076 struct net_device *netdev[MTK_MAX_DEVS]; 1077 struct mtk_mac *mac[MTK_MAX_DEVS]; 1078 int irq[3]; 1079 u32 msg_enable; 1080 unsigned long sysclk; 1081 struct regmap *ethsys; 1082 struct regmap *infra; 1083 struct mtk_sgmii *sgmii; 1084 struct regmap *pctl; 1085 bool hwlro; 1086 refcount_t dma_refcnt; 1087 struct mtk_tx_ring tx_ring; 1088 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 1089 struct mtk_rx_ring rx_ring_qdma; 1090 struct napi_struct tx_napi; 1091 struct napi_struct rx_napi; 1092 void *scratch_ring; 1093 dma_addr_t phy_scratch_ring; 1094 void *scratch_head; 1095 struct clk *clks[MTK_CLK_MAX]; 1096 1097 struct mii_bus *mii_bus; 1098 struct work_struct pending_work; 1099 unsigned long state; 1100 1101 const struct mtk_soc_data *soc; 1102 1103 spinlock_t dim_lock; 1104 1105 u32 rx_events; 1106 u32 rx_packets; 1107 u32 rx_bytes; 1108 struct dim rx_dim; 1109 1110 u32 tx_events; 1111 u32 tx_packets; 1112 u32 tx_bytes; 1113 struct dim tx_dim; 1114 1115 int ip_align; 1116 1117 struct mtk_ppe *ppe[2]; 1118 struct rhashtable flow_table; 1119 1120 struct bpf_prog __rcu *prog; 1121 }; 1122 1123 /* struct mtk_mac - the structure that holds the info about the MACs of the 1124 * SoC 1125 * @id: The number of the MAC 1126 * @interface: Interface mode kept for detecting change in hw settings 1127 * @of_node: Our devicetree node 1128 * @hw: Backpointer to our main datastruture 1129 * @hw_stats: Packet statistics counter 1130 */ 1131 struct mtk_mac { 1132 int id; 1133 phy_interface_t interface; 1134 int speed; 1135 struct device_node *of_node; 1136 struct phylink *phylink; 1137 struct phylink_config phylink_config; 1138 struct mtk_eth *hw; 1139 struct mtk_hw_stats *hw_stats; 1140 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1141 int hwlro_ip_cnt; 1142 unsigned int syscfg0; 1143 }; 1144 1145 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1146 extern const struct of_device_id of_mtk_match[]; 1147 1148 static inline struct mtk_foe_entry * 1149 mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 1150 { 1151 const struct mtk_soc_data *soc = ppe->eth->soc; 1152 1153 return ppe->foe_table + hash * soc->foe_entry_size; 1154 } 1155 1156 static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 1157 { 1158 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1159 return MTK_FOE_IB1_BIND_TIMESTAMP_V2; 1160 1161 return MTK_FOE_IB1_BIND_TIMESTAMP; 1162 } 1163 1164 static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 1165 { 1166 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1167 return MTK_FOE_IB1_BIND_PPPOE_V2; 1168 1169 return MTK_FOE_IB1_BIND_PPPOE; 1170 } 1171 1172 static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 1173 { 1174 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1175 return MTK_FOE_IB1_BIND_VLAN_TAG_V2; 1176 1177 return MTK_FOE_IB1_BIND_VLAN_TAG; 1178 } 1179 1180 static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 1181 { 1182 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1183 return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; 1184 1185 return MTK_FOE_IB1_BIND_VLAN_LAYER; 1186 } 1187 1188 static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1189 { 1190 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1191 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1192 1193 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1194 } 1195 1196 static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1197 { 1198 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1199 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1200 1201 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1202 } 1203 1204 static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 1205 { 1206 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1207 return MTK_FOE_IB1_PACKET_TYPE_V2; 1208 1209 return MTK_FOE_IB1_PACKET_TYPE; 1210 } 1211 1212 static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 1213 { 1214 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1215 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); 1216 1217 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); 1218 } 1219 1220 static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) 1221 { 1222 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1223 return MTK_FOE_IB2_MULTICAST_V2; 1224 1225 return MTK_FOE_IB2_MULTICAST; 1226 } 1227 1228 /* read the hardware status register */ 1229 void mtk_stats_update_mac(struct mtk_mac *mac); 1230 1231 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1232 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1233 1234 struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id); 1235 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 1236 u32 ana_rgc3); 1237 1238 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 1239 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 1240 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 1241 1242 int mtk_eth_offload_init(struct mtk_eth *eth); 1243 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1244 void *type_data); 1245 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1246 1247 1248 #endif /* MTK_ETH_H */ 1249