1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 #include <linux/rhashtable.h> 19 #include <linux/dim.h> 20 #include <linux/bitfield.h> 21 #include <net/page_pool.h> 22 #include <linux/bpf_trace.h> 23 #include "mtk_ppe.h" 24 25 #define MTK_MAX_DSA_PORTS 7 26 #define MTK_DSA_PORT_MASK GENMASK(2, 0) 27 28 #define MTK_QDMA_NUM_QUEUES 16 29 #define MTK_QDMA_PAGE_SIZE 2048 30 #define MTK_MAX_RX_LENGTH 1536 31 #define MTK_MAX_RX_LENGTH_2K 2048 32 #define MTK_TX_DMA_BUF_LEN 0x3fff 33 #define MTK_TX_DMA_BUF_LEN_V2 0xffff 34 #define MTK_QDMA_RING_SIZE 2048 35 #define MTK_DMA_SIZE 512 36 #define MTK_MAC_COUNT 2 37 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 38 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 39 #define MTK_DMA_DUMMY_DESC 0xffffffff 40 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 41 NETIF_MSG_PROBE | \ 42 NETIF_MSG_LINK | \ 43 NETIF_MSG_TIMER | \ 44 NETIF_MSG_IFDOWN | \ 45 NETIF_MSG_IFUP | \ 46 NETIF_MSG_RX_ERR | \ 47 NETIF_MSG_TX_ERR) 48 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 49 NETIF_F_RXCSUM | \ 50 NETIF_F_HW_VLAN_CTAG_TX | \ 51 NETIF_F_HW_VLAN_CTAG_RX | \ 52 NETIF_F_SG | NETIF_F_TSO | \ 53 NETIF_F_TSO6 | \ 54 NETIF_F_IPV6_CSUM |\ 55 NETIF_F_HW_TC) 56 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 57 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 58 59 #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM 60 #define MTK_PP_PAD (MTK_PP_HEADROOM + \ 61 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 62 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD) 63 64 #define MTK_QRX_OFFSET 0x10 65 66 #define MTK_MAX_RX_RING_NUM 4 67 #define MTK_HW_LRO_DMA_SIZE 8 68 69 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 70 #define MTK_MAX_LRO_IP_CNT 2 71 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 72 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 73 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 74 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 75 #define MTK_HW_LRO_MAX_AGG_CNT 64 76 #define MTK_HW_LRO_BW_THRE 3000 77 #define MTK_HW_LRO_REPLACE_DELTA 1000 78 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 79 80 /* Frame Engine Global Reset Register */ 81 #define MTK_RST_GL 0x04 82 #define RST_GL_PSE BIT(0) 83 84 /* Frame Engine Interrupt Status Register */ 85 #define MTK_INT_STATUS2 0x08 86 #define MTK_GDM1_AF BIT(28) 87 #define MTK_GDM2_AF BIT(29) 88 89 /* PDMA HW LRO Alter Flow Timer Register */ 90 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 91 92 /* Frame Engine Interrupt Grouping Register */ 93 #define MTK_FE_INT_GRP 0x20 94 95 /* CDMP Ingress Control Register */ 96 #define MTK_CDMQ_IG_CTRL 0x1400 97 #define MTK_CDMQ_STAG_EN BIT(0) 98 99 /* CDMQ Exgress Control Register */ 100 #define MTK_CDMQ_EG_CTRL 0x1404 101 102 /* CDMP Ingress Control Register */ 103 #define MTK_CDMP_IG_CTRL 0x400 104 #define MTK_CDMP_STAG_EN BIT(0) 105 106 /* CDMP Exgress Control Register */ 107 #define MTK_CDMP_EG_CTRL 0x404 108 109 /* GDM Exgress Control Register */ 110 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 111 #define MTK_GDMA_SPECIAL_TAG BIT(24) 112 #define MTK_GDMA_ICS_EN BIT(22) 113 #define MTK_GDMA_TCS_EN BIT(21) 114 #define MTK_GDMA_UCS_EN BIT(20) 115 #define MTK_GDMA_TO_PDMA 0x0 116 #define MTK_GDMA_DROP_ALL 0x7777 117 118 /* Unicast Filter MAC Address Register - Low */ 119 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 120 121 /* Unicast Filter MAC Address Register - High */ 122 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 123 124 /* FE global misc reg*/ 125 #define MTK_FE_GLO_MISC 0x124 126 127 /* PSE Free Queue Flow Control */ 128 #define PSE_FQFC_CFG1 0x100 129 #define PSE_FQFC_CFG2 0x104 130 #define PSE_DROP_CFG 0x108 131 #define PSE_PPE0_DROP 0x110 132 133 /* PSE Input Queue Reservation Register*/ 134 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 135 136 /* PSE Output Queue Threshold Register*/ 137 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 138 139 /* GDM and CDM Threshold */ 140 #define MTK_GDM2_THRES 0x1530 141 #define MTK_CDMW0_THRES 0x164c 142 #define MTK_CDMW1_THRES 0x1650 143 #define MTK_CDME0_THRES 0x1654 144 #define MTK_CDME1_THRES 0x1658 145 #define MTK_CDMM_THRES 0x165c 146 147 /* PDMA HW LRO Control Registers */ 148 #define MTK_PDMA_LRO_CTRL_DW0 0x980 149 #define MTK_LRO_EN BIT(0) 150 #define MTK_L3_CKS_UPD_EN BIT(7) 151 #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 152 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 153 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 154 #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 155 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 156 #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 157 158 #define MTK_PDMA_LRO_CTRL_DW1 0x984 159 #define MTK_PDMA_LRO_CTRL_DW2 0x988 160 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 161 #define MTK_ADMA_MODE BIT(15) 162 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 163 164 #define MTK_RX_DMA_LRO_EN BIT(8) 165 #define MTK_MULTI_EN BIT(10) 166 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 167 168 /* PDMA Global Configuration Register */ 169 #define MTK_PDMA_LRO_SDL 0x3000 170 #define MTK_RX_CFG_SDL_OFFSET 16 171 172 /* PDMA Reset Index Register */ 173 #define MTK_PST_DRX_IDX0 BIT(16) 174 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 175 176 /* PDMA Delay Interrupt Register */ 177 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 178 #define MTK_PDMA_DELAY_RX_EN BIT(15) 179 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 180 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 181 182 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 183 #define MTK_PDMA_DELAY_TX_EN BIT(31) 184 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 185 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 186 187 #define MTK_PDMA_DELAY_PINT_MASK 0x7f 188 #define MTK_PDMA_DELAY_PTIME_MASK 0xff 189 190 /* PDMA HW LRO Alter Flow Delta Register */ 191 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 192 193 /* PDMA HW LRO IP Setting Registers */ 194 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 195 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 196 #define MTK_RING_MYIP_VLD BIT(9) 197 198 /* PDMA HW LRO Ring Control Registers */ 199 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 200 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 201 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 202 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 203 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 204 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 205 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 206 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 207 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 208 #define MTK_RING_VLD BIT(8) 209 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 210 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 211 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 212 213 /* QDMA TX Queue Configuration Registers */ 214 #define MTK_QTX_OFFSET 0x10 215 #define QDMA_RES_THRES 4 216 217 /* QDMA Tx Queue Scheduler Configuration Registers */ 218 #define MTK_QTX_SCH_TX_SEL BIT(31) 219 #define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30) 220 221 #define MTK_QTX_SCH_LEAKY_BUCKET_EN BIT(30) 222 #define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28) 223 #define MTK_QTX_SCH_MIN_RATE_EN BIT(27) 224 #define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20) 225 #define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16) 226 #define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12) 227 #define MTK_QTX_SCH_MAX_RATE_EN BIT(11) 228 #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4) 229 #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0) 230 231 /* QDMA TX Scheduler Rate Control Register */ 232 #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15) 233 234 /* QDMA Global Configuration Register */ 235 #define MTK_RX_2B_OFFSET BIT(31) 236 #define MTK_RX_BT_32DWORDS (3 << 11) 237 #define MTK_NDP_CO_PRO BIT(10) 238 #define MTK_TX_WB_DDONE BIT(6) 239 #define MTK_TX_BT_32DWORDS (3 << 4) 240 #define MTK_RX_DMA_BUSY BIT(3) 241 #define MTK_TX_DMA_BUSY BIT(1) 242 #define MTK_RX_DMA_EN BIT(2) 243 #define MTK_TX_DMA_EN BIT(0) 244 #define MTK_DMA_BUSY_TIMEOUT_US 1000000 245 246 /* QDMA V2 Global Configuration Register */ 247 #define MTK_CHK_DDONE_EN BIT(28) 248 #define MTK_DMAD_WR_WDONE BIT(26) 249 #define MTK_WCOMP_EN BIT(24) 250 #define MTK_RESV_BUF (0x40 << 16) 251 #define MTK_MUTLI_CNT (0x4 << 12) 252 #define MTK_LEAKY_BUCKET_EN BIT(11) 253 254 /* QDMA Flow Control Register */ 255 #define FC_THRES_DROP_MODE BIT(20) 256 #define FC_THRES_DROP_EN (7 << 16) 257 #define FC_THRES_MIN 0x4444 258 259 /* QDMA Interrupt Status Register */ 260 #define MTK_RX_DONE_DLY BIT(30) 261 #define MTK_TX_DONE_DLY BIT(28) 262 #define MTK_RX_DONE_INT3 BIT(19) 263 #define MTK_RX_DONE_INT2 BIT(18) 264 #define MTK_RX_DONE_INT1 BIT(17) 265 #define MTK_RX_DONE_INT0 BIT(16) 266 #define MTK_TX_DONE_INT3 BIT(3) 267 #define MTK_TX_DONE_INT2 BIT(2) 268 #define MTK_TX_DONE_INT1 BIT(1) 269 #define MTK_TX_DONE_INT0 BIT(0) 270 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 271 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 272 273 #define MTK_RX_DONE_INT_V2 BIT(14) 274 275 /* QDMA Interrupt grouping registers */ 276 #define MTK_RLS_DONE_INT BIT(0) 277 278 #define MTK_STAT_OFFSET 0x40 279 280 /* QDMA TX NUM */ 281 #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 282 #define MTK_QDMA_GMAC2_QID 8 283 284 #define MTK_TX_DMA_BUF_SHIFT 8 285 286 /* QDMA V2 descriptor txd6 */ 287 #define TX_DMA_INS_VLAN_V2 BIT(16) 288 /* QDMA V2 descriptor txd5 */ 289 #define TX_DMA_CHKSUM_V2 (0x7 << 28) 290 #define TX_DMA_TSO_V2 BIT(31) 291 292 /* QDMA V2 descriptor txd4 */ 293 #define TX_DMA_FPORT_SHIFT_V2 8 294 #define TX_DMA_FPORT_MASK_V2 0xf 295 #define TX_DMA_SWC_V2 BIT(30) 296 297 /* QDMA descriptor txd4 */ 298 #define TX_DMA_CHKSUM (0x7 << 29) 299 #define TX_DMA_TSO BIT(28) 300 #define TX_DMA_FPORT_SHIFT 25 301 #define TX_DMA_FPORT_MASK 0x7 302 #define TX_DMA_INS_VLAN BIT(16) 303 304 /* QDMA descriptor txd3 */ 305 #define TX_DMA_OWNER_CPU BIT(31) 306 #define TX_DMA_LS0 BIT(30) 307 #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 308 #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) 309 #define TX_DMA_SWC BIT(14) 310 #define TX_DMA_PQID GENMASK(3, 0) 311 312 /* PDMA on MT7628 */ 313 #define TX_DMA_DONE BIT(31) 314 #define TX_DMA_LS1 BIT(14) 315 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 316 317 /* QDMA descriptor rxd2 */ 318 #define RX_DMA_DONE BIT(31) 319 #define RX_DMA_LSO BIT(30) 320 #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 321 #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) 322 #define RX_DMA_VTAG BIT(15) 323 324 /* QDMA descriptor rxd3 */ 325 #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 326 #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 327 #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 328 329 /* QDMA descriptor rxd4 */ 330 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 331 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 332 #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 333 #define MTK_RXD4_ALG GENMASK(31, 22) 334 335 /* QDMA descriptor rxd4 */ 336 #define RX_DMA_L4_VALID BIT(24) 337 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 338 #define RX_DMA_SPECIAL_TAG BIT(22) 339 340 /* PDMA descriptor rxd5 */ 341 #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) 342 #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) 343 #define MTK_RXD5_SRC_PORT GENMASK(29, 26) 344 345 #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7) 346 #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf) 347 348 /* PDMA V2 descriptor rxd3 */ 349 #define RX_DMA_VTAG_V2 BIT(0) 350 #define RX_DMA_L4_VALID_V2 BIT(2) 351 352 /* PHY Indirect Access Control registers */ 353 #define MTK_PHY_IAC 0x10004 354 #define PHY_IAC_ACCESS BIT(31) 355 #define PHY_IAC_REG_MASK GENMASK(29, 25) 356 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 357 #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 358 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 359 #define PHY_IAC_CMD_MASK GENMASK(19, 18) 360 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 361 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 362 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 363 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 364 #define PHY_IAC_START_MASK GENMASK(17, 16) 365 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 366 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 367 #define PHY_IAC_DATA_MASK GENMASK(15, 0) 368 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 369 #define PHY_IAC_TIMEOUT HZ 370 371 #define MTK_MAC_MISC 0x1000c 372 #define MTK_MUX_TO_ESW BIT(0) 373 374 /* Mac control registers */ 375 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 376 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 377 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 378 #define MAC_MCR_MAX_RX_1518 0x0 379 #define MAC_MCR_MAX_RX_1536 0x1 380 #define MAC_MCR_MAX_RX_1552 0x2 381 #define MAC_MCR_MAX_RX_2048 0x3 382 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 383 #define MAC_MCR_FORCE_MODE BIT(15) 384 #define MAC_MCR_TX_EN BIT(14) 385 #define MAC_MCR_RX_EN BIT(13) 386 #define MAC_MCR_BACKOFF_EN BIT(9) 387 #define MAC_MCR_BACKPR_EN BIT(8) 388 #define MAC_MCR_FORCE_RX_FC BIT(5) 389 #define MAC_MCR_FORCE_TX_FC BIT(4) 390 #define MAC_MCR_SPEED_1000 BIT(3) 391 #define MAC_MCR_SPEED_100 BIT(2) 392 #define MAC_MCR_FORCE_DPX BIT(1) 393 #define MAC_MCR_FORCE_LINK BIT(0) 394 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 395 396 /* Mac status registers */ 397 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 398 #define MAC_MSR_EEE1G BIT(7) 399 #define MAC_MSR_EEE100M BIT(6) 400 #define MAC_MSR_RX_FC BIT(5) 401 #define MAC_MSR_TX_FC BIT(4) 402 #define MAC_MSR_SPEED_1000 BIT(3) 403 #define MAC_MSR_SPEED_100 BIT(2) 404 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 405 #define MAC_MSR_DPX BIT(1) 406 #define MAC_MSR_LINK BIT(0) 407 408 /* TRGMII RXC control register */ 409 #define TRGMII_RCK_CTRL 0x10300 410 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 411 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 412 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 413 #define RXC_RST BIT(31) 414 #define RXC_DQSISEL BIT(30) 415 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 416 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 417 418 #define NUM_TRGMII_CTRL 5 419 420 /* TRGMII RXC control register */ 421 #define TRGMII_TCK_CTRL 0x10340 422 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 423 #define TXC_INV BIT(30) 424 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 425 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 426 427 /* TRGMII TX Drive Strength */ 428 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 429 #define TD_DM_DRVP(x) ((x) & 0xf) 430 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 431 432 /* TRGMII Interface mode register */ 433 #define INTF_MODE 0x10390 434 #define TRGMII_INTF_DIS BIT(0) 435 #define TRGMII_MODE BIT(1) 436 #define TRGMII_CENTRAL_ALIGNED BIT(2) 437 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 438 #define INTF_MODE_RGMII_10_100 0 439 440 /* GPIO port control registers for GMAC 2*/ 441 #define GPIO_OD33_CTRL8 0x4c0 442 #define GPIO_BIAS_CTRL 0xed0 443 #define GPIO_DRV_SEL10 0xf00 444 445 /* ethernet subsystem chip id register */ 446 #define ETHSYS_CHIPID0_3 0x0 447 #define ETHSYS_CHIPID4_7 0x4 448 #define MT7623_ETH 7623 449 #define MT7622_ETH 7622 450 #define MT7621_ETH 7621 451 452 /* ethernet system control register */ 453 #define ETHSYS_SYSCFG 0x10 454 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 455 456 /* ethernet subsystem config register */ 457 #define ETHSYS_SYSCFG0 0x14 458 #define SYSCFG0_GE_MASK 0x3 459 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 460 #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 461 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 462 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 463 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 464 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 465 466 467 /* ethernet subsystem clock register */ 468 #define ETHSYS_CLKCFG0 0x2c 469 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 470 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 471 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 472 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 473 474 /* ethernet reset control register */ 475 #define ETHSYS_RSTCTRL 0x34 476 #define RSTCTRL_FE BIT(6) 477 #define RSTCTRL_PPE0 BIT(31) 478 #define RSTCTRL_PPE0_V2 BIT(30) 479 #define RSTCTRL_PPE1 BIT(31) 480 #define RSTCTRL_ETH BIT(23) 481 482 /* ethernet reset check idle register */ 483 #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 484 485 /* ethernet dma channel agent map */ 486 #define ETHSYS_DMA_AG_MAP 0x408 487 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 488 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 489 #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 490 491 /* SGMII subsystem config registers */ 492 /* BMCR (low 16) BMSR (high 16) */ 493 #define SGMSYS_PCS_CONTROL_1 0x0 494 #define SGMII_BMCR GENMASK(15, 0) 495 #define SGMII_BMSR GENMASK(31, 16) 496 #define SGMII_AN_RESTART BIT(9) 497 #define SGMII_ISOLATE BIT(10) 498 #define SGMII_AN_ENABLE BIT(12) 499 #define SGMII_LINK_STATYS BIT(18) 500 #define SGMII_AN_ABILITY BIT(19) 501 #define SGMII_AN_COMPLETE BIT(21) 502 #define SGMII_PCS_FAULT BIT(23) 503 #define SGMII_AN_EXPANSION_CLR BIT(30) 504 505 #define SGMSYS_PCS_ADVERTISE 0x8 506 #define SGMII_ADVERTISE GENMASK(15, 0) 507 #define SGMII_LPA GENMASK(31, 16) 508 509 /* Register to programmable link timer, the unit in 2 * 8ns */ 510 #define SGMSYS_PCS_LINK_TIMER 0x18 511 #define SGMII_LINK_TIMER_MASK GENMASK(19, 0) 512 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & SGMII_LINK_TIMER_MASK) 513 514 /* Register to control remote fault */ 515 #define SGMSYS_SGMII_MODE 0x20 516 #define SGMII_IF_MODE_SGMII BIT(0) 517 #define SGMII_SPEED_DUPLEX_AN BIT(1) 518 #define SGMII_SPEED_MASK GENMASK(3, 2) 519 #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) 520 #define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) 521 #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) 522 #define SGMII_DUPLEX_FULL BIT(4) 523 #define SGMII_IF_MODE_BIT5 BIT(5) 524 #define SGMII_REMOTE_FAULT_DIS BIT(8) 525 #define SGMII_CODE_SYNC_SET_VAL BIT(9) 526 #define SGMII_CODE_SYNC_SET_EN BIT(10) 527 #define SGMII_SEND_AN_ERROR_EN BIT(11) 528 #define SGMII_IF_MODE_MASK GENMASK(5, 1) 529 530 /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 531 #define SGMSYS_ANA_RG_CS3 0x2028 532 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 533 #define RG_PHY_SPEED_1_25G 0x0 534 #define RG_PHY_SPEED_3_125G BIT(2) 535 536 /* Register to power up QPHY */ 537 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 538 #define SGMII_PHYA_PWD BIT(4) 539 540 /* Infrasys subsystem config registers */ 541 #define INFRA_MISC2 0x70c 542 #define CO_QPHY_SEL BIT(0) 543 #define GEPHY_MAC_SEL BIT(1) 544 545 /* MT7628/88 specific stuff */ 546 #define MT7628_PDMA_OFFSET 0x0800 547 #define MT7628_SDM_OFFSET 0x0c00 548 549 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 550 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 551 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 552 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 553 #define MT7628_PST_DTX_IDX0 BIT(0) 554 555 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 556 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 557 558 /* Counter / stat register */ 559 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 560 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 561 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 562 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 563 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 564 565 struct mtk_rx_dma { 566 unsigned int rxd1; 567 unsigned int rxd2; 568 unsigned int rxd3; 569 unsigned int rxd4; 570 } __packed __aligned(4); 571 572 struct mtk_rx_dma_v2 { 573 unsigned int rxd1; 574 unsigned int rxd2; 575 unsigned int rxd3; 576 unsigned int rxd4; 577 unsigned int rxd5; 578 unsigned int rxd6; 579 unsigned int rxd7; 580 unsigned int rxd8; 581 } __packed __aligned(4); 582 583 struct mtk_tx_dma { 584 unsigned int txd1; 585 unsigned int txd2; 586 unsigned int txd3; 587 unsigned int txd4; 588 } __packed __aligned(4); 589 590 struct mtk_tx_dma_v2 { 591 unsigned int txd1; 592 unsigned int txd2; 593 unsigned int txd3; 594 unsigned int txd4; 595 unsigned int txd5; 596 unsigned int txd6; 597 unsigned int txd7; 598 unsigned int txd8; 599 } __packed __aligned(4); 600 601 struct mtk_eth; 602 struct mtk_mac; 603 604 struct mtk_xdp_stats { 605 u64 rx_xdp_redirect; 606 u64 rx_xdp_pass; 607 u64 rx_xdp_drop; 608 u64 rx_xdp_tx; 609 u64 rx_xdp_tx_errors; 610 u64 tx_xdp_xmit; 611 u64 tx_xdp_xmit_errors; 612 }; 613 614 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 615 * @stats_lock: make sure that stats operations are atomic 616 * @reg_offset: the status register offset of the SoC 617 * @syncp: the refcount 618 * 619 * All of the supported SoCs have hardware counters for traffic statistics. 620 * Whenever the status IRQ triggers we can read the latest stats from these 621 * counters and store them in this struct. 622 */ 623 struct mtk_hw_stats { 624 u64 tx_bytes; 625 u64 tx_packets; 626 u64 tx_skip; 627 u64 tx_collisions; 628 u64 rx_bytes; 629 u64 rx_packets; 630 u64 rx_overflow; 631 u64 rx_fcs_errors; 632 u64 rx_short_errors; 633 u64 rx_long_errors; 634 u64 rx_checksum_errors; 635 u64 rx_flow_control_packets; 636 637 struct mtk_xdp_stats xdp_stats; 638 639 spinlock_t stats_lock; 640 u32 reg_offset; 641 struct u64_stats_sync syncp; 642 }; 643 644 enum mtk_tx_flags { 645 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 646 * track how memory was allocated so that it can be freed properly. 647 */ 648 MTK_TX_FLAGS_SINGLE0 = 0x01, 649 MTK_TX_FLAGS_PAGE0 = 0x02, 650 651 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 652 * SKB out instead of looking up through hardware TX descriptor. 653 */ 654 MTK_TX_FLAGS_FPORT0 = 0x04, 655 MTK_TX_FLAGS_FPORT1 = 0x08, 656 }; 657 658 /* This enum allows us to identify how the clock is defined on the array of the 659 * clock in the order 660 */ 661 enum mtk_clks_map { 662 MTK_CLK_ETHIF, 663 MTK_CLK_SGMIITOP, 664 MTK_CLK_ESW, 665 MTK_CLK_GP0, 666 MTK_CLK_GP1, 667 MTK_CLK_GP2, 668 MTK_CLK_FE, 669 MTK_CLK_TRGPLL, 670 MTK_CLK_SGMII_TX_250M, 671 MTK_CLK_SGMII_RX_250M, 672 MTK_CLK_SGMII_CDR_REF, 673 MTK_CLK_SGMII_CDR_FB, 674 MTK_CLK_SGMII2_TX_250M, 675 MTK_CLK_SGMII2_RX_250M, 676 MTK_CLK_SGMII2_CDR_REF, 677 MTK_CLK_SGMII2_CDR_FB, 678 MTK_CLK_SGMII_CK, 679 MTK_CLK_ETH2PLL, 680 MTK_CLK_WOCPU0, 681 MTK_CLK_WOCPU1, 682 MTK_CLK_NETSYS0, 683 MTK_CLK_NETSYS1, 684 MTK_CLK_MAX 685 }; 686 687 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 688 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 689 BIT(MTK_CLK_TRGPLL)) 690 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 691 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 692 BIT(MTK_CLK_GP2) | \ 693 BIT(MTK_CLK_SGMII_TX_250M) | \ 694 BIT(MTK_CLK_SGMII_RX_250M) | \ 695 BIT(MTK_CLK_SGMII_CDR_REF) | \ 696 BIT(MTK_CLK_SGMII_CDR_FB) | \ 697 BIT(MTK_CLK_SGMII_CK) | \ 698 BIT(MTK_CLK_ETH2PLL)) 699 #define MT7621_CLKS_BITMAP (0) 700 #define MT7628_CLKS_BITMAP (0) 701 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 702 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 703 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 704 BIT(MTK_CLK_SGMII_TX_250M) | \ 705 BIT(MTK_CLK_SGMII_RX_250M) | \ 706 BIT(MTK_CLK_SGMII_CDR_REF) | \ 707 BIT(MTK_CLK_SGMII_CDR_FB) | \ 708 BIT(MTK_CLK_SGMII2_TX_250M) | \ 709 BIT(MTK_CLK_SGMII2_RX_250M) | \ 710 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 711 BIT(MTK_CLK_SGMII2_CDR_FB) | \ 712 BIT(MTK_CLK_SGMII_CK) | \ 713 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 714 #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ 715 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ 716 BIT(MTK_CLK_SGMII_TX_250M) | \ 717 BIT(MTK_CLK_SGMII_RX_250M) | \ 718 BIT(MTK_CLK_SGMII_CDR_REF) | \ 719 BIT(MTK_CLK_SGMII_CDR_FB) | \ 720 BIT(MTK_CLK_SGMII2_TX_250M) | \ 721 BIT(MTK_CLK_SGMII2_RX_250M) | \ 722 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 723 BIT(MTK_CLK_SGMII2_CDR_FB)) 724 725 enum mtk_dev_state { 726 MTK_HW_INIT, 727 MTK_RESETTING 728 }; 729 730 enum mtk_tx_buf_type { 731 MTK_TYPE_SKB, 732 MTK_TYPE_XDP_TX, 733 MTK_TYPE_XDP_NDO, 734 }; 735 736 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 737 * by the TX descriptor s 738 * @skb: The SKB pointer of the packet being sent 739 * @dma_addr0: The base addr of the first segment 740 * @dma_len0: The length of the first segment 741 * @dma_addr1: The base addr of the second segment 742 * @dma_len1: The length of the second segment 743 */ 744 struct mtk_tx_buf { 745 enum mtk_tx_buf_type type; 746 void *data; 747 748 u32 flags; 749 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 750 DEFINE_DMA_UNMAP_LEN(dma_len0); 751 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 752 DEFINE_DMA_UNMAP_LEN(dma_len1); 753 }; 754 755 /* struct mtk_tx_ring - This struct holds info describing a TX ring 756 * @dma: The descriptor ring 757 * @buf: The memory pointed at by the ring 758 * @phys: The physical addr of tx_buf 759 * @next_free: Pointer to the next free descriptor 760 * @last_free: Pointer to the last free descriptor 761 * @last_free_ptr: Hardware pointer value of the last free descriptor 762 * @thresh: The threshold of minimum amount of free descriptors 763 * @free_count: QDMA uses a linked list. Track how many free descriptors 764 * are present 765 */ 766 struct mtk_tx_ring { 767 void *dma; 768 struct mtk_tx_buf *buf; 769 dma_addr_t phys; 770 struct mtk_tx_dma *next_free; 771 struct mtk_tx_dma *last_free; 772 u32 last_free_ptr; 773 u16 thresh; 774 atomic_t free_count; 775 int dma_size; 776 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 777 dma_addr_t phys_pdma; 778 int cpu_idx; 779 }; 780 781 /* PDMA rx ring mode */ 782 enum mtk_rx_flags { 783 MTK_RX_FLAGS_NORMAL = 0, 784 MTK_RX_FLAGS_HWLRO, 785 MTK_RX_FLAGS_QDMA, 786 }; 787 788 /* struct mtk_rx_ring - This struct holds info describing a RX ring 789 * @dma: The descriptor ring 790 * @data: The memory pointed at by the ring 791 * @phys: The physical addr of rx_buf 792 * @frag_size: How big can each fragment be 793 * @buf_size: The size of each packet buffer 794 * @calc_idx: The current head of ring 795 */ 796 struct mtk_rx_ring { 797 void *dma; 798 u8 **data; 799 dma_addr_t phys; 800 u16 frag_size; 801 u16 buf_size; 802 u16 dma_size; 803 bool calc_idx_update; 804 u16 calc_idx; 805 u32 crx_idx_reg; 806 /* page_pool */ 807 struct page_pool *page_pool; 808 struct xdp_rxq_info xdp_q; 809 }; 810 811 enum mkt_eth_capabilities { 812 MTK_RGMII_BIT = 0, 813 MTK_TRGMII_BIT, 814 MTK_SGMII_BIT, 815 MTK_ESW_BIT, 816 MTK_GEPHY_BIT, 817 MTK_MUX_BIT, 818 MTK_INFRA_BIT, 819 MTK_SHARED_SGMII_BIT, 820 MTK_HWLRO_BIT, 821 MTK_SHARED_INT_BIT, 822 MTK_TRGMII_MT7621_CLK_BIT, 823 MTK_QDMA_BIT, 824 MTK_NETSYS_V2_BIT, 825 MTK_SOC_MT7628_BIT, 826 MTK_RSTCTRL_PPE1_BIT, 827 828 /* MUX BITS*/ 829 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 830 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 831 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 832 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 833 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 834 835 /* PATH BITS */ 836 MTK_ETH_PATH_GMAC1_RGMII_BIT, 837 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 838 MTK_ETH_PATH_GMAC1_SGMII_BIT, 839 MTK_ETH_PATH_GMAC2_RGMII_BIT, 840 MTK_ETH_PATH_GMAC2_SGMII_BIT, 841 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 842 MTK_ETH_PATH_GDM1_ESW_BIT, 843 }; 844 845 /* Supported hardware group on SoCs */ 846 #define MTK_RGMII BIT(MTK_RGMII_BIT) 847 #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 848 #define MTK_SGMII BIT(MTK_SGMII_BIT) 849 #define MTK_ESW BIT(MTK_ESW_BIT) 850 #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 851 #define MTK_MUX BIT(MTK_MUX_BIT) 852 #define MTK_INFRA BIT(MTK_INFRA_BIT) 853 #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 854 #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 855 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 856 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 857 #define MTK_QDMA BIT(MTK_QDMA_BIT) 858 #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) 859 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 860 #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) 861 862 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 863 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 864 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 865 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 866 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 867 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 868 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 869 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 870 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 871 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 872 873 /* Supported path present on SoCs */ 874 #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 875 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 876 #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 877 #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 878 #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 879 #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 880 #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 881 882 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 883 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 884 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 885 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 886 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 887 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 888 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 889 890 /* MUXes present on SoCs */ 891 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 892 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 893 894 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 895 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 896 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 897 898 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 899 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 900 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 901 902 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 903 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 904 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 905 MTK_SHARED_SGMII) 906 907 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 908 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 909 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 910 911 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 912 913 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 914 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 915 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 916 917 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 918 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 919 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 920 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 921 922 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 923 MTK_QDMA) 924 925 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 926 927 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 928 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 929 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 930 MTK_MUX_U3_GMAC2_TO_QPHY | \ 931 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 932 933 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 934 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 935 MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) 936 937 struct mtk_tx_dma_desc_info { 938 dma_addr_t addr; 939 u32 size; 940 u16 vlan_tci; 941 u16 qid; 942 u8 gso:1; 943 u8 csum:1; 944 u8 vlan:1; 945 u8 first:1; 946 u8 last:1; 947 }; 948 949 struct mtk_reg_map { 950 u32 tx_irq_mask; 951 u32 tx_irq_status; 952 struct { 953 u32 rx_ptr; /* rx base pointer */ 954 u32 rx_cnt_cfg; /* rx max count configuration */ 955 u32 pcrx_ptr; /* rx cpu pointer */ 956 u32 glo_cfg; /* global configuration */ 957 u32 rst_idx; /* reset index */ 958 u32 delay_irq; /* delay interrupt */ 959 u32 irq_status; /* interrupt status */ 960 u32 irq_mask; /* interrupt mask */ 961 u32 int_grp; 962 } pdma; 963 struct { 964 u32 qtx_cfg; /* tx queue configuration */ 965 u32 qtx_sch; /* tx queue scheduler configuration */ 966 u32 rx_ptr; /* rx base pointer */ 967 u32 rx_cnt_cfg; /* rx max count configuration */ 968 u32 qcrx_ptr; /* rx cpu pointer */ 969 u32 glo_cfg; /* global configuration */ 970 u32 rst_idx; /* reset index */ 971 u32 delay_irq; /* delay interrupt */ 972 u32 fc_th; /* flow control */ 973 u32 int_grp; 974 u32 hred; /* interrupt mask */ 975 u32 ctx_ptr; /* tx acquire cpu pointer */ 976 u32 dtx_ptr; /* tx acquire dma pointer */ 977 u32 crx_ptr; /* tx release cpu pointer */ 978 u32 drx_ptr; /* tx release dma pointer */ 979 u32 fq_head; /* fq head pointer */ 980 u32 fq_tail; /* fq tail pointer */ 981 u32 fq_count; /* fq free page count */ 982 u32 fq_blen; /* fq free page buffer length */ 983 u32 tx_sch_rate; /* tx scheduler rate control registers */ 984 } qdma; 985 u32 gdm1_cnt; 986 u32 gdma_to_ppe; 987 u32 ppe_base; 988 u32 wdma_base[2]; 989 }; 990 991 /* struct mtk_eth_data - This is the structure holding all differences 992 * among various plaforms 993 * @reg_map Soc register map. 994 * @ana_rgc3: The offset for register ANA_RGC3 related to 995 * sgmiisys syscon 996 * @caps Flags shown the extra capability for the SoC 997 * @hw_features Flags shown HW features 998 * @required_clks Flags shown the bitmap for required clocks on 999 * the target SoC 1000 * @required_pctl A bool value to show whether the SoC requires 1001 * the extra setup for those pins used by GMAC. 1002 * @hash_offset Flow table hash offset. 1003 * @foe_entry_size Foe table entry size. 1004 * @txd_size Tx DMA descriptor size. 1005 * @rxd_size Rx DMA descriptor size. 1006 * @rx_irq_done_mask Rx irq done register mask. 1007 * @rx_dma_l4_valid Rx DMA valid register mask. 1008 * @dma_max_len Max DMA tx/rx buffer length. 1009 * @dma_len_offset Tx/Rx DMA length field offset. 1010 */ 1011 struct mtk_soc_data { 1012 const struct mtk_reg_map *reg_map; 1013 u32 ana_rgc3; 1014 u32 caps; 1015 u32 required_clks; 1016 bool required_pctl; 1017 u8 offload_version; 1018 u8 hash_offset; 1019 u16 foe_entry_size; 1020 netdev_features_t hw_features; 1021 struct { 1022 u32 txd_size; 1023 u32 rxd_size; 1024 u32 rx_irq_done_mask; 1025 u32 rx_dma_l4_valid; 1026 u32 dma_max_len; 1027 u32 dma_len_offset; 1028 } txrx; 1029 }; 1030 1031 /* currently no SoC has more than 2 macs */ 1032 #define MTK_MAX_DEVS 2 1033 1034 /* struct mtk_pcs - This structure holds each sgmii regmap and associated 1035 * data 1036 * @regmap: The register map pointing at the range used to setup 1037 * SGMII modes 1038 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 1039 * @pcs: Phylink PCS structure 1040 */ 1041 struct mtk_pcs { 1042 struct regmap *regmap; 1043 u32 ana_rgc3; 1044 struct phylink_pcs pcs; 1045 }; 1046 1047 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 1048 * characteristics 1049 * @pcs Array of individual PCS structures 1050 */ 1051 struct mtk_sgmii { 1052 struct mtk_pcs pcs[MTK_MAX_DEVS]; 1053 }; 1054 1055 /* struct mtk_eth - This is the main datasructure for holding the state 1056 * of the driver 1057 * @dev: The device pointer 1058 * @dev: The device pointer used for dma mapping/alloc 1059 * @base: The mapped register i/o base 1060 * @page_lock: Make sure that register operations are atomic 1061 * @tx_irq__lock: Make sure that IRQ register operations are atomic 1062 * @rx_irq__lock: Make sure that IRQ register operations are atomic 1063 * @dim_lock: Make sure that Net DIM operations are atomic 1064 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 1065 * dummy for NAPI to work 1066 * @netdev: The netdev instances 1067 * @mac: Each netdev is linked to a physical MAC 1068 * @irq: The IRQ that we are using 1069 * @msg_enable: Ethtool msg level 1070 * @ethsys: The register map pointing at the range used to setup 1071 * MII modes 1072 * @infra: The register map pointing at the range used to setup 1073 * SGMII and GePHY path 1074 * @pctl: The register map pointing at the range used to setup 1075 * GMAC port drive/slew values 1076 * @dma_refcnt: track how many netdevs are using the DMA engine 1077 * @tx_ring: Pointer to the memory holding info about the TX ring 1078 * @rx_ring: Pointer to the memory holding info about the RX ring 1079 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 1080 * @tx_napi: The TX NAPI struct 1081 * @rx_napi: The RX NAPI struct 1082 * @rx_events: Net DIM RX event counter 1083 * @rx_packets: Net DIM RX packet counter 1084 * @rx_bytes: Net DIM RX byte counter 1085 * @rx_dim: Net DIM RX context 1086 * @tx_events: Net DIM TX event counter 1087 * @tx_packets: Net DIM TX packet counter 1088 * @tx_bytes: Net DIM TX byte counter 1089 * @tx_dim: Net DIM TX context 1090 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1091 * @phy_scratch_ring: physical address of scratch_ring 1092 * @scratch_head: The scratch memory that scratch_ring points to. 1093 * @clks: clock array for all clocks required 1094 * @mii_bus: If there is a bus we need to create an instance for it 1095 * @pending_work: The workqueue used to reset the dma ring 1096 * @state: Initialization and runtime state of the device 1097 * @soc: Holding specific data among vaious SoCs 1098 */ 1099 1100 struct mtk_eth { 1101 struct device *dev; 1102 struct device *dma_dev; 1103 void __iomem *base; 1104 spinlock_t page_lock; 1105 spinlock_t tx_irq_lock; 1106 spinlock_t rx_irq_lock; 1107 struct net_device dummy_dev; 1108 struct net_device *netdev[MTK_MAX_DEVS]; 1109 struct mtk_mac *mac[MTK_MAX_DEVS]; 1110 int irq[3]; 1111 u32 msg_enable; 1112 unsigned long sysclk; 1113 struct regmap *ethsys; 1114 struct regmap *infra; 1115 struct mtk_sgmii *sgmii; 1116 struct regmap *pctl; 1117 bool hwlro; 1118 refcount_t dma_refcnt; 1119 struct mtk_tx_ring tx_ring; 1120 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 1121 struct mtk_rx_ring rx_ring_qdma; 1122 struct napi_struct tx_napi; 1123 struct napi_struct rx_napi; 1124 void *scratch_ring; 1125 dma_addr_t phy_scratch_ring; 1126 void *scratch_head; 1127 struct clk *clks[MTK_CLK_MAX]; 1128 1129 struct mii_bus *mii_bus; 1130 struct work_struct pending_work; 1131 unsigned long state; 1132 1133 const struct mtk_soc_data *soc; 1134 1135 spinlock_t dim_lock; 1136 1137 u32 rx_events; 1138 u32 rx_packets; 1139 u32 rx_bytes; 1140 struct dim rx_dim; 1141 1142 u32 tx_events; 1143 u32 tx_packets; 1144 u32 tx_bytes; 1145 struct dim tx_dim; 1146 1147 int ip_align; 1148 1149 struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS]; 1150 1151 struct mtk_ppe *ppe[2]; 1152 struct rhashtable flow_table; 1153 1154 struct bpf_prog __rcu *prog; 1155 }; 1156 1157 /* struct mtk_mac - the structure that holds the info about the MACs of the 1158 * SoC 1159 * @id: The number of the MAC 1160 * @interface: Interface mode kept for detecting change in hw settings 1161 * @of_node: Our devicetree node 1162 * @hw: Backpointer to our main datastruture 1163 * @hw_stats: Packet statistics counter 1164 */ 1165 struct mtk_mac { 1166 int id; 1167 phy_interface_t interface; 1168 int speed; 1169 struct device_node *of_node; 1170 struct phylink *phylink; 1171 struct phylink_config phylink_config; 1172 struct mtk_eth *hw; 1173 struct mtk_hw_stats *hw_stats; 1174 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1175 int hwlro_ip_cnt; 1176 unsigned int syscfg0; 1177 struct notifier_block device_notifier; 1178 }; 1179 1180 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1181 extern const struct of_device_id of_mtk_match[]; 1182 1183 static inline struct mtk_foe_entry * 1184 mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 1185 { 1186 const struct mtk_soc_data *soc = ppe->eth->soc; 1187 1188 return ppe->foe_table + hash * soc->foe_entry_size; 1189 } 1190 1191 static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 1192 { 1193 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1194 return MTK_FOE_IB1_BIND_TIMESTAMP_V2; 1195 1196 return MTK_FOE_IB1_BIND_TIMESTAMP; 1197 } 1198 1199 static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 1200 { 1201 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1202 return MTK_FOE_IB1_BIND_PPPOE_V2; 1203 1204 return MTK_FOE_IB1_BIND_PPPOE; 1205 } 1206 1207 static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 1208 { 1209 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1210 return MTK_FOE_IB1_BIND_VLAN_TAG_V2; 1211 1212 return MTK_FOE_IB1_BIND_VLAN_TAG; 1213 } 1214 1215 static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 1216 { 1217 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1218 return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; 1219 1220 return MTK_FOE_IB1_BIND_VLAN_LAYER; 1221 } 1222 1223 static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1224 { 1225 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1226 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1227 1228 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1229 } 1230 1231 static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1232 { 1233 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1234 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1235 1236 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1237 } 1238 1239 static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 1240 { 1241 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1242 return MTK_FOE_IB1_PACKET_TYPE_V2; 1243 1244 return MTK_FOE_IB1_PACKET_TYPE; 1245 } 1246 1247 static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 1248 { 1249 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1250 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); 1251 1252 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); 1253 } 1254 1255 static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) 1256 { 1257 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1258 return MTK_FOE_IB2_MULTICAST_V2; 1259 1260 return MTK_FOE_IB2_MULTICAST; 1261 } 1262 1263 /* read the hardware status register */ 1264 void mtk_stats_update_mac(struct mtk_mac *mac); 1265 1266 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1267 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1268 1269 struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id); 1270 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 1271 u32 ana_rgc3); 1272 1273 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 1274 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 1275 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 1276 1277 int mtk_eth_offload_init(struct mtk_eth *eth); 1278 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1279 void *type_data); 1280 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1281 1282 1283 #endif /* MTK_ETH_H */ 1284