1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 19 #define MTK_QDMA_PAGE_SIZE 2048 20 #define MTK_MAX_RX_LENGTH 1536 21 #define MTK_MAX_RX_LENGTH_2K 2048 22 #define MTK_TX_DMA_BUF_LEN 0x3fff 23 #define MTK_DMA_SIZE 256 24 #define MTK_NAPI_WEIGHT 64 25 #define MTK_MAC_COUNT 2 26 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 27 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 28 #define MTK_DMA_DUMMY_DESC 0xffffffff 29 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 30 NETIF_MSG_PROBE | \ 31 NETIF_MSG_LINK | \ 32 NETIF_MSG_TIMER | \ 33 NETIF_MSG_IFDOWN | \ 34 NETIF_MSG_IFUP | \ 35 NETIF_MSG_RX_ERR | \ 36 NETIF_MSG_TX_ERR) 37 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 38 NETIF_F_RXCSUM | \ 39 NETIF_F_HW_VLAN_CTAG_TX | \ 40 NETIF_F_HW_VLAN_CTAG_RX | \ 41 NETIF_F_SG | NETIF_F_TSO | \ 42 NETIF_F_TSO6 | \ 43 NETIF_F_IPV6_CSUM) 44 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 45 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 46 47 #define MTK_MAX_RX_RING_NUM 4 48 #define MTK_HW_LRO_DMA_SIZE 8 49 50 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 51 #define MTK_MAX_LRO_IP_CNT 2 52 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 53 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 54 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 55 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 56 #define MTK_HW_LRO_MAX_AGG_CNT 64 57 #define MTK_HW_LRO_BW_THRE 3000 58 #define MTK_HW_LRO_REPLACE_DELTA 1000 59 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 60 61 /* Frame Engine Global Reset Register */ 62 #define MTK_RST_GL 0x04 63 #define RST_GL_PSE BIT(0) 64 65 /* Frame Engine Interrupt Status Register */ 66 #define MTK_INT_STATUS2 0x08 67 #define MTK_GDM1_AF BIT(28) 68 #define MTK_GDM2_AF BIT(29) 69 70 /* PDMA HW LRO Alter Flow Timer Register */ 71 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 72 73 /* Frame Engine Interrupt Grouping Register */ 74 #define MTK_FE_INT_GRP 0x20 75 76 /* CDMP Ingress Control Register */ 77 #define MTK_CDMQ_IG_CTRL 0x1400 78 #define MTK_CDMQ_STAG_EN BIT(0) 79 80 /* CDMP Exgress Control Register */ 81 #define MTK_CDMP_EG_CTRL 0x404 82 83 /* GDM Exgress Control Register */ 84 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 85 #define MTK_GDMA_ICS_EN BIT(22) 86 #define MTK_GDMA_TCS_EN BIT(21) 87 #define MTK_GDMA_UCS_EN BIT(20) 88 #define MTK_GDMA_TO_PDMA 0x0 89 #define MTK_GDMA_DROP_ALL 0x7777 90 91 /* Unicast Filter MAC Address Register - Low */ 92 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 93 94 /* Unicast Filter MAC Address Register - High */ 95 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 96 97 /* PDMA RX Base Pointer Register */ 98 #define MTK_PRX_BASE_PTR0 0x900 99 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 100 101 /* PDMA RX Maximum Count Register */ 102 #define MTK_PRX_MAX_CNT0 0x904 103 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 104 105 /* PDMA RX CPU Pointer Register */ 106 #define MTK_PRX_CRX_IDX0 0x908 107 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 108 109 /* PDMA HW LRO Control Registers */ 110 #define MTK_PDMA_LRO_CTRL_DW0 0x980 111 #define MTK_LRO_EN BIT(0) 112 #define MTK_L3_CKS_UPD_EN BIT(7) 113 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 114 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 115 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 116 117 #define MTK_PDMA_LRO_CTRL_DW1 0x984 118 #define MTK_PDMA_LRO_CTRL_DW2 0x988 119 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 120 #define MTK_ADMA_MODE BIT(15) 121 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 122 123 /* PDMA Global Configuration Register */ 124 #define MTK_PDMA_GLO_CFG 0xa04 125 #define MTK_MULTI_EN BIT(10) 126 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 127 128 /* PDMA Reset Index Register */ 129 #define MTK_PDMA_RST_IDX 0xa08 130 #define MTK_PST_DRX_IDX0 BIT(16) 131 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 132 133 /* PDMA Delay Interrupt Register */ 134 #define MTK_PDMA_DELAY_INT 0xa0c 135 #define MTK_PDMA_DELAY_RX_EN BIT(15) 136 #define MTK_PDMA_DELAY_RX_PINT 4 137 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 138 #define MTK_PDMA_DELAY_RX_PTIME 4 139 #define MTK_PDMA_DELAY_RX_DELAY \ 140 (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ 141 (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) 142 143 /* PDMA Interrupt Status Register */ 144 #define MTK_PDMA_INT_STATUS 0xa20 145 146 /* PDMA Interrupt Mask Register */ 147 #define MTK_PDMA_INT_MASK 0xa28 148 149 /* PDMA HW LRO Alter Flow Delta Register */ 150 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 151 152 /* PDMA Interrupt grouping registers */ 153 #define MTK_PDMA_INT_GRP1 0xa50 154 #define MTK_PDMA_INT_GRP2 0xa54 155 156 /* PDMA HW LRO IP Setting Registers */ 157 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 158 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 159 #define MTK_RING_MYIP_VLD BIT(9) 160 161 /* PDMA HW LRO Ring Control Registers */ 162 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 163 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 164 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 165 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 166 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 167 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 168 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 169 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 170 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 171 #define MTK_RING_VLD BIT(8) 172 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 173 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 174 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 175 176 /* QDMA TX Queue Configuration Registers */ 177 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 178 #define QDMA_RES_THRES 4 179 180 /* QDMA TX Queue Scheduler Registers */ 181 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 182 183 /* QDMA RX Base Pointer Register */ 184 #define MTK_QRX_BASE_PTR0 0x1900 185 186 /* QDMA RX Maximum Count Register */ 187 #define MTK_QRX_MAX_CNT0 0x1904 188 189 /* QDMA RX CPU Pointer Register */ 190 #define MTK_QRX_CRX_IDX0 0x1908 191 192 /* QDMA RX DMA Pointer Register */ 193 #define MTK_QRX_DRX_IDX0 0x190C 194 195 /* QDMA Global Configuration Register */ 196 #define MTK_QDMA_GLO_CFG 0x1A04 197 #define MTK_RX_2B_OFFSET BIT(31) 198 #define MTK_RX_BT_32DWORDS (3 << 11) 199 #define MTK_NDP_CO_PRO BIT(10) 200 #define MTK_TX_WB_DDONE BIT(6) 201 #define MTK_DMA_SIZE_16DWORDS (2 << 4) 202 #define MTK_RX_DMA_BUSY BIT(3) 203 #define MTK_TX_DMA_BUSY BIT(1) 204 #define MTK_RX_DMA_EN BIT(2) 205 #define MTK_TX_DMA_EN BIT(0) 206 #define MTK_DMA_BUSY_TIMEOUT HZ 207 208 /* QDMA Reset Index Register */ 209 #define MTK_QDMA_RST_IDX 0x1A08 210 211 /* QDMA Delay Interrupt Register */ 212 #define MTK_QDMA_DELAY_INT 0x1A0C 213 214 /* QDMA Flow Control Register */ 215 #define MTK_QDMA_FC_THRES 0x1A10 216 #define FC_THRES_DROP_MODE BIT(20) 217 #define FC_THRES_DROP_EN (7 << 16) 218 #define FC_THRES_MIN 0x4444 219 220 /* QDMA Interrupt Status Register */ 221 #define MTK_QDMA_INT_STATUS 0x1A18 222 #define MTK_RX_DONE_DLY BIT(30) 223 #define MTK_RX_DONE_INT3 BIT(19) 224 #define MTK_RX_DONE_INT2 BIT(18) 225 #define MTK_RX_DONE_INT1 BIT(17) 226 #define MTK_RX_DONE_INT0 BIT(16) 227 #define MTK_TX_DONE_INT3 BIT(3) 228 #define MTK_TX_DONE_INT2 BIT(2) 229 #define MTK_TX_DONE_INT1 BIT(1) 230 #define MTK_TX_DONE_INT0 BIT(0) 231 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 232 #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 233 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 234 235 /* QDMA Interrupt grouping registers */ 236 #define MTK_QDMA_INT_GRP1 0x1a20 237 #define MTK_QDMA_INT_GRP2 0x1a24 238 #define MTK_RLS_DONE_INT BIT(0) 239 240 /* QDMA Interrupt Status Register */ 241 #define MTK_QDMA_INT_MASK 0x1A1C 242 243 /* QDMA Interrupt Mask Register */ 244 #define MTK_QDMA_HRED2 0x1A44 245 246 /* QDMA TX Forward CPU Pointer Register */ 247 #define MTK_QTX_CTX_PTR 0x1B00 248 249 /* QDMA TX Forward DMA Pointer Register */ 250 #define MTK_QTX_DTX_PTR 0x1B04 251 252 /* QDMA TX Release CPU Pointer Register */ 253 #define MTK_QTX_CRX_PTR 0x1B10 254 255 /* QDMA TX Release DMA Pointer Register */ 256 #define MTK_QTX_DRX_PTR 0x1B14 257 258 /* QDMA FQ Head Pointer Register */ 259 #define MTK_QDMA_FQ_HEAD 0x1B20 260 261 /* QDMA FQ Head Pointer Register */ 262 #define MTK_QDMA_FQ_TAIL 0x1B24 263 264 /* QDMA FQ Free Page Counter Register */ 265 #define MTK_QDMA_FQ_CNT 0x1B28 266 267 /* QDMA FQ Free Page Buffer Length Register */ 268 #define MTK_QDMA_FQ_BLEN 0x1B2C 269 270 /* GMA1 Received Good Byte Count Register */ 271 #define MTK_GDM1_TX_GBCNT 0x2400 272 #define MTK_STAT_OFFSET 0x40 273 274 /* QDMA descriptor txd4 */ 275 #define TX_DMA_CHKSUM (0x7 << 29) 276 #define TX_DMA_TSO BIT(28) 277 #define TX_DMA_FPORT_SHIFT 25 278 #define TX_DMA_FPORT_MASK 0x7 279 #define TX_DMA_INS_VLAN BIT(16) 280 281 /* QDMA descriptor txd3 */ 282 #define TX_DMA_OWNER_CPU BIT(31) 283 #define TX_DMA_LS0 BIT(30) 284 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 285 #define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN) 286 #define TX_DMA_SWC BIT(14) 287 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 288 289 /* PDMA on MT7628 */ 290 #define TX_DMA_DONE BIT(31) 291 #define TX_DMA_LS1 BIT(14) 292 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 293 294 /* QDMA descriptor rxd2 */ 295 #define RX_DMA_DONE BIT(31) 296 #define RX_DMA_LSO BIT(30) 297 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 298 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 299 300 /* QDMA descriptor rxd3 */ 301 #define RX_DMA_VID(_x) ((_x) & 0xfff) 302 303 /* QDMA descriptor rxd4 */ 304 #define RX_DMA_L4_VALID BIT(24) 305 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 306 #define RX_DMA_FPORT_SHIFT 19 307 #define RX_DMA_FPORT_MASK 0x7 308 309 /* PHY Indirect Access Control registers */ 310 #define MTK_PHY_IAC 0x10004 311 #define PHY_IAC_ACCESS BIT(31) 312 #define PHY_IAC_READ BIT(19) 313 #define PHY_IAC_WRITE BIT(18) 314 #define PHY_IAC_START BIT(16) 315 #define PHY_IAC_ADDR_SHIFT 20 316 #define PHY_IAC_REG_SHIFT 25 317 #define PHY_IAC_TIMEOUT HZ 318 319 #define MTK_MAC_MISC 0x1000c 320 #define MTK_MUX_TO_ESW BIT(0) 321 322 /* Mac control registers */ 323 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 324 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 325 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 326 #define MAC_MCR_MAX_RX_1518 0x0 327 #define MAC_MCR_MAX_RX_1536 0x1 328 #define MAC_MCR_MAX_RX_1552 0x2 329 #define MAC_MCR_MAX_RX_2048 0x3 330 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 331 #define MAC_MCR_FORCE_MODE BIT(15) 332 #define MAC_MCR_TX_EN BIT(14) 333 #define MAC_MCR_RX_EN BIT(13) 334 #define MAC_MCR_BACKOFF_EN BIT(9) 335 #define MAC_MCR_BACKPR_EN BIT(8) 336 #define MAC_MCR_FORCE_RX_FC BIT(5) 337 #define MAC_MCR_FORCE_TX_FC BIT(4) 338 #define MAC_MCR_SPEED_1000 BIT(3) 339 #define MAC_MCR_SPEED_100 BIT(2) 340 #define MAC_MCR_FORCE_DPX BIT(1) 341 #define MAC_MCR_FORCE_LINK BIT(0) 342 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 343 344 /* Mac status registers */ 345 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 346 #define MAC_MSR_EEE1G BIT(7) 347 #define MAC_MSR_EEE100M BIT(6) 348 #define MAC_MSR_RX_FC BIT(5) 349 #define MAC_MSR_TX_FC BIT(4) 350 #define MAC_MSR_SPEED_1000 BIT(3) 351 #define MAC_MSR_SPEED_100 BIT(2) 352 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 353 #define MAC_MSR_DPX BIT(1) 354 #define MAC_MSR_LINK BIT(0) 355 356 /* TRGMII RXC control register */ 357 #define TRGMII_RCK_CTRL 0x10300 358 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 359 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 360 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 361 #define RXC_RST BIT(31) 362 #define RXC_DQSISEL BIT(30) 363 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 364 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 365 366 #define NUM_TRGMII_CTRL 5 367 368 /* TRGMII RXC control register */ 369 #define TRGMII_TCK_CTRL 0x10340 370 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 371 #define TXC_INV BIT(30) 372 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 373 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 374 375 /* TRGMII TX Drive Strength */ 376 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 377 #define TD_DM_DRVP(x) ((x) & 0xf) 378 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 379 380 /* TRGMII Interface mode register */ 381 #define INTF_MODE 0x10390 382 #define TRGMII_INTF_DIS BIT(0) 383 #define TRGMII_MODE BIT(1) 384 #define TRGMII_CENTRAL_ALIGNED BIT(2) 385 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 386 #define INTF_MODE_RGMII_10_100 0 387 388 /* GPIO port control registers for GMAC 2*/ 389 #define GPIO_OD33_CTRL8 0x4c0 390 #define GPIO_BIAS_CTRL 0xed0 391 #define GPIO_DRV_SEL10 0xf00 392 393 /* ethernet subsystem chip id register */ 394 #define ETHSYS_CHIPID0_3 0x0 395 #define ETHSYS_CHIPID4_7 0x4 396 #define MT7623_ETH 7623 397 #define MT7622_ETH 7622 398 #define MT7621_ETH 7621 399 400 /* ethernet system control register */ 401 #define ETHSYS_SYSCFG 0x10 402 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 403 404 /* ethernet subsystem config register */ 405 #define ETHSYS_SYSCFG0 0x14 406 #define SYSCFG0_GE_MASK 0x3 407 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 408 #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 409 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 410 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 411 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 412 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 413 414 415 /* ethernet subsystem clock register */ 416 #define ETHSYS_CLKCFG0 0x2c 417 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 418 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 419 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 420 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 421 422 /* ethernet reset control register */ 423 #define ETHSYS_RSTCTRL 0x34 424 #define RSTCTRL_FE BIT(6) 425 #define RSTCTRL_PPE BIT(31) 426 427 /* SGMII subsystem config registers */ 428 /* Register to auto-negotiation restart */ 429 #define SGMSYS_PCS_CONTROL_1 0x0 430 #define SGMII_AN_RESTART BIT(9) 431 #define SGMII_ISOLATE BIT(10) 432 #define SGMII_AN_ENABLE BIT(12) 433 #define SGMII_LINK_STATYS BIT(18) 434 #define SGMII_AN_ABILITY BIT(19) 435 #define SGMII_AN_COMPLETE BIT(21) 436 #define SGMII_PCS_FAULT BIT(23) 437 #define SGMII_AN_EXPANSION_CLR BIT(30) 438 439 /* Register to programmable link timer, the unit in 2 * 8ns */ 440 #define SGMSYS_PCS_LINK_TIMER 0x18 441 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 442 443 /* Register to control remote fault */ 444 #define SGMSYS_SGMII_MODE 0x20 445 #define SGMII_IF_MODE_BIT0 BIT(0) 446 #define SGMII_SPEED_DUPLEX_AN BIT(1) 447 #define SGMII_SPEED_10 0x0 448 #define SGMII_SPEED_100 BIT(2) 449 #define SGMII_SPEED_1000 BIT(3) 450 #define SGMII_DUPLEX_FULL BIT(4) 451 #define SGMII_IF_MODE_BIT5 BIT(5) 452 #define SGMII_REMOTE_FAULT_DIS BIT(8) 453 #define SGMII_CODE_SYNC_SET_VAL BIT(9) 454 #define SGMII_CODE_SYNC_SET_EN BIT(10) 455 #define SGMII_SEND_AN_ERROR_EN BIT(11) 456 #define SGMII_IF_MODE_MASK GENMASK(5, 1) 457 458 /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 459 #define SGMSYS_ANA_RG_CS3 0x2028 460 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 461 #define RG_PHY_SPEED_1_25G 0x0 462 #define RG_PHY_SPEED_3_125G BIT(2) 463 464 /* Register to power up QPHY */ 465 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 466 #define SGMII_PHYA_PWD BIT(4) 467 468 /* Infrasys subsystem config registers */ 469 #define INFRA_MISC2 0x70c 470 #define CO_QPHY_SEL BIT(0) 471 #define GEPHY_MAC_SEL BIT(1) 472 473 /* MT7628/88 specific stuff */ 474 #define MT7628_PDMA_OFFSET 0x0800 475 #define MT7628_SDM_OFFSET 0x0c00 476 477 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 478 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 479 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 480 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 481 #define MT7628_PST_DTX_IDX0 BIT(0) 482 483 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 484 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 485 486 struct mtk_rx_dma { 487 unsigned int rxd1; 488 unsigned int rxd2; 489 unsigned int rxd3; 490 unsigned int rxd4; 491 } __packed __aligned(4); 492 493 struct mtk_tx_dma { 494 unsigned int txd1; 495 unsigned int txd2; 496 unsigned int txd3; 497 unsigned int txd4; 498 } __packed __aligned(4); 499 500 struct mtk_eth; 501 struct mtk_mac; 502 503 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 504 * @stats_lock: make sure that stats operations are atomic 505 * @reg_offset: the status register offset of the SoC 506 * @syncp: the refcount 507 * 508 * All of the supported SoCs have hardware counters for traffic statistics. 509 * Whenever the status IRQ triggers we can read the latest stats from these 510 * counters and store them in this struct. 511 */ 512 struct mtk_hw_stats { 513 u64 tx_bytes; 514 u64 tx_packets; 515 u64 tx_skip; 516 u64 tx_collisions; 517 u64 rx_bytes; 518 u64 rx_packets; 519 u64 rx_overflow; 520 u64 rx_fcs_errors; 521 u64 rx_short_errors; 522 u64 rx_long_errors; 523 u64 rx_checksum_errors; 524 u64 rx_flow_control_packets; 525 526 spinlock_t stats_lock; 527 u32 reg_offset; 528 struct u64_stats_sync syncp; 529 }; 530 531 enum mtk_tx_flags { 532 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 533 * track how memory was allocated so that it can be freed properly. 534 */ 535 MTK_TX_FLAGS_SINGLE0 = 0x01, 536 MTK_TX_FLAGS_PAGE0 = 0x02, 537 538 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 539 * SKB out instead of looking up through hardware TX descriptor. 540 */ 541 MTK_TX_FLAGS_FPORT0 = 0x04, 542 MTK_TX_FLAGS_FPORT1 = 0x08, 543 }; 544 545 /* This enum allows us to identify how the clock is defined on the array of the 546 * clock in the order 547 */ 548 enum mtk_clks_map { 549 MTK_CLK_ETHIF, 550 MTK_CLK_SGMIITOP, 551 MTK_CLK_ESW, 552 MTK_CLK_GP0, 553 MTK_CLK_GP1, 554 MTK_CLK_GP2, 555 MTK_CLK_FE, 556 MTK_CLK_TRGPLL, 557 MTK_CLK_SGMII_TX_250M, 558 MTK_CLK_SGMII_RX_250M, 559 MTK_CLK_SGMII_CDR_REF, 560 MTK_CLK_SGMII_CDR_FB, 561 MTK_CLK_SGMII2_TX_250M, 562 MTK_CLK_SGMII2_RX_250M, 563 MTK_CLK_SGMII2_CDR_REF, 564 MTK_CLK_SGMII2_CDR_FB, 565 MTK_CLK_SGMII_CK, 566 MTK_CLK_ETH2PLL, 567 MTK_CLK_MAX 568 }; 569 570 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 571 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 572 BIT(MTK_CLK_TRGPLL)) 573 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 574 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 575 BIT(MTK_CLK_GP2) | \ 576 BIT(MTK_CLK_SGMII_TX_250M) | \ 577 BIT(MTK_CLK_SGMII_RX_250M) | \ 578 BIT(MTK_CLK_SGMII_CDR_REF) | \ 579 BIT(MTK_CLK_SGMII_CDR_FB) | \ 580 BIT(MTK_CLK_SGMII_CK) | \ 581 BIT(MTK_CLK_ETH2PLL)) 582 #define MT7621_CLKS_BITMAP (0) 583 #define MT7628_CLKS_BITMAP (0) 584 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 585 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 586 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 587 BIT(MTK_CLK_SGMII_TX_250M) | \ 588 BIT(MTK_CLK_SGMII_RX_250M) | \ 589 BIT(MTK_CLK_SGMII_CDR_REF) | \ 590 BIT(MTK_CLK_SGMII_CDR_FB) | \ 591 BIT(MTK_CLK_SGMII2_TX_250M) | \ 592 BIT(MTK_CLK_SGMII2_RX_250M) | \ 593 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 594 BIT(MTK_CLK_SGMII2_CDR_FB) | \ 595 BIT(MTK_CLK_SGMII_CK) | \ 596 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 597 598 enum mtk_dev_state { 599 MTK_HW_INIT, 600 MTK_RESETTING 601 }; 602 603 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 604 * by the TX descriptor s 605 * @skb: The SKB pointer of the packet being sent 606 * @dma_addr0: The base addr of the first segment 607 * @dma_len0: The length of the first segment 608 * @dma_addr1: The base addr of the second segment 609 * @dma_len1: The length of the second segment 610 */ 611 struct mtk_tx_buf { 612 struct sk_buff *skb; 613 u32 flags; 614 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 615 DEFINE_DMA_UNMAP_LEN(dma_len0); 616 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 617 DEFINE_DMA_UNMAP_LEN(dma_len1); 618 }; 619 620 /* struct mtk_tx_ring - This struct holds info describing a TX ring 621 * @dma: The descriptor ring 622 * @buf: The memory pointed at by the ring 623 * @phys: The physical addr of tx_buf 624 * @next_free: Pointer to the next free descriptor 625 * @last_free: Pointer to the last free descriptor 626 * @thresh: The threshold of minimum amount of free descriptors 627 * @free_count: QDMA uses a linked list. Track how many free descriptors 628 * are present 629 */ 630 struct mtk_tx_ring { 631 struct mtk_tx_dma *dma; 632 struct mtk_tx_buf *buf; 633 dma_addr_t phys; 634 struct mtk_tx_dma *next_free; 635 struct mtk_tx_dma *last_free; 636 u16 thresh; 637 atomic_t free_count; 638 int dma_size; 639 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 640 dma_addr_t phys_pdma; 641 int cpu_idx; 642 }; 643 644 /* PDMA rx ring mode */ 645 enum mtk_rx_flags { 646 MTK_RX_FLAGS_NORMAL = 0, 647 MTK_RX_FLAGS_HWLRO, 648 MTK_RX_FLAGS_QDMA, 649 }; 650 651 /* struct mtk_rx_ring - This struct holds info describing a RX ring 652 * @dma: The descriptor ring 653 * @data: The memory pointed at by the ring 654 * @phys: The physical addr of rx_buf 655 * @frag_size: How big can each fragment be 656 * @buf_size: The size of each packet buffer 657 * @calc_idx: The current head of ring 658 */ 659 struct mtk_rx_ring { 660 struct mtk_rx_dma *dma; 661 u8 **data; 662 dma_addr_t phys; 663 u16 frag_size; 664 u16 buf_size; 665 u16 dma_size; 666 bool calc_idx_update; 667 u16 calc_idx; 668 u32 crx_idx_reg; 669 }; 670 671 enum mkt_eth_capabilities { 672 MTK_RGMII_BIT = 0, 673 MTK_TRGMII_BIT, 674 MTK_SGMII_BIT, 675 MTK_ESW_BIT, 676 MTK_GEPHY_BIT, 677 MTK_MUX_BIT, 678 MTK_INFRA_BIT, 679 MTK_SHARED_SGMII_BIT, 680 MTK_HWLRO_BIT, 681 MTK_SHARED_INT_BIT, 682 MTK_TRGMII_MT7621_CLK_BIT, 683 MTK_QDMA_BIT, 684 MTK_SOC_MT7628_BIT, 685 686 /* MUX BITS*/ 687 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 688 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 689 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 690 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 691 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 692 693 /* PATH BITS */ 694 MTK_ETH_PATH_GMAC1_RGMII_BIT, 695 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 696 MTK_ETH_PATH_GMAC1_SGMII_BIT, 697 MTK_ETH_PATH_GMAC2_RGMII_BIT, 698 MTK_ETH_PATH_GMAC2_SGMII_BIT, 699 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 700 MTK_ETH_PATH_GDM1_ESW_BIT, 701 }; 702 703 /* Supported hardware group on SoCs */ 704 #define MTK_RGMII BIT(MTK_RGMII_BIT) 705 #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 706 #define MTK_SGMII BIT(MTK_SGMII_BIT) 707 #define MTK_ESW BIT(MTK_ESW_BIT) 708 #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 709 #define MTK_MUX BIT(MTK_MUX_BIT) 710 #define MTK_INFRA BIT(MTK_INFRA_BIT) 711 #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 712 #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 713 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 714 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 715 #define MTK_QDMA BIT(MTK_QDMA_BIT) 716 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 717 718 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 719 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 720 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 721 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 722 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 723 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 724 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 725 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 726 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 727 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 728 729 /* Supported path present on SoCs */ 730 #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 731 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 732 #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 733 #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 734 #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 735 #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 736 #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 737 738 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 739 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 740 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 741 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 742 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 743 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 744 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 745 746 /* MUXes present on SoCs */ 747 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 748 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 749 750 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 751 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 752 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 753 754 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 755 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 756 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 757 758 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 759 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 760 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 761 MTK_SHARED_SGMII) 762 763 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 764 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 765 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 766 767 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 768 769 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 770 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 771 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 772 773 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 774 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 775 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 776 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 777 778 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 779 MTK_QDMA) 780 781 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 782 783 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 784 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 785 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 786 MTK_MUX_U3_GMAC2_TO_QPHY | \ 787 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 788 789 /* struct mtk_eth_data - This is the structure holding all differences 790 * among various plaforms 791 * @ana_rgc3: The offset for register ANA_RGC3 related to 792 * sgmiisys syscon 793 * @caps Flags shown the extra capability for the SoC 794 * @hw_features Flags shown HW features 795 * @required_clks Flags shown the bitmap for required clocks on 796 * the target SoC 797 * @required_pctl A bool value to show whether the SoC requires 798 * the extra setup for those pins used by GMAC. 799 */ 800 struct mtk_soc_data { 801 u32 ana_rgc3; 802 u32 caps; 803 u32 required_clks; 804 bool required_pctl; 805 netdev_features_t hw_features; 806 }; 807 808 /* currently no SoC has more than 2 macs */ 809 #define MTK_MAX_DEVS 2 810 811 #define MTK_SGMII_PHYSPEED_AN BIT(31) 812 #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) 813 #define MTK_SGMII_PHYSPEED_1000 BIT(0) 814 #define MTK_SGMII_PHYSPEED_2500 BIT(1) 815 #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) 816 817 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 818 * characteristics 819 * @regmap: The register map pointing at the range used to setup 820 * SGMII modes 821 * @flags: The enum refers to which mode the sgmii wants to run on 822 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 823 */ 824 825 struct mtk_sgmii { 826 struct regmap *regmap[MTK_MAX_DEVS]; 827 u32 flags[MTK_MAX_DEVS]; 828 u32 ana_rgc3; 829 }; 830 831 /* struct mtk_eth - This is the main datasructure for holding the state 832 * of the driver 833 * @dev: The device pointer 834 * @base: The mapped register i/o base 835 * @page_lock: Make sure that register operations are atomic 836 * @tx_irq__lock: Make sure that IRQ register operations are atomic 837 * @rx_irq__lock: Make sure that IRQ register operations are atomic 838 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 839 * dummy for NAPI to work 840 * @netdev: The netdev instances 841 * @mac: Each netdev is linked to a physical MAC 842 * @irq: The IRQ that we are using 843 * @msg_enable: Ethtool msg level 844 * @ethsys: The register map pointing at the range used to setup 845 * MII modes 846 * @infra: The register map pointing at the range used to setup 847 * SGMII and GePHY path 848 * @pctl: The register map pointing at the range used to setup 849 * GMAC port drive/slew values 850 * @dma_refcnt: track how many netdevs are using the DMA engine 851 * @tx_ring: Pointer to the memory holding info about the TX ring 852 * @rx_ring: Pointer to the memory holding info about the RX ring 853 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 854 * @tx_napi: The TX NAPI struct 855 * @rx_napi: The RX NAPI struct 856 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 857 * @phy_scratch_ring: physical address of scratch_ring 858 * @scratch_head: The scratch memory that scratch_ring points to. 859 * @clks: clock array for all clocks required 860 * @mii_bus: If there is a bus we need to create an instance for it 861 * @pending_work: The workqueue used to reset the dma ring 862 * @state: Initialization and runtime state of the device 863 * @soc: Holding specific data among vaious SoCs 864 */ 865 866 struct mtk_eth { 867 struct device *dev; 868 void __iomem *base; 869 spinlock_t page_lock; 870 spinlock_t tx_irq_lock; 871 spinlock_t rx_irq_lock; 872 struct net_device dummy_dev; 873 struct net_device *netdev[MTK_MAX_DEVS]; 874 struct mtk_mac *mac[MTK_MAX_DEVS]; 875 int irq[3]; 876 u32 msg_enable; 877 unsigned long sysclk; 878 struct regmap *ethsys; 879 struct regmap *infra; 880 struct mtk_sgmii *sgmii; 881 struct regmap *pctl; 882 bool hwlro; 883 refcount_t dma_refcnt; 884 struct mtk_tx_ring tx_ring; 885 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 886 struct mtk_rx_ring rx_ring_qdma; 887 struct napi_struct tx_napi; 888 struct napi_struct rx_napi; 889 struct mtk_tx_dma *scratch_ring; 890 dma_addr_t phy_scratch_ring; 891 void *scratch_head; 892 struct clk *clks[MTK_CLK_MAX]; 893 894 struct mii_bus *mii_bus; 895 struct work_struct pending_work; 896 unsigned long state; 897 898 const struct mtk_soc_data *soc; 899 900 u32 tx_int_mask_reg; 901 u32 tx_int_status_reg; 902 u32 rx_dma_l4_valid; 903 int ip_align; 904 }; 905 906 /* struct mtk_mac - the structure that holds the info about the MACs of the 907 * SoC 908 * @id: The number of the MAC 909 * @interface: Interface mode kept for detecting change in hw settings 910 * @of_node: Our devicetree node 911 * @hw: Backpointer to our main datastruture 912 * @hw_stats: Packet statistics counter 913 */ 914 struct mtk_mac { 915 int id; 916 phy_interface_t interface; 917 unsigned int mode; 918 int speed; 919 struct device_node *of_node; 920 struct phylink *phylink; 921 struct phylink_config phylink_config; 922 struct mtk_eth *hw; 923 struct mtk_hw_stats *hw_stats; 924 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 925 int hwlro_ip_cnt; 926 }; 927 928 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 929 extern const struct of_device_id of_mtk_match[]; 930 931 /* read the hardware status register */ 932 void mtk_stats_update_mac(struct mtk_mac *mac); 933 934 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 935 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 936 937 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 938 u32 ana_rgc3); 939 int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); 940 int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, 941 const struct phylink_link_state *state); 942 void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); 943 944 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 945 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 946 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 947 948 #endif /* MTK_ETH_H */ 949