1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 #include <linux/rhashtable.h> 19 #include <linux/dim.h> 20 #include <linux/bitfield.h> 21 #include <net/page_pool/types.h> 22 #include <linux/bpf_trace.h> 23 #include "mtk_ppe.h" 24 25 #define MTK_MAX_DSA_PORTS 7 26 #define MTK_DSA_PORT_MASK GENMASK(2, 0) 27 28 #define MTK_QDMA_NUM_QUEUES 16 29 #define MTK_QDMA_PAGE_SIZE 2048 30 #define MTK_MAX_RX_LENGTH 1536 31 #define MTK_MAX_RX_LENGTH_2K 2048 32 #define MTK_TX_DMA_BUF_LEN 0x3fff 33 #define MTK_TX_DMA_BUF_LEN_V2 0xffff 34 #define MTK_QDMA_RING_SIZE 2048 35 #define MTK_DMA_SIZE 512 36 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 37 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 38 #define MTK_DMA_DUMMY_DESC 0xffffffff 39 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 40 NETIF_MSG_PROBE | \ 41 NETIF_MSG_LINK | \ 42 NETIF_MSG_TIMER | \ 43 NETIF_MSG_IFDOWN | \ 44 NETIF_MSG_IFUP | \ 45 NETIF_MSG_RX_ERR | \ 46 NETIF_MSG_TX_ERR) 47 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 48 NETIF_F_RXCSUM | \ 49 NETIF_F_HW_VLAN_CTAG_TX | \ 50 NETIF_F_SG | NETIF_F_TSO | \ 51 NETIF_F_TSO6 | \ 52 NETIF_F_IPV6_CSUM |\ 53 NETIF_F_HW_TC) 54 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 55 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 56 57 #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM 58 #define MTK_PP_PAD (MTK_PP_HEADROOM + \ 59 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 60 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD) 61 62 #define MTK_QRX_OFFSET 0x10 63 64 #define MTK_MAX_RX_RING_NUM 4 65 #define MTK_HW_LRO_DMA_SIZE 8 66 67 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 68 #define MTK_MAX_LRO_IP_CNT 2 69 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 70 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 71 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 72 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 73 #define MTK_HW_LRO_MAX_AGG_CNT 64 74 #define MTK_HW_LRO_BW_THRE 3000 75 #define MTK_HW_LRO_REPLACE_DELTA 1000 76 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 77 78 /* Frame Engine Global Configuration */ 79 #define MTK_FE_GLO_CFG 0x00 80 #define MTK_FE_LINK_DOWN_P3 BIT(11) 81 #define MTK_FE_LINK_DOWN_P4 BIT(12) 82 83 /* Frame Engine Global Reset Register */ 84 #define MTK_RST_GL 0x04 85 #define RST_GL_PSE BIT(0) 86 87 /* Frame Engine Interrupt Status Register */ 88 #define MTK_INT_STATUS2 0x08 89 #define MTK_FE_INT_ENABLE 0x0c 90 #define MTK_FE_INT_FQ_EMPTY BIT(8) 91 #define MTK_FE_INT_TSO_FAIL BIT(12) 92 #define MTK_FE_INT_TSO_ILLEGAL BIT(13) 93 #define MTK_FE_INT_TSO_ALIGN BIT(14) 94 #define MTK_FE_INT_RFIFO_OV BIT(18) 95 #define MTK_FE_INT_RFIFO_UF BIT(19) 96 #define MTK_GDM1_AF BIT(28) 97 #define MTK_GDM2_AF BIT(29) 98 99 /* PDMA HW LRO Alter Flow Timer Register */ 100 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 101 102 /* Frame Engine Interrupt Grouping Register */ 103 #define MTK_FE_INT_GRP 0x20 104 105 /* CDMP Ingress Control Register */ 106 #define MTK_CDMQ_IG_CTRL 0x1400 107 #define MTK_CDMQ_STAG_EN BIT(0) 108 109 /* CDMQ Exgress Control Register */ 110 #define MTK_CDMQ_EG_CTRL 0x1404 111 112 /* CDMP Ingress Control Register */ 113 #define MTK_CDMP_IG_CTRL 0x400 114 #define MTK_CDMP_STAG_EN BIT(0) 115 116 /* CDMP Exgress Control Register */ 117 #define MTK_CDMP_EG_CTRL 0x404 118 119 /* GDM Exgress Control Register */ 120 #define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 121 0x540 : 0x500 + (_x * 0x1000); }) 122 #define MTK_GDMA_SPECIAL_TAG BIT(24) 123 #define MTK_GDMA_ICS_EN BIT(22) 124 #define MTK_GDMA_TCS_EN BIT(21) 125 #define MTK_GDMA_UCS_EN BIT(20) 126 #define MTK_GDMA_STRP_CRC BIT(16) 127 #define MTK_GDMA_TO_PDMA 0x0 128 #define MTK_GDMA_DROP_ALL 0x7777 129 130 /* GDM Egress Control Register */ 131 #define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 132 0x544 : 0x504 + (_x * 0x1000); }) 133 #define MTK_GDMA_XGDM_SEL BIT(31) 134 135 /* Unicast Filter MAC Address Register - Low */ 136 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 137 138 /* Unicast Filter MAC Address Register - High */ 139 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 140 141 /* FE global misc reg*/ 142 #define MTK_FE_GLO_MISC 0x124 143 144 /* PSE Free Queue Flow Control */ 145 #define PSE_FQFC_CFG1 0x100 146 #define PSE_FQFC_CFG2 0x104 147 #define PSE_DROP_CFG 0x108 148 #define PSE_PPE0_DROP 0x110 149 150 /* PSE Input Queue Reservation Register*/ 151 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 152 153 /* PSE Output Queue Threshold Register*/ 154 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 155 156 /* GDM and CDM Threshold */ 157 #define MTK_GDM2_THRES 0x1530 158 #define MTK_CDMW0_THRES 0x164c 159 #define MTK_CDMW1_THRES 0x1650 160 #define MTK_CDME0_THRES 0x1654 161 #define MTK_CDME1_THRES 0x1658 162 #define MTK_CDMM_THRES 0x165c 163 164 /* PDMA HW LRO Control Registers */ 165 #define MTK_PDMA_LRO_CTRL_DW0 0x980 166 #define MTK_LRO_EN BIT(0) 167 #define MTK_L3_CKS_UPD_EN BIT(7) 168 #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 169 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 170 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 171 #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 172 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 173 #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 174 175 #define MTK_PDMA_LRO_CTRL_DW1 0x984 176 #define MTK_PDMA_LRO_CTRL_DW2 0x988 177 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 178 #define MTK_ADMA_MODE BIT(15) 179 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 180 181 #define MTK_RX_DMA_LRO_EN BIT(8) 182 #define MTK_MULTI_EN BIT(10) 183 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 184 185 /* PDMA Global Configuration Register */ 186 #define MTK_PDMA_LRO_SDL 0x3000 187 #define MTK_RX_CFG_SDL_OFFSET 16 188 189 /* PDMA Reset Index Register */ 190 #define MTK_PST_DRX_IDX0 BIT(16) 191 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 192 193 /* PDMA Delay Interrupt Register */ 194 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 195 #define MTK_PDMA_DELAY_RX_EN BIT(15) 196 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 197 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 198 199 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 200 #define MTK_PDMA_DELAY_TX_EN BIT(31) 201 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 202 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 203 204 #define MTK_PDMA_DELAY_PINT_MASK 0x7f 205 #define MTK_PDMA_DELAY_PTIME_MASK 0xff 206 207 /* PDMA HW LRO Alter Flow Delta Register */ 208 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 209 210 /* PDMA HW LRO IP Setting Registers */ 211 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 212 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 213 #define MTK_RING_MYIP_VLD BIT(9) 214 215 /* PDMA HW LRO Ring Control Registers */ 216 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 217 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 218 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 219 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 220 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 221 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 222 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 223 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 224 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 225 #define MTK_RING_VLD BIT(8) 226 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 227 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 228 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 229 230 /* QDMA TX Queue Configuration Registers */ 231 #define MTK_QTX_OFFSET 0x10 232 #define QDMA_RES_THRES 4 233 234 /* QDMA Tx Queue Scheduler Configuration Registers */ 235 #define MTK_QTX_SCH_TX_SEL BIT(31) 236 #define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30) 237 238 #define MTK_QTX_SCH_LEAKY_BUCKET_EN BIT(30) 239 #define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28) 240 #define MTK_QTX_SCH_MIN_RATE_EN BIT(27) 241 #define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20) 242 #define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16) 243 #define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12) 244 #define MTK_QTX_SCH_MAX_RATE_EN BIT(11) 245 #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4) 246 #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0) 247 248 /* QDMA TX Scheduler Rate Control Register */ 249 #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15) 250 251 /* QDMA Global Configuration Register */ 252 #define MTK_RX_2B_OFFSET BIT(31) 253 #define MTK_RX_BT_32DWORDS (3 << 11) 254 #define MTK_NDP_CO_PRO BIT(10) 255 #define MTK_TX_WB_DDONE BIT(6) 256 #define MTK_TX_BT_32DWORDS (3 << 4) 257 #define MTK_RX_DMA_BUSY BIT(3) 258 #define MTK_TX_DMA_BUSY BIT(1) 259 #define MTK_RX_DMA_EN BIT(2) 260 #define MTK_TX_DMA_EN BIT(0) 261 #define MTK_DMA_BUSY_TIMEOUT_US 1000000 262 263 /* QDMA V2 Global Configuration Register */ 264 #define MTK_CHK_DDONE_EN BIT(28) 265 #define MTK_DMAD_WR_WDONE BIT(26) 266 #define MTK_WCOMP_EN BIT(24) 267 #define MTK_RESV_BUF (0x40 << 16) 268 #define MTK_MUTLI_CNT (0x4 << 12) 269 #define MTK_LEAKY_BUCKET_EN BIT(11) 270 271 /* QDMA Flow Control Register */ 272 #define FC_THRES_DROP_MODE BIT(20) 273 #define FC_THRES_DROP_EN (7 << 16) 274 #define FC_THRES_MIN 0x4444 275 276 /* QDMA Interrupt Status Register */ 277 #define MTK_RX_DONE_DLY BIT(30) 278 #define MTK_TX_DONE_DLY BIT(28) 279 #define MTK_RX_DONE_INT3 BIT(19) 280 #define MTK_RX_DONE_INT2 BIT(18) 281 #define MTK_RX_DONE_INT1 BIT(17) 282 #define MTK_RX_DONE_INT0 BIT(16) 283 #define MTK_TX_DONE_INT3 BIT(3) 284 #define MTK_TX_DONE_INT2 BIT(2) 285 #define MTK_TX_DONE_INT1 BIT(1) 286 #define MTK_TX_DONE_INT0 BIT(0) 287 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 288 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 289 290 #define MTK_RX_DONE_INT_V2 BIT(14) 291 292 #define MTK_CDM_TXFIFO_RDY BIT(7) 293 294 /* QDMA Interrupt grouping registers */ 295 #define MTK_RLS_DONE_INT BIT(0) 296 297 /* QDMA TX NUM */ 298 #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 299 #define MTK_QDMA_GMAC2_QID 8 300 301 #define MTK_TX_DMA_BUF_SHIFT 8 302 303 /* QDMA V2 descriptor txd6 */ 304 #define TX_DMA_INS_VLAN_V2 BIT(16) 305 /* QDMA V2 descriptor txd5 */ 306 #define TX_DMA_CHKSUM_V2 (0x7 << 28) 307 #define TX_DMA_TSO_V2 BIT(31) 308 309 #define TX_DMA_SPTAG_V3 BIT(27) 310 311 /* QDMA V2 descriptor txd4 */ 312 #define TX_DMA_FPORT_SHIFT_V2 8 313 #define TX_DMA_FPORT_MASK_V2 0xf 314 #define TX_DMA_SWC_V2 BIT(30) 315 316 /* QDMA descriptor txd4 */ 317 #define TX_DMA_CHKSUM (0x7 << 29) 318 #define TX_DMA_TSO BIT(28) 319 #define TX_DMA_FPORT_SHIFT 25 320 #define TX_DMA_FPORT_MASK 0x7 321 #define TX_DMA_INS_VLAN BIT(16) 322 323 /* QDMA descriptor txd3 */ 324 #define TX_DMA_OWNER_CPU BIT(31) 325 #define TX_DMA_LS0 BIT(30) 326 #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 327 #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) 328 #define TX_DMA_SWC BIT(14) 329 #define TX_DMA_PQID GENMASK(3, 0) 330 331 /* PDMA on MT7628 */ 332 #define TX_DMA_DONE BIT(31) 333 #define TX_DMA_LS1 BIT(14) 334 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 335 336 /* QDMA descriptor rxd2 */ 337 #define RX_DMA_DONE BIT(31) 338 #define RX_DMA_LSO BIT(30) 339 #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 340 #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) 341 #define RX_DMA_VTAG BIT(15) 342 343 /* QDMA descriptor rxd3 */ 344 #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 345 #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 346 #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 347 348 /* QDMA descriptor rxd4 */ 349 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 350 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 351 #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 352 #define MTK_RXD4_ALG GENMASK(31, 22) 353 354 /* QDMA descriptor rxd4 */ 355 #define RX_DMA_L4_VALID BIT(24) 356 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 357 #define RX_DMA_SPECIAL_TAG BIT(22) 358 359 /* PDMA descriptor rxd5 */ 360 #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) 361 #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) 362 #define MTK_RXD5_SRC_PORT GENMASK(29, 26) 363 364 #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7) 365 #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf) 366 367 /* PDMA V2 descriptor rxd3 */ 368 #define RX_DMA_VTAG_V2 BIT(0) 369 #define RX_DMA_L4_VALID_V2 BIT(2) 370 371 /* PHY Polling and SMI Master Control registers */ 372 #define MTK_PPSC 0x10000 373 #define PPSC_MDC_CFG GENMASK(29, 24) 374 #define PPSC_MDC_TURBO BIT(20) 375 #define MDC_MAX_FREQ 25000000 376 #define MDC_MAX_DIVIDER 63 377 378 /* PHY Indirect Access Control registers */ 379 #define MTK_PHY_IAC 0x10004 380 #define PHY_IAC_ACCESS BIT(31) 381 #define PHY_IAC_REG_MASK GENMASK(29, 25) 382 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 383 #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 384 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 385 #define PHY_IAC_CMD_MASK GENMASK(19, 18) 386 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 387 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 388 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 389 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 390 #define PHY_IAC_START_MASK GENMASK(17, 16) 391 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 392 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 393 #define PHY_IAC_DATA_MASK GENMASK(15, 0) 394 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 395 #define PHY_IAC_TIMEOUT HZ 396 397 #define MTK_MAC_MISC 0x1000c 398 #define MTK_MAC_MISC_V3 0x10010 399 #define MTK_MUX_TO_ESW BIT(0) 400 #define MISC_MDC_TURBO BIT(4) 401 402 /* XMAC status registers */ 403 #define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C) 404 #define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15)) 405 #define MTK_USXGMII_PCS_LINK BIT(8) 406 #define MTK_XGMAC_RX_FC BIT(5) 407 #define MTK_XGMAC_TX_FC BIT(4) 408 #define MTK_USXGMII_PCS_MODE GENMASK(3, 1) 409 #define MTK_XGMAC_LINK_STS BIT(0) 410 411 /* GSW bridge registers */ 412 #define MTK_GSW_CFG (0x10080) 413 #define GSWTX_IPG_MASK GENMASK(19, 16) 414 #define GSWTX_IPG_SHIFT 16 415 #define GSWRX_IPG_MASK GENMASK(3, 0) 416 #define GSWRX_IPG_SHIFT 0 417 #define GSW_IPG_11 11 418 419 /* Mac control registers */ 420 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 421 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 422 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 423 #define MAC_MCR_MAX_RX_1518 0x0 424 #define MAC_MCR_MAX_RX_1536 0x1 425 #define MAC_MCR_MAX_RX_1552 0x2 426 #define MAC_MCR_MAX_RX_2048 0x3 427 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 428 #define MAC_MCR_FORCE_MODE BIT(15) 429 #define MAC_MCR_TX_EN BIT(14) 430 #define MAC_MCR_RX_EN BIT(13) 431 #define MAC_MCR_RX_FIFO_CLR_DIS BIT(12) 432 #define MAC_MCR_BACKOFF_EN BIT(9) 433 #define MAC_MCR_BACKPR_EN BIT(8) 434 #define MAC_MCR_FORCE_RX_FC BIT(5) 435 #define MAC_MCR_FORCE_TX_FC BIT(4) 436 #define MAC_MCR_SPEED_1000 BIT(3) 437 #define MAC_MCR_SPEED_100 BIT(2) 438 #define MAC_MCR_FORCE_DPX BIT(1) 439 #define MAC_MCR_FORCE_LINK BIT(0) 440 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 441 442 /* Mac status registers */ 443 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 444 #define MAC_MSR_EEE1G BIT(7) 445 #define MAC_MSR_EEE100M BIT(6) 446 #define MAC_MSR_RX_FC BIT(5) 447 #define MAC_MSR_TX_FC BIT(4) 448 #define MAC_MSR_SPEED_1000 BIT(3) 449 #define MAC_MSR_SPEED_100 BIT(2) 450 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 451 #define MAC_MSR_DPX BIT(1) 452 #define MAC_MSR_LINK BIT(0) 453 454 /* TRGMII RXC control register */ 455 #define TRGMII_RCK_CTRL 0x10300 456 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 457 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 458 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 459 #define RXC_RST BIT(31) 460 #define RXC_DQSISEL BIT(30) 461 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 462 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 463 464 #define NUM_TRGMII_CTRL 5 465 466 /* TRGMII RXC control register */ 467 #define TRGMII_TCK_CTRL 0x10340 468 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 469 #define TXC_INV BIT(30) 470 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 471 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 472 473 /* TRGMII TX Drive Strength */ 474 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 475 #define TD_DM_DRVP(x) ((x) & 0xf) 476 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 477 478 /* TRGMII Interface mode register */ 479 #define INTF_MODE 0x10390 480 #define TRGMII_INTF_DIS BIT(0) 481 #define TRGMII_MODE BIT(1) 482 #define TRGMII_CENTRAL_ALIGNED BIT(2) 483 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 484 #define INTF_MODE_RGMII_10_100 0 485 486 /* GPIO port control registers for GMAC 2*/ 487 #define GPIO_OD33_CTRL8 0x4c0 488 #define GPIO_BIAS_CTRL 0xed0 489 #define GPIO_DRV_SEL10 0xf00 490 491 /* ethernet subsystem chip id register */ 492 #define ETHSYS_CHIPID0_3 0x0 493 #define ETHSYS_CHIPID4_7 0x4 494 #define MT7623_ETH 7623 495 #define MT7622_ETH 7622 496 #define MT7621_ETH 7621 497 498 /* ethernet system control register */ 499 #define ETHSYS_SYSCFG 0x10 500 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 501 502 /* ethernet subsystem config register */ 503 #define ETHSYS_SYSCFG0 0x14 504 #define SYSCFG0_GE_MASK 0x3 505 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 506 #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 507 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 508 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 509 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 510 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 511 512 513 /* ethernet subsystem clock register */ 514 #define ETHSYS_CLKCFG0 0x2c 515 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 516 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 517 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 518 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 519 520 /* ethernet reset control register */ 521 #define ETHSYS_RSTCTRL 0x34 522 #define RSTCTRL_FE BIT(6) 523 #define RSTCTRL_PPE0 BIT(31) 524 #define RSTCTRL_PPE0_V2 BIT(30) 525 #define RSTCTRL_PPE1 BIT(31) 526 #define RSTCTRL_ETH BIT(23) 527 528 /* ethernet reset check idle register */ 529 #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 530 531 /* ethernet dma channel agent map */ 532 #define ETHSYS_DMA_AG_MAP 0x408 533 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 534 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 535 #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 536 537 /* Infrasys subsystem config registers */ 538 #define INFRA_MISC2 0x70c 539 #define CO_QPHY_SEL BIT(0) 540 #define GEPHY_MAC_SEL BIT(1) 541 542 /* Top misc registers */ 543 #define USB_PHY_SWITCH_REG 0x218 544 #define QPHY_SEL_MASK GENMASK(1, 0) 545 #define SGMII_QPHY_SEL 0x2 546 547 /* MT7628/88 specific stuff */ 548 #define MT7628_PDMA_OFFSET 0x0800 549 #define MT7628_SDM_OFFSET 0x0c00 550 551 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 552 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 553 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 554 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 555 #define MT7628_PST_DTX_IDX0 BIT(0) 556 557 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 558 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 559 560 /* Counter / stat register */ 561 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 562 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 563 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 564 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 565 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 566 567 #define MTK_FE_CDM1_FSM 0x220 568 #define MTK_FE_CDM2_FSM 0x224 569 #define MTK_FE_CDM3_FSM 0x238 570 #define MTK_FE_CDM4_FSM 0x298 571 #define MTK_FE_CDM5_FSM 0x318 572 #define MTK_FE_CDM6_FSM 0x328 573 #define MTK_FE_GDM1_FSM 0x228 574 #define MTK_FE_GDM2_FSM 0x22C 575 576 #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100)) 577 578 struct mtk_rx_dma { 579 unsigned int rxd1; 580 unsigned int rxd2; 581 unsigned int rxd3; 582 unsigned int rxd4; 583 } __packed __aligned(4); 584 585 struct mtk_rx_dma_v2 { 586 unsigned int rxd1; 587 unsigned int rxd2; 588 unsigned int rxd3; 589 unsigned int rxd4; 590 unsigned int rxd5; 591 unsigned int rxd6; 592 unsigned int rxd7; 593 unsigned int rxd8; 594 } __packed __aligned(4); 595 596 struct mtk_tx_dma { 597 unsigned int txd1; 598 unsigned int txd2; 599 unsigned int txd3; 600 unsigned int txd4; 601 } __packed __aligned(4); 602 603 struct mtk_tx_dma_v2 { 604 unsigned int txd1; 605 unsigned int txd2; 606 unsigned int txd3; 607 unsigned int txd4; 608 unsigned int txd5; 609 unsigned int txd6; 610 unsigned int txd7; 611 unsigned int txd8; 612 } __packed __aligned(4); 613 614 struct mtk_eth; 615 struct mtk_mac; 616 617 struct mtk_xdp_stats { 618 u64 rx_xdp_redirect; 619 u64 rx_xdp_pass; 620 u64 rx_xdp_drop; 621 u64 rx_xdp_tx; 622 u64 rx_xdp_tx_errors; 623 u64 tx_xdp_xmit; 624 u64 tx_xdp_xmit_errors; 625 }; 626 627 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 628 * @stats_lock: make sure that stats operations are atomic 629 * @reg_offset: the status register offset of the SoC 630 * @syncp: the refcount 631 * 632 * All of the supported SoCs have hardware counters for traffic statistics. 633 * Whenever the status IRQ triggers we can read the latest stats from these 634 * counters and store them in this struct. 635 */ 636 struct mtk_hw_stats { 637 u64 tx_bytes; 638 u64 tx_packets; 639 u64 tx_skip; 640 u64 tx_collisions; 641 u64 rx_bytes; 642 u64 rx_packets; 643 u64 rx_overflow; 644 u64 rx_fcs_errors; 645 u64 rx_short_errors; 646 u64 rx_long_errors; 647 u64 rx_checksum_errors; 648 u64 rx_flow_control_packets; 649 650 struct mtk_xdp_stats xdp_stats; 651 652 spinlock_t stats_lock; 653 u32 reg_offset; 654 struct u64_stats_sync syncp; 655 }; 656 657 enum mtk_tx_flags { 658 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 659 * track how memory was allocated so that it can be freed properly. 660 */ 661 MTK_TX_FLAGS_SINGLE0 = 0x01, 662 MTK_TX_FLAGS_PAGE0 = 0x02, 663 }; 664 665 /* This enum allows us to identify how the clock is defined on the array of the 666 * clock in the order 667 */ 668 enum mtk_clks_map { 669 MTK_CLK_ETHIF, 670 MTK_CLK_SGMIITOP, 671 MTK_CLK_ESW, 672 MTK_CLK_GP0, 673 MTK_CLK_GP1, 674 MTK_CLK_GP2, 675 MTK_CLK_GP3, 676 MTK_CLK_XGP1, 677 MTK_CLK_XGP2, 678 MTK_CLK_XGP3, 679 MTK_CLK_CRYPTO, 680 MTK_CLK_FE, 681 MTK_CLK_TRGPLL, 682 MTK_CLK_SGMII_TX_250M, 683 MTK_CLK_SGMII_RX_250M, 684 MTK_CLK_SGMII_CDR_REF, 685 MTK_CLK_SGMII_CDR_FB, 686 MTK_CLK_SGMII2_TX_250M, 687 MTK_CLK_SGMII2_RX_250M, 688 MTK_CLK_SGMII2_CDR_REF, 689 MTK_CLK_SGMII2_CDR_FB, 690 MTK_CLK_SGMII_CK, 691 MTK_CLK_ETH2PLL, 692 MTK_CLK_WOCPU0, 693 MTK_CLK_WOCPU1, 694 MTK_CLK_NETSYS0, 695 MTK_CLK_NETSYS1, 696 MTK_CLK_ETHWARP_WOCPU2, 697 MTK_CLK_ETHWARP_WOCPU1, 698 MTK_CLK_ETHWARP_WOCPU0, 699 MTK_CLK_TOP_USXGMII_SBUS_0_SEL, 700 MTK_CLK_TOP_USXGMII_SBUS_1_SEL, 701 MTK_CLK_TOP_SGM_0_SEL, 702 MTK_CLK_TOP_SGM_1_SEL, 703 MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL, 704 MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL, 705 MTK_CLK_TOP_ETH_GMII_SEL, 706 MTK_CLK_TOP_ETH_REFCK_50M_SEL, 707 MTK_CLK_TOP_ETH_SYS_200M_SEL, 708 MTK_CLK_TOP_ETH_SYS_SEL, 709 MTK_CLK_TOP_ETH_XGMII_SEL, 710 MTK_CLK_TOP_ETH_MII_SEL, 711 MTK_CLK_TOP_NETSYS_SEL, 712 MTK_CLK_TOP_NETSYS_500M_SEL, 713 MTK_CLK_TOP_NETSYS_PAO_2X_SEL, 714 MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, 715 MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, 716 MTK_CLK_TOP_NETSYS_WARP_SEL, 717 MTK_CLK_MAX 718 }; 719 720 #define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 721 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ 722 BIT_ULL(MTK_CLK_TRGPLL)) 723 #define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 724 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ 725 BIT_ULL(MTK_CLK_GP2) | \ 726 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 727 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 728 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 729 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 730 BIT_ULL(MTK_CLK_SGMII_CK) | \ 731 BIT_ULL(MTK_CLK_ETH2PLL)) 732 #define MT7621_CLKS_BITMAP (0) 733 #define MT7628_CLKS_BITMAP (0) 734 #define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 735 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ 736 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \ 737 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 738 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 739 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 740 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 741 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 742 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 743 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 744 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ 745 BIT_ULL(MTK_CLK_SGMII_CK) | \ 746 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP)) 747 #define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ 748 BIT_ULL(MTK_CLK_GP1) | \ 749 BIT_ULL(MTK_CLK_WOCPU0) | \ 750 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 751 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 752 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 753 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 754 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 755 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 756 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 757 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ 758 BIT_ULL(MTK_CLK_SGMII_CK)) 759 #define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ 760 BIT_ULL(MTK_CLK_GP1) | \ 761 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \ 762 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 763 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 764 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 765 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 766 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 767 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 768 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 769 BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) 770 #define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ 771 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ 772 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ 773 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \ 774 BIT_ULL(MTK_CLK_CRYPTO) | \ 775 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 776 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 777 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 778 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 779 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \ 780 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \ 781 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \ 782 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \ 783 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \ 784 BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \ 785 BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \ 786 BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \ 787 BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \ 788 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ 789 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ 790 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ 791 BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ 792 BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ 793 BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ 794 BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ 795 BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ 796 BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ 797 BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ 798 BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ 799 BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL)) 800 801 enum mtk_dev_state { 802 MTK_HW_INIT, 803 MTK_RESETTING 804 }; 805 806 /* PSE Port Definition */ 807 enum mtk_pse_port { 808 PSE_ADMA_PORT = 0, 809 PSE_GDM1_PORT, 810 PSE_GDM2_PORT, 811 PSE_PPE0_PORT, 812 PSE_PPE1_PORT, 813 PSE_QDMA_TX_PORT, 814 PSE_QDMA_RX_PORT, 815 PSE_DROP_PORT, 816 PSE_WDMA0_PORT, 817 PSE_WDMA1_PORT, 818 PSE_TDMA_PORT, 819 PSE_NONE_PORT, 820 PSE_PPE2_PORT, 821 PSE_WDMA2_PORT, 822 PSE_EIP197_PORT, 823 PSE_GDM3_PORT, 824 PSE_PORT_MAX 825 }; 826 827 /* GMAC Identifier */ 828 enum mtk_gmac_id { 829 MTK_GMAC1_ID = 0, 830 MTK_GMAC2_ID, 831 MTK_GMAC3_ID, 832 MTK_GMAC_ID_MAX 833 }; 834 835 enum mtk_tx_buf_type { 836 MTK_TYPE_SKB, 837 MTK_TYPE_XDP_TX, 838 MTK_TYPE_XDP_NDO, 839 }; 840 841 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 842 * by the TX descriptor s 843 * @skb: The SKB pointer of the packet being sent 844 * @dma_addr0: The base addr of the first segment 845 * @dma_len0: The length of the first segment 846 * @dma_addr1: The base addr of the second segment 847 * @dma_len1: The length of the second segment 848 */ 849 struct mtk_tx_buf { 850 enum mtk_tx_buf_type type; 851 void *data; 852 853 u16 mac_id; 854 u16 flags; 855 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 856 DEFINE_DMA_UNMAP_LEN(dma_len0); 857 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 858 DEFINE_DMA_UNMAP_LEN(dma_len1); 859 }; 860 861 /* struct mtk_tx_ring - This struct holds info describing a TX ring 862 * @dma: The descriptor ring 863 * @buf: The memory pointed at by the ring 864 * @phys: The physical addr of tx_buf 865 * @next_free: Pointer to the next free descriptor 866 * @last_free: Pointer to the last free descriptor 867 * @last_free_ptr: Hardware pointer value of the last free descriptor 868 * @thresh: The threshold of minimum amount of free descriptors 869 * @free_count: QDMA uses a linked list. Track how many free descriptors 870 * are present 871 */ 872 struct mtk_tx_ring { 873 void *dma; 874 struct mtk_tx_buf *buf; 875 dma_addr_t phys; 876 struct mtk_tx_dma *next_free; 877 struct mtk_tx_dma *last_free; 878 u32 last_free_ptr; 879 u16 thresh; 880 atomic_t free_count; 881 int dma_size; 882 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 883 dma_addr_t phys_pdma; 884 int cpu_idx; 885 }; 886 887 /* PDMA rx ring mode */ 888 enum mtk_rx_flags { 889 MTK_RX_FLAGS_NORMAL = 0, 890 MTK_RX_FLAGS_HWLRO, 891 MTK_RX_FLAGS_QDMA, 892 }; 893 894 /* struct mtk_rx_ring - This struct holds info describing a RX ring 895 * @dma: The descriptor ring 896 * @data: The memory pointed at by the ring 897 * @phys: The physical addr of rx_buf 898 * @frag_size: How big can each fragment be 899 * @buf_size: The size of each packet buffer 900 * @calc_idx: The current head of ring 901 */ 902 struct mtk_rx_ring { 903 void *dma; 904 u8 **data; 905 dma_addr_t phys; 906 u16 frag_size; 907 u16 buf_size; 908 u16 dma_size; 909 bool calc_idx_update; 910 u16 calc_idx; 911 u32 crx_idx_reg; 912 /* page_pool */ 913 struct page_pool *page_pool; 914 struct xdp_rxq_info xdp_q; 915 }; 916 917 enum mkt_eth_capabilities { 918 MTK_RGMII_BIT = 0, 919 MTK_TRGMII_BIT, 920 MTK_SGMII_BIT, 921 MTK_ESW_BIT, 922 MTK_GEPHY_BIT, 923 MTK_MUX_BIT, 924 MTK_INFRA_BIT, 925 MTK_SHARED_SGMII_BIT, 926 MTK_HWLRO_BIT, 927 MTK_SHARED_INT_BIT, 928 MTK_TRGMII_MT7621_CLK_BIT, 929 MTK_QDMA_BIT, 930 MTK_SOC_MT7628_BIT, 931 MTK_RSTCTRL_PPE1_BIT, 932 MTK_U3_COPHY_V2_BIT, 933 934 /* MUX BITS*/ 935 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 936 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 937 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 938 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 939 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 940 941 /* PATH BITS */ 942 MTK_ETH_PATH_GMAC1_RGMII_BIT, 943 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 944 MTK_ETH_PATH_GMAC1_SGMII_BIT, 945 MTK_ETH_PATH_GMAC2_RGMII_BIT, 946 MTK_ETH_PATH_GMAC2_SGMII_BIT, 947 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 948 MTK_ETH_PATH_GDM1_ESW_BIT, 949 }; 950 951 /* Supported hardware group on SoCs */ 952 #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) 953 #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) 954 #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) 955 #define MTK_ESW BIT_ULL(MTK_ESW_BIT) 956 #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) 957 #define MTK_MUX BIT_ULL(MTK_MUX_BIT) 958 #define MTK_INFRA BIT_ULL(MTK_INFRA_BIT) 959 #define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT) 960 #define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT) 961 #define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT) 962 #define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT) 963 #define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) 964 #define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) 965 #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) 966 #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) 967 968 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 969 BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 970 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 971 BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 972 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 973 BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 974 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 975 BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 976 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 977 BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 978 979 /* Supported path present on SoCs */ 980 #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) 981 #define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 982 #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) 983 #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) 984 #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) 985 #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 986 #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) 987 988 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 989 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 990 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 991 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 992 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 993 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 994 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 995 996 /* MUXes present on SoCs */ 997 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 998 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 999 1000 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 1001 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 1002 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 1003 1004 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 1005 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 1006 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 1007 1008 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 1009 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 1010 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 1011 MTK_SHARED_SGMII) 1012 1013 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 1014 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 1015 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 1016 1017 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 1018 1019 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 1020 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 1021 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 1022 1023 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 1024 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 1025 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 1026 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 1027 1028 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 1029 MTK_QDMA) 1030 1031 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 1032 1033 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 1034 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 1035 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 1036 MTK_MUX_U3_GMAC2_TO_QPHY | \ 1037 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 1038 1039 #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 1040 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 1041 MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ 1042 MTK_RSTCTRL_PPE1) 1043 1044 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 1045 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 1046 MTK_RSTCTRL_PPE1) 1047 1048 #define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1) 1049 1050 struct mtk_tx_dma_desc_info { 1051 dma_addr_t addr; 1052 u32 size; 1053 u16 vlan_tci; 1054 u16 qid; 1055 u8 gso:1; 1056 u8 csum:1; 1057 u8 vlan:1; 1058 u8 first:1; 1059 u8 last:1; 1060 }; 1061 1062 struct mtk_reg_map { 1063 u32 tx_irq_mask; 1064 u32 tx_irq_status; 1065 struct { 1066 u32 rx_ptr; /* rx base pointer */ 1067 u32 rx_cnt_cfg; /* rx max count configuration */ 1068 u32 pcrx_ptr; /* rx cpu pointer */ 1069 u32 glo_cfg; /* global configuration */ 1070 u32 rst_idx; /* reset index */ 1071 u32 delay_irq; /* delay interrupt */ 1072 u32 irq_status; /* interrupt status */ 1073 u32 irq_mask; /* interrupt mask */ 1074 u32 adma_rx_dbg0; 1075 u32 int_grp; 1076 } pdma; 1077 struct { 1078 u32 qtx_cfg; /* tx queue configuration */ 1079 u32 qtx_sch; /* tx queue scheduler configuration */ 1080 u32 rx_ptr; /* rx base pointer */ 1081 u32 rx_cnt_cfg; /* rx max count configuration */ 1082 u32 qcrx_ptr; /* rx cpu pointer */ 1083 u32 glo_cfg; /* global configuration */ 1084 u32 rst_idx; /* reset index */ 1085 u32 delay_irq; /* delay interrupt */ 1086 u32 fc_th; /* flow control */ 1087 u32 int_grp; 1088 u32 hred; /* interrupt mask */ 1089 u32 ctx_ptr; /* tx acquire cpu pointer */ 1090 u32 dtx_ptr; /* tx acquire dma pointer */ 1091 u32 crx_ptr; /* tx release cpu pointer */ 1092 u32 drx_ptr; /* tx release dma pointer */ 1093 u32 fq_head; /* fq head pointer */ 1094 u32 fq_tail; /* fq tail pointer */ 1095 u32 fq_count; /* fq free page count */ 1096 u32 fq_blen; /* fq free page buffer length */ 1097 u32 tx_sch_rate; /* tx scheduler rate control registers */ 1098 } qdma; 1099 u32 gdm1_cnt; 1100 u32 gdma_to_ppe; 1101 u32 ppe_base; 1102 u32 wdma_base[2]; 1103 u32 pse_iq_sta; 1104 u32 pse_oq_sta; 1105 }; 1106 1107 /* struct mtk_eth_data - This is the structure holding all differences 1108 * among various plaforms 1109 * @reg_map Soc register map. 1110 * @ana_rgc3: The offset for register ANA_RGC3 related to 1111 * sgmiisys syscon 1112 * @caps Flags shown the extra capability for the SoC 1113 * @hw_features Flags shown HW features 1114 * @required_clks Flags shown the bitmap for required clocks on 1115 * the target SoC 1116 * @required_pctl A bool value to show whether the SoC requires 1117 * the extra setup for those pins used by GMAC. 1118 * @hash_offset Flow table hash offset. 1119 * @version SoC version. 1120 * @foe_entry_size Foe table entry size. 1121 * @has_accounting Bool indicating support for accounting of 1122 * offloaded flows. 1123 * @txd_size Tx DMA descriptor size. 1124 * @rxd_size Rx DMA descriptor size. 1125 * @rx_irq_done_mask Rx irq done register mask. 1126 * @rx_dma_l4_valid Rx DMA valid register mask. 1127 * @dma_max_len Max DMA tx/rx buffer length. 1128 * @dma_len_offset Tx/Rx DMA length field offset. 1129 */ 1130 struct mtk_soc_data { 1131 const struct mtk_reg_map *reg_map; 1132 u32 ana_rgc3; 1133 u64 caps; 1134 u64 required_clks; 1135 bool required_pctl; 1136 u8 offload_version; 1137 u8 hash_offset; 1138 u8 version; 1139 u16 foe_entry_size; 1140 netdev_features_t hw_features; 1141 bool has_accounting; 1142 bool disable_pll_modes; 1143 struct { 1144 u32 txd_size; 1145 u32 rxd_size; 1146 u32 rx_irq_done_mask; 1147 u32 rx_dma_l4_valid; 1148 u32 dma_max_len; 1149 u32 dma_len_offset; 1150 } txrx; 1151 }; 1152 1153 #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) 1154 1155 /* currently no SoC has more than 3 macs */ 1156 #define MTK_MAX_DEVS 3 1157 1158 /* struct mtk_eth - This is the main datasructure for holding the state 1159 * of the driver 1160 * @dev: The device pointer 1161 * @dev: The device pointer used for dma mapping/alloc 1162 * @base: The mapped register i/o base 1163 * @page_lock: Make sure that register operations are atomic 1164 * @tx_irq__lock: Make sure that IRQ register operations are atomic 1165 * @rx_irq__lock: Make sure that IRQ register operations are atomic 1166 * @dim_lock: Make sure that Net DIM operations are atomic 1167 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 1168 * dummy for NAPI to work 1169 * @netdev: The netdev instances 1170 * @mac: Each netdev is linked to a physical MAC 1171 * @irq: The IRQ that we are using 1172 * @msg_enable: Ethtool msg level 1173 * @ethsys: The register map pointing at the range used to setup 1174 * MII modes 1175 * @infra: The register map pointing at the range used to setup 1176 * SGMII and GePHY path 1177 * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances 1178 * @pctl: The register map pointing at the range used to setup 1179 * GMAC port drive/slew values 1180 * @dma_refcnt: track how many netdevs are using the DMA engine 1181 * @tx_ring: Pointer to the memory holding info about the TX ring 1182 * @rx_ring: Pointer to the memory holding info about the RX ring 1183 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 1184 * @tx_napi: The TX NAPI struct 1185 * @rx_napi: The RX NAPI struct 1186 * @rx_events: Net DIM RX event counter 1187 * @rx_packets: Net DIM RX packet counter 1188 * @rx_bytes: Net DIM RX byte counter 1189 * @rx_dim: Net DIM RX context 1190 * @tx_events: Net DIM TX event counter 1191 * @tx_packets: Net DIM TX packet counter 1192 * @tx_bytes: Net DIM TX byte counter 1193 * @tx_dim: Net DIM TX context 1194 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1195 * @phy_scratch_ring: physical address of scratch_ring 1196 * @scratch_head: The scratch memory that scratch_ring points to. 1197 * @clks: clock array for all clocks required 1198 * @mii_bus: If there is a bus we need to create an instance for it 1199 * @pending_work: The workqueue used to reset the dma ring 1200 * @state: Initialization and runtime state of the device 1201 * @soc: Holding specific data among vaious SoCs 1202 */ 1203 1204 struct mtk_eth { 1205 struct device *dev; 1206 struct device *dma_dev; 1207 void __iomem *base; 1208 spinlock_t page_lock; 1209 spinlock_t tx_irq_lock; 1210 spinlock_t rx_irq_lock; 1211 struct net_device dummy_dev; 1212 struct net_device *netdev[MTK_MAX_DEVS]; 1213 struct mtk_mac *mac[MTK_MAX_DEVS]; 1214 int irq[3]; 1215 u32 msg_enable; 1216 unsigned long sysclk; 1217 struct regmap *ethsys; 1218 struct regmap *infra; 1219 struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS]; 1220 struct regmap *pctl; 1221 bool hwlro; 1222 refcount_t dma_refcnt; 1223 struct mtk_tx_ring tx_ring; 1224 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 1225 struct mtk_rx_ring rx_ring_qdma; 1226 struct napi_struct tx_napi; 1227 struct napi_struct rx_napi; 1228 void *scratch_ring; 1229 dma_addr_t phy_scratch_ring; 1230 void *scratch_head; 1231 struct clk *clks[MTK_CLK_MAX]; 1232 1233 struct mii_bus *mii_bus; 1234 struct work_struct pending_work; 1235 unsigned long state; 1236 1237 const struct mtk_soc_data *soc; 1238 1239 spinlock_t dim_lock; 1240 1241 u32 rx_events; 1242 u32 rx_packets; 1243 u32 rx_bytes; 1244 struct dim rx_dim; 1245 1246 u32 tx_events; 1247 u32 tx_packets; 1248 u32 tx_bytes; 1249 struct dim tx_dim; 1250 1251 int ip_align; 1252 1253 struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS]; 1254 1255 struct mtk_ppe *ppe[2]; 1256 struct rhashtable flow_table; 1257 1258 struct bpf_prog __rcu *prog; 1259 1260 struct { 1261 struct delayed_work monitor_work; 1262 u32 wdidx; 1263 u8 wdma_hang_count; 1264 u8 qdma_hang_count; 1265 u8 adma_hang_count; 1266 } reset; 1267 }; 1268 1269 /* struct mtk_mac - the structure that holds the info about the MACs of the 1270 * SoC 1271 * @id: The number of the MAC 1272 * @interface: Interface mode kept for detecting change in hw settings 1273 * @of_node: Our devicetree node 1274 * @hw: Backpointer to our main datastruture 1275 * @hw_stats: Packet statistics counter 1276 */ 1277 struct mtk_mac { 1278 int id; 1279 phy_interface_t interface; 1280 int speed; 1281 struct device_node *of_node; 1282 struct phylink *phylink; 1283 struct phylink_config phylink_config; 1284 struct mtk_eth *hw; 1285 struct mtk_hw_stats *hw_stats; 1286 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1287 int hwlro_ip_cnt; 1288 unsigned int syscfg0; 1289 struct notifier_block device_notifier; 1290 }; 1291 1292 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1293 extern const struct of_device_id of_mtk_match[]; 1294 1295 static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) 1296 { 1297 return eth->soc->version == 1; 1298 } 1299 1300 static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth) 1301 { 1302 return eth->soc->version > 1; 1303 } 1304 1305 static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth) 1306 { 1307 return eth->soc->version > 2; 1308 } 1309 1310 static inline struct mtk_foe_entry * 1311 mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 1312 { 1313 const struct mtk_soc_data *soc = ppe->eth->soc; 1314 1315 return ppe->foe_table + hash * soc->foe_entry_size; 1316 } 1317 1318 static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 1319 { 1320 if (mtk_is_netsys_v2_or_greater(eth)) 1321 return MTK_FOE_IB1_BIND_TIMESTAMP_V2; 1322 1323 return MTK_FOE_IB1_BIND_TIMESTAMP; 1324 } 1325 1326 static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 1327 { 1328 if (mtk_is_netsys_v2_or_greater(eth)) 1329 return MTK_FOE_IB1_BIND_PPPOE_V2; 1330 1331 return MTK_FOE_IB1_BIND_PPPOE; 1332 } 1333 1334 static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 1335 { 1336 if (mtk_is_netsys_v2_or_greater(eth)) 1337 return MTK_FOE_IB1_BIND_VLAN_TAG_V2; 1338 1339 return MTK_FOE_IB1_BIND_VLAN_TAG; 1340 } 1341 1342 static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 1343 { 1344 if (mtk_is_netsys_v2_or_greater(eth)) 1345 return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; 1346 1347 return MTK_FOE_IB1_BIND_VLAN_LAYER; 1348 } 1349 1350 static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1351 { 1352 if (mtk_is_netsys_v2_or_greater(eth)) 1353 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1354 1355 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1356 } 1357 1358 static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1359 { 1360 if (mtk_is_netsys_v2_or_greater(eth)) 1361 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1362 1363 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1364 } 1365 1366 static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 1367 { 1368 if (mtk_is_netsys_v2_or_greater(eth)) 1369 return MTK_FOE_IB1_PACKET_TYPE_V2; 1370 1371 return MTK_FOE_IB1_PACKET_TYPE; 1372 } 1373 1374 static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 1375 { 1376 if (mtk_is_netsys_v2_or_greater(eth)) 1377 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); 1378 1379 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); 1380 } 1381 1382 static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) 1383 { 1384 if (mtk_is_netsys_v2_or_greater(eth)) 1385 return MTK_FOE_IB2_MULTICAST_V2; 1386 1387 return MTK_FOE_IB2_MULTICAST; 1388 } 1389 1390 /* read the hardware status register */ 1391 void mtk_stats_update_mac(struct mtk_mac *mac); 1392 1393 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1394 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1395 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg); 1396 1397 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 1398 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 1399 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 1400 1401 int mtk_eth_offload_init(struct mtk_eth *eth); 1402 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1403 void *type_data); 1404 int mtk_flow_offload_cmd(struct mtk_eth *eth, struct flow_cls_offload *cls, 1405 int ppe_index); 1406 void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list); 1407 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1408 1409 1410 #endif /* MTK_ETH_H */ 1411