1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 #include <linux/rhashtable.h> 19 #include "mtk_ppe.h" 20 21 #define MTK_QDMA_PAGE_SIZE 2048 22 #define MTK_MAX_RX_LENGTH 1536 23 #define MTK_MAX_RX_LENGTH_2K 2048 24 #define MTK_TX_DMA_BUF_LEN 0x3fff 25 #define MTK_DMA_SIZE 256 26 #define MTK_NAPI_WEIGHT 64 27 #define MTK_MAC_COUNT 2 28 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 29 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 30 #define MTK_DMA_DUMMY_DESC 0xffffffff 31 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 32 NETIF_MSG_PROBE | \ 33 NETIF_MSG_LINK | \ 34 NETIF_MSG_TIMER | \ 35 NETIF_MSG_IFDOWN | \ 36 NETIF_MSG_IFUP | \ 37 NETIF_MSG_RX_ERR | \ 38 NETIF_MSG_TX_ERR) 39 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 40 NETIF_F_RXCSUM | \ 41 NETIF_F_HW_VLAN_CTAG_TX | \ 42 NETIF_F_HW_VLAN_CTAG_RX | \ 43 NETIF_F_SG | NETIF_F_TSO | \ 44 NETIF_F_TSO6 | \ 45 NETIF_F_IPV6_CSUM |\ 46 NETIF_F_HW_TC) 47 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 48 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 49 50 #define MTK_MAX_RX_RING_NUM 4 51 #define MTK_HW_LRO_DMA_SIZE 8 52 53 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 54 #define MTK_MAX_LRO_IP_CNT 2 55 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 56 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 57 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 58 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 59 #define MTK_HW_LRO_MAX_AGG_CNT 64 60 #define MTK_HW_LRO_BW_THRE 3000 61 #define MTK_HW_LRO_REPLACE_DELTA 1000 62 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 63 64 /* Frame Engine Global Reset Register */ 65 #define MTK_RST_GL 0x04 66 #define RST_GL_PSE BIT(0) 67 68 /* Frame Engine Interrupt Status Register */ 69 #define MTK_INT_STATUS2 0x08 70 #define MTK_GDM1_AF BIT(28) 71 #define MTK_GDM2_AF BIT(29) 72 73 /* PDMA HW LRO Alter Flow Timer Register */ 74 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 75 76 /* Frame Engine Interrupt Grouping Register */ 77 #define MTK_FE_INT_GRP 0x20 78 79 /* CDMP Ingress Control Register */ 80 #define MTK_CDMQ_IG_CTRL 0x1400 81 #define MTK_CDMQ_STAG_EN BIT(0) 82 83 /* CDMP Exgress Control Register */ 84 #define MTK_CDMP_EG_CTRL 0x404 85 86 /* GDM Exgress Control Register */ 87 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 88 #define MTK_GDMA_SPECIAL_TAG BIT(24) 89 #define MTK_GDMA_ICS_EN BIT(22) 90 #define MTK_GDMA_TCS_EN BIT(21) 91 #define MTK_GDMA_UCS_EN BIT(20) 92 #define MTK_GDMA_TO_PDMA 0x0 93 #define MTK_GDMA_TO_PPE 0x4444 94 #define MTK_GDMA_DROP_ALL 0x7777 95 96 /* Unicast Filter MAC Address Register - Low */ 97 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 98 99 /* Unicast Filter MAC Address Register - High */ 100 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 101 102 /* PDMA RX Base Pointer Register */ 103 #define MTK_PRX_BASE_PTR0 0x900 104 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 105 106 /* PDMA RX Maximum Count Register */ 107 #define MTK_PRX_MAX_CNT0 0x904 108 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 109 110 /* PDMA RX CPU Pointer Register */ 111 #define MTK_PRX_CRX_IDX0 0x908 112 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 113 114 /* PDMA HW LRO Control Registers */ 115 #define MTK_PDMA_LRO_CTRL_DW0 0x980 116 #define MTK_LRO_EN BIT(0) 117 #define MTK_L3_CKS_UPD_EN BIT(7) 118 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 119 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 120 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 121 122 #define MTK_PDMA_LRO_CTRL_DW1 0x984 123 #define MTK_PDMA_LRO_CTRL_DW2 0x988 124 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 125 #define MTK_ADMA_MODE BIT(15) 126 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 127 128 /* PDMA Global Configuration Register */ 129 #define MTK_PDMA_GLO_CFG 0xa04 130 #define MTK_MULTI_EN BIT(10) 131 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 132 133 /* PDMA Reset Index Register */ 134 #define MTK_PDMA_RST_IDX 0xa08 135 #define MTK_PST_DRX_IDX0 BIT(16) 136 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 137 138 /* PDMA Delay Interrupt Register */ 139 #define MTK_PDMA_DELAY_INT 0xa0c 140 #define MTK_PDMA_DELAY_RX_EN BIT(15) 141 #define MTK_PDMA_DELAY_RX_PINT 4 142 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 143 #define MTK_PDMA_DELAY_RX_PTIME 4 144 #define MTK_PDMA_DELAY_RX_DELAY \ 145 (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ 146 (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) 147 148 /* PDMA Interrupt Status Register */ 149 #define MTK_PDMA_INT_STATUS 0xa20 150 151 /* PDMA Interrupt Mask Register */ 152 #define MTK_PDMA_INT_MASK 0xa28 153 154 /* PDMA HW LRO Alter Flow Delta Register */ 155 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 156 157 /* PDMA Interrupt grouping registers */ 158 #define MTK_PDMA_INT_GRP1 0xa50 159 #define MTK_PDMA_INT_GRP2 0xa54 160 161 /* PDMA HW LRO IP Setting Registers */ 162 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 163 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 164 #define MTK_RING_MYIP_VLD BIT(9) 165 166 /* PDMA HW LRO Ring Control Registers */ 167 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 168 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 169 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 170 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 171 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 172 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 173 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 174 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 175 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 176 #define MTK_RING_VLD BIT(8) 177 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 178 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 179 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 180 181 /* QDMA TX Queue Configuration Registers */ 182 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 183 #define QDMA_RES_THRES 4 184 185 /* QDMA TX Queue Scheduler Registers */ 186 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 187 188 /* QDMA RX Base Pointer Register */ 189 #define MTK_QRX_BASE_PTR0 0x1900 190 191 /* QDMA RX Maximum Count Register */ 192 #define MTK_QRX_MAX_CNT0 0x1904 193 194 /* QDMA RX CPU Pointer Register */ 195 #define MTK_QRX_CRX_IDX0 0x1908 196 197 /* QDMA RX DMA Pointer Register */ 198 #define MTK_QRX_DRX_IDX0 0x190C 199 200 /* QDMA Global Configuration Register */ 201 #define MTK_QDMA_GLO_CFG 0x1A04 202 #define MTK_RX_2B_OFFSET BIT(31) 203 #define MTK_RX_BT_32DWORDS (3 << 11) 204 #define MTK_NDP_CO_PRO BIT(10) 205 #define MTK_TX_WB_DDONE BIT(6) 206 #define MTK_DMA_SIZE_16DWORDS (2 << 4) 207 #define MTK_RX_DMA_BUSY BIT(3) 208 #define MTK_TX_DMA_BUSY BIT(1) 209 #define MTK_RX_DMA_EN BIT(2) 210 #define MTK_TX_DMA_EN BIT(0) 211 #define MTK_DMA_BUSY_TIMEOUT HZ 212 213 /* QDMA Reset Index Register */ 214 #define MTK_QDMA_RST_IDX 0x1A08 215 216 /* QDMA Delay Interrupt Register */ 217 #define MTK_QDMA_DELAY_INT 0x1A0C 218 219 /* QDMA Flow Control Register */ 220 #define MTK_QDMA_FC_THRES 0x1A10 221 #define FC_THRES_DROP_MODE BIT(20) 222 #define FC_THRES_DROP_EN (7 << 16) 223 #define FC_THRES_MIN 0x4444 224 225 /* QDMA Interrupt Status Register */ 226 #define MTK_QDMA_INT_STATUS 0x1A18 227 #define MTK_RX_DONE_DLY BIT(30) 228 #define MTK_RX_DONE_INT3 BIT(19) 229 #define MTK_RX_DONE_INT2 BIT(18) 230 #define MTK_RX_DONE_INT1 BIT(17) 231 #define MTK_RX_DONE_INT0 BIT(16) 232 #define MTK_TX_DONE_INT3 BIT(3) 233 #define MTK_TX_DONE_INT2 BIT(2) 234 #define MTK_TX_DONE_INT1 BIT(1) 235 #define MTK_TX_DONE_INT0 BIT(0) 236 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 237 #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 238 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 239 240 /* QDMA Interrupt grouping registers */ 241 #define MTK_QDMA_INT_GRP1 0x1a20 242 #define MTK_QDMA_INT_GRP2 0x1a24 243 #define MTK_RLS_DONE_INT BIT(0) 244 245 /* QDMA Interrupt Status Register */ 246 #define MTK_QDMA_INT_MASK 0x1A1C 247 248 /* QDMA Interrupt Mask Register */ 249 #define MTK_QDMA_HRED2 0x1A44 250 251 /* QDMA TX Forward CPU Pointer Register */ 252 #define MTK_QTX_CTX_PTR 0x1B00 253 254 /* QDMA TX Forward DMA Pointer Register */ 255 #define MTK_QTX_DTX_PTR 0x1B04 256 257 /* QDMA TX Release CPU Pointer Register */ 258 #define MTK_QTX_CRX_PTR 0x1B10 259 260 /* QDMA TX Release DMA Pointer Register */ 261 #define MTK_QTX_DRX_PTR 0x1B14 262 263 /* QDMA FQ Head Pointer Register */ 264 #define MTK_QDMA_FQ_HEAD 0x1B20 265 266 /* QDMA FQ Head Pointer Register */ 267 #define MTK_QDMA_FQ_TAIL 0x1B24 268 269 /* QDMA FQ Free Page Counter Register */ 270 #define MTK_QDMA_FQ_CNT 0x1B28 271 272 /* QDMA FQ Free Page Buffer Length Register */ 273 #define MTK_QDMA_FQ_BLEN 0x1B2C 274 275 /* GMA1 Received Good Byte Count Register */ 276 #define MTK_GDM1_TX_GBCNT 0x2400 277 #define MTK_STAT_OFFSET 0x40 278 279 /* QDMA descriptor txd4 */ 280 #define TX_DMA_CHKSUM (0x7 << 29) 281 #define TX_DMA_TSO BIT(28) 282 #define TX_DMA_FPORT_SHIFT 25 283 #define TX_DMA_FPORT_MASK 0x7 284 #define TX_DMA_INS_VLAN BIT(16) 285 286 /* QDMA descriptor txd3 */ 287 #define TX_DMA_OWNER_CPU BIT(31) 288 #define TX_DMA_LS0 BIT(30) 289 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 290 #define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN) 291 #define TX_DMA_SWC BIT(14) 292 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 293 294 /* PDMA on MT7628 */ 295 #define TX_DMA_DONE BIT(31) 296 #define TX_DMA_LS1 BIT(14) 297 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 298 299 /* QDMA descriptor rxd2 */ 300 #define RX_DMA_DONE BIT(31) 301 #define RX_DMA_LSO BIT(30) 302 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 303 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 304 305 /* QDMA descriptor rxd3 */ 306 #define RX_DMA_VID(_x) ((_x) & 0xfff) 307 308 /* QDMA descriptor rxd4 */ 309 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 310 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 311 #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 312 #define MTK_RXD4_ALG GENMASK(31, 22) 313 314 /* QDMA descriptor rxd4 */ 315 #define RX_DMA_L4_VALID BIT(24) 316 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 317 #define RX_DMA_FPORT_SHIFT 19 318 #define RX_DMA_FPORT_MASK 0x7 319 #define RX_DMA_SPECIAL_TAG BIT(22) 320 321 /* PHY Indirect Access Control registers */ 322 #define MTK_PHY_IAC 0x10004 323 #define PHY_IAC_ACCESS BIT(31) 324 #define PHY_IAC_READ BIT(19) 325 #define PHY_IAC_WRITE BIT(18) 326 #define PHY_IAC_START BIT(16) 327 #define PHY_IAC_ADDR_SHIFT 20 328 #define PHY_IAC_REG_SHIFT 25 329 #define PHY_IAC_TIMEOUT HZ 330 331 #define MTK_MAC_MISC 0x1000c 332 #define MTK_MUX_TO_ESW BIT(0) 333 334 /* Mac control registers */ 335 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 336 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 337 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 338 #define MAC_MCR_MAX_RX_1518 0x0 339 #define MAC_MCR_MAX_RX_1536 0x1 340 #define MAC_MCR_MAX_RX_1552 0x2 341 #define MAC_MCR_MAX_RX_2048 0x3 342 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 343 #define MAC_MCR_FORCE_MODE BIT(15) 344 #define MAC_MCR_TX_EN BIT(14) 345 #define MAC_MCR_RX_EN BIT(13) 346 #define MAC_MCR_BACKOFF_EN BIT(9) 347 #define MAC_MCR_BACKPR_EN BIT(8) 348 #define MAC_MCR_FORCE_RX_FC BIT(5) 349 #define MAC_MCR_FORCE_TX_FC BIT(4) 350 #define MAC_MCR_SPEED_1000 BIT(3) 351 #define MAC_MCR_SPEED_100 BIT(2) 352 #define MAC_MCR_FORCE_DPX BIT(1) 353 #define MAC_MCR_FORCE_LINK BIT(0) 354 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 355 356 /* Mac status registers */ 357 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 358 #define MAC_MSR_EEE1G BIT(7) 359 #define MAC_MSR_EEE100M BIT(6) 360 #define MAC_MSR_RX_FC BIT(5) 361 #define MAC_MSR_TX_FC BIT(4) 362 #define MAC_MSR_SPEED_1000 BIT(3) 363 #define MAC_MSR_SPEED_100 BIT(2) 364 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 365 #define MAC_MSR_DPX BIT(1) 366 #define MAC_MSR_LINK BIT(0) 367 368 /* TRGMII RXC control register */ 369 #define TRGMII_RCK_CTRL 0x10300 370 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 371 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 372 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 373 #define RXC_RST BIT(31) 374 #define RXC_DQSISEL BIT(30) 375 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 376 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 377 378 #define NUM_TRGMII_CTRL 5 379 380 /* TRGMII RXC control register */ 381 #define TRGMII_TCK_CTRL 0x10340 382 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 383 #define TXC_INV BIT(30) 384 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 385 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 386 387 /* TRGMII TX Drive Strength */ 388 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 389 #define TD_DM_DRVP(x) ((x) & 0xf) 390 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 391 392 /* TRGMII Interface mode register */ 393 #define INTF_MODE 0x10390 394 #define TRGMII_INTF_DIS BIT(0) 395 #define TRGMII_MODE BIT(1) 396 #define TRGMII_CENTRAL_ALIGNED BIT(2) 397 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 398 #define INTF_MODE_RGMII_10_100 0 399 400 /* GPIO port control registers for GMAC 2*/ 401 #define GPIO_OD33_CTRL8 0x4c0 402 #define GPIO_BIAS_CTRL 0xed0 403 #define GPIO_DRV_SEL10 0xf00 404 405 /* ethernet subsystem chip id register */ 406 #define ETHSYS_CHIPID0_3 0x0 407 #define ETHSYS_CHIPID4_7 0x4 408 #define MT7623_ETH 7623 409 #define MT7622_ETH 7622 410 #define MT7621_ETH 7621 411 412 /* ethernet system control register */ 413 #define ETHSYS_SYSCFG 0x10 414 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 415 416 /* ethernet subsystem config register */ 417 #define ETHSYS_SYSCFG0 0x14 418 #define SYSCFG0_GE_MASK 0x3 419 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 420 #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 421 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 422 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 423 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 424 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 425 426 427 /* ethernet subsystem clock register */ 428 #define ETHSYS_CLKCFG0 0x2c 429 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 430 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 431 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 432 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 433 434 /* ethernet reset control register */ 435 #define ETHSYS_RSTCTRL 0x34 436 #define RSTCTRL_FE BIT(6) 437 #define RSTCTRL_PPE BIT(31) 438 439 /* SGMII subsystem config registers */ 440 /* Register to auto-negotiation restart */ 441 #define SGMSYS_PCS_CONTROL_1 0x0 442 #define SGMII_AN_RESTART BIT(9) 443 #define SGMII_ISOLATE BIT(10) 444 #define SGMII_AN_ENABLE BIT(12) 445 #define SGMII_LINK_STATYS BIT(18) 446 #define SGMII_AN_ABILITY BIT(19) 447 #define SGMII_AN_COMPLETE BIT(21) 448 #define SGMII_PCS_FAULT BIT(23) 449 #define SGMII_AN_EXPANSION_CLR BIT(30) 450 451 /* Register to programmable link timer, the unit in 2 * 8ns */ 452 #define SGMSYS_PCS_LINK_TIMER 0x18 453 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 454 455 /* Register to control remote fault */ 456 #define SGMSYS_SGMII_MODE 0x20 457 #define SGMII_IF_MODE_BIT0 BIT(0) 458 #define SGMII_SPEED_DUPLEX_AN BIT(1) 459 #define SGMII_SPEED_10 0x0 460 #define SGMII_SPEED_100 BIT(2) 461 #define SGMII_SPEED_1000 BIT(3) 462 #define SGMII_DUPLEX_FULL BIT(4) 463 #define SGMII_IF_MODE_BIT5 BIT(5) 464 #define SGMII_REMOTE_FAULT_DIS BIT(8) 465 #define SGMII_CODE_SYNC_SET_VAL BIT(9) 466 #define SGMII_CODE_SYNC_SET_EN BIT(10) 467 #define SGMII_SEND_AN_ERROR_EN BIT(11) 468 #define SGMII_IF_MODE_MASK GENMASK(5, 1) 469 470 /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 471 #define SGMSYS_ANA_RG_CS3 0x2028 472 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 473 #define RG_PHY_SPEED_1_25G 0x0 474 #define RG_PHY_SPEED_3_125G BIT(2) 475 476 /* Register to power up QPHY */ 477 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 478 #define SGMII_PHYA_PWD BIT(4) 479 480 /* Infrasys subsystem config registers */ 481 #define INFRA_MISC2 0x70c 482 #define CO_QPHY_SEL BIT(0) 483 #define GEPHY_MAC_SEL BIT(1) 484 485 /* MT7628/88 specific stuff */ 486 #define MT7628_PDMA_OFFSET 0x0800 487 #define MT7628_SDM_OFFSET 0x0c00 488 489 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 490 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 491 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 492 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 493 #define MT7628_PST_DTX_IDX0 BIT(0) 494 495 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 496 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 497 498 struct mtk_rx_dma { 499 unsigned int rxd1; 500 unsigned int rxd2; 501 unsigned int rxd3; 502 unsigned int rxd4; 503 } __packed __aligned(4); 504 505 struct mtk_tx_dma { 506 unsigned int txd1; 507 unsigned int txd2; 508 unsigned int txd3; 509 unsigned int txd4; 510 } __packed __aligned(4); 511 512 struct mtk_eth; 513 struct mtk_mac; 514 515 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 516 * @stats_lock: make sure that stats operations are atomic 517 * @reg_offset: the status register offset of the SoC 518 * @syncp: the refcount 519 * 520 * All of the supported SoCs have hardware counters for traffic statistics. 521 * Whenever the status IRQ triggers we can read the latest stats from these 522 * counters and store them in this struct. 523 */ 524 struct mtk_hw_stats { 525 u64 tx_bytes; 526 u64 tx_packets; 527 u64 tx_skip; 528 u64 tx_collisions; 529 u64 rx_bytes; 530 u64 rx_packets; 531 u64 rx_overflow; 532 u64 rx_fcs_errors; 533 u64 rx_short_errors; 534 u64 rx_long_errors; 535 u64 rx_checksum_errors; 536 u64 rx_flow_control_packets; 537 538 spinlock_t stats_lock; 539 u32 reg_offset; 540 struct u64_stats_sync syncp; 541 }; 542 543 enum mtk_tx_flags { 544 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 545 * track how memory was allocated so that it can be freed properly. 546 */ 547 MTK_TX_FLAGS_SINGLE0 = 0x01, 548 MTK_TX_FLAGS_PAGE0 = 0x02, 549 550 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 551 * SKB out instead of looking up through hardware TX descriptor. 552 */ 553 MTK_TX_FLAGS_FPORT0 = 0x04, 554 MTK_TX_FLAGS_FPORT1 = 0x08, 555 }; 556 557 /* This enum allows us to identify how the clock is defined on the array of the 558 * clock in the order 559 */ 560 enum mtk_clks_map { 561 MTK_CLK_ETHIF, 562 MTK_CLK_SGMIITOP, 563 MTK_CLK_ESW, 564 MTK_CLK_GP0, 565 MTK_CLK_GP1, 566 MTK_CLK_GP2, 567 MTK_CLK_FE, 568 MTK_CLK_TRGPLL, 569 MTK_CLK_SGMII_TX_250M, 570 MTK_CLK_SGMII_RX_250M, 571 MTK_CLK_SGMII_CDR_REF, 572 MTK_CLK_SGMII_CDR_FB, 573 MTK_CLK_SGMII2_TX_250M, 574 MTK_CLK_SGMII2_RX_250M, 575 MTK_CLK_SGMII2_CDR_REF, 576 MTK_CLK_SGMII2_CDR_FB, 577 MTK_CLK_SGMII_CK, 578 MTK_CLK_ETH2PLL, 579 MTK_CLK_MAX 580 }; 581 582 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 583 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 584 BIT(MTK_CLK_TRGPLL)) 585 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 586 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 587 BIT(MTK_CLK_GP2) | \ 588 BIT(MTK_CLK_SGMII_TX_250M) | \ 589 BIT(MTK_CLK_SGMII_RX_250M) | \ 590 BIT(MTK_CLK_SGMII_CDR_REF) | \ 591 BIT(MTK_CLK_SGMII_CDR_FB) | \ 592 BIT(MTK_CLK_SGMII_CK) | \ 593 BIT(MTK_CLK_ETH2PLL)) 594 #define MT7621_CLKS_BITMAP (0) 595 #define MT7628_CLKS_BITMAP (0) 596 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 597 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 598 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 599 BIT(MTK_CLK_SGMII_TX_250M) | \ 600 BIT(MTK_CLK_SGMII_RX_250M) | \ 601 BIT(MTK_CLK_SGMII_CDR_REF) | \ 602 BIT(MTK_CLK_SGMII_CDR_FB) | \ 603 BIT(MTK_CLK_SGMII2_TX_250M) | \ 604 BIT(MTK_CLK_SGMII2_RX_250M) | \ 605 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 606 BIT(MTK_CLK_SGMII2_CDR_FB) | \ 607 BIT(MTK_CLK_SGMII_CK) | \ 608 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 609 610 enum mtk_dev_state { 611 MTK_HW_INIT, 612 MTK_RESETTING 613 }; 614 615 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 616 * by the TX descriptor s 617 * @skb: The SKB pointer of the packet being sent 618 * @dma_addr0: The base addr of the first segment 619 * @dma_len0: The length of the first segment 620 * @dma_addr1: The base addr of the second segment 621 * @dma_len1: The length of the second segment 622 */ 623 struct mtk_tx_buf { 624 struct sk_buff *skb; 625 u32 flags; 626 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 627 DEFINE_DMA_UNMAP_LEN(dma_len0); 628 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 629 DEFINE_DMA_UNMAP_LEN(dma_len1); 630 }; 631 632 /* struct mtk_tx_ring - This struct holds info describing a TX ring 633 * @dma: The descriptor ring 634 * @buf: The memory pointed at by the ring 635 * @phys: The physical addr of tx_buf 636 * @next_free: Pointer to the next free descriptor 637 * @last_free: Pointer to the last free descriptor 638 * @thresh: The threshold of minimum amount of free descriptors 639 * @free_count: QDMA uses a linked list. Track how many free descriptors 640 * are present 641 */ 642 struct mtk_tx_ring { 643 struct mtk_tx_dma *dma; 644 struct mtk_tx_buf *buf; 645 dma_addr_t phys; 646 struct mtk_tx_dma *next_free; 647 struct mtk_tx_dma *last_free; 648 u16 thresh; 649 atomic_t free_count; 650 int dma_size; 651 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 652 dma_addr_t phys_pdma; 653 int cpu_idx; 654 }; 655 656 /* PDMA rx ring mode */ 657 enum mtk_rx_flags { 658 MTK_RX_FLAGS_NORMAL = 0, 659 MTK_RX_FLAGS_HWLRO, 660 MTK_RX_FLAGS_QDMA, 661 }; 662 663 /* struct mtk_rx_ring - This struct holds info describing a RX ring 664 * @dma: The descriptor ring 665 * @data: The memory pointed at by the ring 666 * @phys: The physical addr of rx_buf 667 * @frag_size: How big can each fragment be 668 * @buf_size: The size of each packet buffer 669 * @calc_idx: The current head of ring 670 */ 671 struct mtk_rx_ring { 672 struct mtk_rx_dma *dma; 673 u8 **data; 674 dma_addr_t phys; 675 u16 frag_size; 676 u16 buf_size; 677 u16 dma_size; 678 bool calc_idx_update; 679 u16 calc_idx; 680 u32 crx_idx_reg; 681 }; 682 683 enum mkt_eth_capabilities { 684 MTK_RGMII_BIT = 0, 685 MTK_TRGMII_BIT, 686 MTK_SGMII_BIT, 687 MTK_ESW_BIT, 688 MTK_GEPHY_BIT, 689 MTK_MUX_BIT, 690 MTK_INFRA_BIT, 691 MTK_SHARED_SGMII_BIT, 692 MTK_HWLRO_BIT, 693 MTK_SHARED_INT_BIT, 694 MTK_TRGMII_MT7621_CLK_BIT, 695 MTK_QDMA_BIT, 696 MTK_SOC_MT7628_BIT, 697 698 /* MUX BITS*/ 699 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 700 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 701 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 702 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 703 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 704 705 /* PATH BITS */ 706 MTK_ETH_PATH_GMAC1_RGMII_BIT, 707 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 708 MTK_ETH_PATH_GMAC1_SGMII_BIT, 709 MTK_ETH_PATH_GMAC2_RGMII_BIT, 710 MTK_ETH_PATH_GMAC2_SGMII_BIT, 711 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 712 MTK_ETH_PATH_GDM1_ESW_BIT, 713 }; 714 715 /* Supported hardware group on SoCs */ 716 #define MTK_RGMII BIT(MTK_RGMII_BIT) 717 #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 718 #define MTK_SGMII BIT(MTK_SGMII_BIT) 719 #define MTK_ESW BIT(MTK_ESW_BIT) 720 #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 721 #define MTK_MUX BIT(MTK_MUX_BIT) 722 #define MTK_INFRA BIT(MTK_INFRA_BIT) 723 #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 724 #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 725 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 726 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 727 #define MTK_QDMA BIT(MTK_QDMA_BIT) 728 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 729 730 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 731 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 732 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 733 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 734 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 735 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 736 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 737 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 738 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 739 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 740 741 /* Supported path present on SoCs */ 742 #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 743 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 744 #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 745 #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 746 #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 747 #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 748 #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 749 750 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 751 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 752 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 753 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 754 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 755 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 756 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 757 758 /* MUXes present on SoCs */ 759 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 760 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 761 762 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 763 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 764 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 765 766 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 767 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 768 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 769 770 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 771 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 772 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 773 MTK_SHARED_SGMII) 774 775 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 776 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 777 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 778 779 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 780 781 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 782 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 783 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 784 785 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 786 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 787 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 788 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 789 790 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 791 MTK_QDMA) 792 793 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 794 795 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 796 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 797 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 798 MTK_MUX_U3_GMAC2_TO_QPHY | \ 799 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 800 801 /* struct mtk_eth_data - This is the structure holding all differences 802 * among various plaforms 803 * @ana_rgc3: The offset for register ANA_RGC3 related to 804 * sgmiisys syscon 805 * @caps Flags shown the extra capability for the SoC 806 * @hw_features Flags shown HW features 807 * @required_clks Flags shown the bitmap for required clocks on 808 * the target SoC 809 * @required_pctl A bool value to show whether the SoC requires 810 * the extra setup for those pins used by GMAC. 811 */ 812 struct mtk_soc_data { 813 u32 ana_rgc3; 814 u32 caps; 815 u32 required_clks; 816 bool required_pctl; 817 u8 offload_version; 818 netdev_features_t hw_features; 819 }; 820 821 /* currently no SoC has more than 2 macs */ 822 #define MTK_MAX_DEVS 2 823 824 #define MTK_SGMII_PHYSPEED_AN BIT(31) 825 #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) 826 #define MTK_SGMII_PHYSPEED_1000 BIT(0) 827 #define MTK_SGMII_PHYSPEED_2500 BIT(1) 828 #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) 829 830 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 831 * characteristics 832 * @regmap: The register map pointing at the range used to setup 833 * SGMII modes 834 * @flags: The enum refers to which mode the sgmii wants to run on 835 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 836 */ 837 838 struct mtk_sgmii { 839 struct regmap *regmap[MTK_MAX_DEVS]; 840 u32 flags[MTK_MAX_DEVS]; 841 u32 ana_rgc3; 842 }; 843 844 /* struct mtk_eth - This is the main datasructure for holding the state 845 * of the driver 846 * @dev: The device pointer 847 * @base: The mapped register i/o base 848 * @page_lock: Make sure that register operations are atomic 849 * @tx_irq__lock: Make sure that IRQ register operations are atomic 850 * @rx_irq__lock: Make sure that IRQ register operations are atomic 851 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 852 * dummy for NAPI to work 853 * @netdev: The netdev instances 854 * @mac: Each netdev is linked to a physical MAC 855 * @irq: The IRQ that we are using 856 * @msg_enable: Ethtool msg level 857 * @ethsys: The register map pointing at the range used to setup 858 * MII modes 859 * @infra: The register map pointing at the range used to setup 860 * SGMII and GePHY path 861 * @pctl: The register map pointing at the range used to setup 862 * GMAC port drive/slew values 863 * @dma_refcnt: track how many netdevs are using the DMA engine 864 * @tx_ring: Pointer to the memory holding info about the TX ring 865 * @rx_ring: Pointer to the memory holding info about the RX ring 866 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 867 * @tx_napi: The TX NAPI struct 868 * @rx_napi: The RX NAPI struct 869 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 870 * @phy_scratch_ring: physical address of scratch_ring 871 * @scratch_head: The scratch memory that scratch_ring points to. 872 * @clks: clock array for all clocks required 873 * @mii_bus: If there is a bus we need to create an instance for it 874 * @pending_work: The workqueue used to reset the dma ring 875 * @state: Initialization and runtime state of the device 876 * @soc: Holding specific data among vaious SoCs 877 */ 878 879 struct mtk_eth { 880 struct device *dev; 881 void __iomem *base; 882 spinlock_t page_lock; 883 spinlock_t tx_irq_lock; 884 spinlock_t rx_irq_lock; 885 struct net_device dummy_dev; 886 struct net_device *netdev[MTK_MAX_DEVS]; 887 struct mtk_mac *mac[MTK_MAX_DEVS]; 888 int irq[3]; 889 u32 msg_enable; 890 unsigned long sysclk; 891 struct regmap *ethsys; 892 struct regmap *infra; 893 struct mtk_sgmii *sgmii; 894 struct regmap *pctl; 895 bool hwlro; 896 refcount_t dma_refcnt; 897 struct mtk_tx_ring tx_ring; 898 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 899 struct mtk_rx_ring rx_ring_qdma; 900 struct napi_struct tx_napi; 901 struct napi_struct rx_napi; 902 struct mtk_tx_dma *scratch_ring; 903 dma_addr_t phy_scratch_ring; 904 void *scratch_head; 905 struct clk *clks[MTK_CLK_MAX]; 906 907 struct mii_bus *mii_bus; 908 struct work_struct pending_work; 909 unsigned long state; 910 911 const struct mtk_soc_data *soc; 912 913 u32 tx_int_mask_reg; 914 u32 tx_int_status_reg; 915 u32 rx_dma_l4_valid; 916 int ip_align; 917 918 struct mtk_ppe ppe; 919 struct rhashtable flow_table; 920 }; 921 922 /* struct mtk_mac - the structure that holds the info about the MACs of the 923 * SoC 924 * @id: The number of the MAC 925 * @interface: Interface mode kept for detecting change in hw settings 926 * @of_node: Our devicetree node 927 * @hw: Backpointer to our main datastruture 928 * @hw_stats: Packet statistics counter 929 */ 930 struct mtk_mac { 931 int id; 932 phy_interface_t interface; 933 unsigned int mode; 934 int speed; 935 struct device_node *of_node; 936 struct phylink *phylink; 937 struct phylink_config phylink_config; 938 struct mtk_eth *hw; 939 struct mtk_hw_stats *hw_stats; 940 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 941 int hwlro_ip_cnt; 942 }; 943 944 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 945 extern const struct of_device_id of_mtk_match[]; 946 947 /* read the hardware status register */ 948 void mtk_stats_update_mac(struct mtk_mac *mac); 949 950 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 951 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 952 953 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 954 u32 ana_rgc3); 955 int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); 956 int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, 957 const struct phylink_link_state *state); 958 void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); 959 960 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 961 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 962 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 963 964 int mtk_eth_offload_init(struct mtk_eth *eth); 965 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 966 void *type_data); 967 968 969 #endif /* MTK_ETH_H */ 970