1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *
4  *   Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5  *   Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6  *   Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7  */
8 
9 #ifndef MTK_ETH_H
10 #define MTK_ETH_H
11 
12 #include <linux/dma-mapping.h>
13 #include <linux/netdevice.h>
14 #include <linux/of_net.h>
15 #include <linux/u64_stats_sync.h>
16 #include <linux/refcount.h>
17 #include <linux/phylink.h>
18 
19 #define MTK_QDMA_PAGE_SIZE	2048
20 #define	MTK_MAX_RX_LENGTH	1536
21 #define MTK_TX_DMA_BUF_LEN	0x3fff
22 #define MTK_DMA_SIZE		256
23 #define MTK_NAPI_WEIGHT		64
24 #define MTK_MAC_COUNT		2
25 #define MTK_RX_ETH_HLEN		(VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
26 #define MTK_RX_HLEN		(NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
27 #define MTK_DMA_DUMMY_DESC	0xffffffff
28 #define MTK_DEFAULT_MSG_ENABLE	(NETIF_MSG_DRV | \
29 				 NETIF_MSG_PROBE | \
30 				 NETIF_MSG_LINK | \
31 				 NETIF_MSG_TIMER | \
32 				 NETIF_MSG_IFDOWN | \
33 				 NETIF_MSG_IFUP | \
34 				 NETIF_MSG_RX_ERR | \
35 				 NETIF_MSG_TX_ERR)
36 #define MTK_HW_FEATURES		(NETIF_F_IP_CSUM | \
37 				 NETIF_F_RXCSUM | \
38 				 NETIF_F_HW_VLAN_CTAG_TX | \
39 				 NETIF_F_HW_VLAN_CTAG_RX | \
40 				 NETIF_F_SG | NETIF_F_TSO | \
41 				 NETIF_F_TSO6 | \
42 				 NETIF_F_IPV6_CSUM)
43 #define MTK_HW_FEATURES_MT7628	(NETIF_F_SG | NETIF_F_RXCSUM)
44 #define NEXT_DESP_IDX(X, Y)	(((X) + 1) & ((Y) - 1))
45 
46 #define MTK_MAX_RX_RING_NUM	4
47 #define MTK_HW_LRO_DMA_SIZE	8
48 
49 #define	MTK_MAX_LRO_RX_LENGTH		(4096 * 3)
50 #define	MTK_MAX_LRO_IP_CNT		2
51 #define	MTK_HW_LRO_TIMER_UNIT		1	/* 20 us */
52 #define	MTK_HW_LRO_REFRESH_TIME		50000	/* 1 sec. */
53 #define	MTK_HW_LRO_AGG_TIME		10	/* 200us */
54 #define	MTK_HW_LRO_AGE_TIME		50	/* 1ms */
55 #define	MTK_HW_LRO_MAX_AGG_CNT		64
56 #define	MTK_HW_LRO_BW_THRE		3000
57 #define	MTK_HW_LRO_REPLACE_DELTA	1000
58 #define	MTK_HW_LRO_SDL_REMAIN_ROOM	1522
59 
60 /* Frame Engine Global Reset Register */
61 #define MTK_RST_GL		0x04
62 #define RST_GL_PSE		BIT(0)
63 
64 /* Frame Engine Interrupt Status Register */
65 #define MTK_INT_STATUS2		0x08
66 #define MTK_GDM1_AF		BIT(28)
67 #define MTK_GDM2_AF		BIT(29)
68 
69 /* PDMA HW LRO Alter Flow Timer Register */
70 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER	0x1c
71 
72 /* Frame Engine Interrupt Grouping Register */
73 #define MTK_FE_INT_GRP		0x20
74 
75 /* CDMP Ingress Control Register */
76 #define MTK_CDMQ_IG_CTRL	0x1400
77 #define MTK_CDMQ_STAG_EN	BIT(0)
78 
79 /* CDMP Exgress Control Register */
80 #define MTK_CDMP_EG_CTRL	0x404
81 
82 /* GDM Exgress Control Register */
83 #define MTK_GDMA_FWD_CFG(x)	(0x500 + (x * 0x1000))
84 #define MTK_GDMA_ICS_EN		BIT(22)
85 #define MTK_GDMA_TCS_EN		BIT(21)
86 #define MTK_GDMA_UCS_EN		BIT(20)
87 #define MTK_GDMA_TO_PDMA	0x0
88 #define MTK_GDMA_DROP_ALL       0x7777
89 
90 /* Unicast Filter MAC Address Register - Low */
91 #define MTK_GDMA_MAC_ADRL(x)	(0x508 + (x * 0x1000))
92 
93 /* Unicast Filter MAC Address Register - High */
94 #define MTK_GDMA_MAC_ADRH(x)	(0x50C + (x * 0x1000))
95 
96 /* PDMA RX Base Pointer Register */
97 #define MTK_PRX_BASE_PTR0	0x900
98 #define MTK_PRX_BASE_PTR_CFG(x)	(MTK_PRX_BASE_PTR0 + (x * 0x10))
99 
100 /* PDMA RX Maximum Count Register */
101 #define MTK_PRX_MAX_CNT0	0x904
102 #define MTK_PRX_MAX_CNT_CFG(x)	(MTK_PRX_MAX_CNT0 + (x * 0x10))
103 
104 /* PDMA RX CPU Pointer Register */
105 #define MTK_PRX_CRX_IDX0	0x908
106 #define MTK_PRX_CRX_IDX_CFG(x)	(MTK_PRX_CRX_IDX0 + (x * 0x10))
107 
108 /* PDMA HW LRO Control Registers */
109 #define MTK_PDMA_LRO_CTRL_DW0	0x980
110 #define MTK_LRO_EN			BIT(0)
111 #define MTK_L3_CKS_UPD_EN		BIT(7)
112 #define MTK_LRO_ALT_PKT_CNT_MODE	BIT(21)
113 #define MTK_LRO_RING_RELINQUISH_REQ	(0x7 << 26)
114 #define MTK_LRO_RING_RELINQUISH_DONE	(0x7 << 29)
115 
116 #define MTK_PDMA_LRO_CTRL_DW1	0x984
117 #define MTK_PDMA_LRO_CTRL_DW2	0x988
118 #define MTK_PDMA_LRO_CTRL_DW3	0x98c
119 #define MTK_ADMA_MODE		BIT(15)
120 #define MTK_LRO_MIN_RXD_SDL	(MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
121 
122 /* PDMA Global Configuration Register */
123 #define MTK_PDMA_GLO_CFG	0xa04
124 #define MTK_MULTI_EN		BIT(10)
125 #define MTK_PDMA_SIZE_8DWORDS	(1 << 4)
126 
127 /* PDMA Reset Index Register */
128 #define MTK_PDMA_RST_IDX	0xa08
129 #define MTK_PST_DRX_IDX0	BIT(16)
130 #define MTK_PST_DRX_IDX_CFG(x)	(MTK_PST_DRX_IDX0 << (x))
131 
132 /* PDMA Delay Interrupt Register */
133 #define MTK_PDMA_DELAY_INT		0xa0c
134 #define MTK_PDMA_DELAY_RX_EN		BIT(15)
135 #define MTK_PDMA_DELAY_RX_PINT		4
136 #define MTK_PDMA_DELAY_RX_PINT_SHIFT	8
137 #define MTK_PDMA_DELAY_RX_PTIME		4
138 #define MTK_PDMA_DELAY_RX_DELAY		\
139 	(MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \
140 	(MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT))
141 
142 /* PDMA Interrupt Status Register */
143 #define MTK_PDMA_INT_STATUS	0xa20
144 
145 /* PDMA Interrupt Mask Register */
146 #define MTK_PDMA_INT_MASK	0xa28
147 
148 /* PDMA HW LRO Alter Flow Delta Register */
149 #define MTK_PDMA_LRO_ALT_SCORE_DELTA	0xa4c
150 
151 /* PDMA Interrupt grouping registers */
152 #define MTK_PDMA_INT_GRP1	0xa50
153 #define MTK_PDMA_INT_GRP2	0xa54
154 
155 /* PDMA HW LRO IP Setting Registers */
156 #define MTK_LRO_RX_RING0_DIP_DW0	0xb04
157 #define MTK_LRO_DIP_DW0_CFG(x)		(MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
158 #define MTK_RING_MYIP_VLD		BIT(9)
159 
160 /* PDMA HW LRO Ring Control Registers */
161 #define MTK_LRO_RX_RING0_CTRL_DW1	0xb28
162 #define MTK_LRO_RX_RING0_CTRL_DW2	0xb2c
163 #define MTK_LRO_RX_RING0_CTRL_DW3	0xb30
164 #define MTK_LRO_CTRL_DW1_CFG(x)		(MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
165 #define MTK_LRO_CTRL_DW2_CFG(x)		(MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
166 #define MTK_LRO_CTRL_DW3_CFG(x)		(MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
167 #define MTK_RING_AGE_TIME_L		((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
168 #define MTK_RING_AGE_TIME_H		((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
169 #define MTK_RING_AUTO_LERAN_MODE	(3 << 6)
170 #define MTK_RING_VLD			BIT(8)
171 #define MTK_RING_MAX_AGG_TIME		((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
172 #define MTK_RING_MAX_AGG_CNT_L		((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
173 #define MTK_RING_MAX_AGG_CNT_H		((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
174 
175 /* QDMA TX Queue Configuration Registers */
176 #define MTK_QTX_CFG(x)		(0x1800 + (x * 0x10))
177 #define QDMA_RES_THRES		4
178 
179 /* QDMA TX Queue Scheduler Registers */
180 #define MTK_QTX_SCH(x)		(0x1804 + (x * 0x10))
181 
182 /* QDMA RX Base Pointer Register */
183 #define MTK_QRX_BASE_PTR0	0x1900
184 
185 /* QDMA RX Maximum Count Register */
186 #define MTK_QRX_MAX_CNT0	0x1904
187 
188 /* QDMA RX CPU Pointer Register */
189 #define MTK_QRX_CRX_IDX0	0x1908
190 
191 /* QDMA RX DMA Pointer Register */
192 #define MTK_QRX_DRX_IDX0	0x190C
193 
194 /* QDMA Global Configuration Register */
195 #define MTK_QDMA_GLO_CFG	0x1A04
196 #define MTK_RX_2B_OFFSET	BIT(31)
197 #define MTK_RX_BT_32DWORDS	(3 << 11)
198 #define MTK_NDP_CO_PRO		BIT(10)
199 #define MTK_TX_WB_DDONE		BIT(6)
200 #define MTK_DMA_SIZE_16DWORDS	(2 << 4)
201 #define MTK_RX_DMA_BUSY		BIT(3)
202 #define MTK_TX_DMA_BUSY		BIT(1)
203 #define MTK_RX_DMA_EN		BIT(2)
204 #define MTK_TX_DMA_EN		BIT(0)
205 #define MTK_DMA_BUSY_TIMEOUT	HZ
206 
207 /* QDMA Reset Index Register */
208 #define MTK_QDMA_RST_IDX	0x1A08
209 
210 /* QDMA Delay Interrupt Register */
211 #define MTK_QDMA_DELAY_INT	0x1A0C
212 
213 /* QDMA Flow Control Register */
214 #define MTK_QDMA_FC_THRES	0x1A10
215 #define FC_THRES_DROP_MODE	BIT(20)
216 #define FC_THRES_DROP_EN	(7 << 16)
217 #define FC_THRES_MIN		0x4444
218 
219 /* QDMA Interrupt Status Register */
220 #define MTK_QDMA_INT_STATUS	0x1A18
221 #define MTK_RX_DONE_DLY		BIT(30)
222 #define MTK_RX_DONE_INT3	BIT(19)
223 #define MTK_RX_DONE_INT2	BIT(18)
224 #define MTK_RX_DONE_INT1	BIT(17)
225 #define MTK_RX_DONE_INT0	BIT(16)
226 #define MTK_TX_DONE_INT3	BIT(3)
227 #define MTK_TX_DONE_INT2	BIT(2)
228 #define MTK_TX_DONE_INT1	BIT(1)
229 #define MTK_TX_DONE_INT0	BIT(0)
230 #define MTK_RX_DONE_INT		MTK_RX_DONE_DLY
231 #define MTK_TX_DONE_INT		(MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
232 				 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
233 
234 /* QDMA Interrupt grouping registers */
235 #define MTK_QDMA_INT_GRP1	0x1a20
236 #define MTK_QDMA_INT_GRP2	0x1a24
237 #define MTK_RLS_DONE_INT	BIT(0)
238 
239 /* QDMA Interrupt Status Register */
240 #define MTK_QDMA_INT_MASK	0x1A1C
241 
242 /* QDMA Interrupt Mask Register */
243 #define MTK_QDMA_HRED2		0x1A44
244 
245 /* QDMA TX Forward CPU Pointer Register */
246 #define MTK_QTX_CTX_PTR		0x1B00
247 
248 /* QDMA TX Forward DMA Pointer Register */
249 #define MTK_QTX_DTX_PTR		0x1B04
250 
251 /* QDMA TX Release CPU Pointer Register */
252 #define MTK_QTX_CRX_PTR		0x1B10
253 
254 /* QDMA TX Release DMA Pointer Register */
255 #define MTK_QTX_DRX_PTR		0x1B14
256 
257 /* QDMA FQ Head Pointer Register */
258 #define MTK_QDMA_FQ_HEAD	0x1B20
259 
260 /* QDMA FQ Head Pointer Register */
261 #define MTK_QDMA_FQ_TAIL	0x1B24
262 
263 /* QDMA FQ Free Page Counter Register */
264 #define MTK_QDMA_FQ_CNT		0x1B28
265 
266 /* QDMA FQ Free Page Buffer Length Register */
267 #define MTK_QDMA_FQ_BLEN	0x1B2C
268 
269 /* GMA1 Received Good Byte Count Register */
270 #define MTK_GDM1_TX_GBCNT	0x2400
271 #define MTK_STAT_OFFSET		0x40
272 
273 /* QDMA descriptor txd4 */
274 #define TX_DMA_CHKSUM		(0x7 << 29)
275 #define TX_DMA_TSO		BIT(28)
276 #define TX_DMA_FPORT_SHIFT	25
277 #define TX_DMA_FPORT_MASK	0x7
278 #define TX_DMA_INS_VLAN		BIT(16)
279 
280 /* QDMA descriptor txd3 */
281 #define TX_DMA_OWNER_CPU	BIT(31)
282 #define TX_DMA_LS0		BIT(30)
283 #define TX_DMA_PLEN0(_x)	(((_x) & MTK_TX_DMA_BUF_LEN) << 16)
284 #define TX_DMA_PLEN1(_x)	((_x) & MTK_TX_DMA_BUF_LEN)
285 #define TX_DMA_SWC		BIT(14)
286 #define TX_DMA_SDL(_x)		(((_x) & 0x3fff) << 16)
287 
288 /* PDMA on MT7628 */
289 #define TX_DMA_DONE		BIT(31)
290 #define TX_DMA_LS1		BIT(14)
291 #define TX_DMA_DESP2_DEF	(TX_DMA_LS0 | TX_DMA_DONE)
292 
293 /* QDMA descriptor rxd2 */
294 #define RX_DMA_DONE		BIT(31)
295 #define RX_DMA_LSO		BIT(30)
296 #define RX_DMA_PLEN0(_x)	(((_x) & 0x3fff) << 16)
297 #define RX_DMA_GET_PLEN0(_x)	(((_x) >> 16) & 0x3fff)
298 
299 /* QDMA descriptor rxd3 */
300 #define RX_DMA_VID(_x)		((_x) & 0xfff)
301 
302 /* QDMA descriptor rxd4 */
303 #define RX_DMA_L4_VALID		BIT(24)
304 #define RX_DMA_L4_VALID_PDMA	BIT(30)		/* when PDMA is used */
305 #define RX_DMA_FPORT_SHIFT	19
306 #define RX_DMA_FPORT_MASK	0x7
307 
308 /* PHY Indirect Access Control registers */
309 #define MTK_PHY_IAC		0x10004
310 #define PHY_IAC_ACCESS		BIT(31)
311 #define PHY_IAC_READ		BIT(19)
312 #define PHY_IAC_WRITE		BIT(18)
313 #define PHY_IAC_START		BIT(16)
314 #define PHY_IAC_ADDR_SHIFT	20
315 #define PHY_IAC_REG_SHIFT	25
316 #define PHY_IAC_TIMEOUT		HZ
317 
318 #define MTK_MAC_MISC		0x1000c
319 #define MTK_MUX_TO_ESW		BIT(0)
320 
321 /* Mac control registers */
322 #define MTK_MAC_MCR(x)		(0x10100 + (x * 0x100))
323 #define MAC_MCR_MAX_RX_1536	BIT(24)
324 #define MAC_MCR_IPG_CFG		(BIT(18) | BIT(16))
325 #define MAC_MCR_FORCE_MODE	BIT(15)
326 #define MAC_MCR_TX_EN		BIT(14)
327 #define MAC_MCR_RX_EN		BIT(13)
328 #define MAC_MCR_BACKOFF_EN	BIT(9)
329 #define MAC_MCR_BACKPR_EN	BIT(8)
330 #define MAC_MCR_FORCE_RX_FC	BIT(5)
331 #define MAC_MCR_FORCE_TX_FC	BIT(4)
332 #define MAC_MCR_SPEED_1000	BIT(3)
333 #define MAC_MCR_SPEED_100	BIT(2)
334 #define MAC_MCR_FORCE_DPX	BIT(1)
335 #define MAC_MCR_FORCE_LINK	BIT(0)
336 #define MAC_MCR_FORCE_LINK_DOWN	(MAC_MCR_FORCE_MODE)
337 
338 /* Mac status registers */
339 #define MTK_MAC_MSR(x)		(0x10108 + (x * 0x100))
340 #define MAC_MSR_EEE1G		BIT(7)
341 #define MAC_MSR_EEE100M		BIT(6)
342 #define MAC_MSR_RX_FC		BIT(5)
343 #define MAC_MSR_TX_FC		BIT(4)
344 #define MAC_MSR_SPEED_1000	BIT(3)
345 #define MAC_MSR_SPEED_100	BIT(2)
346 #define MAC_MSR_SPEED_MASK	(MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)
347 #define MAC_MSR_DPX		BIT(1)
348 #define MAC_MSR_LINK		BIT(0)
349 
350 /* TRGMII RXC control register */
351 #define TRGMII_RCK_CTRL		0x10300
352 #define DQSI0(x)		((x << 0) & GENMASK(6, 0))
353 #define DQSI1(x)		((x << 8) & GENMASK(14, 8))
354 #define RXCTL_DMWTLAT(x)	((x << 16) & GENMASK(18, 16))
355 #define RXC_DQSISEL		BIT(30)
356 #define RCK_CTRL_RGMII_1000	(RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
357 #define RCK_CTRL_RGMII_10_100	RXCTL_DMWTLAT(2)
358 
359 /* TRGMII RXC control register */
360 #define TRGMII_TCK_CTRL		0x10340
361 #define TXCTL_DMWTLAT(x)	((x << 16) & GENMASK(18, 16))
362 #define TXC_INV			BIT(30)
363 #define TCK_CTRL_RGMII_1000	TXCTL_DMWTLAT(2)
364 #define TCK_CTRL_RGMII_10_100	(TXC_INV | TXCTL_DMWTLAT(2))
365 
366 /* TRGMII Interface mode register */
367 #define INTF_MODE		0x10390
368 #define TRGMII_INTF_DIS		BIT(0)
369 #define TRGMII_MODE		BIT(1)
370 #define TRGMII_CENTRAL_ALIGNED	BIT(2)
371 #define INTF_MODE_RGMII_1000    (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
372 #define INTF_MODE_RGMII_10_100  0
373 
374 /* GPIO port control registers for GMAC 2*/
375 #define GPIO_OD33_CTRL8		0x4c0
376 #define GPIO_BIAS_CTRL		0xed0
377 #define GPIO_DRV_SEL10		0xf00
378 
379 /* ethernet subsystem chip id register */
380 #define ETHSYS_CHIPID0_3	0x0
381 #define ETHSYS_CHIPID4_7	0x4
382 #define MT7623_ETH		7623
383 #define MT7622_ETH		7622
384 #define MT7621_ETH		7621
385 
386 /* ethernet system control register */
387 #define ETHSYS_SYSCFG		0x10
388 #define SYSCFG_DRAM_TYPE_DDR2	BIT(4)
389 
390 /* ethernet subsystem config register */
391 #define ETHSYS_SYSCFG0		0x14
392 #define SYSCFG0_GE_MASK		0x3
393 #define SYSCFG0_GE_MODE(x, y)	(x << (12 + (y * 2)))
394 #define SYSCFG0_SGMII_MASK     GENMASK(9, 8)
395 #define SYSCFG0_SGMII_GMAC1    ((2 << 8) & SYSCFG0_SGMII_MASK)
396 #define SYSCFG0_SGMII_GMAC2    ((3 << 8) & SYSCFG0_SGMII_MASK)
397 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
398 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
399 
400 
401 /* ethernet subsystem clock register */
402 #define ETHSYS_CLKCFG0		0x2c
403 #define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
404 #define ETHSYS_TRGMII_MT7621_MASK	(BIT(5) | BIT(6))
405 #define ETHSYS_TRGMII_MT7621_APLL	BIT(6)
406 #define ETHSYS_TRGMII_MT7621_DDR_PLL	BIT(5)
407 
408 /* ethernet reset control register */
409 #define ETHSYS_RSTCTRL		0x34
410 #define RSTCTRL_FE		BIT(6)
411 #define RSTCTRL_PPE		BIT(31)
412 
413 /* SGMII subsystem config registers */
414 /* Register to auto-negotiation restart */
415 #define SGMSYS_PCS_CONTROL_1	0x0
416 #define SGMII_AN_RESTART	BIT(9)
417 #define SGMII_ISOLATE		BIT(10)
418 #define SGMII_AN_ENABLE		BIT(12)
419 #define SGMII_LINK_STATYS	BIT(18)
420 #define SGMII_AN_ABILITY	BIT(19)
421 #define SGMII_AN_COMPLETE	BIT(21)
422 #define SGMII_PCS_FAULT		BIT(23)
423 #define SGMII_AN_EXPANSION_CLR	BIT(30)
424 
425 /* Register to programmable link timer, the unit in 2 * 8ns */
426 #define SGMSYS_PCS_LINK_TIMER	0x18
427 #define SGMII_LINK_TIMER_DEFAULT	(0x186a0 & GENMASK(19, 0))
428 
429 /* Register to control remote fault */
430 #define SGMSYS_SGMII_MODE		0x20
431 #define SGMII_IF_MODE_BIT0		BIT(0)
432 #define SGMII_SPEED_DUPLEX_AN		BIT(1)
433 #define SGMII_SPEED_10			0x0
434 #define SGMII_SPEED_100			BIT(2)
435 #define SGMII_SPEED_1000		BIT(3)
436 #define SGMII_DUPLEX_FULL		BIT(4)
437 #define SGMII_IF_MODE_BIT5		BIT(5)
438 #define SGMII_REMOTE_FAULT_DIS		BIT(8)
439 #define SGMII_CODE_SYNC_SET_VAL		BIT(9)
440 #define SGMII_CODE_SYNC_SET_EN		BIT(10)
441 #define SGMII_SEND_AN_ERROR_EN		BIT(11)
442 #define SGMII_IF_MODE_MASK		GENMASK(5, 1)
443 
444 /* Register to set SGMII speed, ANA RG_ Control Signals III*/
445 #define SGMSYS_ANA_RG_CS3	0x2028
446 #define RG_PHY_SPEED_MASK	(BIT(2) | BIT(3))
447 #define RG_PHY_SPEED_1_25G	0x0
448 #define RG_PHY_SPEED_3_125G	BIT(2)
449 
450 /* Register to power up QPHY */
451 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
452 #define	SGMII_PHYA_PWD		BIT(4)
453 
454 /* Infrasys subsystem config registers */
455 #define INFRA_MISC2            0x70c
456 #define CO_QPHY_SEL            BIT(0)
457 #define GEPHY_MAC_SEL          BIT(1)
458 
459 /* MT7628/88 specific stuff */
460 #define MT7628_PDMA_OFFSET	0x0800
461 #define MT7628_SDM_OFFSET	0x0c00
462 
463 #define MT7628_TX_BASE_PTR0	(MT7628_PDMA_OFFSET + 0x00)
464 #define MT7628_TX_MAX_CNT0	(MT7628_PDMA_OFFSET + 0x04)
465 #define MT7628_TX_CTX_IDX0	(MT7628_PDMA_OFFSET + 0x08)
466 #define MT7628_TX_DTX_IDX0	(MT7628_PDMA_OFFSET + 0x0c)
467 #define MT7628_PST_DTX_IDX0	BIT(0)
468 
469 #define MT7628_SDM_MAC_ADRL	(MT7628_SDM_OFFSET + 0x0c)
470 #define MT7628_SDM_MAC_ADRH	(MT7628_SDM_OFFSET + 0x10)
471 
472 struct mtk_rx_dma {
473 	unsigned int rxd1;
474 	unsigned int rxd2;
475 	unsigned int rxd3;
476 	unsigned int rxd4;
477 } __packed __aligned(4);
478 
479 struct mtk_tx_dma {
480 	unsigned int txd1;
481 	unsigned int txd2;
482 	unsigned int txd3;
483 	unsigned int txd4;
484 } __packed __aligned(4);
485 
486 struct mtk_eth;
487 struct mtk_mac;
488 
489 /* struct mtk_hw_stats - the structure that holds the traffic statistics.
490  * @stats_lock:		make sure that stats operations are atomic
491  * @reg_offset:		the status register offset of the SoC
492  * @syncp:		the refcount
493  *
494  * All of the supported SoCs have hardware counters for traffic statistics.
495  * Whenever the status IRQ triggers we can read the latest stats from these
496  * counters and store them in this struct.
497  */
498 struct mtk_hw_stats {
499 	u64 tx_bytes;
500 	u64 tx_packets;
501 	u64 tx_skip;
502 	u64 tx_collisions;
503 	u64 rx_bytes;
504 	u64 rx_packets;
505 	u64 rx_overflow;
506 	u64 rx_fcs_errors;
507 	u64 rx_short_errors;
508 	u64 rx_long_errors;
509 	u64 rx_checksum_errors;
510 	u64 rx_flow_control_packets;
511 
512 	spinlock_t		stats_lock;
513 	u32			reg_offset;
514 	struct u64_stats_sync	syncp;
515 };
516 
517 enum mtk_tx_flags {
518 	/* PDMA descriptor can point at 1-2 segments. This enum allows us to
519 	 * track how memory was allocated so that it can be freed properly.
520 	 */
521 	MTK_TX_FLAGS_SINGLE0	= 0x01,
522 	MTK_TX_FLAGS_PAGE0	= 0x02,
523 
524 	/* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted
525 	 * SKB out instead of looking up through hardware TX descriptor.
526 	 */
527 	MTK_TX_FLAGS_FPORT0	= 0x04,
528 	MTK_TX_FLAGS_FPORT1	= 0x08,
529 };
530 
531 /* This enum allows us to identify how the clock is defined on the array of the
532  * clock in the order
533  */
534 enum mtk_clks_map {
535 	MTK_CLK_ETHIF,
536 	MTK_CLK_SGMIITOP,
537 	MTK_CLK_ESW,
538 	MTK_CLK_GP0,
539 	MTK_CLK_GP1,
540 	MTK_CLK_GP2,
541 	MTK_CLK_FE,
542 	MTK_CLK_TRGPLL,
543 	MTK_CLK_SGMII_TX_250M,
544 	MTK_CLK_SGMII_RX_250M,
545 	MTK_CLK_SGMII_CDR_REF,
546 	MTK_CLK_SGMII_CDR_FB,
547 	MTK_CLK_SGMII2_TX_250M,
548 	MTK_CLK_SGMII2_RX_250M,
549 	MTK_CLK_SGMII2_CDR_REF,
550 	MTK_CLK_SGMII2_CDR_FB,
551 	MTK_CLK_SGMII_CK,
552 	MTK_CLK_ETH2PLL,
553 	MTK_CLK_MAX
554 };
555 
556 #define MT7623_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
557 				 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
558 				 BIT(MTK_CLK_TRGPLL))
559 #define MT7622_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
560 				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
561 				 BIT(MTK_CLK_GP2) | \
562 				 BIT(MTK_CLK_SGMII_TX_250M) | \
563 				 BIT(MTK_CLK_SGMII_RX_250M) | \
564 				 BIT(MTK_CLK_SGMII_CDR_REF) | \
565 				 BIT(MTK_CLK_SGMII_CDR_FB) | \
566 				 BIT(MTK_CLK_SGMII_CK) | \
567 				 BIT(MTK_CLK_ETH2PLL))
568 #define MT7621_CLKS_BITMAP	(0)
569 #define MT7628_CLKS_BITMAP	(0)
570 #define MT7629_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
571 				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
572 				 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
573 				 BIT(MTK_CLK_SGMII_TX_250M) | \
574 				 BIT(MTK_CLK_SGMII_RX_250M) | \
575 				 BIT(MTK_CLK_SGMII_CDR_REF) | \
576 				 BIT(MTK_CLK_SGMII_CDR_FB) | \
577 				 BIT(MTK_CLK_SGMII2_TX_250M) | \
578 				 BIT(MTK_CLK_SGMII2_RX_250M) | \
579 				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
580 				 BIT(MTK_CLK_SGMII2_CDR_FB) | \
581 				 BIT(MTK_CLK_SGMII_CK) | \
582 				 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
583 
584 enum mtk_dev_state {
585 	MTK_HW_INIT,
586 	MTK_RESETTING
587 };
588 
589 /* struct mtk_tx_buf -	This struct holds the pointers to the memory pointed at
590  *			by the TX descriptor	s
591  * @skb:		The SKB pointer of the packet being sent
592  * @dma_addr0:		The base addr of the first segment
593  * @dma_len0:		The length of the first segment
594  * @dma_addr1:		The base addr of the second segment
595  * @dma_len1:		The length of the second segment
596  */
597 struct mtk_tx_buf {
598 	struct sk_buff *skb;
599 	u32 flags;
600 	DEFINE_DMA_UNMAP_ADDR(dma_addr0);
601 	DEFINE_DMA_UNMAP_LEN(dma_len0);
602 	DEFINE_DMA_UNMAP_ADDR(dma_addr1);
603 	DEFINE_DMA_UNMAP_LEN(dma_len1);
604 };
605 
606 /* struct mtk_tx_ring -	This struct holds info describing a TX ring
607  * @dma:		The descriptor ring
608  * @buf:		The memory pointed at by the ring
609  * @phys:		The physical addr of tx_buf
610  * @next_free:		Pointer to the next free descriptor
611  * @last_free:		Pointer to the last free descriptor
612  * @thresh:		The threshold of minimum amount of free descriptors
613  * @free_count:		QDMA uses a linked list. Track how many free descriptors
614  *			are present
615  */
616 struct mtk_tx_ring {
617 	struct mtk_tx_dma *dma;
618 	struct mtk_tx_buf *buf;
619 	dma_addr_t phys;
620 	struct mtk_tx_dma *next_free;
621 	struct mtk_tx_dma *last_free;
622 	u16 thresh;
623 	atomic_t free_count;
624 	int dma_size;
625 	struct mtk_tx_dma *dma_pdma;	/* For MT7628/88 PDMA handling */
626 	dma_addr_t phys_pdma;
627 	int cpu_idx;
628 };
629 
630 /* PDMA rx ring mode */
631 enum mtk_rx_flags {
632 	MTK_RX_FLAGS_NORMAL = 0,
633 	MTK_RX_FLAGS_HWLRO,
634 	MTK_RX_FLAGS_QDMA,
635 };
636 
637 /* struct mtk_rx_ring -	This struct holds info describing a RX ring
638  * @dma:		The descriptor ring
639  * @data:		The memory pointed at by the ring
640  * @phys:		The physical addr of rx_buf
641  * @frag_size:		How big can each fragment be
642  * @buf_size:		The size of each packet buffer
643  * @calc_idx:		The current head of ring
644  */
645 struct mtk_rx_ring {
646 	struct mtk_rx_dma *dma;
647 	u8 **data;
648 	dma_addr_t phys;
649 	u16 frag_size;
650 	u16 buf_size;
651 	u16 dma_size;
652 	bool calc_idx_update;
653 	u16 calc_idx;
654 	u32 crx_idx_reg;
655 };
656 
657 enum mkt_eth_capabilities {
658 	MTK_RGMII_BIT = 0,
659 	MTK_TRGMII_BIT,
660 	MTK_SGMII_BIT,
661 	MTK_ESW_BIT,
662 	MTK_GEPHY_BIT,
663 	MTK_MUX_BIT,
664 	MTK_INFRA_BIT,
665 	MTK_SHARED_SGMII_BIT,
666 	MTK_HWLRO_BIT,
667 	MTK_SHARED_INT_BIT,
668 	MTK_TRGMII_MT7621_CLK_BIT,
669 	MTK_QDMA_BIT,
670 	MTK_SOC_MT7628_BIT,
671 
672 	/* MUX BITS*/
673 	MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
674 	MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
675 	MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
676 	MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
677 	MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
678 
679 	/* PATH BITS */
680 	MTK_ETH_PATH_GMAC1_RGMII_BIT,
681 	MTK_ETH_PATH_GMAC1_TRGMII_BIT,
682 	MTK_ETH_PATH_GMAC1_SGMII_BIT,
683 	MTK_ETH_PATH_GMAC2_RGMII_BIT,
684 	MTK_ETH_PATH_GMAC2_SGMII_BIT,
685 	MTK_ETH_PATH_GMAC2_GEPHY_BIT,
686 	MTK_ETH_PATH_GDM1_ESW_BIT,
687 };
688 
689 /* Supported hardware group on SoCs */
690 #define MTK_RGMII		BIT(MTK_RGMII_BIT)
691 #define MTK_TRGMII		BIT(MTK_TRGMII_BIT)
692 #define MTK_SGMII		BIT(MTK_SGMII_BIT)
693 #define MTK_ESW			BIT(MTK_ESW_BIT)
694 #define MTK_GEPHY		BIT(MTK_GEPHY_BIT)
695 #define MTK_MUX			BIT(MTK_MUX_BIT)
696 #define MTK_INFRA		BIT(MTK_INFRA_BIT)
697 #define MTK_SHARED_SGMII	BIT(MTK_SHARED_SGMII_BIT)
698 #define MTK_HWLRO		BIT(MTK_HWLRO_BIT)
699 #define MTK_SHARED_INT		BIT(MTK_SHARED_INT_BIT)
700 #define MTK_TRGMII_MT7621_CLK	BIT(MTK_TRGMII_MT7621_CLK_BIT)
701 #define MTK_QDMA		BIT(MTK_QDMA_BIT)
702 #define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)
703 
704 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW		\
705 	BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
706 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY	\
707 	BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
708 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY		\
709 	BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
710 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII	\
711 	BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
712 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII	\
713 	BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
714 
715 /* Supported path present on SoCs */
716 #define MTK_ETH_PATH_GMAC1_RGMII	BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)
717 #define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
718 #define MTK_ETH_PATH_GMAC1_SGMII	BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)
719 #define MTK_ETH_PATH_GMAC2_RGMII	BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)
720 #define MTK_ETH_PATH_GMAC2_SGMII	BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
721 #define MTK_ETH_PATH_GMAC2_GEPHY	BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
722 #define MTK_ETH_PATH_GDM1_ESW		BIT(MTK_ETH_PATH_GDM1_ESW_BIT)
723 
724 #define MTK_GMAC1_RGMII		(MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
725 #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
726 #define MTK_GMAC1_SGMII		(MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII)
727 #define MTK_GMAC2_RGMII		(MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
728 #define MTK_GMAC2_SGMII		(MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
729 #define MTK_GMAC2_GEPHY		(MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
730 #define MTK_GDM1_ESW		(MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
731 
732 /* MUXes present on SoCs */
733 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
734 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX)
735 
736 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
737 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY    \
738 	(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
739 
740 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
741 #define MTK_MUX_U3_GMAC2_TO_QPHY        \
742 	(MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
743 
744 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
745 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII      \
746 	(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
747 	MTK_SHARED_SGMII)
748 
749 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
750 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII   \
751 	(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
752 
753 #define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))
754 
755 #define MT7621_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
756 		      MTK_GMAC2_RGMII | MTK_SHARED_INT | \
757 		      MTK_TRGMII_MT7621_CLK | MTK_QDMA)
758 
759 #define MT7622_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
760 		      MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
761 		      MTK_MUX_GDM1_TO_GMAC1_ESW | \
762 		      MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
763 
764 #define MT7623_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
765 		      MTK_QDMA)
766 
767 #define MT7628_CAPS  (MTK_SHARED_INT | MTK_SOC_MT7628)
768 
769 #define MT7629_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
770 		      MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
771 		      MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
772 		      MTK_MUX_U3_GMAC2_TO_QPHY | \
773 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
774 
775 /* struct mtk_eth_data -	This is the structure holding all differences
776  *				among various plaforms
777  * @ana_rgc3:                   The offset for register ANA_RGC3 related to
778  *				sgmiisys syscon
779  * @caps			Flags shown the extra capability for the SoC
780  * @hw_features			Flags shown HW features
781  * @required_clks		Flags shown the bitmap for required clocks on
782  *				the target SoC
783  * @required_pctl		A bool value to show whether the SoC requires
784  *				the extra setup for those pins used by GMAC.
785  */
786 struct mtk_soc_data {
787 	u32             ana_rgc3;
788 	u32		caps;
789 	u32		required_clks;
790 	bool		required_pctl;
791 	netdev_features_t hw_features;
792 };
793 
794 /* currently no SoC has more than 2 macs */
795 #define MTK_MAX_DEVS			2
796 
797 #define MTK_SGMII_PHYSPEED_AN          BIT(31)
798 #define MTK_SGMII_PHYSPEED_MASK        GENMASK(2, 0)
799 #define MTK_SGMII_PHYSPEED_1000        BIT(0)
800 #define MTK_SGMII_PHYSPEED_2500        BIT(1)
801 #define MTK_HAS_FLAGS(flags, _x)       (((flags) & (_x)) == (_x))
802 
803 /* struct mtk_sgmii -  This is the structure holding sgmii regmap and its
804  *                     characteristics
805  * @regmap:            The register map pointing at the range used to setup
806  *                     SGMII modes
807  * @flags:             The enum refers to which mode the sgmii wants to run on
808  * @ana_rgc3:          The offset refers to register ANA_RGC3 related to regmap
809  */
810 
811 struct mtk_sgmii {
812 	struct regmap   *regmap[MTK_MAX_DEVS];
813 	u32             flags[MTK_MAX_DEVS];
814 	u32             ana_rgc3;
815 };
816 
817 /* struct mtk_eth -	This is the main datasructure for holding the state
818  *			of the driver
819  * @dev:		The device pointer
820  * @base:		The mapped register i/o base
821  * @page_lock:		Make sure that register operations are atomic
822  * @tx_irq__lock:	Make sure that IRQ register operations are atomic
823  * @rx_irq__lock:	Make sure that IRQ register operations are atomic
824  * @dummy_dev:		we run 2 netdevs on 1 physical DMA ring and need a
825  *			dummy for NAPI to work
826  * @netdev:		The netdev instances
827  * @mac:		Each netdev is linked to a physical MAC
828  * @irq:		The IRQ that we are using
829  * @msg_enable:		Ethtool msg level
830  * @ethsys:		The register map pointing at the range used to setup
831  *			MII modes
832  * @infra:              The register map pointing at the range used to setup
833  *                      SGMII and GePHY path
834  * @pctl:		The register map pointing at the range used to setup
835  *			GMAC port drive/slew values
836  * @dma_refcnt:		track how many netdevs are using the DMA engine
837  * @tx_ring:		Pointer to the memory holding info about the TX ring
838  * @rx_ring:		Pointer to the memory holding info about the RX ring
839  * @rx_ring_qdma:	Pointer to the memory holding info about the QDMA RX ring
840  * @tx_napi:		The TX NAPI struct
841  * @rx_napi:		The RX NAPI struct
842  * @scratch_ring:	Newer SoCs need memory for a second HW managed TX ring
843  * @phy_scratch_ring:	physical address of scratch_ring
844  * @scratch_head:	The scratch memory that scratch_ring points to.
845  * @clks:		clock array for all clocks required
846  * @mii_bus:		If there is a bus we need to create an instance for it
847  * @pending_work:	The workqueue used to reset the dma ring
848  * @state:		Initialization and runtime state of the device
849  * @soc:		Holding specific data among vaious SoCs
850  */
851 
852 struct mtk_eth {
853 	struct device			*dev;
854 	void __iomem			*base;
855 	spinlock_t			page_lock;
856 	spinlock_t			tx_irq_lock;
857 	spinlock_t			rx_irq_lock;
858 	struct net_device		dummy_dev;
859 	struct net_device		*netdev[MTK_MAX_DEVS];
860 	struct mtk_mac			*mac[MTK_MAX_DEVS];
861 	int				irq[3];
862 	u32				msg_enable;
863 	unsigned long			sysclk;
864 	struct regmap			*ethsys;
865 	struct regmap                   *infra;
866 	struct mtk_sgmii                *sgmii;
867 	struct regmap			*pctl;
868 	bool				hwlro;
869 	refcount_t			dma_refcnt;
870 	struct mtk_tx_ring		tx_ring;
871 	struct mtk_rx_ring		rx_ring[MTK_MAX_RX_RING_NUM];
872 	struct mtk_rx_ring		rx_ring_qdma;
873 	struct napi_struct		tx_napi;
874 	struct napi_struct		rx_napi;
875 	struct mtk_tx_dma		*scratch_ring;
876 	dma_addr_t			phy_scratch_ring;
877 	void				*scratch_head;
878 	struct clk			*clks[MTK_CLK_MAX];
879 
880 	struct mii_bus			*mii_bus;
881 	struct work_struct		pending_work;
882 	unsigned long			state;
883 
884 	const struct mtk_soc_data	*soc;
885 
886 	u32				tx_int_mask_reg;
887 	u32				tx_int_status_reg;
888 	u32				rx_dma_l4_valid;
889 	int				ip_align;
890 };
891 
892 /* struct mtk_mac -	the structure that holds the info about the MACs of the
893  *			SoC
894  * @id:			The number of the MAC
895  * @interface:		Interface mode kept for detecting change in hw settings
896  * @of_node:		Our devicetree node
897  * @hw:			Backpointer to our main datastruture
898  * @hw_stats:		Packet statistics counter
899  */
900 struct mtk_mac {
901 	int				id;
902 	phy_interface_t			interface;
903 	unsigned int			mode;
904 	int				speed;
905 	struct device_node		*of_node;
906 	struct phylink			*phylink;
907 	struct phylink_config		phylink_config;
908 	struct mtk_eth			*hw;
909 	struct mtk_hw_stats		*hw_stats;
910 	__be32				hwlro_ip[MTK_MAX_LRO_IP_CNT];
911 	int				hwlro_ip_cnt;
912 };
913 
914 /* the struct describing the SoC. these are declared in the soc_xyz.c files */
915 extern const struct of_device_id of_mtk_match[];
916 
917 /* read the hardware status register */
918 void mtk_stats_update_mac(struct mtk_mac *mac);
919 
920 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
921 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
922 
923 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
924 		   u32 ana_rgc3);
925 int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id);
926 int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
927 			       const struct phylink_link_state *state);
928 void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id);
929 
930 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
931 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
932 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
933 
934 #endif /* MTK_ETH_H */
935