1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #ifndef MTK_ETH_H 16 #define MTK_ETH_H 17 18 #define MTK_QDMA_PAGE_SIZE 2048 19 #define MTK_MAX_RX_LENGTH 1536 20 #define MTK_TX_DMA_BUF_LEN 0x3fff 21 #define MTK_DMA_SIZE 256 22 #define MTK_NAPI_WEIGHT 64 23 #define MTK_MAC_COUNT 2 24 #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 25 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 26 #define MTK_DMA_DUMMY_DESC 0xffffffff 27 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 28 NETIF_MSG_PROBE | \ 29 NETIF_MSG_LINK | \ 30 NETIF_MSG_TIMER | \ 31 NETIF_MSG_IFDOWN | \ 32 NETIF_MSG_IFUP | \ 33 NETIF_MSG_RX_ERR | \ 34 NETIF_MSG_TX_ERR) 35 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 36 NETIF_F_RXCSUM | \ 37 NETIF_F_HW_VLAN_CTAG_TX | \ 38 NETIF_F_HW_VLAN_CTAG_RX | \ 39 NETIF_F_SG | NETIF_F_TSO | \ 40 NETIF_F_TSO6 | \ 41 NETIF_F_IPV6_CSUM) 42 #define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 43 44 #define MTK_MAX_RX_RING_NUM 4 45 #define MTK_HW_LRO_DMA_SIZE 8 46 47 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 48 #define MTK_MAX_LRO_IP_CNT 2 49 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 50 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 51 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 52 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 53 #define MTK_HW_LRO_MAX_AGG_CNT 64 54 #define MTK_HW_LRO_BW_THRE 3000 55 #define MTK_HW_LRO_REPLACE_DELTA 1000 56 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 57 58 /* Frame Engine Global Reset Register */ 59 #define MTK_RST_GL 0x04 60 #define RST_GL_PSE BIT(0) 61 62 /* Frame Engine Interrupt Status Register */ 63 #define MTK_INT_STATUS2 0x08 64 #define MTK_GDM1_AF BIT(28) 65 #define MTK_GDM2_AF BIT(29) 66 67 /* PDMA HW LRO Alter Flow Timer Register */ 68 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 69 70 /* Frame Engine Interrupt Grouping Register */ 71 #define MTK_FE_INT_GRP 0x20 72 73 /* CDMP Ingress Control Register */ 74 #define MTK_CDMQ_IG_CTRL 0x1400 75 #define MTK_CDMQ_STAG_EN BIT(0) 76 77 /* CDMP Exgress Control Register */ 78 #define MTK_CDMP_EG_CTRL 0x404 79 80 /* GDM Exgress Control Register */ 81 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 82 #define MTK_GDMA_ICS_EN BIT(22) 83 #define MTK_GDMA_TCS_EN BIT(21) 84 #define MTK_GDMA_UCS_EN BIT(20) 85 86 /* Unicast Filter MAC Address Register - Low */ 87 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 88 89 /* Unicast Filter MAC Address Register - High */ 90 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 91 92 /* PDMA RX Base Pointer Register */ 93 #define MTK_PRX_BASE_PTR0 0x900 94 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 95 96 /* PDMA RX Maximum Count Register */ 97 #define MTK_PRX_MAX_CNT0 0x904 98 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 99 100 /* PDMA RX CPU Pointer Register */ 101 #define MTK_PRX_CRX_IDX0 0x908 102 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 103 104 /* PDMA HW LRO Control Registers */ 105 #define MTK_PDMA_LRO_CTRL_DW0 0x980 106 #define MTK_LRO_EN BIT(0) 107 #define MTK_L3_CKS_UPD_EN BIT(7) 108 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 109 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 110 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 111 112 #define MTK_PDMA_LRO_CTRL_DW1 0x984 113 #define MTK_PDMA_LRO_CTRL_DW2 0x988 114 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 115 #define MTK_ADMA_MODE BIT(15) 116 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 117 118 /* PDMA Global Configuration Register */ 119 #define MTK_PDMA_GLO_CFG 0xa04 120 #define MTK_MULTI_EN BIT(10) 121 122 /* PDMA Reset Index Register */ 123 #define MTK_PDMA_RST_IDX 0xa08 124 #define MTK_PST_DRX_IDX0 BIT(16) 125 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 126 127 /* PDMA Delay Interrupt Register */ 128 #define MTK_PDMA_DELAY_INT 0xa0c 129 #define MTK_PDMA_DELAY_RX_EN BIT(15) 130 #define MTK_PDMA_DELAY_RX_PINT 4 131 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 132 #define MTK_PDMA_DELAY_RX_PTIME 4 133 #define MTK_PDMA_DELAY_RX_DELAY \ 134 (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ 135 (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) 136 137 /* PDMA Interrupt Status Register */ 138 #define MTK_PDMA_INT_STATUS 0xa20 139 140 /* PDMA Interrupt Mask Register */ 141 #define MTK_PDMA_INT_MASK 0xa28 142 143 /* PDMA HW LRO Alter Flow Delta Register */ 144 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 145 146 /* PDMA Interrupt grouping registers */ 147 #define MTK_PDMA_INT_GRP1 0xa50 148 #define MTK_PDMA_INT_GRP2 0xa54 149 150 /* PDMA HW LRO IP Setting Registers */ 151 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 152 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 153 #define MTK_RING_MYIP_VLD BIT(9) 154 155 /* PDMA HW LRO Ring Control Registers */ 156 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 157 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 158 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 159 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 160 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 161 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 162 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 163 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 164 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 165 #define MTK_RING_VLD BIT(8) 166 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 167 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 168 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 169 170 /* QDMA TX Queue Configuration Registers */ 171 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 172 #define QDMA_RES_THRES 4 173 174 /* QDMA TX Queue Scheduler Registers */ 175 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 176 177 /* QDMA RX Base Pointer Register */ 178 #define MTK_QRX_BASE_PTR0 0x1900 179 180 /* QDMA RX Maximum Count Register */ 181 #define MTK_QRX_MAX_CNT0 0x1904 182 183 /* QDMA RX CPU Pointer Register */ 184 #define MTK_QRX_CRX_IDX0 0x1908 185 186 /* QDMA RX DMA Pointer Register */ 187 #define MTK_QRX_DRX_IDX0 0x190C 188 189 /* QDMA Global Configuration Register */ 190 #define MTK_QDMA_GLO_CFG 0x1A04 191 #define MTK_RX_2B_OFFSET BIT(31) 192 #define MTK_RX_BT_32DWORDS (3 << 11) 193 #define MTK_NDP_CO_PRO BIT(10) 194 #define MTK_TX_WB_DDONE BIT(6) 195 #define MTK_DMA_SIZE_16DWORDS (2 << 4) 196 #define MTK_RX_DMA_BUSY BIT(3) 197 #define MTK_TX_DMA_BUSY BIT(1) 198 #define MTK_RX_DMA_EN BIT(2) 199 #define MTK_TX_DMA_EN BIT(0) 200 #define MTK_DMA_BUSY_TIMEOUT HZ 201 202 /* QDMA Reset Index Register */ 203 #define MTK_QDMA_RST_IDX 0x1A08 204 205 /* QDMA Delay Interrupt Register */ 206 #define MTK_QDMA_DELAY_INT 0x1A0C 207 208 /* QDMA Flow Control Register */ 209 #define MTK_QDMA_FC_THRES 0x1A10 210 #define FC_THRES_DROP_MODE BIT(20) 211 #define FC_THRES_DROP_EN (7 << 16) 212 #define FC_THRES_MIN 0x4444 213 214 /* QDMA Interrupt Status Register */ 215 #define MTK_QMTK_INT_STATUS 0x1A18 216 #define MTK_RX_DONE_DLY BIT(30) 217 #define MTK_RX_DONE_INT3 BIT(19) 218 #define MTK_RX_DONE_INT2 BIT(18) 219 #define MTK_RX_DONE_INT1 BIT(17) 220 #define MTK_RX_DONE_INT0 BIT(16) 221 #define MTK_TX_DONE_INT3 BIT(3) 222 #define MTK_TX_DONE_INT2 BIT(2) 223 #define MTK_TX_DONE_INT1 BIT(1) 224 #define MTK_TX_DONE_INT0 BIT(0) 225 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 226 #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 227 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 228 229 /* QDMA Interrupt grouping registers */ 230 #define MTK_QDMA_INT_GRP1 0x1a20 231 #define MTK_QDMA_INT_GRP2 0x1a24 232 #define MTK_RLS_DONE_INT BIT(0) 233 234 /* QDMA Interrupt Status Register */ 235 #define MTK_QDMA_INT_MASK 0x1A1C 236 237 /* QDMA Interrupt Mask Register */ 238 #define MTK_QDMA_HRED2 0x1A44 239 240 /* QDMA TX Forward CPU Pointer Register */ 241 #define MTK_QTX_CTX_PTR 0x1B00 242 243 /* QDMA TX Forward DMA Pointer Register */ 244 #define MTK_QTX_DTX_PTR 0x1B04 245 246 /* QDMA TX Release CPU Pointer Register */ 247 #define MTK_QTX_CRX_PTR 0x1B10 248 249 /* QDMA TX Release DMA Pointer Register */ 250 #define MTK_QTX_DRX_PTR 0x1B14 251 252 /* QDMA FQ Head Pointer Register */ 253 #define MTK_QDMA_FQ_HEAD 0x1B20 254 255 /* QDMA FQ Head Pointer Register */ 256 #define MTK_QDMA_FQ_TAIL 0x1B24 257 258 /* QDMA FQ Free Page Counter Register */ 259 #define MTK_QDMA_FQ_CNT 0x1B28 260 261 /* QDMA FQ Free Page Buffer Length Register */ 262 #define MTK_QDMA_FQ_BLEN 0x1B2C 263 264 /* GMA1 Received Good Byte Count Register */ 265 #define MTK_GDM1_TX_GBCNT 0x2400 266 #define MTK_STAT_OFFSET 0x40 267 268 /* QDMA descriptor txd4 */ 269 #define TX_DMA_CHKSUM (0x7 << 29) 270 #define TX_DMA_TSO BIT(28) 271 #define TX_DMA_FPORT_SHIFT 25 272 #define TX_DMA_FPORT_MASK 0x7 273 #define TX_DMA_INS_VLAN BIT(16) 274 275 /* QDMA descriptor txd3 */ 276 #define TX_DMA_OWNER_CPU BIT(31) 277 #define TX_DMA_LS0 BIT(30) 278 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 279 #define TX_DMA_SWC BIT(14) 280 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 281 282 /* QDMA descriptor rxd2 */ 283 #define RX_DMA_DONE BIT(31) 284 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 285 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 286 287 /* QDMA descriptor rxd3 */ 288 #define RX_DMA_VID(_x) ((_x) & 0xfff) 289 290 /* QDMA descriptor rxd4 */ 291 #define RX_DMA_L4_VALID BIT(24) 292 #define RX_DMA_FPORT_SHIFT 19 293 #define RX_DMA_FPORT_MASK 0x7 294 295 /* PHY Indirect Access Control registers */ 296 #define MTK_PHY_IAC 0x10004 297 #define PHY_IAC_ACCESS BIT(31) 298 #define PHY_IAC_READ BIT(19) 299 #define PHY_IAC_WRITE BIT(18) 300 #define PHY_IAC_START BIT(16) 301 #define PHY_IAC_ADDR_SHIFT 20 302 #define PHY_IAC_REG_SHIFT 25 303 #define PHY_IAC_TIMEOUT HZ 304 305 /* Mac control registers */ 306 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 307 #define MAC_MCR_MAX_RX_1536 BIT(24) 308 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 309 #define MAC_MCR_FORCE_MODE BIT(15) 310 #define MAC_MCR_TX_EN BIT(14) 311 #define MAC_MCR_RX_EN BIT(13) 312 #define MAC_MCR_BACKOFF_EN BIT(9) 313 #define MAC_MCR_BACKPR_EN BIT(8) 314 #define MAC_MCR_FORCE_RX_FC BIT(5) 315 #define MAC_MCR_FORCE_TX_FC BIT(4) 316 #define MAC_MCR_SPEED_1000 BIT(3) 317 #define MAC_MCR_SPEED_100 BIT(2) 318 #define MAC_MCR_FORCE_DPX BIT(1) 319 #define MAC_MCR_FORCE_LINK BIT(0) 320 #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ 321 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ 322 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ 323 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ 324 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ 325 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) 326 327 /* TRGMII RXC control register */ 328 #define TRGMII_RCK_CTRL 0x10300 329 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 330 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 331 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 332 #define RXC_DQSISEL BIT(30) 333 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 334 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 335 336 /* TRGMII RXC control register */ 337 #define TRGMII_TCK_CTRL 0x10340 338 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 339 #define TXC_INV BIT(30) 340 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 341 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 342 343 /* TRGMII Interface mode register */ 344 #define INTF_MODE 0x10390 345 #define TRGMII_INTF_DIS BIT(0) 346 #define TRGMII_MODE BIT(1) 347 #define TRGMII_CENTRAL_ALIGNED BIT(2) 348 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 349 #define INTF_MODE_RGMII_10_100 0 350 351 /* GPIO port control registers for GMAC 2*/ 352 #define GPIO_OD33_CTRL8 0x4c0 353 #define GPIO_BIAS_CTRL 0xed0 354 #define GPIO_DRV_SEL10 0xf00 355 356 /* ethernet subsystem chip id register */ 357 #define ETHSYS_CHIPID0_3 0x0 358 #define ETHSYS_CHIPID4_7 0x4 359 #define MT7623_ETH 7623 360 361 /* ethernet subsystem config register */ 362 #define ETHSYS_SYSCFG0 0x14 363 #define SYSCFG0_GE_MASK 0x3 364 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 365 366 /* ethernet subsystem clock register */ 367 #define ETHSYS_CLKCFG0 0x2c 368 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 369 370 /* ethernet reset control register */ 371 #define ETHSYS_RSTCTRL 0x34 372 #define RSTCTRL_FE BIT(6) 373 #define RSTCTRL_PPE BIT(31) 374 375 struct mtk_rx_dma { 376 unsigned int rxd1; 377 unsigned int rxd2; 378 unsigned int rxd3; 379 unsigned int rxd4; 380 } __packed __aligned(4); 381 382 struct mtk_tx_dma { 383 unsigned int txd1; 384 unsigned int txd2; 385 unsigned int txd3; 386 unsigned int txd4; 387 } __packed __aligned(4); 388 389 struct mtk_eth; 390 struct mtk_mac; 391 392 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 393 * @stats_lock: make sure that stats operations are atomic 394 * @reg_offset: the status register offset of the SoC 395 * @syncp: the refcount 396 * 397 * All of the supported SoCs have hardware counters for traffic statistics. 398 * Whenever the status IRQ triggers we can read the latest stats from these 399 * counters and store them in this struct. 400 */ 401 struct mtk_hw_stats { 402 u64 tx_bytes; 403 u64 tx_packets; 404 u64 tx_skip; 405 u64 tx_collisions; 406 u64 rx_bytes; 407 u64 rx_packets; 408 u64 rx_overflow; 409 u64 rx_fcs_errors; 410 u64 rx_short_errors; 411 u64 rx_long_errors; 412 u64 rx_checksum_errors; 413 u64 rx_flow_control_packets; 414 415 spinlock_t stats_lock; 416 u32 reg_offset; 417 struct u64_stats_sync syncp; 418 }; 419 420 enum mtk_tx_flags { 421 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 422 * track how memory was allocated so that it can be freed properly. 423 */ 424 MTK_TX_FLAGS_SINGLE0 = 0x01, 425 MTK_TX_FLAGS_PAGE0 = 0x02, 426 427 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 428 * SKB out instead of looking up through hardware TX descriptor. 429 */ 430 MTK_TX_FLAGS_FPORT0 = 0x04, 431 MTK_TX_FLAGS_FPORT1 = 0x08, 432 }; 433 434 /* This enum allows us to identify how the clock is defined on the array of the 435 * clock in the order 436 */ 437 enum mtk_clks_map { 438 MTK_CLK_ETHIF, 439 MTK_CLK_ESW, 440 MTK_CLK_GP1, 441 MTK_CLK_GP2, 442 MTK_CLK_TRGPLL, 443 MTK_CLK_MAX 444 }; 445 446 enum mtk_dev_state { 447 MTK_HW_INIT, 448 MTK_RESETTING 449 }; 450 451 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 452 * by the TX descriptor s 453 * @skb: The SKB pointer of the packet being sent 454 * @dma_addr0: The base addr of the first segment 455 * @dma_len0: The length of the first segment 456 * @dma_addr1: The base addr of the second segment 457 * @dma_len1: The length of the second segment 458 */ 459 struct mtk_tx_buf { 460 struct sk_buff *skb; 461 u32 flags; 462 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 463 DEFINE_DMA_UNMAP_LEN(dma_len0); 464 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 465 DEFINE_DMA_UNMAP_LEN(dma_len1); 466 }; 467 468 /* struct mtk_tx_ring - This struct holds info describing a TX ring 469 * @dma: The descriptor ring 470 * @buf: The memory pointed at by the ring 471 * @phys: The physical addr of tx_buf 472 * @next_free: Pointer to the next free descriptor 473 * @last_free: Pointer to the last free descriptor 474 * @thresh: The threshold of minimum amount of free descriptors 475 * @free_count: QDMA uses a linked list. Track how many free descriptors 476 * are present 477 */ 478 struct mtk_tx_ring { 479 struct mtk_tx_dma *dma; 480 struct mtk_tx_buf *buf; 481 dma_addr_t phys; 482 struct mtk_tx_dma *next_free; 483 struct mtk_tx_dma *last_free; 484 u16 thresh; 485 atomic_t free_count; 486 }; 487 488 /* PDMA rx ring mode */ 489 enum mtk_rx_flags { 490 MTK_RX_FLAGS_NORMAL = 0, 491 MTK_RX_FLAGS_HWLRO, 492 }; 493 494 /* struct mtk_rx_ring - This struct holds info describing a RX ring 495 * @dma: The descriptor ring 496 * @data: The memory pointed at by the ring 497 * @phys: The physical addr of rx_buf 498 * @frag_size: How big can each fragment be 499 * @buf_size: The size of each packet buffer 500 * @calc_idx: The current head of ring 501 */ 502 struct mtk_rx_ring { 503 struct mtk_rx_dma *dma; 504 u8 **data; 505 dma_addr_t phys; 506 u16 frag_size; 507 u16 buf_size; 508 u16 dma_size; 509 bool calc_idx_update; 510 u16 calc_idx; 511 u32 crx_idx_reg; 512 }; 513 514 /* currently no SoC has more than 2 macs */ 515 #define MTK_MAX_DEVS 2 516 517 /* struct mtk_eth - This is the main datasructure for holding the state 518 * of the driver 519 * @dev: The device pointer 520 * @base: The mapped register i/o base 521 * @page_lock: Make sure that register operations are atomic 522 * @tx_irq__lock: Make sure that IRQ register operations are atomic 523 * @rx_irq__lock: Make sure that IRQ register operations are atomic 524 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 525 * dummy for NAPI to work 526 * @netdev: The netdev instances 527 * @mac: Each netdev is linked to a physical MAC 528 * @irq: The IRQ that we are using 529 * @msg_enable: Ethtool msg level 530 * @ethsys: The register map pointing at the range used to setup 531 * MII modes 532 * @pctl: The register map pointing at the range used to setup 533 * GMAC port drive/slew values 534 * @dma_refcnt: track how many netdevs are using the DMA engine 535 * @tx_ring: Pointer to the memore holding info about the TX ring 536 * @rx_ring: Pointer to the memore holding info about the RX ring 537 * @tx_napi: The TX NAPI struct 538 * @rx_napi: The RX NAPI struct 539 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 540 * @phy_scratch_ring: physical address of scratch_ring 541 * @scratch_head: The scratch memory that scratch_ring points to. 542 * @clks: clock array for all clocks required 543 * @mii_bus: If there is a bus we need to create an instance for it 544 * @pending_work: The workqueue used to reset the dma ring 545 * @state Initialization and runtime state of the device. 546 */ 547 548 struct mtk_eth { 549 struct device *dev; 550 void __iomem *base; 551 spinlock_t page_lock; 552 spinlock_t tx_irq_lock; 553 spinlock_t rx_irq_lock; 554 struct net_device dummy_dev; 555 struct net_device *netdev[MTK_MAX_DEVS]; 556 struct mtk_mac *mac[MTK_MAX_DEVS]; 557 int irq[3]; 558 u32 msg_enable; 559 unsigned long sysclk; 560 struct regmap *ethsys; 561 struct regmap *pctl; 562 u32 chip_id; 563 bool hwlro; 564 atomic_t dma_refcnt; 565 struct mtk_tx_ring tx_ring; 566 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 567 struct napi_struct tx_napi; 568 struct napi_struct rx_napi; 569 struct mtk_tx_dma *scratch_ring; 570 dma_addr_t phy_scratch_ring; 571 void *scratch_head; 572 struct clk *clks[MTK_CLK_MAX]; 573 574 struct mii_bus *mii_bus; 575 struct work_struct pending_work; 576 unsigned long state; 577 }; 578 579 /* struct mtk_mac - the structure that holds the info about the MACs of the 580 * SoC 581 * @id: The number of the MAC 582 * @ge_mode: Interface mode kept for setup restoring 583 * @of_node: Our devicetree node 584 * @hw: Backpointer to our main datastruture 585 * @hw_stats: Packet statistics counter 586 * @trgmii Indicate if the MAC uses TRGMII connected to internal 587 switch 588 */ 589 struct mtk_mac { 590 int id; 591 int ge_mode; 592 struct device_node *of_node; 593 struct mtk_eth *hw; 594 struct mtk_hw_stats *hw_stats; 595 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 596 int hwlro_ip_cnt; 597 bool trgmii; 598 }; 599 600 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 601 extern const struct of_device_id of_mtk_match[]; 602 603 /* read the hardware status register */ 604 void mtk_stats_update_mac(struct mtk_mac *mac); 605 606 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 607 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 608 609 #endif /* MTK_ETH_H */ 610