1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #ifndef MTK_ETH_H 16 #define MTK_ETH_H 17 18 #define MTK_QDMA_PAGE_SIZE 2048 19 #define MTK_MAX_RX_LENGTH 1536 20 #define MTK_TX_DMA_BUF_LEN 0x3fff 21 #define MTK_DMA_SIZE 256 22 #define MTK_NAPI_WEIGHT 64 23 #define MTK_MAC_COUNT 2 24 #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 25 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 26 #define MTK_DMA_DUMMY_DESC 0xffffffff 27 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 28 NETIF_MSG_PROBE | \ 29 NETIF_MSG_LINK | \ 30 NETIF_MSG_TIMER | \ 31 NETIF_MSG_IFDOWN | \ 32 NETIF_MSG_IFUP | \ 33 NETIF_MSG_RX_ERR | \ 34 NETIF_MSG_TX_ERR) 35 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 36 NETIF_F_RXCSUM | \ 37 NETIF_F_HW_VLAN_CTAG_TX | \ 38 NETIF_F_HW_VLAN_CTAG_RX | \ 39 NETIF_F_SG | NETIF_F_TSO | \ 40 NETIF_F_TSO6 | \ 41 NETIF_F_IPV6_CSUM) 42 #define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 43 44 #define MTK_MAX_RX_RING_NUM 4 45 #define MTK_HW_LRO_DMA_SIZE 8 46 47 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 48 #define MTK_MAX_LRO_IP_CNT 2 49 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 50 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 51 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 52 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 53 #define MTK_HW_LRO_MAX_AGG_CNT 64 54 #define MTK_HW_LRO_BW_THRE 3000 55 #define MTK_HW_LRO_REPLACE_DELTA 1000 56 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 57 58 /* Frame Engine Global Reset Register */ 59 #define MTK_RST_GL 0x04 60 #define RST_GL_PSE BIT(0) 61 62 /* Frame Engine Interrupt Status Register */ 63 #define MTK_INT_STATUS2 0x08 64 #define MTK_GDM1_AF BIT(28) 65 #define MTK_GDM2_AF BIT(29) 66 67 /* PDMA HW LRO Alter Flow Timer Register */ 68 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 69 70 /* Frame Engine Interrupt Grouping Register */ 71 #define MTK_FE_INT_GRP 0x20 72 73 /* CDMP Exgress Control Register */ 74 #define MTK_CDMP_EG_CTRL 0x404 75 76 /* GDM Exgress Control Register */ 77 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 78 #define MTK_GDMA_ICS_EN BIT(22) 79 #define MTK_GDMA_TCS_EN BIT(21) 80 #define MTK_GDMA_UCS_EN BIT(20) 81 82 /* Unicast Filter MAC Address Register - Low */ 83 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 84 85 /* Unicast Filter MAC Address Register - High */ 86 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 87 88 /* PDMA RX Base Pointer Register */ 89 #define MTK_PRX_BASE_PTR0 0x900 90 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 91 92 /* PDMA RX Maximum Count Register */ 93 #define MTK_PRX_MAX_CNT0 0x904 94 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 95 96 /* PDMA RX CPU Pointer Register */ 97 #define MTK_PRX_CRX_IDX0 0x908 98 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 99 100 /* PDMA HW LRO Control Registers */ 101 #define MTK_PDMA_LRO_CTRL_DW0 0x980 102 #define MTK_LRO_EN BIT(0) 103 #define MTK_L3_CKS_UPD_EN BIT(7) 104 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 105 #define MTK_LRO_RING_RELINQUISH_REQ (0x3 << 26) 106 #define MTK_LRO_RING_RELINQUISH_DONE (0x3 << 29) 107 108 #define MTK_PDMA_LRO_CTRL_DW1 0x984 109 #define MTK_PDMA_LRO_CTRL_DW2 0x988 110 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 111 #define MTK_ADMA_MODE BIT(15) 112 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 113 114 /* PDMA Global Configuration Register */ 115 #define MTK_PDMA_GLO_CFG 0xa04 116 #define MTK_MULTI_EN BIT(10) 117 118 /* PDMA Reset Index Register */ 119 #define MTK_PDMA_RST_IDX 0xa08 120 #define MTK_PST_DRX_IDX0 BIT(16) 121 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 122 123 /* PDMA Delay Interrupt Register */ 124 #define MTK_PDMA_DELAY_INT 0xa0c 125 126 /* PDMA Interrupt Status Register */ 127 #define MTK_PDMA_INT_STATUS 0xa20 128 129 /* PDMA Interrupt Mask Register */ 130 #define MTK_PDMA_INT_MASK 0xa28 131 132 /* PDMA HW LRO Alter Flow Delta Register */ 133 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 134 135 /* PDMA Interrupt grouping registers */ 136 #define MTK_PDMA_INT_GRP1 0xa50 137 #define MTK_PDMA_INT_GRP2 0xa54 138 139 /* PDMA HW LRO IP Setting Registers */ 140 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 141 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 142 #define MTK_RING_MYIP_VLD BIT(9) 143 144 /* PDMA HW LRO Ring Control Registers */ 145 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 146 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 147 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 148 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 149 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 150 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 151 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 152 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 153 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 154 #define MTK_RING_VLD BIT(8) 155 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 156 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 157 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 158 159 /* QDMA TX Queue Configuration Registers */ 160 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 161 #define QDMA_RES_THRES 4 162 163 /* QDMA TX Queue Scheduler Registers */ 164 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 165 166 /* QDMA RX Base Pointer Register */ 167 #define MTK_QRX_BASE_PTR0 0x1900 168 169 /* QDMA RX Maximum Count Register */ 170 #define MTK_QRX_MAX_CNT0 0x1904 171 172 /* QDMA RX CPU Pointer Register */ 173 #define MTK_QRX_CRX_IDX0 0x1908 174 175 /* QDMA RX DMA Pointer Register */ 176 #define MTK_QRX_DRX_IDX0 0x190C 177 178 /* QDMA Global Configuration Register */ 179 #define MTK_QDMA_GLO_CFG 0x1A04 180 #define MTK_RX_2B_OFFSET BIT(31) 181 #define MTK_RX_BT_32DWORDS (3 << 11) 182 #define MTK_NDP_CO_PRO BIT(10) 183 #define MTK_TX_WB_DDONE BIT(6) 184 #define MTK_DMA_SIZE_16DWORDS (2 << 4) 185 #define MTK_RX_DMA_BUSY BIT(3) 186 #define MTK_TX_DMA_BUSY BIT(1) 187 #define MTK_RX_DMA_EN BIT(2) 188 #define MTK_TX_DMA_EN BIT(0) 189 #define MTK_DMA_BUSY_TIMEOUT HZ 190 191 /* QDMA Reset Index Register */ 192 #define MTK_QDMA_RST_IDX 0x1A08 193 194 /* QDMA Delay Interrupt Register */ 195 #define MTK_QDMA_DELAY_INT 0x1A0C 196 197 /* QDMA Flow Control Register */ 198 #define MTK_QDMA_FC_THRES 0x1A10 199 #define FC_THRES_DROP_MODE BIT(20) 200 #define FC_THRES_DROP_EN (7 << 16) 201 #define FC_THRES_MIN 0x4444 202 203 /* QDMA Interrupt Status Register */ 204 #define MTK_QMTK_INT_STATUS 0x1A18 205 #define MTK_RX_DONE_INT3 BIT(19) 206 #define MTK_RX_DONE_INT2 BIT(18) 207 #define MTK_RX_DONE_INT1 BIT(17) 208 #define MTK_RX_DONE_INT0 BIT(16) 209 #define MTK_TX_DONE_INT3 BIT(3) 210 #define MTK_TX_DONE_INT2 BIT(2) 211 #define MTK_TX_DONE_INT1 BIT(1) 212 #define MTK_TX_DONE_INT0 BIT(0) 213 #define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1 | \ 214 MTK_RX_DONE_INT2 | MTK_RX_DONE_INT3) 215 #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 216 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 217 218 /* QDMA Interrupt grouping registers */ 219 #define MTK_QDMA_INT_GRP1 0x1a20 220 #define MTK_QDMA_INT_GRP2 0x1a24 221 #define MTK_RLS_DONE_INT BIT(0) 222 223 /* QDMA Interrupt Status Register */ 224 #define MTK_QDMA_INT_MASK 0x1A1C 225 226 /* QDMA Interrupt Mask Register */ 227 #define MTK_QDMA_HRED2 0x1A44 228 229 /* QDMA TX Forward CPU Pointer Register */ 230 #define MTK_QTX_CTX_PTR 0x1B00 231 232 /* QDMA TX Forward DMA Pointer Register */ 233 #define MTK_QTX_DTX_PTR 0x1B04 234 235 /* QDMA TX Release CPU Pointer Register */ 236 #define MTK_QTX_CRX_PTR 0x1B10 237 238 /* QDMA TX Release DMA Pointer Register */ 239 #define MTK_QTX_DRX_PTR 0x1B14 240 241 /* QDMA FQ Head Pointer Register */ 242 #define MTK_QDMA_FQ_HEAD 0x1B20 243 244 /* QDMA FQ Head Pointer Register */ 245 #define MTK_QDMA_FQ_TAIL 0x1B24 246 247 /* QDMA FQ Free Page Counter Register */ 248 #define MTK_QDMA_FQ_CNT 0x1B28 249 250 /* QDMA FQ Free Page Buffer Length Register */ 251 #define MTK_QDMA_FQ_BLEN 0x1B2C 252 253 /* GMA1 Received Good Byte Count Register */ 254 #define MTK_GDM1_TX_GBCNT 0x2400 255 #define MTK_STAT_OFFSET 0x40 256 257 /* QDMA descriptor txd4 */ 258 #define TX_DMA_CHKSUM (0x7 << 29) 259 #define TX_DMA_TSO BIT(28) 260 #define TX_DMA_FPORT_SHIFT 25 261 #define TX_DMA_FPORT_MASK 0x7 262 #define TX_DMA_INS_VLAN BIT(16) 263 264 /* QDMA descriptor txd3 */ 265 #define TX_DMA_OWNER_CPU BIT(31) 266 #define TX_DMA_LS0 BIT(30) 267 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 268 #define TX_DMA_SWC BIT(14) 269 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 270 271 /* QDMA descriptor rxd2 */ 272 #define RX_DMA_DONE BIT(31) 273 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 274 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 275 276 /* QDMA descriptor rxd3 */ 277 #define RX_DMA_VID(_x) ((_x) & 0xfff) 278 279 /* QDMA descriptor rxd4 */ 280 #define RX_DMA_L4_VALID BIT(24) 281 #define RX_DMA_FPORT_SHIFT 19 282 #define RX_DMA_FPORT_MASK 0x7 283 284 /* PHY Indirect Access Control registers */ 285 #define MTK_PHY_IAC 0x10004 286 #define PHY_IAC_ACCESS BIT(31) 287 #define PHY_IAC_READ BIT(19) 288 #define PHY_IAC_WRITE BIT(18) 289 #define PHY_IAC_START BIT(16) 290 #define PHY_IAC_ADDR_SHIFT 20 291 #define PHY_IAC_REG_SHIFT 25 292 #define PHY_IAC_TIMEOUT HZ 293 294 /* Mac control registers */ 295 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 296 #define MAC_MCR_MAX_RX_1536 BIT(24) 297 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 298 #define MAC_MCR_FORCE_MODE BIT(15) 299 #define MAC_MCR_TX_EN BIT(14) 300 #define MAC_MCR_RX_EN BIT(13) 301 #define MAC_MCR_BACKOFF_EN BIT(9) 302 #define MAC_MCR_BACKPR_EN BIT(8) 303 #define MAC_MCR_FORCE_RX_FC BIT(5) 304 #define MAC_MCR_FORCE_TX_FC BIT(4) 305 #define MAC_MCR_SPEED_1000 BIT(3) 306 #define MAC_MCR_SPEED_100 BIT(2) 307 #define MAC_MCR_FORCE_DPX BIT(1) 308 #define MAC_MCR_FORCE_LINK BIT(0) 309 #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ 310 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ 311 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ 312 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ 313 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ 314 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) 315 316 /* GPIO port control registers for GMAC 2*/ 317 #define GPIO_OD33_CTRL8 0x4c0 318 #define GPIO_BIAS_CTRL 0xed0 319 #define GPIO_DRV_SEL10 0xf00 320 321 /* ethernet subsystem config register */ 322 #define ETHSYS_SYSCFG0 0x14 323 #define SYSCFG0_GE_MASK 0x3 324 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 325 326 /*ethernet reset control register*/ 327 #define ETHSYS_RSTCTRL 0x34 328 #define RSTCTRL_FE BIT(6) 329 #define RSTCTRL_PPE BIT(31) 330 331 struct mtk_rx_dma { 332 unsigned int rxd1; 333 unsigned int rxd2; 334 unsigned int rxd3; 335 unsigned int rxd4; 336 } __packed __aligned(4); 337 338 struct mtk_tx_dma { 339 unsigned int txd1; 340 unsigned int txd2; 341 unsigned int txd3; 342 unsigned int txd4; 343 } __packed __aligned(4); 344 345 struct mtk_eth; 346 struct mtk_mac; 347 348 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 349 * @stats_lock: make sure that stats operations are atomic 350 * @reg_offset: the status register offset of the SoC 351 * @syncp: the refcount 352 * 353 * All of the supported SoCs have hardware counters for traffic statistics. 354 * Whenever the status IRQ triggers we can read the latest stats from these 355 * counters and store them in this struct. 356 */ 357 struct mtk_hw_stats { 358 u64 tx_bytes; 359 u64 tx_packets; 360 u64 tx_skip; 361 u64 tx_collisions; 362 u64 rx_bytes; 363 u64 rx_packets; 364 u64 rx_overflow; 365 u64 rx_fcs_errors; 366 u64 rx_short_errors; 367 u64 rx_long_errors; 368 u64 rx_checksum_errors; 369 u64 rx_flow_control_packets; 370 371 spinlock_t stats_lock; 372 u32 reg_offset; 373 struct u64_stats_sync syncp; 374 }; 375 376 /* PDMA descriptor can point at 1-2 segments. This enum allows us to track how 377 * memory was allocated so that it can be freed properly 378 */ 379 enum mtk_tx_flags { 380 MTK_TX_FLAGS_SINGLE0 = 0x01, 381 MTK_TX_FLAGS_PAGE0 = 0x02, 382 }; 383 384 /* This enum allows us to identify how the clock is defined on the array of the 385 * clock in the order 386 */ 387 enum mtk_clks_map { 388 MTK_CLK_ETHIF, 389 MTK_CLK_ESW, 390 MTK_CLK_GP1, 391 MTK_CLK_GP2, 392 MTK_CLK_MAX 393 }; 394 395 enum mtk_dev_state { 396 MTK_HW_INIT, 397 MTK_RESETTING 398 }; 399 400 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 401 * by the TX descriptor s 402 * @skb: The SKB pointer of the packet being sent 403 * @dma_addr0: The base addr of the first segment 404 * @dma_len0: The length of the first segment 405 * @dma_addr1: The base addr of the second segment 406 * @dma_len1: The length of the second segment 407 */ 408 struct mtk_tx_buf { 409 struct sk_buff *skb; 410 u32 flags; 411 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 412 DEFINE_DMA_UNMAP_LEN(dma_len0); 413 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 414 DEFINE_DMA_UNMAP_LEN(dma_len1); 415 }; 416 417 /* struct mtk_tx_ring - This struct holds info describing a TX ring 418 * @dma: The descriptor ring 419 * @buf: The memory pointed at by the ring 420 * @phys: The physical addr of tx_buf 421 * @next_free: Pointer to the next free descriptor 422 * @last_free: Pointer to the last free descriptor 423 * @thresh: The threshold of minimum amount of free descriptors 424 * @free_count: QDMA uses a linked list. Track how many free descriptors 425 * are present 426 */ 427 struct mtk_tx_ring { 428 struct mtk_tx_dma *dma; 429 struct mtk_tx_buf *buf; 430 dma_addr_t phys; 431 struct mtk_tx_dma *next_free; 432 struct mtk_tx_dma *last_free; 433 u16 thresh; 434 atomic_t free_count; 435 }; 436 437 /* PDMA rx ring mode */ 438 enum mtk_rx_flags { 439 MTK_RX_FLAGS_NORMAL = 0, 440 MTK_RX_FLAGS_HWLRO, 441 }; 442 443 /* struct mtk_rx_ring - This struct holds info describing a RX ring 444 * @dma: The descriptor ring 445 * @data: The memory pointed at by the ring 446 * @phys: The physical addr of rx_buf 447 * @frag_size: How big can each fragment be 448 * @buf_size: The size of each packet buffer 449 * @calc_idx: The current head of ring 450 */ 451 struct mtk_rx_ring { 452 struct mtk_rx_dma *dma; 453 u8 **data; 454 dma_addr_t phys; 455 u16 frag_size; 456 u16 buf_size; 457 u16 dma_size; 458 bool calc_idx_update; 459 u16 calc_idx; 460 u32 crx_idx_reg; 461 }; 462 463 /* currently no SoC has more than 2 macs */ 464 #define MTK_MAX_DEVS 2 465 466 /* struct mtk_eth - This is the main datasructure for holding the state 467 * of the driver 468 * @dev: The device pointer 469 * @base: The mapped register i/o base 470 * @page_lock: Make sure that register operations are atomic 471 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 472 * dummy for NAPI to work 473 * @netdev: The netdev instances 474 * @mac: Each netdev is linked to a physical MAC 475 * @irq: The IRQ that we are using 476 * @msg_enable: Ethtool msg level 477 * @ethsys: The register map pointing at the range used to setup 478 * MII modes 479 * @pctl: The register map pointing at the range used to setup 480 * GMAC port drive/slew values 481 * @dma_refcnt: track how many netdevs are using the DMA engine 482 * @tx_ring: Pointer to the memore holding info about the TX ring 483 * @rx_ring: Pointer to the memore holding info about the RX ring 484 * @tx_napi: The TX NAPI struct 485 * @rx_napi: The RX NAPI struct 486 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 487 * @phy_scratch_ring: physical address of scratch_ring 488 * @scratch_head: The scratch memory that scratch_ring points to. 489 * @clks: clock array for all clocks required 490 * @mii_bus: If there is a bus we need to create an instance for it 491 * @pending_work: The workqueue used to reset the dma ring 492 * @state Initialization and runtime state of the device. 493 */ 494 495 struct mtk_eth { 496 struct device *dev; 497 void __iomem *base; 498 spinlock_t page_lock; 499 spinlock_t irq_lock; 500 struct net_device dummy_dev; 501 struct net_device *netdev[MTK_MAX_DEVS]; 502 struct mtk_mac *mac[MTK_MAX_DEVS]; 503 int irq[3]; 504 u32 msg_enable; 505 unsigned long sysclk; 506 struct regmap *ethsys; 507 struct regmap *pctl; 508 bool hwlro; 509 atomic_t dma_refcnt; 510 struct mtk_tx_ring tx_ring; 511 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 512 struct napi_struct tx_napi; 513 struct napi_struct rx_napi; 514 struct mtk_tx_dma *scratch_ring; 515 dma_addr_t phy_scratch_ring; 516 void *scratch_head; 517 struct clk *clks[MTK_CLK_MAX]; 518 519 struct mii_bus *mii_bus; 520 struct work_struct pending_work; 521 unsigned long state; 522 }; 523 524 /* struct mtk_mac - the structure that holds the info about the MACs of the 525 * SoC 526 * @id: The number of the MAC 527 * @ge_mode: Interface mode kept for setup restoring 528 * @of_node: Our devicetree node 529 * @hw: Backpointer to our main datastruture 530 * @hw_stats: Packet statistics counter 531 * @phy_dev: The attached PHY if available 532 * @trgmii Indicate if the MAC uses TRGMII connected to internal 533 switch 534 */ 535 struct mtk_mac { 536 int id; 537 int ge_mode; 538 struct device_node *of_node; 539 struct mtk_eth *hw; 540 struct mtk_hw_stats *hw_stats; 541 struct phy_device *phy_dev; 542 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 543 int hwlro_ip_cnt; 544 bool trgmii; 545 }; 546 547 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 548 extern const struct of_device_id of_mtk_match[]; 549 550 /* read the hardware status register */ 551 void mtk_stats_update_mac(struct mtk_mac *mac); 552 553 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 554 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 555 556 #endif /* MTK_ETH_H */ 557