1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #ifndef MTK_ETH_H 16 #define MTK_ETH_H 17 18 #define MTK_QDMA_PAGE_SIZE 2048 19 #define MTK_MAX_RX_LENGTH 1536 20 #define MTK_TX_DMA_BUF_LEN 0x3fff 21 #define MTK_DMA_SIZE 256 22 #define MTK_NAPI_WEIGHT 64 23 #define MTK_MAC_COUNT 2 24 #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 25 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 26 #define MTK_DMA_DUMMY_DESC 0xffffffff 27 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 28 NETIF_MSG_PROBE | \ 29 NETIF_MSG_LINK | \ 30 NETIF_MSG_TIMER | \ 31 NETIF_MSG_IFDOWN | \ 32 NETIF_MSG_IFUP | \ 33 NETIF_MSG_RX_ERR | \ 34 NETIF_MSG_TX_ERR) 35 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 36 NETIF_F_RXCSUM | \ 37 NETIF_F_HW_VLAN_CTAG_TX | \ 38 NETIF_F_HW_VLAN_CTAG_RX | \ 39 NETIF_F_SG | NETIF_F_TSO | \ 40 NETIF_F_TSO6 | \ 41 NETIF_F_IPV6_CSUM) 42 #define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 43 44 #define MTK_MAX_RX_RING_NUM 4 45 #define MTK_HW_LRO_DMA_SIZE 8 46 47 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 48 #define MTK_MAX_LRO_IP_CNT 2 49 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 50 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 51 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 52 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 53 #define MTK_HW_LRO_MAX_AGG_CNT 64 54 #define MTK_HW_LRO_BW_THRE 3000 55 #define MTK_HW_LRO_REPLACE_DELTA 1000 56 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 57 58 /* Frame Engine Global Reset Register */ 59 #define MTK_RST_GL 0x04 60 #define RST_GL_PSE BIT(0) 61 62 /* Frame Engine Interrupt Status Register */ 63 #define MTK_INT_STATUS2 0x08 64 #define MTK_GDM1_AF BIT(28) 65 #define MTK_GDM2_AF BIT(29) 66 67 /* PDMA HW LRO Alter Flow Timer Register */ 68 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 69 70 /* Frame Engine Interrupt Grouping Register */ 71 #define MTK_FE_INT_GRP 0x20 72 73 /* CDMP Ingress Control Register */ 74 #define MTK_CDMQ_IG_CTRL 0x1400 75 #define MTK_CDMQ_STAG_EN BIT(0) 76 77 /* CDMP Exgress Control Register */ 78 #define MTK_CDMP_EG_CTRL 0x404 79 80 /* GDM Exgress Control Register */ 81 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 82 #define MTK_GDMA_ICS_EN BIT(22) 83 #define MTK_GDMA_TCS_EN BIT(21) 84 #define MTK_GDMA_UCS_EN BIT(20) 85 86 /* Unicast Filter MAC Address Register - Low */ 87 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 88 89 /* Unicast Filter MAC Address Register - High */ 90 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 91 92 /* PDMA RX Base Pointer Register */ 93 #define MTK_PRX_BASE_PTR0 0x900 94 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 95 96 /* PDMA RX Maximum Count Register */ 97 #define MTK_PRX_MAX_CNT0 0x904 98 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 99 100 /* PDMA RX CPU Pointer Register */ 101 #define MTK_PRX_CRX_IDX0 0x908 102 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 103 104 /* PDMA HW LRO Control Registers */ 105 #define MTK_PDMA_LRO_CTRL_DW0 0x980 106 #define MTK_LRO_EN BIT(0) 107 #define MTK_L3_CKS_UPD_EN BIT(7) 108 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 109 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 110 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 111 112 #define MTK_PDMA_LRO_CTRL_DW1 0x984 113 #define MTK_PDMA_LRO_CTRL_DW2 0x988 114 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 115 #define MTK_ADMA_MODE BIT(15) 116 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 117 118 /* PDMA Global Configuration Register */ 119 #define MTK_PDMA_GLO_CFG 0xa04 120 #define MTK_MULTI_EN BIT(10) 121 122 /* PDMA Reset Index Register */ 123 #define MTK_PDMA_RST_IDX 0xa08 124 #define MTK_PST_DRX_IDX0 BIT(16) 125 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 126 127 /* PDMA Delay Interrupt Register */ 128 #define MTK_PDMA_DELAY_INT 0xa0c 129 130 /* PDMA Interrupt Status Register */ 131 #define MTK_PDMA_INT_STATUS 0xa20 132 133 /* PDMA Interrupt Mask Register */ 134 #define MTK_PDMA_INT_MASK 0xa28 135 136 /* PDMA HW LRO Alter Flow Delta Register */ 137 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 138 139 /* PDMA Interrupt grouping registers */ 140 #define MTK_PDMA_INT_GRP1 0xa50 141 #define MTK_PDMA_INT_GRP2 0xa54 142 143 /* PDMA HW LRO IP Setting Registers */ 144 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 145 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 146 #define MTK_RING_MYIP_VLD BIT(9) 147 148 /* PDMA HW LRO Ring Control Registers */ 149 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 150 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 151 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 152 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 153 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 154 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 155 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 156 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 157 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 158 #define MTK_RING_VLD BIT(8) 159 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 160 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 161 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 162 163 /* QDMA TX Queue Configuration Registers */ 164 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 165 #define QDMA_RES_THRES 4 166 167 /* QDMA TX Queue Scheduler Registers */ 168 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 169 170 /* QDMA RX Base Pointer Register */ 171 #define MTK_QRX_BASE_PTR0 0x1900 172 173 /* QDMA RX Maximum Count Register */ 174 #define MTK_QRX_MAX_CNT0 0x1904 175 176 /* QDMA RX CPU Pointer Register */ 177 #define MTK_QRX_CRX_IDX0 0x1908 178 179 /* QDMA RX DMA Pointer Register */ 180 #define MTK_QRX_DRX_IDX0 0x190C 181 182 /* QDMA Global Configuration Register */ 183 #define MTK_QDMA_GLO_CFG 0x1A04 184 #define MTK_RX_2B_OFFSET BIT(31) 185 #define MTK_RX_BT_32DWORDS (3 << 11) 186 #define MTK_NDP_CO_PRO BIT(10) 187 #define MTK_TX_WB_DDONE BIT(6) 188 #define MTK_DMA_SIZE_16DWORDS (2 << 4) 189 #define MTK_RX_DMA_BUSY BIT(3) 190 #define MTK_TX_DMA_BUSY BIT(1) 191 #define MTK_RX_DMA_EN BIT(2) 192 #define MTK_TX_DMA_EN BIT(0) 193 #define MTK_DMA_BUSY_TIMEOUT HZ 194 195 /* QDMA Reset Index Register */ 196 #define MTK_QDMA_RST_IDX 0x1A08 197 198 /* QDMA Delay Interrupt Register */ 199 #define MTK_QDMA_DELAY_INT 0x1A0C 200 201 /* QDMA Flow Control Register */ 202 #define MTK_QDMA_FC_THRES 0x1A10 203 #define FC_THRES_DROP_MODE BIT(20) 204 #define FC_THRES_DROP_EN (7 << 16) 205 #define FC_THRES_MIN 0x4444 206 207 /* QDMA Interrupt Status Register */ 208 #define MTK_QMTK_INT_STATUS 0x1A18 209 #define MTK_RX_DONE_INT3 BIT(19) 210 #define MTK_RX_DONE_INT2 BIT(18) 211 #define MTK_RX_DONE_INT1 BIT(17) 212 #define MTK_RX_DONE_INT0 BIT(16) 213 #define MTK_TX_DONE_INT3 BIT(3) 214 #define MTK_TX_DONE_INT2 BIT(2) 215 #define MTK_TX_DONE_INT1 BIT(1) 216 #define MTK_TX_DONE_INT0 BIT(0) 217 #define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1 | \ 218 MTK_RX_DONE_INT2 | MTK_RX_DONE_INT3) 219 #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 220 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 221 222 /* QDMA Interrupt grouping registers */ 223 #define MTK_QDMA_INT_GRP1 0x1a20 224 #define MTK_QDMA_INT_GRP2 0x1a24 225 #define MTK_RLS_DONE_INT BIT(0) 226 227 /* QDMA Interrupt Status Register */ 228 #define MTK_QDMA_INT_MASK 0x1A1C 229 230 /* QDMA Interrupt Mask Register */ 231 #define MTK_QDMA_HRED2 0x1A44 232 233 /* QDMA TX Forward CPU Pointer Register */ 234 #define MTK_QTX_CTX_PTR 0x1B00 235 236 /* QDMA TX Forward DMA Pointer Register */ 237 #define MTK_QTX_DTX_PTR 0x1B04 238 239 /* QDMA TX Release CPU Pointer Register */ 240 #define MTK_QTX_CRX_PTR 0x1B10 241 242 /* QDMA TX Release DMA Pointer Register */ 243 #define MTK_QTX_DRX_PTR 0x1B14 244 245 /* QDMA FQ Head Pointer Register */ 246 #define MTK_QDMA_FQ_HEAD 0x1B20 247 248 /* QDMA FQ Head Pointer Register */ 249 #define MTK_QDMA_FQ_TAIL 0x1B24 250 251 /* QDMA FQ Free Page Counter Register */ 252 #define MTK_QDMA_FQ_CNT 0x1B28 253 254 /* QDMA FQ Free Page Buffer Length Register */ 255 #define MTK_QDMA_FQ_BLEN 0x1B2C 256 257 /* GMA1 Received Good Byte Count Register */ 258 #define MTK_GDM1_TX_GBCNT 0x2400 259 #define MTK_STAT_OFFSET 0x40 260 261 /* QDMA descriptor txd4 */ 262 #define TX_DMA_CHKSUM (0x7 << 29) 263 #define TX_DMA_TSO BIT(28) 264 #define TX_DMA_FPORT_SHIFT 25 265 #define TX_DMA_FPORT_MASK 0x7 266 #define TX_DMA_INS_VLAN BIT(16) 267 268 /* QDMA descriptor txd3 */ 269 #define TX_DMA_OWNER_CPU BIT(31) 270 #define TX_DMA_LS0 BIT(30) 271 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 272 #define TX_DMA_SWC BIT(14) 273 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 274 275 /* QDMA descriptor rxd2 */ 276 #define RX_DMA_DONE BIT(31) 277 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 278 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 279 280 /* QDMA descriptor rxd3 */ 281 #define RX_DMA_VID(_x) ((_x) & 0xfff) 282 283 /* QDMA descriptor rxd4 */ 284 #define RX_DMA_L4_VALID BIT(24) 285 #define RX_DMA_FPORT_SHIFT 19 286 #define RX_DMA_FPORT_MASK 0x7 287 288 /* PHY Indirect Access Control registers */ 289 #define MTK_PHY_IAC 0x10004 290 #define PHY_IAC_ACCESS BIT(31) 291 #define PHY_IAC_READ BIT(19) 292 #define PHY_IAC_WRITE BIT(18) 293 #define PHY_IAC_START BIT(16) 294 #define PHY_IAC_ADDR_SHIFT 20 295 #define PHY_IAC_REG_SHIFT 25 296 #define PHY_IAC_TIMEOUT HZ 297 298 /* Mac control registers */ 299 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 300 #define MAC_MCR_MAX_RX_1536 BIT(24) 301 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 302 #define MAC_MCR_FORCE_MODE BIT(15) 303 #define MAC_MCR_TX_EN BIT(14) 304 #define MAC_MCR_RX_EN BIT(13) 305 #define MAC_MCR_BACKOFF_EN BIT(9) 306 #define MAC_MCR_BACKPR_EN BIT(8) 307 #define MAC_MCR_FORCE_RX_FC BIT(5) 308 #define MAC_MCR_FORCE_TX_FC BIT(4) 309 #define MAC_MCR_SPEED_1000 BIT(3) 310 #define MAC_MCR_SPEED_100 BIT(2) 311 #define MAC_MCR_FORCE_DPX BIT(1) 312 #define MAC_MCR_FORCE_LINK BIT(0) 313 #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ 314 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ 315 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ 316 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ 317 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ 318 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) 319 320 /* TRGMII RXC control register */ 321 #define TRGMII_RCK_CTRL 0x10300 322 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 323 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 324 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 325 #define RXC_DQSISEL BIT(30) 326 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 327 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 328 329 /* TRGMII RXC control register */ 330 #define TRGMII_TCK_CTRL 0x10340 331 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 332 #define TXC_INV BIT(30) 333 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 334 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 335 336 /* TRGMII Interface mode register */ 337 #define INTF_MODE 0x10390 338 #define TRGMII_INTF_DIS BIT(0) 339 #define TRGMII_MODE BIT(1) 340 #define TRGMII_CENTRAL_ALIGNED BIT(2) 341 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 342 #define INTF_MODE_RGMII_10_100 0 343 344 /* GPIO port control registers for GMAC 2*/ 345 #define GPIO_OD33_CTRL8 0x4c0 346 #define GPIO_BIAS_CTRL 0xed0 347 #define GPIO_DRV_SEL10 0xf00 348 349 /* ethernet subsystem chip id register */ 350 #define ETHSYS_CHIPID0_3 0x0 351 #define ETHSYS_CHIPID4_7 0x4 352 #define MT7623_ETH 7623 353 354 /* ethernet subsystem config register */ 355 #define ETHSYS_SYSCFG0 0x14 356 #define SYSCFG0_GE_MASK 0x3 357 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 358 359 /* ethernet subsystem clock register */ 360 #define ETHSYS_CLKCFG0 0x2c 361 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 362 363 /* ethernet reset control register */ 364 #define ETHSYS_RSTCTRL 0x34 365 #define RSTCTRL_FE BIT(6) 366 #define RSTCTRL_PPE BIT(31) 367 368 struct mtk_rx_dma { 369 unsigned int rxd1; 370 unsigned int rxd2; 371 unsigned int rxd3; 372 unsigned int rxd4; 373 } __packed __aligned(4); 374 375 struct mtk_tx_dma { 376 unsigned int txd1; 377 unsigned int txd2; 378 unsigned int txd3; 379 unsigned int txd4; 380 } __packed __aligned(4); 381 382 struct mtk_eth; 383 struct mtk_mac; 384 385 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 386 * @stats_lock: make sure that stats operations are atomic 387 * @reg_offset: the status register offset of the SoC 388 * @syncp: the refcount 389 * 390 * All of the supported SoCs have hardware counters for traffic statistics. 391 * Whenever the status IRQ triggers we can read the latest stats from these 392 * counters and store them in this struct. 393 */ 394 struct mtk_hw_stats { 395 u64 tx_bytes; 396 u64 tx_packets; 397 u64 tx_skip; 398 u64 tx_collisions; 399 u64 rx_bytes; 400 u64 rx_packets; 401 u64 rx_overflow; 402 u64 rx_fcs_errors; 403 u64 rx_short_errors; 404 u64 rx_long_errors; 405 u64 rx_checksum_errors; 406 u64 rx_flow_control_packets; 407 408 spinlock_t stats_lock; 409 u32 reg_offset; 410 struct u64_stats_sync syncp; 411 }; 412 413 enum mtk_tx_flags { 414 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 415 * track how memory was allocated so that it can be freed properly. 416 */ 417 MTK_TX_FLAGS_SINGLE0 = 0x01, 418 MTK_TX_FLAGS_PAGE0 = 0x02, 419 420 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 421 * SKB out instead of looking up through hardware TX descriptor. 422 */ 423 MTK_TX_FLAGS_FPORT0 = 0x04, 424 MTK_TX_FLAGS_FPORT1 = 0x08, 425 }; 426 427 /* This enum allows us to identify how the clock is defined on the array of the 428 * clock in the order 429 */ 430 enum mtk_clks_map { 431 MTK_CLK_ETHIF, 432 MTK_CLK_ESW, 433 MTK_CLK_GP1, 434 MTK_CLK_GP2, 435 MTK_CLK_TRGPLL, 436 MTK_CLK_MAX 437 }; 438 439 enum mtk_dev_state { 440 MTK_HW_INIT, 441 MTK_RESETTING 442 }; 443 444 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 445 * by the TX descriptor s 446 * @skb: The SKB pointer of the packet being sent 447 * @dma_addr0: The base addr of the first segment 448 * @dma_len0: The length of the first segment 449 * @dma_addr1: The base addr of the second segment 450 * @dma_len1: The length of the second segment 451 */ 452 struct mtk_tx_buf { 453 struct sk_buff *skb; 454 u32 flags; 455 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 456 DEFINE_DMA_UNMAP_LEN(dma_len0); 457 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 458 DEFINE_DMA_UNMAP_LEN(dma_len1); 459 }; 460 461 /* struct mtk_tx_ring - This struct holds info describing a TX ring 462 * @dma: The descriptor ring 463 * @buf: The memory pointed at by the ring 464 * @phys: The physical addr of tx_buf 465 * @next_free: Pointer to the next free descriptor 466 * @last_free: Pointer to the last free descriptor 467 * @thresh: The threshold of minimum amount of free descriptors 468 * @free_count: QDMA uses a linked list. Track how many free descriptors 469 * are present 470 */ 471 struct mtk_tx_ring { 472 struct mtk_tx_dma *dma; 473 struct mtk_tx_buf *buf; 474 dma_addr_t phys; 475 struct mtk_tx_dma *next_free; 476 struct mtk_tx_dma *last_free; 477 u16 thresh; 478 atomic_t free_count; 479 }; 480 481 /* PDMA rx ring mode */ 482 enum mtk_rx_flags { 483 MTK_RX_FLAGS_NORMAL = 0, 484 MTK_RX_FLAGS_HWLRO, 485 }; 486 487 /* struct mtk_rx_ring - This struct holds info describing a RX ring 488 * @dma: The descriptor ring 489 * @data: The memory pointed at by the ring 490 * @phys: The physical addr of rx_buf 491 * @frag_size: How big can each fragment be 492 * @buf_size: The size of each packet buffer 493 * @calc_idx: The current head of ring 494 */ 495 struct mtk_rx_ring { 496 struct mtk_rx_dma *dma; 497 u8 **data; 498 dma_addr_t phys; 499 u16 frag_size; 500 u16 buf_size; 501 u16 dma_size; 502 bool calc_idx_update; 503 u16 calc_idx; 504 u32 crx_idx_reg; 505 }; 506 507 /* currently no SoC has more than 2 macs */ 508 #define MTK_MAX_DEVS 2 509 510 /* struct mtk_eth - This is the main datasructure for holding the state 511 * of the driver 512 * @dev: The device pointer 513 * @base: The mapped register i/o base 514 * @page_lock: Make sure that register operations are atomic 515 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 516 * dummy for NAPI to work 517 * @netdev: The netdev instances 518 * @mac: Each netdev is linked to a physical MAC 519 * @irq: The IRQ that we are using 520 * @msg_enable: Ethtool msg level 521 * @ethsys: The register map pointing at the range used to setup 522 * MII modes 523 * @pctl: The register map pointing at the range used to setup 524 * GMAC port drive/slew values 525 * @dma_refcnt: track how many netdevs are using the DMA engine 526 * @tx_ring: Pointer to the memore holding info about the TX ring 527 * @rx_ring: Pointer to the memore holding info about the RX ring 528 * @tx_napi: The TX NAPI struct 529 * @rx_napi: The RX NAPI struct 530 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 531 * @phy_scratch_ring: physical address of scratch_ring 532 * @scratch_head: The scratch memory that scratch_ring points to. 533 * @clks: clock array for all clocks required 534 * @mii_bus: If there is a bus we need to create an instance for it 535 * @pending_work: The workqueue used to reset the dma ring 536 * @state Initialization and runtime state of the device. 537 */ 538 539 struct mtk_eth { 540 struct device *dev; 541 void __iomem *base; 542 spinlock_t page_lock; 543 spinlock_t irq_lock; 544 struct net_device dummy_dev; 545 struct net_device *netdev[MTK_MAX_DEVS]; 546 struct mtk_mac *mac[MTK_MAX_DEVS]; 547 int irq[3]; 548 u32 msg_enable; 549 unsigned long sysclk; 550 struct regmap *ethsys; 551 struct regmap *pctl; 552 u32 chip_id; 553 bool hwlro; 554 atomic_t dma_refcnt; 555 struct mtk_tx_ring tx_ring; 556 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 557 struct napi_struct tx_napi; 558 struct napi_struct rx_napi; 559 struct mtk_tx_dma *scratch_ring; 560 dma_addr_t phy_scratch_ring; 561 void *scratch_head; 562 struct clk *clks[MTK_CLK_MAX]; 563 564 struct mii_bus *mii_bus; 565 struct work_struct pending_work; 566 unsigned long state; 567 }; 568 569 /* struct mtk_mac - the structure that holds the info about the MACs of the 570 * SoC 571 * @id: The number of the MAC 572 * @ge_mode: Interface mode kept for setup restoring 573 * @of_node: Our devicetree node 574 * @hw: Backpointer to our main datastruture 575 * @hw_stats: Packet statistics counter 576 * @trgmii Indicate if the MAC uses TRGMII connected to internal 577 switch 578 */ 579 struct mtk_mac { 580 int id; 581 int ge_mode; 582 struct device_node *of_node; 583 struct mtk_eth *hw; 584 struct mtk_hw_stats *hw_stats; 585 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 586 int hwlro_ip_cnt; 587 bool trgmii; 588 }; 589 590 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 591 extern const struct of_device_id of_mtk_match[]; 592 593 /* read the hardware status register */ 594 void mtk_stats_update_mac(struct mtk_mac *mac); 595 596 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 597 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 598 599 #endif /* MTK_ETH_H */ 600