1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 #include <linux/rhashtable.h> 19 #include <linux/dim.h> 20 #include <linux/bitfield.h> 21 #include <net/page_pool.h> 22 #include <linux/bpf_trace.h> 23 #include "mtk_ppe.h" 24 25 #define MTK_QDMA_PAGE_SIZE 2048 26 #define MTK_MAX_RX_LENGTH 1536 27 #define MTK_MAX_RX_LENGTH_2K 2048 28 #define MTK_TX_DMA_BUF_LEN 0x3fff 29 #define MTK_TX_DMA_BUF_LEN_V2 0xffff 30 #define MTK_DMA_SIZE 512 31 #define MTK_MAC_COUNT 2 32 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 33 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 34 #define MTK_DMA_DUMMY_DESC 0xffffffff 35 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 36 NETIF_MSG_PROBE | \ 37 NETIF_MSG_LINK | \ 38 NETIF_MSG_TIMER | \ 39 NETIF_MSG_IFDOWN | \ 40 NETIF_MSG_IFUP | \ 41 NETIF_MSG_RX_ERR | \ 42 NETIF_MSG_TX_ERR) 43 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 44 NETIF_F_RXCSUM | \ 45 NETIF_F_HW_VLAN_CTAG_TX | \ 46 NETIF_F_HW_VLAN_CTAG_RX | \ 47 NETIF_F_SG | NETIF_F_TSO | \ 48 NETIF_F_TSO6 | \ 49 NETIF_F_IPV6_CSUM |\ 50 NETIF_F_HW_TC) 51 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 52 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 53 54 #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM 55 #define MTK_PP_PAD (MTK_PP_HEADROOM + \ 56 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 57 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD) 58 59 #define MTK_QRX_OFFSET 0x10 60 61 #define MTK_MAX_RX_RING_NUM 4 62 #define MTK_HW_LRO_DMA_SIZE 8 63 64 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 65 #define MTK_MAX_LRO_IP_CNT 2 66 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 67 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 68 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 69 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 70 #define MTK_HW_LRO_MAX_AGG_CNT 64 71 #define MTK_HW_LRO_BW_THRE 3000 72 #define MTK_HW_LRO_REPLACE_DELTA 1000 73 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 74 75 /* Frame Engine Global Reset Register */ 76 #define MTK_RST_GL 0x04 77 #define RST_GL_PSE BIT(0) 78 79 /* Frame Engine Interrupt Status Register */ 80 #define MTK_INT_STATUS2 0x08 81 #define MTK_GDM1_AF BIT(28) 82 #define MTK_GDM2_AF BIT(29) 83 84 /* PDMA HW LRO Alter Flow Timer Register */ 85 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 86 87 /* Frame Engine Interrupt Grouping Register */ 88 #define MTK_FE_INT_GRP 0x20 89 90 /* CDMP Ingress Control Register */ 91 #define MTK_CDMQ_IG_CTRL 0x1400 92 #define MTK_CDMQ_STAG_EN BIT(0) 93 94 /* CDMP Ingress Control Register */ 95 #define MTK_CDMP_IG_CTRL 0x400 96 #define MTK_CDMP_STAG_EN BIT(0) 97 98 /* CDMP Exgress Control Register */ 99 #define MTK_CDMP_EG_CTRL 0x404 100 101 /* GDM Exgress Control Register */ 102 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 103 #define MTK_GDMA_SPECIAL_TAG BIT(24) 104 #define MTK_GDMA_ICS_EN BIT(22) 105 #define MTK_GDMA_TCS_EN BIT(21) 106 #define MTK_GDMA_UCS_EN BIT(20) 107 #define MTK_GDMA_TO_PDMA 0x0 108 #define MTK_GDMA_TO_PPE 0x4444 109 #define MTK_GDMA_DROP_ALL 0x7777 110 111 /* Unicast Filter MAC Address Register - Low */ 112 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 113 114 /* Unicast Filter MAC Address Register - High */ 115 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 116 117 /* FE global misc reg*/ 118 #define MTK_FE_GLO_MISC 0x124 119 120 /* PSE Free Queue Flow Control */ 121 #define PSE_FQFC_CFG1 0x100 122 #define PSE_FQFC_CFG2 0x104 123 #define PSE_DROP_CFG 0x108 124 125 /* PSE Input Queue Reservation Register*/ 126 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 127 128 /* PSE Output Queue Threshold Register*/ 129 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 130 131 /* GDM and CDM Threshold */ 132 #define MTK_GDM2_THRES 0x1530 133 #define MTK_CDMW0_THRES 0x164c 134 #define MTK_CDMW1_THRES 0x1650 135 #define MTK_CDME0_THRES 0x1654 136 #define MTK_CDME1_THRES 0x1658 137 #define MTK_CDMM_THRES 0x165c 138 139 /* PDMA HW LRO Control Registers */ 140 #define MTK_PDMA_LRO_CTRL_DW0 0x980 141 #define MTK_LRO_EN BIT(0) 142 #define MTK_L3_CKS_UPD_EN BIT(7) 143 #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 144 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 145 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 146 #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 147 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 148 #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 149 150 #define MTK_PDMA_LRO_CTRL_DW1 0x984 151 #define MTK_PDMA_LRO_CTRL_DW2 0x988 152 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 153 #define MTK_ADMA_MODE BIT(15) 154 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 155 156 #define MTK_RX_DMA_LRO_EN BIT(8) 157 #define MTK_MULTI_EN BIT(10) 158 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 159 160 /* PDMA Global Configuration Register */ 161 #define MTK_PDMA_LRO_SDL 0x3000 162 #define MTK_RX_CFG_SDL_OFFSET 16 163 164 /* PDMA Reset Index Register */ 165 #define MTK_PST_DRX_IDX0 BIT(16) 166 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 167 168 /* PDMA Delay Interrupt Register */ 169 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 170 #define MTK_PDMA_DELAY_RX_EN BIT(15) 171 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 172 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 173 174 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 175 #define MTK_PDMA_DELAY_TX_EN BIT(31) 176 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 177 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 178 179 #define MTK_PDMA_DELAY_PINT_MASK 0x7f 180 #define MTK_PDMA_DELAY_PTIME_MASK 0xff 181 182 /* PDMA HW LRO Alter Flow Delta Register */ 183 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 184 185 /* PDMA HW LRO IP Setting Registers */ 186 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 187 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 188 #define MTK_RING_MYIP_VLD BIT(9) 189 190 /* PDMA HW LRO Ring Control Registers */ 191 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 192 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 193 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 194 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 195 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 196 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 197 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 198 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 199 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 200 #define MTK_RING_VLD BIT(8) 201 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 202 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 203 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 204 205 /* QDMA TX Queue Configuration Registers */ 206 #define QDMA_RES_THRES 4 207 208 /* QDMA Global Configuration Register */ 209 #define MTK_RX_2B_OFFSET BIT(31) 210 #define MTK_RX_BT_32DWORDS (3 << 11) 211 #define MTK_NDP_CO_PRO BIT(10) 212 #define MTK_TX_WB_DDONE BIT(6) 213 #define MTK_TX_BT_32DWORDS (3 << 4) 214 #define MTK_RX_DMA_BUSY BIT(3) 215 #define MTK_TX_DMA_BUSY BIT(1) 216 #define MTK_RX_DMA_EN BIT(2) 217 #define MTK_TX_DMA_EN BIT(0) 218 #define MTK_DMA_BUSY_TIMEOUT_US 1000000 219 220 /* QDMA V2 Global Configuration Register */ 221 #define MTK_CHK_DDONE_EN BIT(28) 222 #define MTK_DMAD_WR_WDONE BIT(26) 223 #define MTK_WCOMP_EN BIT(24) 224 #define MTK_RESV_BUF (0x40 << 16) 225 #define MTK_MUTLI_CNT (0x4 << 12) 226 227 /* QDMA Flow Control Register */ 228 #define FC_THRES_DROP_MODE BIT(20) 229 #define FC_THRES_DROP_EN (7 << 16) 230 #define FC_THRES_MIN 0x4444 231 232 /* QDMA Interrupt Status Register */ 233 #define MTK_RX_DONE_DLY BIT(30) 234 #define MTK_TX_DONE_DLY BIT(28) 235 #define MTK_RX_DONE_INT3 BIT(19) 236 #define MTK_RX_DONE_INT2 BIT(18) 237 #define MTK_RX_DONE_INT1 BIT(17) 238 #define MTK_RX_DONE_INT0 BIT(16) 239 #define MTK_TX_DONE_INT3 BIT(3) 240 #define MTK_TX_DONE_INT2 BIT(2) 241 #define MTK_TX_DONE_INT1 BIT(1) 242 #define MTK_TX_DONE_INT0 BIT(0) 243 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 244 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 245 246 #define MTK_RX_DONE_INT_V2 BIT(14) 247 248 /* QDMA Interrupt grouping registers */ 249 #define MTK_RLS_DONE_INT BIT(0) 250 251 #define MTK_STAT_OFFSET 0x40 252 253 /* QDMA TX NUM */ 254 #define MTK_QDMA_TX_NUM 16 255 #define MTK_QDMA_TX_MASK (MTK_QDMA_TX_NUM - 1) 256 #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 257 #define MTK_QDMA_GMAC2_QID 8 258 259 #define MTK_TX_DMA_BUF_SHIFT 8 260 261 /* QDMA V2 descriptor txd6 */ 262 #define TX_DMA_INS_VLAN_V2 BIT(16) 263 /* QDMA V2 descriptor txd5 */ 264 #define TX_DMA_CHKSUM_V2 (0x7 << 28) 265 #define TX_DMA_TSO_V2 BIT(31) 266 267 /* QDMA V2 descriptor txd4 */ 268 #define TX_DMA_FPORT_SHIFT_V2 8 269 #define TX_DMA_FPORT_MASK_V2 0xf 270 #define TX_DMA_SWC_V2 BIT(30) 271 272 #define MTK_WDMA0_BASE 0x2800 273 #define MTK_WDMA1_BASE 0x2c00 274 275 /* QDMA descriptor txd4 */ 276 #define TX_DMA_CHKSUM (0x7 << 29) 277 #define TX_DMA_TSO BIT(28) 278 #define TX_DMA_FPORT_SHIFT 25 279 #define TX_DMA_FPORT_MASK 0x7 280 #define TX_DMA_INS_VLAN BIT(16) 281 282 /* QDMA descriptor txd3 */ 283 #define TX_DMA_OWNER_CPU BIT(31) 284 #define TX_DMA_LS0 BIT(30) 285 #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 286 #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) 287 #define TX_DMA_SWC BIT(14) 288 289 /* PDMA on MT7628 */ 290 #define TX_DMA_DONE BIT(31) 291 #define TX_DMA_LS1 BIT(14) 292 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 293 294 /* QDMA descriptor rxd2 */ 295 #define RX_DMA_DONE BIT(31) 296 #define RX_DMA_LSO BIT(30) 297 #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 298 #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) 299 #define RX_DMA_VTAG BIT(15) 300 301 /* QDMA descriptor rxd3 */ 302 #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 303 #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 304 #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 305 306 /* QDMA descriptor rxd4 */ 307 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 308 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 309 #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 310 #define MTK_RXD4_ALG GENMASK(31, 22) 311 312 /* QDMA descriptor rxd4 */ 313 #define RX_DMA_L4_VALID BIT(24) 314 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 315 #define RX_DMA_SPECIAL_TAG BIT(22) 316 317 /* PDMA descriptor rxd5 */ 318 #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) 319 #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) 320 #define MTK_RXD5_SRC_PORT GENMASK(29, 26) 321 322 #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0xf) 323 #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0x7) 324 325 /* PDMA V2 descriptor rxd3 */ 326 #define RX_DMA_VTAG_V2 BIT(0) 327 #define RX_DMA_L4_VALID_V2 BIT(2) 328 329 /* PHY Indirect Access Control registers */ 330 #define MTK_PHY_IAC 0x10004 331 #define PHY_IAC_ACCESS BIT(31) 332 #define PHY_IAC_REG_MASK GENMASK(29, 25) 333 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 334 #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 335 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 336 #define PHY_IAC_CMD_MASK GENMASK(19, 18) 337 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 338 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 339 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 340 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 341 #define PHY_IAC_START_MASK GENMASK(17, 16) 342 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 343 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 344 #define PHY_IAC_DATA_MASK GENMASK(15, 0) 345 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 346 #define PHY_IAC_TIMEOUT HZ 347 348 #define MTK_MAC_MISC 0x1000c 349 #define MTK_MUX_TO_ESW BIT(0) 350 351 /* Mac control registers */ 352 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 353 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 354 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 355 #define MAC_MCR_MAX_RX_1518 0x0 356 #define MAC_MCR_MAX_RX_1536 0x1 357 #define MAC_MCR_MAX_RX_1552 0x2 358 #define MAC_MCR_MAX_RX_2048 0x3 359 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 360 #define MAC_MCR_FORCE_MODE BIT(15) 361 #define MAC_MCR_TX_EN BIT(14) 362 #define MAC_MCR_RX_EN BIT(13) 363 #define MAC_MCR_BACKOFF_EN BIT(9) 364 #define MAC_MCR_BACKPR_EN BIT(8) 365 #define MAC_MCR_FORCE_RX_FC BIT(5) 366 #define MAC_MCR_FORCE_TX_FC BIT(4) 367 #define MAC_MCR_SPEED_1000 BIT(3) 368 #define MAC_MCR_SPEED_100 BIT(2) 369 #define MAC_MCR_FORCE_DPX BIT(1) 370 #define MAC_MCR_FORCE_LINK BIT(0) 371 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 372 373 /* Mac status registers */ 374 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 375 #define MAC_MSR_EEE1G BIT(7) 376 #define MAC_MSR_EEE100M BIT(6) 377 #define MAC_MSR_RX_FC BIT(5) 378 #define MAC_MSR_TX_FC BIT(4) 379 #define MAC_MSR_SPEED_1000 BIT(3) 380 #define MAC_MSR_SPEED_100 BIT(2) 381 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 382 #define MAC_MSR_DPX BIT(1) 383 #define MAC_MSR_LINK BIT(0) 384 385 /* TRGMII RXC control register */ 386 #define TRGMII_RCK_CTRL 0x10300 387 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 388 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 389 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 390 #define RXC_RST BIT(31) 391 #define RXC_DQSISEL BIT(30) 392 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 393 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 394 395 #define NUM_TRGMII_CTRL 5 396 397 /* TRGMII RXC control register */ 398 #define TRGMII_TCK_CTRL 0x10340 399 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 400 #define TXC_INV BIT(30) 401 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 402 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 403 404 /* TRGMII TX Drive Strength */ 405 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 406 #define TD_DM_DRVP(x) ((x) & 0xf) 407 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 408 409 /* TRGMII Interface mode register */ 410 #define INTF_MODE 0x10390 411 #define TRGMII_INTF_DIS BIT(0) 412 #define TRGMII_MODE BIT(1) 413 #define TRGMII_CENTRAL_ALIGNED BIT(2) 414 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 415 #define INTF_MODE_RGMII_10_100 0 416 417 /* GPIO port control registers for GMAC 2*/ 418 #define GPIO_OD33_CTRL8 0x4c0 419 #define GPIO_BIAS_CTRL 0xed0 420 #define GPIO_DRV_SEL10 0xf00 421 422 /* ethernet subsystem chip id register */ 423 #define ETHSYS_CHIPID0_3 0x0 424 #define ETHSYS_CHIPID4_7 0x4 425 #define MT7623_ETH 7623 426 #define MT7622_ETH 7622 427 #define MT7621_ETH 7621 428 429 /* ethernet system control register */ 430 #define ETHSYS_SYSCFG 0x10 431 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 432 433 /* ethernet subsystem config register */ 434 #define ETHSYS_SYSCFG0 0x14 435 #define SYSCFG0_GE_MASK 0x3 436 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 437 #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 438 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 439 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 440 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 441 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 442 443 444 /* ethernet subsystem clock register */ 445 #define ETHSYS_CLKCFG0 0x2c 446 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 447 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 448 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 449 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 450 451 /* ethernet reset control register */ 452 #define ETHSYS_RSTCTRL 0x34 453 #define RSTCTRL_FE BIT(6) 454 #define RSTCTRL_PPE BIT(31) 455 #define RSTCTRL_PPE1 BIT(30) 456 #define RSTCTRL_ETH BIT(23) 457 458 /* ethernet reset check idle register */ 459 #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 460 461 /* ethernet reset control register */ 462 #define ETHSYS_RSTCTRL 0x34 463 #define RSTCTRL_FE BIT(6) 464 #define RSTCTRL_PPE BIT(31) 465 466 /* ethernet dma channel agent map */ 467 #define ETHSYS_DMA_AG_MAP 0x408 468 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 469 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 470 #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 471 472 /* SGMII subsystem config registers */ 473 /* Register to auto-negotiation restart */ 474 #define SGMSYS_PCS_CONTROL_1 0x0 475 #define SGMII_AN_RESTART BIT(9) 476 #define SGMII_ISOLATE BIT(10) 477 #define SGMII_AN_ENABLE BIT(12) 478 #define SGMII_LINK_STATYS BIT(18) 479 #define SGMII_AN_ABILITY BIT(19) 480 #define SGMII_AN_COMPLETE BIT(21) 481 #define SGMII_PCS_FAULT BIT(23) 482 #define SGMII_AN_EXPANSION_CLR BIT(30) 483 484 /* Register to programmable link timer, the unit in 2 * 8ns */ 485 #define SGMSYS_PCS_LINK_TIMER 0x18 486 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 487 488 /* Register to control remote fault */ 489 #define SGMSYS_SGMII_MODE 0x20 490 #define SGMII_IF_MODE_BIT0 BIT(0) 491 #define SGMII_SPEED_DUPLEX_AN BIT(1) 492 #define SGMII_SPEED_MASK GENMASK(3, 2) 493 #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) 494 #define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) 495 #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) 496 #define SGMII_DUPLEX_FULL BIT(4) 497 #define SGMII_IF_MODE_BIT5 BIT(5) 498 #define SGMII_REMOTE_FAULT_DIS BIT(8) 499 #define SGMII_CODE_SYNC_SET_VAL BIT(9) 500 #define SGMII_CODE_SYNC_SET_EN BIT(10) 501 #define SGMII_SEND_AN_ERROR_EN BIT(11) 502 #define SGMII_IF_MODE_MASK GENMASK(5, 1) 503 504 /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 505 #define SGMSYS_ANA_RG_CS3 0x2028 506 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 507 #define RG_PHY_SPEED_1_25G 0x0 508 #define RG_PHY_SPEED_3_125G BIT(2) 509 510 /* Register to power up QPHY */ 511 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 512 #define SGMII_PHYA_PWD BIT(4) 513 514 /* Infrasys subsystem config registers */ 515 #define INFRA_MISC2 0x70c 516 #define CO_QPHY_SEL BIT(0) 517 #define GEPHY_MAC_SEL BIT(1) 518 519 /* MT7628/88 specific stuff */ 520 #define MT7628_PDMA_OFFSET 0x0800 521 #define MT7628_SDM_OFFSET 0x0c00 522 523 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 524 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 525 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 526 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 527 #define MT7628_PST_DTX_IDX0 BIT(0) 528 529 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 530 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 531 532 /* Counter / stat register */ 533 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 534 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 535 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 536 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 537 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 538 539 struct mtk_rx_dma { 540 unsigned int rxd1; 541 unsigned int rxd2; 542 unsigned int rxd3; 543 unsigned int rxd4; 544 } __packed __aligned(4); 545 546 struct mtk_rx_dma_v2 { 547 unsigned int rxd1; 548 unsigned int rxd2; 549 unsigned int rxd3; 550 unsigned int rxd4; 551 unsigned int rxd5; 552 unsigned int rxd6; 553 unsigned int rxd7; 554 unsigned int rxd8; 555 } __packed __aligned(4); 556 557 struct mtk_tx_dma { 558 unsigned int txd1; 559 unsigned int txd2; 560 unsigned int txd3; 561 unsigned int txd4; 562 } __packed __aligned(4); 563 564 struct mtk_tx_dma_v2 { 565 unsigned int txd1; 566 unsigned int txd2; 567 unsigned int txd3; 568 unsigned int txd4; 569 unsigned int txd5; 570 unsigned int txd6; 571 unsigned int txd7; 572 unsigned int txd8; 573 } __packed __aligned(4); 574 575 struct mtk_eth; 576 struct mtk_mac; 577 578 struct mtk_xdp_stats { 579 u64 rx_xdp_redirect; 580 u64 rx_xdp_pass; 581 u64 rx_xdp_drop; 582 u64 rx_xdp_tx; 583 u64 rx_xdp_tx_errors; 584 u64 tx_xdp_xmit; 585 u64 tx_xdp_xmit_errors; 586 }; 587 588 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 589 * @stats_lock: make sure that stats operations are atomic 590 * @reg_offset: the status register offset of the SoC 591 * @syncp: the refcount 592 * 593 * All of the supported SoCs have hardware counters for traffic statistics. 594 * Whenever the status IRQ triggers we can read the latest stats from these 595 * counters and store them in this struct. 596 */ 597 struct mtk_hw_stats { 598 u64 tx_bytes; 599 u64 tx_packets; 600 u64 tx_skip; 601 u64 tx_collisions; 602 u64 rx_bytes; 603 u64 rx_packets; 604 u64 rx_overflow; 605 u64 rx_fcs_errors; 606 u64 rx_short_errors; 607 u64 rx_long_errors; 608 u64 rx_checksum_errors; 609 u64 rx_flow_control_packets; 610 611 struct mtk_xdp_stats xdp_stats; 612 613 spinlock_t stats_lock; 614 u32 reg_offset; 615 struct u64_stats_sync syncp; 616 }; 617 618 enum mtk_tx_flags { 619 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 620 * track how memory was allocated so that it can be freed properly. 621 */ 622 MTK_TX_FLAGS_SINGLE0 = 0x01, 623 MTK_TX_FLAGS_PAGE0 = 0x02, 624 625 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 626 * SKB out instead of looking up through hardware TX descriptor. 627 */ 628 MTK_TX_FLAGS_FPORT0 = 0x04, 629 MTK_TX_FLAGS_FPORT1 = 0x08, 630 }; 631 632 /* This enum allows us to identify how the clock is defined on the array of the 633 * clock in the order 634 */ 635 enum mtk_clks_map { 636 MTK_CLK_ETHIF, 637 MTK_CLK_SGMIITOP, 638 MTK_CLK_ESW, 639 MTK_CLK_GP0, 640 MTK_CLK_GP1, 641 MTK_CLK_GP2, 642 MTK_CLK_FE, 643 MTK_CLK_TRGPLL, 644 MTK_CLK_SGMII_TX_250M, 645 MTK_CLK_SGMII_RX_250M, 646 MTK_CLK_SGMII_CDR_REF, 647 MTK_CLK_SGMII_CDR_FB, 648 MTK_CLK_SGMII2_TX_250M, 649 MTK_CLK_SGMII2_RX_250M, 650 MTK_CLK_SGMII2_CDR_REF, 651 MTK_CLK_SGMII2_CDR_FB, 652 MTK_CLK_SGMII_CK, 653 MTK_CLK_ETH2PLL, 654 MTK_CLK_WOCPU0, 655 MTK_CLK_WOCPU1, 656 MTK_CLK_NETSYS0, 657 MTK_CLK_NETSYS1, 658 MTK_CLK_MAX 659 }; 660 661 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 662 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 663 BIT(MTK_CLK_TRGPLL)) 664 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 665 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 666 BIT(MTK_CLK_GP2) | \ 667 BIT(MTK_CLK_SGMII_TX_250M) | \ 668 BIT(MTK_CLK_SGMII_RX_250M) | \ 669 BIT(MTK_CLK_SGMII_CDR_REF) | \ 670 BIT(MTK_CLK_SGMII_CDR_FB) | \ 671 BIT(MTK_CLK_SGMII_CK) | \ 672 BIT(MTK_CLK_ETH2PLL)) 673 #define MT7621_CLKS_BITMAP (0) 674 #define MT7628_CLKS_BITMAP (0) 675 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 676 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 677 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 678 BIT(MTK_CLK_SGMII_TX_250M) | \ 679 BIT(MTK_CLK_SGMII_RX_250M) | \ 680 BIT(MTK_CLK_SGMII_CDR_REF) | \ 681 BIT(MTK_CLK_SGMII_CDR_FB) | \ 682 BIT(MTK_CLK_SGMII2_TX_250M) | \ 683 BIT(MTK_CLK_SGMII2_RX_250M) | \ 684 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 685 BIT(MTK_CLK_SGMII2_CDR_FB) | \ 686 BIT(MTK_CLK_SGMII_CK) | \ 687 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 688 #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ 689 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ 690 BIT(MTK_CLK_SGMII_TX_250M) | \ 691 BIT(MTK_CLK_SGMII_RX_250M) | \ 692 BIT(MTK_CLK_SGMII_CDR_REF) | \ 693 BIT(MTK_CLK_SGMII_CDR_FB) | \ 694 BIT(MTK_CLK_SGMII2_TX_250M) | \ 695 BIT(MTK_CLK_SGMII2_RX_250M) | \ 696 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 697 BIT(MTK_CLK_SGMII2_CDR_FB)) 698 699 enum mtk_dev_state { 700 MTK_HW_INIT, 701 MTK_RESETTING 702 }; 703 704 enum mtk_tx_buf_type { 705 MTK_TYPE_SKB, 706 MTK_TYPE_XDP_TX, 707 MTK_TYPE_XDP_NDO, 708 }; 709 710 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 711 * by the TX descriptor s 712 * @skb: The SKB pointer of the packet being sent 713 * @dma_addr0: The base addr of the first segment 714 * @dma_len0: The length of the first segment 715 * @dma_addr1: The base addr of the second segment 716 * @dma_len1: The length of the second segment 717 */ 718 struct mtk_tx_buf { 719 enum mtk_tx_buf_type type; 720 void *data; 721 722 u32 flags; 723 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 724 DEFINE_DMA_UNMAP_LEN(dma_len0); 725 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 726 DEFINE_DMA_UNMAP_LEN(dma_len1); 727 }; 728 729 /* struct mtk_tx_ring - This struct holds info describing a TX ring 730 * @dma: The descriptor ring 731 * @buf: The memory pointed at by the ring 732 * @phys: The physical addr of tx_buf 733 * @next_free: Pointer to the next free descriptor 734 * @last_free: Pointer to the last free descriptor 735 * @last_free_ptr: Hardware pointer value of the last free descriptor 736 * @thresh: The threshold of minimum amount of free descriptors 737 * @free_count: QDMA uses a linked list. Track how many free descriptors 738 * are present 739 */ 740 struct mtk_tx_ring { 741 void *dma; 742 struct mtk_tx_buf *buf; 743 dma_addr_t phys; 744 struct mtk_tx_dma *next_free; 745 struct mtk_tx_dma *last_free; 746 u32 last_free_ptr; 747 u16 thresh; 748 atomic_t free_count; 749 int dma_size; 750 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 751 dma_addr_t phys_pdma; 752 int cpu_idx; 753 }; 754 755 /* PDMA rx ring mode */ 756 enum mtk_rx_flags { 757 MTK_RX_FLAGS_NORMAL = 0, 758 MTK_RX_FLAGS_HWLRO, 759 MTK_RX_FLAGS_QDMA, 760 }; 761 762 /* struct mtk_rx_ring - This struct holds info describing a RX ring 763 * @dma: The descriptor ring 764 * @data: The memory pointed at by the ring 765 * @phys: The physical addr of rx_buf 766 * @frag_size: How big can each fragment be 767 * @buf_size: The size of each packet buffer 768 * @calc_idx: The current head of ring 769 */ 770 struct mtk_rx_ring { 771 void *dma; 772 u8 **data; 773 dma_addr_t phys; 774 u16 frag_size; 775 u16 buf_size; 776 u16 dma_size; 777 bool calc_idx_update; 778 u16 calc_idx; 779 u32 crx_idx_reg; 780 /* page_pool */ 781 struct page_pool *page_pool; 782 struct xdp_rxq_info xdp_q; 783 }; 784 785 enum mkt_eth_capabilities { 786 MTK_RGMII_BIT = 0, 787 MTK_TRGMII_BIT, 788 MTK_SGMII_BIT, 789 MTK_ESW_BIT, 790 MTK_GEPHY_BIT, 791 MTK_MUX_BIT, 792 MTK_INFRA_BIT, 793 MTK_SHARED_SGMII_BIT, 794 MTK_HWLRO_BIT, 795 MTK_SHARED_INT_BIT, 796 MTK_TRGMII_MT7621_CLK_BIT, 797 MTK_QDMA_BIT, 798 MTK_NETSYS_V2_BIT, 799 MTK_SOC_MT7628_BIT, 800 MTK_RSTCTRL_PPE1_BIT, 801 802 /* MUX BITS*/ 803 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 804 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 805 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 806 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 807 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 808 809 /* PATH BITS */ 810 MTK_ETH_PATH_GMAC1_RGMII_BIT, 811 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 812 MTK_ETH_PATH_GMAC1_SGMII_BIT, 813 MTK_ETH_PATH_GMAC2_RGMII_BIT, 814 MTK_ETH_PATH_GMAC2_SGMII_BIT, 815 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 816 MTK_ETH_PATH_GDM1_ESW_BIT, 817 }; 818 819 /* Supported hardware group on SoCs */ 820 #define MTK_RGMII BIT(MTK_RGMII_BIT) 821 #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 822 #define MTK_SGMII BIT(MTK_SGMII_BIT) 823 #define MTK_ESW BIT(MTK_ESW_BIT) 824 #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 825 #define MTK_MUX BIT(MTK_MUX_BIT) 826 #define MTK_INFRA BIT(MTK_INFRA_BIT) 827 #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 828 #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 829 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 830 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 831 #define MTK_QDMA BIT(MTK_QDMA_BIT) 832 #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) 833 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 834 #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) 835 836 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 837 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 838 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 839 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 840 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 841 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 842 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 843 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 844 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 845 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 846 847 /* Supported path present on SoCs */ 848 #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 849 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 850 #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 851 #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 852 #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 853 #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 854 #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 855 856 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 857 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 858 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 859 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 860 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 861 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 862 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 863 864 /* MUXes present on SoCs */ 865 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 866 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 867 868 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 869 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 870 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 871 872 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 873 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 874 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 875 876 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 877 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 878 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 879 MTK_SHARED_SGMII) 880 881 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 882 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 883 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 884 885 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 886 887 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 888 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 889 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 890 891 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 892 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 893 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 894 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 895 896 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 897 MTK_QDMA) 898 899 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 900 901 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 902 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 903 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 904 MTK_MUX_U3_GMAC2_TO_QPHY | \ 905 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 906 907 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 908 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 909 MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) 910 911 struct mtk_tx_dma_desc_info { 912 dma_addr_t addr; 913 u32 size; 914 u16 vlan_tci; 915 u16 qid; 916 u8 gso:1; 917 u8 csum:1; 918 u8 vlan:1; 919 u8 first:1; 920 u8 last:1; 921 }; 922 923 struct mtk_reg_map { 924 u32 tx_irq_mask; 925 u32 tx_irq_status; 926 struct { 927 u32 rx_ptr; /* rx base pointer */ 928 u32 rx_cnt_cfg; /* rx max count configuration */ 929 u32 pcrx_ptr; /* rx cpu pointer */ 930 u32 glo_cfg; /* global configuration */ 931 u32 rst_idx; /* reset index */ 932 u32 delay_irq; /* delay interrupt */ 933 u32 irq_status; /* interrupt status */ 934 u32 irq_mask; /* interrupt mask */ 935 u32 int_grp; 936 } pdma; 937 struct { 938 u32 qtx_cfg; /* tx queue configuration */ 939 u32 rx_ptr; /* rx base pointer */ 940 u32 rx_cnt_cfg; /* rx max count configuration */ 941 u32 qcrx_ptr; /* rx cpu pointer */ 942 u32 glo_cfg; /* global configuration */ 943 u32 rst_idx; /* reset index */ 944 u32 delay_irq; /* delay interrupt */ 945 u32 fc_th; /* flow control */ 946 u32 int_grp; 947 u32 hred; /* interrupt mask */ 948 u32 ctx_ptr; /* tx acquire cpu pointer */ 949 u32 dtx_ptr; /* tx acquire dma pointer */ 950 u32 crx_ptr; /* tx release cpu pointer */ 951 u32 drx_ptr; /* tx release dma pointer */ 952 u32 fq_head; /* fq head pointer */ 953 u32 fq_tail; /* fq tail pointer */ 954 u32 fq_count; /* fq free page count */ 955 u32 fq_blen; /* fq free page buffer length */ 956 } qdma; 957 u32 gdm1_cnt; 958 }; 959 960 /* struct mtk_eth_data - This is the structure holding all differences 961 * among various plaforms 962 * @reg_map Soc register map. 963 * @ana_rgc3: The offset for register ANA_RGC3 related to 964 * sgmiisys syscon 965 * @caps Flags shown the extra capability for the SoC 966 * @hw_features Flags shown HW features 967 * @required_clks Flags shown the bitmap for required clocks on 968 * the target SoC 969 * @required_pctl A bool value to show whether the SoC requires 970 * the extra setup for those pins used by GMAC. 971 * @txd_size Tx DMA descriptor size. 972 * @rxd_size Rx DMA descriptor size. 973 * @rx_irq_done_mask Rx irq done register mask. 974 * @rx_dma_l4_valid Rx DMA valid register mask. 975 * @dma_max_len Max DMA tx/rx buffer length. 976 * @dma_len_offset Tx/Rx DMA length field offset. 977 */ 978 struct mtk_soc_data { 979 const struct mtk_reg_map *reg_map; 980 u32 ana_rgc3; 981 u32 caps; 982 u32 required_clks; 983 bool required_pctl; 984 u8 offload_version; 985 netdev_features_t hw_features; 986 struct { 987 u32 txd_size; 988 u32 rxd_size; 989 u32 rx_irq_done_mask; 990 u32 rx_dma_l4_valid; 991 u32 dma_max_len; 992 u32 dma_len_offset; 993 } txrx; 994 }; 995 996 /* currently no SoC has more than 2 macs */ 997 #define MTK_MAX_DEVS 2 998 999 /* struct mtk_pcs - This structure holds each sgmii regmap and associated 1000 * data 1001 * @regmap: The register map pointing at the range used to setup 1002 * SGMII modes 1003 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 1004 * @pcs: Phylink PCS structure 1005 */ 1006 struct mtk_pcs { 1007 struct regmap *regmap; 1008 u32 ana_rgc3; 1009 struct phylink_pcs pcs; 1010 }; 1011 1012 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 1013 * characteristics 1014 * @pcs Array of individual PCS structures 1015 */ 1016 struct mtk_sgmii { 1017 struct mtk_pcs pcs[MTK_MAX_DEVS]; 1018 }; 1019 1020 /* struct mtk_eth - This is the main datasructure for holding the state 1021 * of the driver 1022 * @dev: The device pointer 1023 * @dev: The device pointer used for dma mapping/alloc 1024 * @base: The mapped register i/o base 1025 * @page_lock: Make sure that register operations are atomic 1026 * @tx_irq__lock: Make sure that IRQ register operations are atomic 1027 * @rx_irq__lock: Make sure that IRQ register operations are atomic 1028 * @dim_lock: Make sure that Net DIM operations are atomic 1029 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 1030 * dummy for NAPI to work 1031 * @netdev: The netdev instances 1032 * @mac: Each netdev is linked to a physical MAC 1033 * @irq: The IRQ that we are using 1034 * @msg_enable: Ethtool msg level 1035 * @ethsys: The register map pointing at the range used to setup 1036 * MII modes 1037 * @infra: The register map pointing at the range used to setup 1038 * SGMII and GePHY path 1039 * @pctl: The register map pointing at the range used to setup 1040 * GMAC port drive/slew values 1041 * @dma_refcnt: track how many netdevs are using the DMA engine 1042 * @tx_ring: Pointer to the memory holding info about the TX ring 1043 * @rx_ring: Pointer to the memory holding info about the RX ring 1044 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 1045 * @tx_napi: The TX NAPI struct 1046 * @rx_napi: The RX NAPI struct 1047 * @rx_events: Net DIM RX event counter 1048 * @rx_packets: Net DIM RX packet counter 1049 * @rx_bytes: Net DIM RX byte counter 1050 * @rx_dim: Net DIM RX context 1051 * @tx_events: Net DIM TX event counter 1052 * @tx_packets: Net DIM TX packet counter 1053 * @tx_bytes: Net DIM TX byte counter 1054 * @tx_dim: Net DIM TX context 1055 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1056 * @phy_scratch_ring: physical address of scratch_ring 1057 * @scratch_head: The scratch memory that scratch_ring points to. 1058 * @clks: clock array for all clocks required 1059 * @mii_bus: If there is a bus we need to create an instance for it 1060 * @pending_work: The workqueue used to reset the dma ring 1061 * @state: Initialization and runtime state of the device 1062 * @soc: Holding specific data among vaious SoCs 1063 */ 1064 1065 struct mtk_eth { 1066 struct device *dev; 1067 struct device *dma_dev; 1068 void __iomem *base; 1069 spinlock_t page_lock; 1070 spinlock_t tx_irq_lock; 1071 spinlock_t rx_irq_lock; 1072 struct net_device dummy_dev; 1073 struct net_device *netdev[MTK_MAX_DEVS]; 1074 struct mtk_mac *mac[MTK_MAX_DEVS]; 1075 int irq[3]; 1076 u32 msg_enable; 1077 unsigned long sysclk; 1078 struct regmap *ethsys; 1079 struct regmap *infra; 1080 struct mtk_sgmii *sgmii; 1081 struct regmap *pctl; 1082 bool hwlro; 1083 refcount_t dma_refcnt; 1084 struct mtk_tx_ring tx_ring; 1085 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 1086 struct mtk_rx_ring rx_ring_qdma; 1087 struct napi_struct tx_napi; 1088 struct napi_struct rx_napi; 1089 void *scratch_ring; 1090 dma_addr_t phy_scratch_ring; 1091 void *scratch_head; 1092 struct clk *clks[MTK_CLK_MAX]; 1093 1094 struct mii_bus *mii_bus; 1095 struct work_struct pending_work; 1096 unsigned long state; 1097 1098 const struct mtk_soc_data *soc; 1099 1100 spinlock_t dim_lock; 1101 1102 u32 rx_events; 1103 u32 rx_packets; 1104 u32 rx_bytes; 1105 struct dim rx_dim; 1106 1107 u32 tx_events; 1108 u32 tx_packets; 1109 u32 tx_bytes; 1110 struct dim tx_dim; 1111 1112 int ip_align; 1113 1114 struct mtk_ppe *ppe; 1115 struct rhashtable flow_table; 1116 1117 struct bpf_prog __rcu *prog; 1118 }; 1119 1120 /* struct mtk_mac - the structure that holds the info about the MACs of the 1121 * SoC 1122 * @id: The number of the MAC 1123 * @interface: Interface mode kept for detecting change in hw settings 1124 * @of_node: Our devicetree node 1125 * @hw: Backpointer to our main datastruture 1126 * @hw_stats: Packet statistics counter 1127 */ 1128 struct mtk_mac { 1129 int id; 1130 phy_interface_t interface; 1131 int speed; 1132 struct device_node *of_node; 1133 struct phylink *phylink; 1134 struct phylink_config phylink_config; 1135 struct mtk_eth *hw; 1136 struct mtk_hw_stats *hw_stats; 1137 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1138 int hwlro_ip_cnt; 1139 unsigned int syscfg0; 1140 }; 1141 1142 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1143 extern const struct of_device_id of_mtk_match[]; 1144 1145 /* read the hardware status register */ 1146 void mtk_stats_update_mac(struct mtk_mac *mac); 1147 1148 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1149 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1150 1151 struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id); 1152 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 1153 u32 ana_rgc3); 1154 1155 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 1156 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 1157 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 1158 1159 int mtk_eth_offload_init(struct mtk_eth *eth); 1160 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1161 void *type_data); 1162 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1163 1164 1165 #endif /* MTK_ETH_H */ 1166