1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #ifndef MTK_ETH_H 10 #define MTK_ETH_H 11 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/of_net.h> 15 #include <linux/u64_stats_sync.h> 16 #include <linux/refcount.h> 17 #include <linux/phylink.h> 18 #include <linux/rhashtable.h> 19 #include <linux/dim.h> 20 #include <linux/bitfield.h> 21 #include <net/page_pool.h> 22 #include <linux/bpf_trace.h> 23 #include "mtk_ppe.h" 24 25 #define MTK_MAX_DSA_PORTS 7 26 #define MTK_DSA_PORT_MASK GENMASK(2, 0) 27 28 #define MTK_QDMA_NUM_QUEUES 16 29 #define MTK_QDMA_PAGE_SIZE 2048 30 #define MTK_MAX_RX_LENGTH 1536 31 #define MTK_MAX_RX_LENGTH_2K 2048 32 #define MTK_TX_DMA_BUF_LEN 0x3fff 33 #define MTK_TX_DMA_BUF_LEN_V2 0xffff 34 #define MTK_QDMA_RING_SIZE 2048 35 #define MTK_DMA_SIZE 512 36 #define MTK_MAC_COUNT 2 37 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 38 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 39 #define MTK_DMA_DUMMY_DESC 0xffffffff 40 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 41 NETIF_MSG_PROBE | \ 42 NETIF_MSG_LINK | \ 43 NETIF_MSG_TIMER | \ 44 NETIF_MSG_IFDOWN | \ 45 NETIF_MSG_IFUP | \ 46 NETIF_MSG_RX_ERR | \ 47 NETIF_MSG_TX_ERR) 48 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 49 NETIF_F_RXCSUM | \ 50 NETIF_F_HW_VLAN_CTAG_TX | \ 51 NETIF_F_HW_VLAN_CTAG_RX | \ 52 NETIF_F_SG | NETIF_F_TSO | \ 53 NETIF_F_TSO6 | \ 54 NETIF_F_IPV6_CSUM |\ 55 NETIF_F_HW_TC) 56 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 57 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 58 59 #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM 60 #define MTK_PP_PAD (MTK_PP_HEADROOM + \ 61 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 62 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD) 63 64 #define MTK_QRX_OFFSET 0x10 65 66 #define MTK_MAX_RX_RING_NUM 4 67 #define MTK_HW_LRO_DMA_SIZE 8 68 69 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 70 #define MTK_MAX_LRO_IP_CNT 2 71 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 72 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 73 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 74 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 75 #define MTK_HW_LRO_MAX_AGG_CNT 64 76 #define MTK_HW_LRO_BW_THRE 3000 77 #define MTK_HW_LRO_REPLACE_DELTA 1000 78 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 79 80 /* Frame Engine Global Configuration */ 81 #define MTK_FE_GLO_CFG 0x00 82 #define MTK_FE_LINK_DOWN_P3 BIT(11) 83 #define MTK_FE_LINK_DOWN_P4 BIT(12) 84 85 /* Frame Engine Global Reset Register */ 86 #define MTK_RST_GL 0x04 87 #define RST_GL_PSE BIT(0) 88 89 /* Frame Engine Interrupt Status Register */ 90 #define MTK_INT_STATUS2 0x08 91 #define MTK_FE_INT_ENABLE 0x0c 92 #define MTK_FE_INT_FQ_EMPTY BIT(8) 93 #define MTK_FE_INT_TSO_FAIL BIT(12) 94 #define MTK_FE_INT_TSO_ILLEGAL BIT(13) 95 #define MTK_FE_INT_TSO_ALIGN BIT(14) 96 #define MTK_FE_INT_RFIFO_OV BIT(18) 97 #define MTK_FE_INT_RFIFO_UF BIT(19) 98 #define MTK_GDM1_AF BIT(28) 99 #define MTK_GDM2_AF BIT(29) 100 101 /* PDMA HW LRO Alter Flow Timer Register */ 102 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 103 104 /* Frame Engine Interrupt Grouping Register */ 105 #define MTK_FE_INT_GRP 0x20 106 107 /* CDMP Ingress Control Register */ 108 #define MTK_CDMQ_IG_CTRL 0x1400 109 #define MTK_CDMQ_STAG_EN BIT(0) 110 111 /* CDMQ Exgress Control Register */ 112 #define MTK_CDMQ_EG_CTRL 0x1404 113 114 /* CDMP Ingress Control Register */ 115 #define MTK_CDMP_IG_CTRL 0x400 116 #define MTK_CDMP_STAG_EN BIT(0) 117 118 /* CDMP Exgress Control Register */ 119 #define MTK_CDMP_EG_CTRL 0x404 120 121 /* GDM Exgress Control Register */ 122 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 123 #define MTK_GDMA_SPECIAL_TAG BIT(24) 124 #define MTK_GDMA_ICS_EN BIT(22) 125 #define MTK_GDMA_TCS_EN BIT(21) 126 #define MTK_GDMA_UCS_EN BIT(20) 127 #define MTK_GDMA_TO_PDMA 0x0 128 #define MTK_GDMA_DROP_ALL 0x7777 129 130 /* Unicast Filter MAC Address Register - Low */ 131 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 132 133 /* Unicast Filter MAC Address Register - High */ 134 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 135 136 /* FE global misc reg*/ 137 #define MTK_FE_GLO_MISC 0x124 138 139 /* PSE Free Queue Flow Control */ 140 #define PSE_FQFC_CFG1 0x100 141 #define PSE_FQFC_CFG2 0x104 142 #define PSE_DROP_CFG 0x108 143 #define PSE_PPE0_DROP 0x110 144 145 /* PSE Input Queue Reservation Register*/ 146 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 147 148 /* PSE Output Queue Threshold Register*/ 149 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 150 151 /* GDM and CDM Threshold */ 152 #define MTK_GDM2_THRES 0x1530 153 #define MTK_CDMW0_THRES 0x164c 154 #define MTK_CDMW1_THRES 0x1650 155 #define MTK_CDME0_THRES 0x1654 156 #define MTK_CDME1_THRES 0x1658 157 #define MTK_CDMM_THRES 0x165c 158 159 /* PDMA HW LRO Control Registers */ 160 #define MTK_PDMA_LRO_CTRL_DW0 0x980 161 #define MTK_LRO_EN BIT(0) 162 #define MTK_L3_CKS_UPD_EN BIT(7) 163 #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 164 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 165 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 166 #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 167 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 168 #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 169 170 #define MTK_PDMA_LRO_CTRL_DW1 0x984 171 #define MTK_PDMA_LRO_CTRL_DW2 0x988 172 #define MTK_PDMA_LRO_CTRL_DW3 0x98c 173 #define MTK_ADMA_MODE BIT(15) 174 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 175 176 #define MTK_RX_DMA_LRO_EN BIT(8) 177 #define MTK_MULTI_EN BIT(10) 178 #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 179 180 /* PDMA Global Configuration Register */ 181 #define MTK_PDMA_LRO_SDL 0x3000 182 #define MTK_RX_CFG_SDL_OFFSET 16 183 184 /* PDMA Reset Index Register */ 185 #define MTK_PST_DRX_IDX0 BIT(16) 186 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 187 188 /* PDMA Delay Interrupt Register */ 189 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 190 #define MTK_PDMA_DELAY_RX_EN BIT(15) 191 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 192 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 193 194 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 195 #define MTK_PDMA_DELAY_TX_EN BIT(31) 196 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 197 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 198 199 #define MTK_PDMA_DELAY_PINT_MASK 0x7f 200 #define MTK_PDMA_DELAY_PTIME_MASK 0xff 201 202 /* PDMA HW LRO Alter Flow Delta Register */ 203 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 204 205 /* PDMA HW LRO IP Setting Registers */ 206 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 207 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 208 #define MTK_RING_MYIP_VLD BIT(9) 209 210 /* PDMA HW LRO Ring Control Registers */ 211 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 212 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 213 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 214 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 215 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 216 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 217 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 218 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 219 #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 220 #define MTK_RING_VLD BIT(8) 221 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 222 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 223 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 224 225 /* QDMA TX Queue Configuration Registers */ 226 #define MTK_QTX_OFFSET 0x10 227 #define QDMA_RES_THRES 4 228 229 /* QDMA Tx Queue Scheduler Configuration Registers */ 230 #define MTK_QTX_SCH_TX_SEL BIT(31) 231 #define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30) 232 233 #define MTK_QTX_SCH_LEAKY_BUCKET_EN BIT(30) 234 #define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28) 235 #define MTK_QTX_SCH_MIN_RATE_EN BIT(27) 236 #define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20) 237 #define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16) 238 #define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12) 239 #define MTK_QTX_SCH_MAX_RATE_EN BIT(11) 240 #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4) 241 #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0) 242 243 /* QDMA TX Scheduler Rate Control Register */ 244 #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15) 245 246 /* QDMA Global Configuration Register */ 247 #define MTK_RX_2B_OFFSET BIT(31) 248 #define MTK_RX_BT_32DWORDS (3 << 11) 249 #define MTK_NDP_CO_PRO BIT(10) 250 #define MTK_TX_WB_DDONE BIT(6) 251 #define MTK_TX_BT_32DWORDS (3 << 4) 252 #define MTK_RX_DMA_BUSY BIT(3) 253 #define MTK_TX_DMA_BUSY BIT(1) 254 #define MTK_RX_DMA_EN BIT(2) 255 #define MTK_TX_DMA_EN BIT(0) 256 #define MTK_DMA_BUSY_TIMEOUT_US 1000000 257 258 /* QDMA V2 Global Configuration Register */ 259 #define MTK_CHK_DDONE_EN BIT(28) 260 #define MTK_DMAD_WR_WDONE BIT(26) 261 #define MTK_WCOMP_EN BIT(24) 262 #define MTK_RESV_BUF (0x40 << 16) 263 #define MTK_MUTLI_CNT (0x4 << 12) 264 #define MTK_LEAKY_BUCKET_EN BIT(11) 265 266 /* QDMA Flow Control Register */ 267 #define FC_THRES_DROP_MODE BIT(20) 268 #define FC_THRES_DROP_EN (7 << 16) 269 #define FC_THRES_MIN 0x4444 270 271 /* QDMA Interrupt Status Register */ 272 #define MTK_RX_DONE_DLY BIT(30) 273 #define MTK_TX_DONE_DLY BIT(28) 274 #define MTK_RX_DONE_INT3 BIT(19) 275 #define MTK_RX_DONE_INT2 BIT(18) 276 #define MTK_RX_DONE_INT1 BIT(17) 277 #define MTK_RX_DONE_INT0 BIT(16) 278 #define MTK_TX_DONE_INT3 BIT(3) 279 #define MTK_TX_DONE_INT2 BIT(2) 280 #define MTK_TX_DONE_INT1 BIT(1) 281 #define MTK_TX_DONE_INT0 BIT(0) 282 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 283 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 284 285 #define MTK_RX_DONE_INT_V2 BIT(14) 286 287 #define MTK_CDM_TXFIFO_RDY BIT(7) 288 289 /* QDMA Interrupt grouping registers */ 290 #define MTK_RLS_DONE_INT BIT(0) 291 292 #define MTK_STAT_OFFSET 0x40 293 294 /* QDMA TX NUM */ 295 #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 296 #define MTK_QDMA_GMAC2_QID 8 297 298 #define MTK_TX_DMA_BUF_SHIFT 8 299 300 /* QDMA V2 descriptor txd6 */ 301 #define TX_DMA_INS_VLAN_V2 BIT(16) 302 /* QDMA V2 descriptor txd5 */ 303 #define TX_DMA_CHKSUM_V2 (0x7 << 28) 304 #define TX_DMA_TSO_V2 BIT(31) 305 306 /* QDMA V2 descriptor txd4 */ 307 #define TX_DMA_FPORT_SHIFT_V2 8 308 #define TX_DMA_FPORT_MASK_V2 0xf 309 #define TX_DMA_SWC_V2 BIT(30) 310 311 /* QDMA descriptor txd4 */ 312 #define TX_DMA_CHKSUM (0x7 << 29) 313 #define TX_DMA_TSO BIT(28) 314 #define TX_DMA_FPORT_SHIFT 25 315 #define TX_DMA_FPORT_MASK 0x7 316 #define TX_DMA_INS_VLAN BIT(16) 317 318 /* QDMA descriptor txd3 */ 319 #define TX_DMA_OWNER_CPU BIT(31) 320 #define TX_DMA_LS0 BIT(30) 321 #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 322 #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) 323 #define TX_DMA_SWC BIT(14) 324 #define TX_DMA_PQID GENMASK(3, 0) 325 326 /* PDMA on MT7628 */ 327 #define TX_DMA_DONE BIT(31) 328 #define TX_DMA_LS1 BIT(14) 329 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 330 331 /* QDMA descriptor rxd2 */ 332 #define RX_DMA_DONE BIT(31) 333 #define RX_DMA_LSO BIT(30) 334 #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 335 #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) 336 #define RX_DMA_VTAG BIT(15) 337 338 /* QDMA descriptor rxd3 */ 339 #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 340 #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 341 #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 342 343 /* QDMA descriptor rxd4 */ 344 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 345 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 346 #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 347 #define MTK_RXD4_ALG GENMASK(31, 22) 348 349 /* QDMA descriptor rxd4 */ 350 #define RX_DMA_L4_VALID BIT(24) 351 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 352 #define RX_DMA_SPECIAL_TAG BIT(22) 353 354 /* PDMA descriptor rxd5 */ 355 #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) 356 #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) 357 #define MTK_RXD5_SRC_PORT GENMASK(29, 26) 358 359 #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7) 360 #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf) 361 362 /* PDMA V2 descriptor rxd3 */ 363 #define RX_DMA_VTAG_V2 BIT(0) 364 #define RX_DMA_L4_VALID_V2 BIT(2) 365 366 /* PHY Indirect Access Control registers */ 367 #define MTK_PHY_IAC 0x10004 368 #define PHY_IAC_ACCESS BIT(31) 369 #define PHY_IAC_REG_MASK GENMASK(29, 25) 370 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 371 #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 372 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 373 #define PHY_IAC_CMD_MASK GENMASK(19, 18) 374 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 375 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 376 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 377 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 378 #define PHY_IAC_START_MASK GENMASK(17, 16) 379 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 380 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 381 #define PHY_IAC_DATA_MASK GENMASK(15, 0) 382 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 383 #define PHY_IAC_TIMEOUT HZ 384 385 #define MTK_MAC_MISC 0x1000c 386 #define MTK_MUX_TO_ESW BIT(0) 387 388 /* Mac control registers */ 389 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 390 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 391 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 392 #define MAC_MCR_MAX_RX_1518 0x0 393 #define MAC_MCR_MAX_RX_1536 0x1 394 #define MAC_MCR_MAX_RX_1552 0x2 395 #define MAC_MCR_MAX_RX_2048 0x3 396 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 397 #define MAC_MCR_FORCE_MODE BIT(15) 398 #define MAC_MCR_TX_EN BIT(14) 399 #define MAC_MCR_RX_EN BIT(13) 400 #define MAC_MCR_RX_FIFO_CLR_DIS BIT(12) 401 #define MAC_MCR_BACKOFF_EN BIT(9) 402 #define MAC_MCR_BACKPR_EN BIT(8) 403 #define MAC_MCR_FORCE_RX_FC BIT(5) 404 #define MAC_MCR_FORCE_TX_FC BIT(4) 405 #define MAC_MCR_SPEED_1000 BIT(3) 406 #define MAC_MCR_SPEED_100 BIT(2) 407 #define MAC_MCR_FORCE_DPX BIT(1) 408 #define MAC_MCR_FORCE_LINK BIT(0) 409 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 410 411 /* Mac status registers */ 412 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 413 #define MAC_MSR_EEE1G BIT(7) 414 #define MAC_MSR_EEE100M BIT(6) 415 #define MAC_MSR_RX_FC BIT(5) 416 #define MAC_MSR_TX_FC BIT(4) 417 #define MAC_MSR_SPEED_1000 BIT(3) 418 #define MAC_MSR_SPEED_100 BIT(2) 419 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 420 #define MAC_MSR_DPX BIT(1) 421 #define MAC_MSR_LINK BIT(0) 422 423 /* TRGMII RXC control register */ 424 #define TRGMII_RCK_CTRL 0x10300 425 #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 426 #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 427 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 428 #define RXC_RST BIT(31) 429 #define RXC_DQSISEL BIT(30) 430 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 431 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 432 433 #define NUM_TRGMII_CTRL 5 434 435 /* TRGMII RXC control register */ 436 #define TRGMII_TCK_CTRL 0x10340 437 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 438 #define TXC_INV BIT(30) 439 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 440 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 441 442 /* TRGMII TX Drive Strength */ 443 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 444 #define TD_DM_DRVP(x) ((x) & 0xf) 445 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 446 447 /* TRGMII Interface mode register */ 448 #define INTF_MODE 0x10390 449 #define TRGMII_INTF_DIS BIT(0) 450 #define TRGMII_MODE BIT(1) 451 #define TRGMII_CENTRAL_ALIGNED BIT(2) 452 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 453 #define INTF_MODE_RGMII_10_100 0 454 455 /* GPIO port control registers for GMAC 2*/ 456 #define GPIO_OD33_CTRL8 0x4c0 457 #define GPIO_BIAS_CTRL 0xed0 458 #define GPIO_DRV_SEL10 0xf00 459 460 /* ethernet subsystem chip id register */ 461 #define ETHSYS_CHIPID0_3 0x0 462 #define ETHSYS_CHIPID4_7 0x4 463 #define MT7623_ETH 7623 464 #define MT7622_ETH 7622 465 #define MT7621_ETH 7621 466 467 /* ethernet system control register */ 468 #define ETHSYS_SYSCFG 0x10 469 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 470 471 /* ethernet subsystem config register */ 472 #define ETHSYS_SYSCFG0 0x14 473 #define SYSCFG0_GE_MASK 0x3 474 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 475 #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 476 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 477 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 478 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 479 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 480 481 482 /* ethernet subsystem clock register */ 483 #define ETHSYS_CLKCFG0 0x2c 484 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 485 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 486 #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 487 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 488 489 /* ethernet reset control register */ 490 #define ETHSYS_RSTCTRL 0x34 491 #define RSTCTRL_FE BIT(6) 492 #define RSTCTRL_PPE0 BIT(31) 493 #define RSTCTRL_PPE0_V2 BIT(30) 494 #define RSTCTRL_PPE1 BIT(31) 495 #define RSTCTRL_ETH BIT(23) 496 497 /* ethernet reset check idle register */ 498 #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 499 500 /* ethernet dma channel agent map */ 501 #define ETHSYS_DMA_AG_MAP 0x408 502 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 503 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 504 #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 505 506 /* SGMII subsystem config registers */ 507 /* BMCR (low 16) BMSR (high 16) */ 508 #define SGMSYS_PCS_CONTROL_1 0x0 509 #define SGMII_BMCR GENMASK(15, 0) 510 #define SGMII_BMSR GENMASK(31, 16) 511 #define SGMII_AN_RESTART BIT(9) 512 #define SGMII_ISOLATE BIT(10) 513 #define SGMII_AN_ENABLE BIT(12) 514 #define SGMII_LINK_STATYS BIT(18) 515 #define SGMII_AN_ABILITY BIT(19) 516 #define SGMII_AN_COMPLETE BIT(21) 517 #define SGMII_PCS_FAULT BIT(23) 518 #define SGMII_AN_EXPANSION_CLR BIT(30) 519 520 #define SGMSYS_PCS_ADVERTISE 0x8 521 #define SGMII_ADVERTISE GENMASK(15, 0) 522 #define SGMII_LPA GENMASK(31, 16) 523 524 /* Register to programmable link timer, the unit in 2 * 8ns */ 525 #define SGMSYS_PCS_LINK_TIMER 0x18 526 #define SGMII_LINK_TIMER_MASK GENMASK(19, 0) 527 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & SGMII_LINK_TIMER_MASK) 528 529 /* Register to control remote fault */ 530 #define SGMSYS_SGMII_MODE 0x20 531 #define SGMII_IF_MODE_SGMII BIT(0) 532 #define SGMII_SPEED_DUPLEX_AN BIT(1) 533 #define SGMII_SPEED_MASK GENMASK(3, 2) 534 #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) 535 #define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) 536 #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) 537 #define SGMII_DUPLEX_HALF BIT(4) 538 #define SGMII_IF_MODE_BIT5 BIT(5) 539 #define SGMII_REMOTE_FAULT_DIS BIT(8) 540 #define SGMII_CODE_SYNC_SET_VAL BIT(9) 541 #define SGMII_CODE_SYNC_SET_EN BIT(10) 542 #define SGMII_SEND_AN_ERROR_EN BIT(11) 543 #define SGMII_IF_MODE_MASK GENMASK(5, 1) 544 545 /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 546 #define SGMSYS_ANA_RG_CS3 0x2028 547 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 548 #define RG_PHY_SPEED_1_25G 0x0 549 #define RG_PHY_SPEED_3_125G BIT(2) 550 551 /* Register to power up QPHY */ 552 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 553 #define SGMII_PHYA_PWD BIT(4) 554 555 /* Infrasys subsystem config registers */ 556 #define INFRA_MISC2 0x70c 557 #define CO_QPHY_SEL BIT(0) 558 #define GEPHY_MAC_SEL BIT(1) 559 560 /* MT7628/88 specific stuff */ 561 #define MT7628_PDMA_OFFSET 0x0800 562 #define MT7628_SDM_OFFSET 0x0c00 563 564 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 565 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 566 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 567 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 568 #define MT7628_PST_DTX_IDX0 BIT(0) 569 570 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 571 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 572 573 /* Counter / stat register */ 574 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 575 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 576 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 577 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 578 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 579 580 #define MTK_FE_CDM1_FSM 0x220 581 #define MTK_FE_CDM2_FSM 0x224 582 #define MTK_FE_CDM3_FSM 0x238 583 #define MTK_FE_CDM4_FSM 0x298 584 #define MTK_FE_CDM5_FSM 0x318 585 #define MTK_FE_CDM6_FSM 0x328 586 #define MTK_FE_GDM1_FSM 0x228 587 #define MTK_FE_GDM2_FSM 0x22C 588 589 #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100)) 590 591 struct mtk_rx_dma { 592 unsigned int rxd1; 593 unsigned int rxd2; 594 unsigned int rxd3; 595 unsigned int rxd4; 596 } __packed __aligned(4); 597 598 struct mtk_rx_dma_v2 { 599 unsigned int rxd1; 600 unsigned int rxd2; 601 unsigned int rxd3; 602 unsigned int rxd4; 603 unsigned int rxd5; 604 unsigned int rxd6; 605 unsigned int rxd7; 606 unsigned int rxd8; 607 } __packed __aligned(4); 608 609 struct mtk_tx_dma { 610 unsigned int txd1; 611 unsigned int txd2; 612 unsigned int txd3; 613 unsigned int txd4; 614 } __packed __aligned(4); 615 616 struct mtk_tx_dma_v2 { 617 unsigned int txd1; 618 unsigned int txd2; 619 unsigned int txd3; 620 unsigned int txd4; 621 unsigned int txd5; 622 unsigned int txd6; 623 unsigned int txd7; 624 unsigned int txd8; 625 } __packed __aligned(4); 626 627 struct mtk_eth; 628 struct mtk_mac; 629 630 struct mtk_xdp_stats { 631 u64 rx_xdp_redirect; 632 u64 rx_xdp_pass; 633 u64 rx_xdp_drop; 634 u64 rx_xdp_tx; 635 u64 rx_xdp_tx_errors; 636 u64 tx_xdp_xmit; 637 u64 tx_xdp_xmit_errors; 638 }; 639 640 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 641 * @stats_lock: make sure that stats operations are atomic 642 * @reg_offset: the status register offset of the SoC 643 * @syncp: the refcount 644 * 645 * All of the supported SoCs have hardware counters for traffic statistics. 646 * Whenever the status IRQ triggers we can read the latest stats from these 647 * counters and store them in this struct. 648 */ 649 struct mtk_hw_stats { 650 u64 tx_bytes; 651 u64 tx_packets; 652 u64 tx_skip; 653 u64 tx_collisions; 654 u64 rx_bytes; 655 u64 rx_packets; 656 u64 rx_overflow; 657 u64 rx_fcs_errors; 658 u64 rx_short_errors; 659 u64 rx_long_errors; 660 u64 rx_checksum_errors; 661 u64 rx_flow_control_packets; 662 663 struct mtk_xdp_stats xdp_stats; 664 665 spinlock_t stats_lock; 666 u32 reg_offset; 667 struct u64_stats_sync syncp; 668 }; 669 670 enum mtk_tx_flags { 671 /* PDMA descriptor can point at 1-2 segments. This enum allows us to 672 * track how memory was allocated so that it can be freed properly. 673 */ 674 MTK_TX_FLAGS_SINGLE0 = 0x01, 675 MTK_TX_FLAGS_PAGE0 = 0x02, 676 677 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 678 * SKB out instead of looking up through hardware TX descriptor. 679 */ 680 MTK_TX_FLAGS_FPORT0 = 0x04, 681 MTK_TX_FLAGS_FPORT1 = 0x08, 682 }; 683 684 /* This enum allows us to identify how the clock is defined on the array of the 685 * clock in the order 686 */ 687 enum mtk_clks_map { 688 MTK_CLK_ETHIF, 689 MTK_CLK_SGMIITOP, 690 MTK_CLK_ESW, 691 MTK_CLK_GP0, 692 MTK_CLK_GP1, 693 MTK_CLK_GP2, 694 MTK_CLK_FE, 695 MTK_CLK_TRGPLL, 696 MTK_CLK_SGMII_TX_250M, 697 MTK_CLK_SGMII_RX_250M, 698 MTK_CLK_SGMII_CDR_REF, 699 MTK_CLK_SGMII_CDR_FB, 700 MTK_CLK_SGMII2_TX_250M, 701 MTK_CLK_SGMII2_RX_250M, 702 MTK_CLK_SGMII2_CDR_REF, 703 MTK_CLK_SGMII2_CDR_FB, 704 MTK_CLK_SGMII_CK, 705 MTK_CLK_ETH2PLL, 706 MTK_CLK_WOCPU0, 707 MTK_CLK_WOCPU1, 708 MTK_CLK_NETSYS0, 709 MTK_CLK_NETSYS1, 710 MTK_CLK_MAX 711 }; 712 713 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 714 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 715 BIT(MTK_CLK_TRGPLL)) 716 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 717 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 718 BIT(MTK_CLK_GP2) | \ 719 BIT(MTK_CLK_SGMII_TX_250M) | \ 720 BIT(MTK_CLK_SGMII_RX_250M) | \ 721 BIT(MTK_CLK_SGMII_CDR_REF) | \ 722 BIT(MTK_CLK_SGMII_CDR_FB) | \ 723 BIT(MTK_CLK_SGMII_CK) | \ 724 BIT(MTK_CLK_ETH2PLL)) 725 #define MT7621_CLKS_BITMAP (0) 726 #define MT7628_CLKS_BITMAP (0) 727 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 728 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 729 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 730 BIT(MTK_CLK_SGMII_TX_250M) | \ 731 BIT(MTK_CLK_SGMII_RX_250M) | \ 732 BIT(MTK_CLK_SGMII_CDR_REF) | \ 733 BIT(MTK_CLK_SGMII_CDR_FB) | \ 734 BIT(MTK_CLK_SGMII2_TX_250M) | \ 735 BIT(MTK_CLK_SGMII2_RX_250M) | \ 736 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 737 BIT(MTK_CLK_SGMII2_CDR_FB) | \ 738 BIT(MTK_CLK_SGMII_CK) | \ 739 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 740 #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ 741 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ 742 BIT(MTK_CLK_SGMII_TX_250M) | \ 743 BIT(MTK_CLK_SGMII_RX_250M) | \ 744 BIT(MTK_CLK_SGMII_CDR_REF) | \ 745 BIT(MTK_CLK_SGMII_CDR_FB) | \ 746 BIT(MTK_CLK_SGMII2_TX_250M) | \ 747 BIT(MTK_CLK_SGMII2_RX_250M) | \ 748 BIT(MTK_CLK_SGMII2_CDR_REF) | \ 749 BIT(MTK_CLK_SGMII2_CDR_FB)) 750 751 enum mtk_dev_state { 752 MTK_HW_INIT, 753 MTK_RESETTING 754 }; 755 756 enum mtk_tx_buf_type { 757 MTK_TYPE_SKB, 758 MTK_TYPE_XDP_TX, 759 MTK_TYPE_XDP_NDO, 760 }; 761 762 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 763 * by the TX descriptor s 764 * @skb: The SKB pointer of the packet being sent 765 * @dma_addr0: The base addr of the first segment 766 * @dma_len0: The length of the first segment 767 * @dma_addr1: The base addr of the second segment 768 * @dma_len1: The length of the second segment 769 */ 770 struct mtk_tx_buf { 771 enum mtk_tx_buf_type type; 772 void *data; 773 774 u32 flags; 775 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 776 DEFINE_DMA_UNMAP_LEN(dma_len0); 777 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 778 DEFINE_DMA_UNMAP_LEN(dma_len1); 779 }; 780 781 /* struct mtk_tx_ring - This struct holds info describing a TX ring 782 * @dma: The descriptor ring 783 * @buf: The memory pointed at by the ring 784 * @phys: The physical addr of tx_buf 785 * @next_free: Pointer to the next free descriptor 786 * @last_free: Pointer to the last free descriptor 787 * @last_free_ptr: Hardware pointer value of the last free descriptor 788 * @thresh: The threshold of minimum amount of free descriptors 789 * @free_count: QDMA uses a linked list. Track how many free descriptors 790 * are present 791 */ 792 struct mtk_tx_ring { 793 void *dma; 794 struct mtk_tx_buf *buf; 795 dma_addr_t phys; 796 struct mtk_tx_dma *next_free; 797 struct mtk_tx_dma *last_free; 798 u32 last_free_ptr; 799 u16 thresh; 800 atomic_t free_count; 801 int dma_size; 802 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 803 dma_addr_t phys_pdma; 804 int cpu_idx; 805 }; 806 807 /* PDMA rx ring mode */ 808 enum mtk_rx_flags { 809 MTK_RX_FLAGS_NORMAL = 0, 810 MTK_RX_FLAGS_HWLRO, 811 MTK_RX_FLAGS_QDMA, 812 }; 813 814 /* struct mtk_rx_ring - This struct holds info describing a RX ring 815 * @dma: The descriptor ring 816 * @data: The memory pointed at by the ring 817 * @phys: The physical addr of rx_buf 818 * @frag_size: How big can each fragment be 819 * @buf_size: The size of each packet buffer 820 * @calc_idx: The current head of ring 821 */ 822 struct mtk_rx_ring { 823 void *dma; 824 u8 **data; 825 dma_addr_t phys; 826 u16 frag_size; 827 u16 buf_size; 828 u16 dma_size; 829 bool calc_idx_update; 830 u16 calc_idx; 831 u32 crx_idx_reg; 832 /* page_pool */ 833 struct page_pool *page_pool; 834 struct xdp_rxq_info xdp_q; 835 }; 836 837 enum mkt_eth_capabilities { 838 MTK_RGMII_BIT = 0, 839 MTK_TRGMII_BIT, 840 MTK_SGMII_BIT, 841 MTK_ESW_BIT, 842 MTK_GEPHY_BIT, 843 MTK_MUX_BIT, 844 MTK_INFRA_BIT, 845 MTK_SHARED_SGMII_BIT, 846 MTK_HWLRO_BIT, 847 MTK_SHARED_INT_BIT, 848 MTK_TRGMII_MT7621_CLK_BIT, 849 MTK_QDMA_BIT, 850 MTK_NETSYS_V2_BIT, 851 MTK_SOC_MT7628_BIT, 852 MTK_RSTCTRL_PPE1_BIT, 853 854 /* MUX BITS*/ 855 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 856 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 857 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 858 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 859 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 860 861 /* PATH BITS */ 862 MTK_ETH_PATH_GMAC1_RGMII_BIT, 863 MTK_ETH_PATH_GMAC1_TRGMII_BIT, 864 MTK_ETH_PATH_GMAC1_SGMII_BIT, 865 MTK_ETH_PATH_GMAC2_RGMII_BIT, 866 MTK_ETH_PATH_GMAC2_SGMII_BIT, 867 MTK_ETH_PATH_GMAC2_GEPHY_BIT, 868 MTK_ETH_PATH_GDM1_ESW_BIT, 869 }; 870 871 /* Supported hardware group on SoCs */ 872 #define MTK_RGMII BIT(MTK_RGMII_BIT) 873 #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 874 #define MTK_SGMII BIT(MTK_SGMII_BIT) 875 #define MTK_ESW BIT(MTK_ESW_BIT) 876 #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 877 #define MTK_MUX BIT(MTK_MUX_BIT) 878 #define MTK_INFRA BIT(MTK_INFRA_BIT) 879 #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 880 #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 881 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 882 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 883 #define MTK_QDMA BIT(MTK_QDMA_BIT) 884 #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) 885 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 886 #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) 887 888 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 889 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 890 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 891 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 892 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 893 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 894 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 895 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 896 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 897 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 898 899 /* Supported path present on SoCs */ 900 #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 901 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 902 #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 903 #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 904 #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 905 #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 906 #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 907 908 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 909 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 910 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 911 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 912 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 913 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 914 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 915 916 /* MUXes present on SoCs */ 917 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 918 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 919 920 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 921 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 922 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 923 924 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 925 #define MTK_MUX_U3_GMAC2_TO_QPHY \ 926 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 927 928 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 929 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 930 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 931 MTK_SHARED_SGMII) 932 933 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 934 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 935 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 936 937 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 938 939 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 940 MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 941 MTK_TRGMII_MT7621_CLK | MTK_QDMA) 942 943 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 944 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 945 MTK_MUX_GDM1_TO_GMAC1_ESW | \ 946 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 947 948 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 949 MTK_QDMA) 950 951 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 952 953 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 954 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 955 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 956 MTK_MUX_U3_GMAC2_TO_QPHY | \ 957 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 958 959 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 960 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 961 MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) 962 963 struct mtk_tx_dma_desc_info { 964 dma_addr_t addr; 965 u32 size; 966 u16 vlan_tci; 967 u16 qid; 968 u8 gso:1; 969 u8 csum:1; 970 u8 vlan:1; 971 u8 first:1; 972 u8 last:1; 973 }; 974 975 struct mtk_reg_map { 976 u32 tx_irq_mask; 977 u32 tx_irq_status; 978 struct { 979 u32 rx_ptr; /* rx base pointer */ 980 u32 rx_cnt_cfg; /* rx max count configuration */ 981 u32 pcrx_ptr; /* rx cpu pointer */ 982 u32 glo_cfg; /* global configuration */ 983 u32 rst_idx; /* reset index */ 984 u32 delay_irq; /* delay interrupt */ 985 u32 irq_status; /* interrupt status */ 986 u32 irq_mask; /* interrupt mask */ 987 u32 adma_rx_dbg0; 988 u32 int_grp; 989 } pdma; 990 struct { 991 u32 qtx_cfg; /* tx queue configuration */ 992 u32 qtx_sch; /* tx queue scheduler configuration */ 993 u32 rx_ptr; /* rx base pointer */ 994 u32 rx_cnt_cfg; /* rx max count configuration */ 995 u32 qcrx_ptr; /* rx cpu pointer */ 996 u32 glo_cfg; /* global configuration */ 997 u32 rst_idx; /* reset index */ 998 u32 delay_irq; /* delay interrupt */ 999 u32 fc_th; /* flow control */ 1000 u32 int_grp; 1001 u32 hred; /* interrupt mask */ 1002 u32 ctx_ptr; /* tx acquire cpu pointer */ 1003 u32 dtx_ptr; /* tx acquire dma pointer */ 1004 u32 crx_ptr; /* tx release cpu pointer */ 1005 u32 drx_ptr; /* tx release dma pointer */ 1006 u32 fq_head; /* fq head pointer */ 1007 u32 fq_tail; /* fq tail pointer */ 1008 u32 fq_count; /* fq free page count */ 1009 u32 fq_blen; /* fq free page buffer length */ 1010 u32 tx_sch_rate; /* tx scheduler rate control registers */ 1011 } qdma; 1012 u32 gdm1_cnt; 1013 u32 gdma_to_ppe; 1014 u32 ppe_base; 1015 u32 wdma_base[2]; 1016 u32 pse_iq_sta; 1017 u32 pse_oq_sta; 1018 }; 1019 1020 /* struct mtk_eth_data - This is the structure holding all differences 1021 * among various plaforms 1022 * @reg_map Soc register map. 1023 * @ana_rgc3: The offset for register ANA_RGC3 related to 1024 * sgmiisys syscon 1025 * @caps Flags shown the extra capability for the SoC 1026 * @hw_features Flags shown HW features 1027 * @required_clks Flags shown the bitmap for required clocks on 1028 * the target SoC 1029 * @required_pctl A bool value to show whether the SoC requires 1030 * the extra setup for those pins used by GMAC. 1031 * @hash_offset Flow table hash offset. 1032 * @foe_entry_size Foe table entry size. 1033 * @txd_size Tx DMA descriptor size. 1034 * @rxd_size Rx DMA descriptor size. 1035 * @rx_irq_done_mask Rx irq done register mask. 1036 * @rx_dma_l4_valid Rx DMA valid register mask. 1037 * @dma_max_len Max DMA tx/rx buffer length. 1038 * @dma_len_offset Tx/Rx DMA length field offset. 1039 */ 1040 struct mtk_soc_data { 1041 const struct mtk_reg_map *reg_map; 1042 u32 ana_rgc3; 1043 u32 caps; 1044 u32 required_clks; 1045 bool required_pctl; 1046 u8 offload_version; 1047 u8 hash_offset; 1048 u16 foe_entry_size; 1049 netdev_features_t hw_features; 1050 struct { 1051 u32 txd_size; 1052 u32 rxd_size; 1053 u32 rx_irq_done_mask; 1054 u32 rx_dma_l4_valid; 1055 u32 dma_max_len; 1056 u32 dma_len_offset; 1057 } txrx; 1058 }; 1059 1060 #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) 1061 1062 /* currently no SoC has more than 2 macs */ 1063 #define MTK_MAX_DEVS 2 1064 1065 /* struct mtk_pcs - This structure holds each sgmii regmap and associated 1066 * data 1067 * @regmap: The register map pointing at the range used to setup 1068 * SGMII modes 1069 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 1070 * @interface: Currently configured interface mode 1071 * @pcs: Phylink PCS structure 1072 */ 1073 struct mtk_pcs { 1074 struct regmap *regmap; 1075 u32 ana_rgc3; 1076 phy_interface_t interface; 1077 struct phylink_pcs pcs; 1078 }; 1079 1080 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 1081 * characteristics 1082 * @pcs Array of individual PCS structures 1083 */ 1084 struct mtk_sgmii { 1085 struct mtk_pcs pcs[MTK_MAX_DEVS]; 1086 }; 1087 1088 /* struct mtk_eth - This is the main datasructure for holding the state 1089 * of the driver 1090 * @dev: The device pointer 1091 * @dev: The device pointer used for dma mapping/alloc 1092 * @base: The mapped register i/o base 1093 * @page_lock: Make sure that register operations are atomic 1094 * @tx_irq__lock: Make sure that IRQ register operations are atomic 1095 * @rx_irq__lock: Make sure that IRQ register operations are atomic 1096 * @dim_lock: Make sure that Net DIM operations are atomic 1097 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 1098 * dummy for NAPI to work 1099 * @netdev: The netdev instances 1100 * @mac: Each netdev is linked to a physical MAC 1101 * @irq: The IRQ that we are using 1102 * @msg_enable: Ethtool msg level 1103 * @ethsys: The register map pointing at the range used to setup 1104 * MII modes 1105 * @infra: The register map pointing at the range used to setup 1106 * SGMII and GePHY path 1107 * @pctl: The register map pointing at the range used to setup 1108 * GMAC port drive/slew values 1109 * @dma_refcnt: track how many netdevs are using the DMA engine 1110 * @tx_ring: Pointer to the memory holding info about the TX ring 1111 * @rx_ring: Pointer to the memory holding info about the RX ring 1112 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 1113 * @tx_napi: The TX NAPI struct 1114 * @rx_napi: The RX NAPI struct 1115 * @rx_events: Net DIM RX event counter 1116 * @rx_packets: Net DIM RX packet counter 1117 * @rx_bytes: Net DIM RX byte counter 1118 * @rx_dim: Net DIM RX context 1119 * @tx_events: Net DIM TX event counter 1120 * @tx_packets: Net DIM TX packet counter 1121 * @tx_bytes: Net DIM TX byte counter 1122 * @tx_dim: Net DIM TX context 1123 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1124 * @phy_scratch_ring: physical address of scratch_ring 1125 * @scratch_head: The scratch memory that scratch_ring points to. 1126 * @clks: clock array for all clocks required 1127 * @mii_bus: If there is a bus we need to create an instance for it 1128 * @pending_work: The workqueue used to reset the dma ring 1129 * @state: Initialization and runtime state of the device 1130 * @soc: Holding specific data among vaious SoCs 1131 */ 1132 1133 struct mtk_eth { 1134 struct device *dev; 1135 struct device *dma_dev; 1136 void __iomem *base; 1137 spinlock_t page_lock; 1138 spinlock_t tx_irq_lock; 1139 spinlock_t rx_irq_lock; 1140 struct net_device dummy_dev; 1141 struct net_device *netdev[MTK_MAX_DEVS]; 1142 struct mtk_mac *mac[MTK_MAX_DEVS]; 1143 int irq[3]; 1144 u32 msg_enable; 1145 unsigned long sysclk; 1146 struct regmap *ethsys; 1147 struct regmap *infra; 1148 struct mtk_sgmii *sgmii; 1149 struct regmap *pctl; 1150 bool hwlro; 1151 refcount_t dma_refcnt; 1152 struct mtk_tx_ring tx_ring; 1153 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 1154 struct mtk_rx_ring rx_ring_qdma; 1155 struct napi_struct tx_napi; 1156 struct napi_struct rx_napi; 1157 void *scratch_ring; 1158 dma_addr_t phy_scratch_ring; 1159 void *scratch_head; 1160 struct clk *clks[MTK_CLK_MAX]; 1161 1162 struct mii_bus *mii_bus; 1163 struct work_struct pending_work; 1164 unsigned long state; 1165 1166 const struct mtk_soc_data *soc; 1167 1168 spinlock_t dim_lock; 1169 1170 u32 rx_events; 1171 u32 rx_packets; 1172 u32 rx_bytes; 1173 struct dim rx_dim; 1174 1175 u32 tx_events; 1176 u32 tx_packets; 1177 u32 tx_bytes; 1178 struct dim tx_dim; 1179 1180 int ip_align; 1181 1182 struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS]; 1183 1184 struct mtk_ppe *ppe[2]; 1185 struct rhashtable flow_table; 1186 1187 struct bpf_prog __rcu *prog; 1188 1189 struct { 1190 struct delayed_work monitor_work; 1191 u32 wdidx; 1192 u8 wdma_hang_count; 1193 u8 qdma_hang_count; 1194 u8 adma_hang_count; 1195 } reset; 1196 }; 1197 1198 /* struct mtk_mac - the structure that holds the info about the MACs of the 1199 * SoC 1200 * @id: The number of the MAC 1201 * @interface: Interface mode kept for detecting change in hw settings 1202 * @of_node: Our devicetree node 1203 * @hw: Backpointer to our main datastruture 1204 * @hw_stats: Packet statistics counter 1205 */ 1206 struct mtk_mac { 1207 int id; 1208 phy_interface_t interface; 1209 int speed; 1210 struct device_node *of_node; 1211 struct phylink *phylink; 1212 struct phylink_config phylink_config; 1213 struct mtk_eth *hw; 1214 struct mtk_hw_stats *hw_stats; 1215 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1216 int hwlro_ip_cnt; 1217 unsigned int syscfg0; 1218 struct notifier_block device_notifier; 1219 }; 1220 1221 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1222 extern const struct of_device_id of_mtk_match[]; 1223 1224 static inline struct mtk_foe_entry * 1225 mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 1226 { 1227 const struct mtk_soc_data *soc = ppe->eth->soc; 1228 1229 return ppe->foe_table + hash * soc->foe_entry_size; 1230 } 1231 1232 static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 1233 { 1234 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1235 return MTK_FOE_IB1_BIND_TIMESTAMP_V2; 1236 1237 return MTK_FOE_IB1_BIND_TIMESTAMP; 1238 } 1239 1240 static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 1241 { 1242 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1243 return MTK_FOE_IB1_BIND_PPPOE_V2; 1244 1245 return MTK_FOE_IB1_BIND_PPPOE; 1246 } 1247 1248 static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 1249 { 1250 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1251 return MTK_FOE_IB1_BIND_VLAN_TAG_V2; 1252 1253 return MTK_FOE_IB1_BIND_VLAN_TAG; 1254 } 1255 1256 static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 1257 { 1258 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1259 return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; 1260 1261 return MTK_FOE_IB1_BIND_VLAN_LAYER; 1262 } 1263 1264 static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1265 { 1266 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1267 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1268 1269 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1270 } 1271 1272 static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1273 { 1274 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1275 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1276 1277 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 1278 } 1279 1280 static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 1281 { 1282 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1283 return MTK_FOE_IB1_PACKET_TYPE_V2; 1284 1285 return MTK_FOE_IB1_PACKET_TYPE; 1286 } 1287 1288 static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 1289 { 1290 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1291 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); 1292 1293 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); 1294 } 1295 1296 static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) 1297 { 1298 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1299 return MTK_FOE_IB2_MULTICAST_V2; 1300 1301 return MTK_FOE_IB2_MULTICAST; 1302 } 1303 1304 /* read the hardware status register */ 1305 void mtk_stats_update_mac(struct mtk_mac *mac); 1306 1307 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1308 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1309 1310 struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id); 1311 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 1312 u32 ana_rgc3); 1313 1314 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 1315 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 1316 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 1317 1318 int mtk_eth_offload_init(struct mtk_eth *eth); 1319 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1320 void *type_data); 1321 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1322 1323 1324 #endif /* MTK_ETH_H */ 1325