1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #ifndef MTK_ETH_H 16 #define MTK_ETH_H 17 18 #define MTK_QDMA_PAGE_SIZE 2048 19 #define MTK_MAX_RX_LENGTH 1536 20 #define MTK_TX_DMA_BUF_LEN 0x3fff 21 #define MTK_DMA_SIZE 256 22 #define MTK_NAPI_WEIGHT 64 23 #define MTK_MAC_COUNT 2 24 #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 25 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 26 #define MTK_DMA_DUMMY_DESC 0xffffffff 27 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 28 NETIF_MSG_PROBE | \ 29 NETIF_MSG_LINK | \ 30 NETIF_MSG_TIMER | \ 31 NETIF_MSG_IFDOWN | \ 32 NETIF_MSG_IFUP | \ 33 NETIF_MSG_RX_ERR | \ 34 NETIF_MSG_TX_ERR) 35 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 36 NETIF_F_RXCSUM | \ 37 NETIF_F_HW_VLAN_CTAG_TX | \ 38 NETIF_F_HW_VLAN_CTAG_RX | \ 39 NETIF_F_SG | NETIF_F_TSO | \ 40 NETIF_F_TSO6 | \ 41 NETIF_F_IPV6_CSUM) 42 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (MTK_DMA_SIZE - 1)) 43 44 /* Frame Engine Global Reset Register */ 45 #define MTK_RST_GL 0x04 46 #define RST_GL_PSE BIT(0) 47 48 /* Frame Engine Interrupt Status Register */ 49 #define MTK_INT_STATUS2 0x08 50 #define MTK_GDM1_AF BIT(28) 51 #define MTK_GDM2_AF BIT(29) 52 53 /* Frame Engine Interrupt Grouping Register */ 54 #define MTK_FE_INT_GRP 0x20 55 56 /* CDMP Exgress Control Register */ 57 #define MTK_CDMP_EG_CTRL 0x404 58 59 /* GDM Exgress Control Register */ 60 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 61 #define MTK_GDMA_ICS_EN BIT(22) 62 #define MTK_GDMA_TCS_EN BIT(21) 63 #define MTK_GDMA_UCS_EN BIT(20) 64 65 /* Unicast Filter MAC Address Register - Low */ 66 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 67 68 /* Unicast Filter MAC Address Register - High */ 69 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 70 71 /* QDMA TX Queue Configuration Registers */ 72 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 73 #define QDMA_RES_THRES 4 74 75 /* QDMA TX Queue Scheduler Registers */ 76 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 77 78 /* QDMA RX Base Pointer Register */ 79 #define MTK_QRX_BASE_PTR0 0x1900 80 81 /* QDMA RX Maximum Count Register */ 82 #define MTK_QRX_MAX_CNT0 0x1904 83 84 /* QDMA RX CPU Pointer Register */ 85 #define MTK_QRX_CRX_IDX0 0x1908 86 87 /* QDMA RX DMA Pointer Register */ 88 #define MTK_QRX_DRX_IDX0 0x190C 89 90 /* QDMA Global Configuration Register */ 91 #define MTK_QDMA_GLO_CFG 0x1A04 92 #define MTK_RX_2B_OFFSET BIT(31) 93 #define MTK_RX_BT_32DWORDS (3 << 11) 94 #define MTK_NDP_CO_PRO BIT(10) 95 #define MTK_TX_WB_DDONE BIT(6) 96 #define MTK_DMA_SIZE_16DWORDS (2 << 4) 97 #define MTK_RX_DMA_BUSY BIT(3) 98 #define MTK_TX_DMA_BUSY BIT(1) 99 #define MTK_RX_DMA_EN BIT(2) 100 #define MTK_TX_DMA_EN BIT(0) 101 #define MTK_DMA_BUSY_TIMEOUT HZ 102 103 /* QDMA Reset Index Register */ 104 #define MTK_QDMA_RST_IDX 0x1A08 105 #define MTK_PST_DRX_IDX0 BIT(16) 106 107 /* QDMA Delay Interrupt Register */ 108 #define MTK_QDMA_DELAY_INT 0x1A0C 109 110 /* QDMA Flow Control Register */ 111 #define MTK_QDMA_FC_THRES 0x1A10 112 #define FC_THRES_DROP_MODE BIT(20) 113 #define FC_THRES_DROP_EN (7 << 16) 114 #define FC_THRES_MIN 0x4444 115 116 /* QDMA Interrupt Status Register */ 117 #define MTK_QMTK_INT_STATUS 0x1A18 118 #define MTK_RX_DONE_INT1 BIT(17) 119 #define MTK_RX_DONE_INT0 BIT(16) 120 #define MTK_TX_DONE_INT3 BIT(3) 121 #define MTK_TX_DONE_INT2 BIT(2) 122 #define MTK_TX_DONE_INT1 BIT(1) 123 #define MTK_TX_DONE_INT0 BIT(0) 124 #define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1) 125 #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 126 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 127 128 /* QDMA Interrupt Status Register */ 129 #define MTK_QDMA_INT_MASK 0x1A1C 130 131 /* QDMA Interrupt Mask Register */ 132 #define MTK_QDMA_HRED2 0x1A44 133 134 /* QDMA TX Forward CPU Pointer Register */ 135 #define MTK_QTX_CTX_PTR 0x1B00 136 137 /* QDMA TX Forward DMA Pointer Register */ 138 #define MTK_QTX_DTX_PTR 0x1B04 139 140 /* QDMA TX Release CPU Pointer Register */ 141 #define MTK_QTX_CRX_PTR 0x1B10 142 143 /* QDMA TX Release DMA Pointer Register */ 144 #define MTK_QTX_DRX_PTR 0x1B14 145 146 /* QDMA FQ Head Pointer Register */ 147 #define MTK_QDMA_FQ_HEAD 0x1B20 148 149 /* QDMA FQ Head Pointer Register */ 150 #define MTK_QDMA_FQ_TAIL 0x1B24 151 152 /* QDMA FQ Free Page Counter Register */ 153 #define MTK_QDMA_FQ_CNT 0x1B28 154 155 /* QDMA FQ Free Page Buffer Length Register */ 156 #define MTK_QDMA_FQ_BLEN 0x1B2C 157 158 /* GMA1 Received Good Byte Count Register */ 159 #define MTK_GDM1_TX_GBCNT 0x2400 160 #define MTK_STAT_OFFSET 0x40 161 162 /* QDMA descriptor txd4 */ 163 #define TX_DMA_CHKSUM (0x7 << 29) 164 #define TX_DMA_TSO BIT(28) 165 #define TX_DMA_FPORT_SHIFT 25 166 #define TX_DMA_FPORT_MASK 0x7 167 #define TX_DMA_INS_VLAN BIT(16) 168 169 /* QDMA descriptor txd3 */ 170 #define TX_DMA_OWNER_CPU BIT(31) 171 #define TX_DMA_LS0 BIT(30) 172 #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 173 #define TX_DMA_SWC BIT(14) 174 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 175 176 /* QDMA descriptor rxd2 */ 177 #define RX_DMA_DONE BIT(31) 178 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 179 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 180 181 /* QDMA descriptor rxd3 */ 182 #define RX_DMA_VID(_x) ((_x) & 0xfff) 183 184 /* QDMA descriptor rxd4 */ 185 #define RX_DMA_L4_VALID BIT(24) 186 #define RX_DMA_FPORT_SHIFT 19 187 #define RX_DMA_FPORT_MASK 0x7 188 189 /* PHY Indirect Access Control registers */ 190 #define MTK_PHY_IAC 0x10004 191 #define PHY_IAC_ACCESS BIT(31) 192 #define PHY_IAC_READ BIT(19) 193 #define PHY_IAC_WRITE BIT(18) 194 #define PHY_IAC_START BIT(16) 195 #define PHY_IAC_ADDR_SHIFT 20 196 #define PHY_IAC_REG_SHIFT 25 197 #define PHY_IAC_TIMEOUT HZ 198 199 /* Mac control registers */ 200 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 201 #define MAC_MCR_MAX_RX_1536 BIT(24) 202 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 203 #define MAC_MCR_FORCE_MODE BIT(15) 204 #define MAC_MCR_TX_EN BIT(14) 205 #define MAC_MCR_RX_EN BIT(13) 206 #define MAC_MCR_BACKOFF_EN BIT(9) 207 #define MAC_MCR_BACKPR_EN BIT(8) 208 #define MAC_MCR_FORCE_RX_FC BIT(5) 209 #define MAC_MCR_FORCE_TX_FC BIT(4) 210 #define MAC_MCR_SPEED_1000 BIT(3) 211 #define MAC_MCR_SPEED_100 BIT(2) 212 #define MAC_MCR_FORCE_DPX BIT(1) 213 #define MAC_MCR_FORCE_LINK BIT(0) 214 #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ 215 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ 216 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ 217 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ 218 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ 219 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) 220 221 /* GPIO port control registers for GMAC 2*/ 222 #define GPIO_OD33_CTRL8 0x4c0 223 #define GPIO_BIAS_CTRL 0xed0 224 #define GPIO_DRV_SEL10 0xf00 225 226 /* ethernet subsystem config register */ 227 #define ETHSYS_SYSCFG0 0x14 228 #define SYSCFG0_GE_MASK 0x3 229 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 230 231 struct mtk_rx_dma { 232 unsigned int rxd1; 233 unsigned int rxd2; 234 unsigned int rxd3; 235 unsigned int rxd4; 236 } __packed __aligned(4); 237 238 struct mtk_tx_dma { 239 unsigned int txd1; 240 unsigned int txd2; 241 unsigned int txd3; 242 unsigned int txd4; 243 } __packed __aligned(4); 244 245 struct mtk_eth; 246 struct mtk_mac; 247 248 /* struct mtk_hw_stats - the structure that holds the traffic statistics. 249 * @stats_lock: make sure that stats operations are atomic 250 * @reg_offset: the status register offset of the SoC 251 * @syncp: the refcount 252 * 253 * All of the supported SoCs have hardware counters for traffic statistics. 254 * Whenever the status IRQ triggers we can read the latest stats from these 255 * counters and store them in this struct. 256 */ 257 struct mtk_hw_stats { 258 u64 tx_bytes; 259 u64 tx_packets; 260 u64 tx_skip; 261 u64 tx_collisions; 262 u64 rx_bytes; 263 u64 rx_packets; 264 u64 rx_overflow; 265 u64 rx_fcs_errors; 266 u64 rx_short_errors; 267 u64 rx_long_errors; 268 u64 rx_checksum_errors; 269 u64 rx_flow_control_packets; 270 271 spinlock_t stats_lock; 272 u32 reg_offset; 273 struct u64_stats_sync syncp; 274 }; 275 276 /* PDMA descriptor can point at 1-2 segments. This enum allows us to track how 277 * memory was allocated so that it can be freed properly 278 */ 279 enum mtk_tx_flags { 280 MTK_TX_FLAGS_SINGLE0 = 0x01, 281 MTK_TX_FLAGS_PAGE0 = 0x02, 282 }; 283 284 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 285 * by the TX descriptor s 286 * @skb: The SKB pointer of the packet being sent 287 * @dma_addr0: The base addr of the first segment 288 * @dma_len0: The length of the first segment 289 * @dma_addr1: The base addr of the second segment 290 * @dma_len1: The length of the second segment 291 */ 292 struct mtk_tx_buf { 293 struct sk_buff *skb; 294 u32 flags; 295 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 296 DEFINE_DMA_UNMAP_LEN(dma_len0); 297 DEFINE_DMA_UNMAP_ADDR(dma_addr1); 298 DEFINE_DMA_UNMAP_LEN(dma_len1); 299 }; 300 301 /* struct mtk_tx_ring - This struct holds info describing a TX ring 302 * @dma: The descriptor ring 303 * @buf: The memory pointed at by the ring 304 * @phys: The physical addr of tx_buf 305 * @next_free: Pointer to the next free descriptor 306 * @last_free: Pointer to the last free descriptor 307 * @thresh: The threshold of minimum amount of free descriptors 308 * @free_count: QDMA uses a linked list. Track how many free descriptors 309 * are present 310 */ 311 struct mtk_tx_ring { 312 struct mtk_tx_dma *dma; 313 struct mtk_tx_buf *buf; 314 dma_addr_t phys; 315 struct mtk_tx_dma *next_free; 316 struct mtk_tx_dma *last_free; 317 u16 thresh; 318 atomic_t free_count; 319 }; 320 321 /* struct mtk_rx_ring - This struct holds info describing a RX ring 322 * @dma: The descriptor ring 323 * @data: The memory pointed at by the ring 324 * @phys: The physical addr of rx_buf 325 * @frag_size: How big can each fragment be 326 * @buf_size: The size of each packet buffer 327 * @calc_idx: The current head of ring 328 */ 329 struct mtk_rx_ring { 330 struct mtk_rx_dma *dma; 331 u8 **data; 332 dma_addr_t phys; 333 u16 frag_size; 334 u16 buf_size; 335 u16 calc_idx; 336 }; 337 338 /* currently no SoC has more than 2 macs */ 339 #define MTK_MAX_DEVS 2 340 341 /* struct mtk_eth - This is the main datasructure for holding the state 342 * of the driver 343 * @dev: The device pointer 344 * @base: The mapped register i/o base 345 * @page_lock: Make sure that register operations are atomic 346 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 347 * dummy for NAPI to work 348 * @netdev: The netdev instances 349 * @mac: Each netdev is linked to a physical MAC 350 * @irq: The IRQ that we are using 351 * @msg_enable: Ethtool msg level 352 * @ethsys: The register map pointing at the range used to setup 353 * MII modes 354 * @pctl: The register map pointing at the range used to setup 355 * GMAC port drive/slew values 356 * @dma_refcnt: track how many netdevs are using the DMA engine 357 * @tx_ring: Pointer to the memore holding info about the TX ring 358 * @rx_ring: Pointer to the memore holding info about the RX ring 359 * @rx_napi: The NAPI struct 360 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 361 * @phy_scratch_ring: physical address of scratch_ring 362 * @scratch_head: The scratch memory that scratch_ring points to. 363 * @clk_ethif: The ethif clock 364 * @clk_esw: The switch clock 365 * @clk_gp1: The gmac1 clock 366 * @clk_gp2: The gmac2 clock 367 * @mii_bus: If there is a bus we need to create an instance for it 368 * @pending_work: The workqueue used to reset the dma ring 369 */ 370 371 struct mtk_eth { 372 struct device *dev; 373 void __iomem *base; 374 struct reset_control *rstc; 375 spinlock_t page_lock; 376 struct net_device dummy_dev; 377 struct net_device *netdev[MTK_MAX_DEVS]; 378 struct mtk_mac *mac[MTK_MAX_DEVS]; 379 int irq; 380 u32 msg_enable; 381 unsigned long sysclk; 382 struct regmap *ethsys; 383 struct regmap *pctl; 384 atomic_t dma_refcnt; 385 struct mtk_tx_ring tx_ring; 386 struct mtk_rx_ring rx_ring; 387 struct napi_struct rx_napi; 388 struct mtk_tx_dma *scratch_ring; 389 dma_addr_t phy_scratch_ring; 390 void *scratch_head; 391 struct clk *clk_ethif; 392 struct clk *clk_esw; 393 struct clk *clk_gp1; 394 struct clk *clk_gp2; 395 struct mii_bus *mii_bus; 396 struct work_struct pending_work; 397 }; 398 399 /* struct mtk_mac - the structure that holds the info about the MACs of the 400 * SoC 401 * @id: The number of the MAC 402 * @of_node: Our devicetree node 403 * @hw: Backpointer to our main datastruture 404 * @hw_stats: Packet statistics counter 405 * @phy_dev: The attached PHY if available 406 */ 407 struct mtk_mac { 408 int id; 409 struct device_node *of_node; 410 struct mtk_eth *hw; 411 struct mtk_hw_stats *hw_stats; 412 struct phy_device *phy_dev; 413 }; 414 415 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 416 extern const struct of_device_id of_mtk_match[]; 417 418 /* read the hardware status register */ 419 void mtk_stats_update_mac(struct mtk_mac *mac); 420 421 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 422 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 423 424 #endif /* MTK_ETH_H */ 425