18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28e8e69d6SThomas Gleixner /* 3656e7052SJohn Crispin * 4656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7656e7052SJohn Crispin */ 8656e7052SJohn Crispin 9656e7052SJohn Crispin #ifndef MTK_ETH_H 10656e7052SJohn Crispin #define MTK_ETH_H 11656e7052SJohn Crispin 129ffee4a8SSean Wang #include <linux/dma-mapping.h> 139ffee4a8SSean Wang #include <linux/netdevice.h> 149ffee4a8SSean Wang #include <linux/of_net.h> 159ffee4a8SSean Wang #include <linux/u64_stats_sync.h> 16c6d4e63eSElena Reshetova #include <linux/refcount.h> 17c6d4e63eSElena Reshetova 18656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 19656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 20656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 21656e7052SJohn Crispin #define MTK_DMA_SIZE 256 22656e7052SJohn Crispin #define MTK_NAPI_WEIGHT 64 23656e7052SJohn Crispin #define MTK_MAC_COUNT 2 24656e7052SJohn Crispin #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 25656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 26656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 27656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 28656e7052SJohn Crispin NETIF_MSG_PROBE | \ 29656e7052SJohn Crispin NETIF_MSG_LINK | \ 30656e7052SJohn Crispin NETIF_MSG_TIMER | \ 31656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 32656e7052SJohn Crispin NETIF_MSG_IFUP | \ 33656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 34656e7052SJohn Crispin NETIF_MSG_TX_ERR) 35656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 36656e7052SJohn Crispin NETIF_F_RXCSUM | \ 37656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 38656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_RX | \ 39656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 40656e7052SJohn Crispin NETIF_F_TSO6 | \ 41656e7052SJohn Crispin NETIF_F_IPV6_CSUM) 42ee406810SNelson Chang #define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 43ee406810SNelson Chang 44ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4 45ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8 46ee406810SNelson Chang 47ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 48ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2 49ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 50ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 51ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 52ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 53ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64 54ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000 55ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000 56ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 57656e7052SJohn Crispin 58656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 59656e7052SJohn Crispin #define MTK_RST_GL 0x04 60656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 61656e7052SJohn Crispin 62656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 63656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 64656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 65656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 66656e7052SJohn Crispin 67ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */ 68ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 69ee406810SNelson Chang 70656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 71656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 72656e7052SJohn Crispin 7387e3df49SSean Wang /* CDMP Ingress Control Register */ 7487e3df49SSean Wang #define MTK_CDMQ_IG_CTRL 0x1400 7587e3df49SSean Wang #define MTK_CDMQ_STAG_EN BIT(0) 7687e3df49SSean Wang 77656e7052SJohn Crispin /* CDMP Exgress Control Register */ 78656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 79656e7052SJohn Crispin 80656e7052SJohn Crispin /* GDM Exgress Control Register */ 81656e7052SJohn Crispin #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 82656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 83656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 84656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 85656e7052SJohn Crispin 86656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 87656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 88656e7052SJohn Crispin 89656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 90656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 91656e7052SJohn Crispin 92bacfd110SNelson Chang /* PDMA RX Base Pointer Register */ 93bacfd110SNelson Chang #define MTK_PRX_BASE_PTR0 0x900 94ee406810SNelson Chang #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 95bacfd110SNelson Chang 96bacfd110SNelson Chang /* PDMA RX Maximum Count Register */ 97bacfd110SNelson Chang #define MTK_PRX_MAX_CNT0 0x904 98ee406810SNelson Chang #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 99bacfd110SNelson Chang 100bacfd110SNelson Chang /* PDMA RX CPU Pointer Register */ 101bacfd110SNelson Chang #define MTK_PRX_CRX_IDX0 0x908 102ee406810SNelson Chang #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 103ee406810SNelson Chang 104ee406810SNelson Chang /* PDMA HW LRO Control Registers */ 105ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980 106ee406810SNelson Chang #define MTK_LRO_EN BIT(0) 107ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7) 108ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 109ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 110ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 111ee406810SNelson Chang 112ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984 113ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988 114ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c 115ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15) 116ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 117bacfd110SNelson Chang 118bacfd110SNelson Chang /* PDMA Global Configuration Register */ 119bacfd110SNelson Chang #define MTK_PDMA_GLO_CFG 0xa04 120bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10) 121bacfd110SNelson Chang 122bacfd110SNelson Chang /* PDMA Reset Index Register */ 123bacfd110SNelson Chang #define MTK_PDMA_RST_IDX 0xa08 124bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16) 125ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 126bacfd110SNelson Chang 127bacfd110SNelson Chang /* PDMA Delay Interrupt Register */ 128bacfd110SNelson Chang #define MTK_PDMA_DELAY_INT 0xa0c 129671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_EN BIT(15) 130671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT 4 131671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 132671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PTIME 4 133671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_DELAY \ 134671d41e6SJohn Crispin (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ 135671d41e6SJohn Crispin (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) 136bacfd110SNelson Chang 137bacfd110SNelson Chang /* PDMA Interrupt Status Register */ 138bacfd110SNelson Chang #define MTK_PDMA_INT_STATUS 0xa20 139bacfd110SNelson Chang 140bacfd110SNelson Chang /* PDMA Interrupt Mask Register */ 141bacfd110SNelson Chang #define MTK_PDMA_INT_MASK 0xa28 142bacfd110SNelson Chang 143ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */ 144ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 145ee406810SNelson Chang 14680673029SJohn Crispin /* PDMA Interrupt grouping registers */ 14780673029SJohn Crispin #define MTK_PDMA_INT_GRP1 0xa50 14880673029SJohn Crispin #define MTK_PDMA_INT_GRP2 0xa54 14980673029SJohn Crispin 150ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */ 151ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 152ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 153ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9) 154ee406810SNelson Chang 155ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */ 156ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 157ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 158ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 159ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 160ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 161ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 162ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 163ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 164ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 165ee406810SNelson Chang #define MTK_RING_VLD BIT(8) 166ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 167ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 168ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 169ee406810SNelson Chang 170656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 171656e7052SJohn Crispin #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 172656e7052SJohn Crispin #define QDMA_RES_THRES 4 173656e7052SJohn Crispin 174656e7052SJohn Crispin /* QDMA TX Queue Scheduler Registers */ 175656e7052SJohn Crispin #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 176656e7052SJohn Crispin 177656e7052SJohn Crispin /* QDMA RX Base Pointer Register */ 178656e7052SJohn Crispin #define MTK_QRX_BASE_PTR0 0x1900 179656e7052SJohn Crispin 180656e7052SJohn Crispin /* QDMA RX Maximum Count Register */ 181656e7052SJohn Crispin #define MTK_QRX_MAX_CNT0 0x1904 182656e7052SJohn Crispin 183656e7052SJohn Crispin /* QDMA RX CPU Pointer Register */ 184656e7052SJohn Crispin #define MTK_QRX_CRX_IDX0 0x1908 185656e7052SJohn Crispin 186656e7052SJohn Crispin /* QDMA RX DMA Pointer Register */ 187656e7052SJohn Crispin #define MTK_QRX_DRX_IDX0 0x190C 188656e7052SJohn Crispin 189656e7052SJohn Crispin /* QDMA Global Configuration Register */ 190656e7052SJohn Crispin #define MTK_QDMA_GLO_CFG 0x1A04 191656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 192656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 1936675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 194656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 195656e7052SJohn Crispin #define MTK_DMA_SIZE_16DWORDS (2 << 4) 196656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 197656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 198656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 199656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 200656e7052SJohn Crispin #define MTK_DMA_BUSY_TIMEOUT HZ 201656e7052SJohn Crispin 202656e7052SJohn Crispin /* QDMA Reset Index Register */ 203656e7052SJohn Crispin #define MTK_QDMA_RST_IDX 0x1A08 204656e7052SJohn Crispin 205656e7052SJohn Crispin /* QDMA Delay Interrupt Register */ 206656e7052SJohn Crispin #define MTK_QDMA_DELAY_INT 0x1A0C 207656e7052SJohn Crispin 208656e7052SJohn Crispin /* QDMA Flow Control Register */ 209656e7052SJohn Crispin #define MTK_QDMA_FC_THRES 0x1A10 210656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 211656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 212656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 213656e7052SJohn Crispin 214656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 215656e7052SJohn Crispin #define MTK_QMTK_INT_STATUS 0x1A18 216671d41e6SJohn Crispin #define MTK_RX_DONE_DLY BIT(30) 217bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19) 218bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18) 219656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 220656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 221656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 222656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 223656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 224656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 225671d41e6SJohn Crispin #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 226656e7052SJohn Crispin #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 227656e7052SJohn Crispin MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 228656e7052SJohn Crispin 22980673029SJohn Crispin /* QDMA Interrupt grouping registers */ 23080673029SJohn Crispin #define MTK_QDMA_INT_GRP1 0x1a20 23180673029SJohn Crispin #define MTK_QDMA_INT_GRP2 0x1a24 23280673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0) 23380673029SJohn Crispin 234656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 235656e7052SJohn Crispin #define MTK_QDMA_INT_MASK 0x1A1C 236656e7052SJohn Crispin 237656e7052SJohn Crispin /* QDMA Interrupt Mask Register */ 238656e7052SJohn Crispin #define MTK_QDMA_HRED2 0x1A44 239656e7052SJohn Crispin 240656e7052SJohn Crispin /* QDMA TX Forward CPU Pointer Register */ 241656e7052SJohn Crispin #define MTK_QTX_CTX_PTR 0x1B00 242656e7052SJohn Crispin 243656e7052SJohn Crispin /* QDMA TX Forward DMA Pointer Register */ 244656e7052SJohn Crispin #define MTK_QTX_DTX_PTR 0x1B04 245656e7052SJohn Crispin 246656e7052SJohn Crispin /* QDMA TX Release CPU Pointer Register */ 247656e7052SJohn Crispin #define MTK_QTX_CRX_PTR 0x1B10 248656e7052SJohn Crispin 249656e7052SJohn Crispin /* QDMA TX Release DMA Pointer Register */ 250656e7052SJohn Crispin #define MTK_QTX_DRX_PTR 0x1B14 251656e7052SJohn Crispin 252656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 253656e7052SJohn Crispin #define MTK_QDMA_FQ_HEAD 0x1B20 254656e7052SJohn Crispin 255656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 256656e7052SJohn Crispin #define MTK_QDMA_FQ_TAIL 0x1B24 257656e7052SJohn Crispin 258656e7052SJohn Crispin /* QDMA FQ Free Page Counter Register */ 259656e7052SJohn Crispin #define MTK_QDMA_FQ_CNT 0x1B28 260656e7052SJohn Crispin 261656e7052SJohn Crispin /* QDMA FQ Free Page Buffer Length Register */ 262656e7052SJohn Crispin #define MTK_QDMA_FQ_BLEN 0x1B2C 263656e7052SJohn Crispin 264656e7052SJohn Crispin /* GMA1 Received Good Byte Count Register */ 265656e7052SJohn Crispin #define MTK_GDM1_TX_GBCNT 0x2400 266656e7052SJohn Crispin #define MTK_STAT_OFFSET 0x40 267656e7052SJohn Crispin 268656e7052SJohn Crispin /* QDMA descriptor txd4 */ 269656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 270656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 271656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 272656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 273656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 274656e7052SJohn Crispin 275656e7052SJohn Crispin /* QDMA descriptor txd3 */ 276656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 277656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 278656e7052SJohn Crispin #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 279656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 280656e7052SJohn Crispin #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 281656e7052SJohn Crispin 282656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 283656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 284656e7052SJohn Crispin #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 285656e7052SJohn Crispin #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 286656e7052SJohn Crispin 287656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 288656e7052SJohn Crispin #define RX_DMA_VID(_x) ((_x) & 0xfff) 289656e7052SJohn Crispin 290656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 291656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 292656e7052SJohn Crispin #define RX_DMA_FPORT_SHIFT 19 293656e7052SJohn Crispin #define RX_DMA_FPORT_MASK 0x7 294656e7052SJohn Crispin 295656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 296656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 297656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 298656e7052SJohn Crispin #define PHY_IAC_READ BIT(19) 299656e7052SJohn Crispin #define PHY_IAC_WRITE BIT(18) 300656e7052SJohn Crispin #define PHY_IAC_START BIT(16) 301656e7052SJohn Crispin #define PHY_IAC_ADDR_SHIFT 20 302656e7052SJohn Crispin #define PHY_IAC_REG_SHIFT 25 303656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 304656e7052SJohn Crispin 30542c03844SSean Wang #define MTK_MAC_MISC 0x1000c 30642c03844SSean Wang #define MTK_MUX_TO_ESW BIT(0) 30742c03844SSean Wang 308656e7052SJohn Crispin /* Mac control registers */ 309656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 310656e7052SJohn Crispin #define MAC_MCR_MAX_RX_1536 BIT(24) 311656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 312656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 313656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 314656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 315656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 316656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 317656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 318656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 319656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 320656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 321656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 322656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 323656e7052SJohn Crispin #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ 324656e7052SJohn Crispin MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ 325656e7052SJohn Crispin MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ 326656e7052SJohn Crispin MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ 327656e7052SJohn Crispin MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ 328656e7052SJohn Crispin MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) 329656e7052SJohn Crispin 330f430dea7SSean Wang /* TRGMII RXC control register */ 331f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300 332f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 333f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 334f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 335f430dea7SSean Wang #define RXC_DQSISEL BIT(30) 336f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 337f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 338f430dea7SSean Wang 339f430dea7SSean Wang /* TRGMII RXC control register */ 340f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340 341f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 342f430dea7SSean Wang #define TXC_INV BIT(30) 343f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 344f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 345f430dea7SSean Wang 346f430dea7SSean Wang /* TRGMII Interface mode register */ 347f430dea7SSean Wang #define INTF_MODE 0x10390 348f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0) 349f430dea7SSean Wang #define TRGMII_MODE BIT(1) 350f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2) 351f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 352f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0 353f430dea7SSean Wang 354656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 355656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 356656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 357656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 358656e7052SJohn Crispin 359b95b6d99SNelson Chang /* ethernet subsystem chip id register */ 360b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0 361b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4 362983e1a6cSNelson Chang #define MT7623_ETH 7623 36342c03844SSean Wang #define MT7622_ETH 7622 364889bcbdeSBjørn Mork #define MT7621_ETH 7621 365b95b6d99SNelson Chang 3668efaa653SRené van Dorst /* ethernet system control register */ 3678efaa653SRené van Dorst #define ETHSYS_SYSCFG 0x10 3688efaa653SRené van Dorst #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 3698efaa653SRené van Dorst 370656e7052SJohn Crispin /* ethernet subsystem config register */ 371656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 372656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 373656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 3747093f9d8SSean Wang #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 3757093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 3767093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 3777093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 3787093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 3797093f9d8SSean Wang 380656e7052SJohn Crispin 381f430dea7SSean Wang /* ethernet subsystem clock register */ 382f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c 383f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 3848efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 3858efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 3868efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 387f430dea7SSean Wang 3882a8307aaSSean Wang /* ethernet reset control register */ 3892a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34 3902a8307aaSSean Wang #define RSTCTRL_FE BIT(6) 3912a8307aaSSean Wang #define RSTCTRL_PPE BIT(31) 3922a8307aaSSean Wang 39342c03844SSean Wang /* SGMII subsystem config registers */ 39442c03844SSean Wang /* Register to auto-negotiation restart */ 39542c03844SSean Wang #define SGMSYS_PCS_CONTROL_1 0x0 39642c03844SSean Wang #define SGMII_AN_RESTART BIT(9) 39742c03844SSean Wang 39842c03844SSean Wang /* Register to programmable link timer, the unit in 2 * 8ns */ 39942c03844SSean Wang #define SGMSYS_PCS_LINK_TIMER 0x18 40042c03844SSean Wang #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 40142c03844SSean Wang 40242c03844SSean Wang /* Register to control remote fault */ 40342c03844SSean Wang #define SGMSYS_SGMII_MODE 0x20 40442c03844SSean Wang #define SGMII_REMOTE_FAULT_DIS BIT(8) 40542c03844SSean Wang 40642c03844SSean Wang /* Register to power up QPHY */ 40742c03844SSean Wang #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 40842c03844SSean Wang #define SGMII_PHYA_PWD BIT(4) 40942c03844SSean Wang 4107093f9d8SSean Wang /* Infrasys subsystem config registers */ 4117093f9d8SSean Wang #define INFRA_MISC2 0x70c 4127093f9d8SSean Wang #define CO_QPHY_SEL BIT(0) 4137093f9d8SSean Wang #define GEPHY_MAC_SEL BIT(1) 4147093f9d8SSean Wang 415656e7052SJohn Crispin struct mtk_rx_dma { 416656e7052SJohn Crispin unsigned int rxd1; 417656e7052SJohn Crispin unsigned int rxd2; 418656e7052SJohn Crispin unsigned int rxd3; 419656e7052SJohn Crispin unsigned int rxd4; 420656e7052SJohn Crispin } __packed __aligned(4); 421656e7052SJohn Crispin 422656e7052SJohn Crispin struct mtk_tx_dma { 423656e7052SJohn Crispin unsigned int txd1; 424656e7052SJohn Crispin unsigned int txd2; 425656e7052SJohn Crispin unsigned int txd3; 426656e7052SJohn Crispin unsigned int txd4; 427656e7052SJohn Crispin } __packed __aligned(4); 428656e7052SJohn Crispin 429656e7052SJohn Crispin struct mtk_eth; 430656e7052SJohn Crispin struct mtk_mac; 431656e7052SJohn Crispin 432656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 433656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 434656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 435656e7052SJohn Crispin * @syncp: the refcount 436656e7052SJohn Crispin * 437656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 438656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 439656e7052SJohn Crispin * counters and store them in this struct. 440656e7052SJohn Crispin */ 441656e7052SJohn Crispin struct mtk_hw_stats { 442656e7052SJohn Crispin u64 tx_bytes; 443656e7052SJohn Crispin u64 tx_packets; 444656e7052SJohn Crispin u64 tx_skip; 445656e7052SJohn Crispin u64 tx_collisions; 446656e7052SJohn Crispin u64 rx_bytes; 447656e7052SJohn Crispin u64 rx_packets; 448656e7052SJohn Crispin u64 rx_overflow; 449656e7052SJohn Crispin u64 rx_fcs_errors; 450656e7052SJohn Crispin u64 rx_short_errors; 451656e7052SJohn Crispin u64 rx_long_errors; 452656e7052SJohn Crispin u64 rx_checksum_errors; 453656e7052SJohn Crispin u64 rx_flow_control_packets; 454656e7052SJohn Crispin 455656e7052SJohn Crispin spinlock_t stats_lock; 456656e7052SJohn Crispin u32 reg_offset; 457656e7052SJohn Crispin struct u64_stats_sync syncp; 458656e7052SJohn Crispin }; 459656e7052SJohn Crispin 460656e7052SJohn Crispin enum mtk_tx_flags { 461134d2152SSean Wang /* PDMA descriptor can point at 1-2 segments. This enum allows us to 462134d2152SSean Wang * track how memory was allocated so that it can be freed properly. 463134d2152SSean Wang */ 464656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 465656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 466134d2152SSean Wang 467134d2152SSean Wang /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 468134d2152SSean Wang * SKB out instead of looking up through hardware TX descriptor. 469134d2152SSean Wang */ 470134d2152SSean Wang MTK_TX_FLAGS_FPORT0 = 0x04, 471134d2152SSean Wang MTK_TX_FLAGS_FPORT1 = 0x08, 472656e7052SJohn Crispin }; 473656e7052SJohn Crispin 474549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the 475549e5495SSean Wang * clock in the order 476549e5495SSean Wang */ 477549e5495SSean Wang enum mtk_clks_map { 478549e5495SSean Wang MTK_CLK_ETHIF, 479d438e298SSean Wang MTK_CLK_SGMIITOP, 480549e5495SSean Wang MTK_CLK_ESW, 48142c03844SSean Wang MTK_CLK_GP0, 482549e5495SSean Wang MTK_CLK_GP1, 483549e5495SSean Wang MTK_CLK_GP2, 484d438e298SSean Wang MTK_CLK_FE, 485f430dea7SSean Wang MTK_CLK_TRGPLL, 48642c03844SSean Wang MTK_CLK_SGMII_TX_250M, 48742c03844SSean Wang MTK_CLK_SGMII_RX_250M, 48842c03844SSean Wang MTK_CLK_SGMII_CDR_REF, 48942c03844SSean Wang MTK_CLK_SGMII_CDR_FB, 490d438e298SSean Wang MTK_CLK_SGMII2_TX_250M, 491d438e298SSean Wang MTK_CLK_SGMII2_RX_250M, 492d438e298SSean Wang MTK_CLK_SGMII2_CDR_REF, 493d438e298SSean Wang MTK_CLK_SGMII2_CDR_FB, 49442c03844SSean Wang MTK_CLK_SGMII_CK, 49542c03844SSean Wang MTK_CLK_ETH2PLL, 496549e5495SSean Wang MTK_CLK_MAX 497549e5495SSean Wang }; 498549e5495SSean Wang 4992ec50f57SSean Wang #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 5002ec50f57SSean Wang BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 5012ec50f57SSean Wang BIT(MTK_CLK_TRGPLL)) 50242c03844SSean Wang #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 50342c03844SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 50442c03844SSean Wang BIT(MTK_CLK_GP2) | \ 50542c03844SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 50642c03844SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 50742c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 50842c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 50942c03844SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 51042c03844SSean Wang BIT(MTK_CLK_ETH2PLL)) 511889bcbdeSBjørn Mork #define MT7621_CLKS_BITMAP (0) 512d438e298SSean Wang #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 513d438e298SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 514d438e298SSean Wang BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 515d438e298SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 516d438e298SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 517d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 518d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 519d438e298SSean Wang BIT(MTK_CLK_SGMII2_TX_250M) | \ 520d438e298SSean Wang BIT(MTK_CLK_SGMII2_RX_250M) | \ 521d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_REF) | \ 522d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_FB) | \ 523d438e298SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 524d438e298SSean Wang BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 525889bcbdeSBjørn Mork 5269ea4d311SSean Wang enum mtk_dev_state { 527dce6fa42SSean Wang MTK_HW_INIT, 528dce6fa42SSean Wang MTK_RESETTING 5299ea4d311SSean Wang }; 5309ea4d311SSean Wang 531656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 532656e7052SJohn Crispin * by the TX descriptor s 533656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 534656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 535656e7052SJohn Crispin * @dma_len0: The length of the first segment 536656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 537656e7052SJohn Crispin * @dma_len1: The length of the second segment 538656e7052SJohn Crispin */ 539656e7052SJohn Crispin struct mtk_tx_buf { 540656e7052SJohn Crispin struct sk_buff *skb; 541656e7052SJohn Crispin u32 flags; 542656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 543656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 544656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 545656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 546656e7052SJohn Crispin }; 547656e7052SJohn Crispin 548656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 549656e7052SJohn Crispin * @dma: The descriptor ring 550656e7052SJohn Crispin * @buf: The memory pointed at by the ring 551656e7052SJohn Crispin * @phys: The physical addr of tx_buf 552656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 553656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 554656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 555656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 556656e7052SJohn Crispin * are present 557656e7052SJohn Crispin */ 558656e7052SJohn Crispin struct mtk_tx_ring { 559656e7052SJohn Crispin struct mtk_tx_dma *dma; 560656e7052SJohn Crispin struct mtk_tx_buf *buf; 561656e7052SJohn Crispin dma_addr_t phys; 562656e7052SJohn Crispin struct mtk_tx_dma *next_free; 563656e7052SJohn Crispin struct mtk_tx_dma *last_free; 564656e7052SJohn Crispin u16 thresh; 565656e7052SJohn Crispin atomic_t free_count; 566656e7052SJohn Crispin }; 567656e7052SJohn Crispin 568ee406810SNelson Chang /* PDMA rx ring mode */ 569ee406810SNelson Chang enum mtk_rx_flags { 570ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0, 571ee406810SNelson Chang MTK_RX_FLAGS_HWLRO, 5726427dc1dSJohn Crispin MTK_RX_FLAGS_QDMA, 573ee406810SNelson Chang }; 574ee406810SNelson Chang 575656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 576656e7052SJohn Crispin * @dma: The descriptor ring 577656e7052SJohn Crispin * @data: The memory pointed at by the ring 578656e7052SJohn Crispin * @phys: The physical addr of rx_buf 579656e7052SJohn Crispin * @frag_size: How big can each fragment be 580656e7052SJohn Crispin * @buf_size: The size of each packet buffer 581656e7052SJohn Crispin * @calc_idx: The current head of ring 582656e7052SJohn Crispin */ 583656e7052SJohn Crispin struct mtk_rx_ring { 584656e7052SJohn Crispin struct mtk_rx_dma *dma; 585656e7052SJohn Crispin u8 **data; 586656e7052SJohn Crispin dma_addr_t phys; 587656e7052SJohn Crispin u16 frag_size; 588656e7052SJohn Crispin u16 buf_size; 589ee406810SNelson Chang u16 dma_size; 590ee406810SNelson Chang bool calc_idx_update; 591656e7052SJohn Crispin u16 calc_idx; 592ee406810SNelson Chang u32 crx_idx_reg; 593656e7052SJohn Crispin }; 594656e7052SJohn Crispin 595e2c74694SRené van Dorst enum mkt_eth_capabilities { 596e2c74694SRené van Dorst MTK_RGMII_BIT = 0, 597e2c74694SRené van Dorst MTK_TRGMII_BIT, 598e2c74694SRené van Dorst MTK_SGMII_BIT, 599e2c74694SRené van Dorst MTK_ESW_BIT, 600e2c74694SRené van Dorst MTK_GEPHY_BIT, 601e2c74694SRené van Dorst MTK_MUX_BIT, 602e2c74694SRené van Dorst MTK_INFRA_BIT, 603e2c74694SRené van Dorst MTK_SHARED_SGMII_BIT, 604e2c74694SRené van Dorst MTK_HWLRO_BIT, 605e2c74694SRené van Dorst MTK_SHARED_INT_BIT, 606e2c74694SRené van Dorst MTK_TRGMII_MT7621_CLK_BIT, 6077093f9d8SSean Wang 608e2c74694SRené van Dorst /* MUX BITS*/ 609e2c74694SRené van Dorst MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 610e2c74694SRené van Dorst MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 611e2c74694SRené van Dorst MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 612e2c74694SRené van Dorst MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 613e2c74694SRené van Dorst MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 614e2c74694SRené van Dorst 615e2c74694SRené van Dorst /* PATH BITS */ 616e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_RGMII_BIT, 617e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_TRGMII_BIT, 618e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_SGMII_BIT, 619e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_RGMII_BIT, 620e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_SGMII_BIT, 621e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_GEPHY_BIT, 622e2c74694SRené van Dorst MTK_ETH_PATH_GDM1_ESW_BIT, 6237093f9d8SSean Wang }; 6247093f9d8SSean Wang 6257093f9d8SSean Wang /* Supported hardware group on SoCs */ 626e2c74694SRené van Dorst #define MTK_RGMII BIT(MTK_RGMII_BIT) 627e2c74694SRené van Dorst #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 628e2c74694SRené van Dorst #define MTK_SGMII BIT(MTK_SGMII_BIT) 629e2c74694SRené van Dorst #define MTK_ESW BIT(MTK_ESW_BIT) 630e2c74694SRené van Dorst #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 631e2c74694SRené van Dorst #define MTK_MUX BIT(MTK_MUX_BIT) 632e2c74694SRené van Dorst #define MTK_INFRA BIT(MTK_INFRA_BIT) 633e2c74694SRené van Dorst #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 634e2c74694SRené van Dorst #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 635e2c74694SRené van Dorst #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 636e2c74694SRené van Dorst #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 637e2c74694SRené van Dorst 638e2c74694SRené van Dorst #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 639e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 640e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 641e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 642e2c74694SRené van Dorst #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 643e2c74694SRené van Dorst BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 644e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 645e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 646e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 647e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 6487093f9d8SSean Wang 6497093f9d8SSean Wang /* Supported path present on SoCs */ 650e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 651e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 652e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 653e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 654e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 655e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 656e2c74694SRené van Dorst #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 6577093f9d8SSean Wang 658e2c74694SRené van Dorst #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 659e2c74694SRené van Dorst #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 660e2c74694SRené van Dorst #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 661e2c74694SRené van Dorst #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 662e2c74694SRené van Dorst #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 663e2c74694SRené van Dorst #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 664e2c74694SRené van Dorst #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 6657093f9d8SSean Wang 6667093f9d8SSean Wang /* MUXes present on SoCs */ 6677093f9d8SSean Wang /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 668e2c74694SRené van Dorst #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 6697093f9d8SSean Wang 6707093f9d8SSean Wang /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 6717093f9d8SSean Wang #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 672e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 6737093f9d8SSean Wang 6747093f9d8SSean Wang /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 6757093f9d8SSean Wang #define MTK_MUX_U3_GMAC2_TO_QPHY \ 676e2c74694SRené van Dorst (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 6777093f9d8SSean Wang 6787093f9d8SSean Wang /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 6797093f9d8SSean Wang #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 680e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 6817093f9d8SSean Wang MTK_SHARED_SGMII) 6827093f9d8SSean Wang 6837093f9d8SSean Wang /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 6847093f9d8SSean Wang #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 685e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 6867093f9d8SSean Wang 6872ec50f57SSean Wang #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 6882ec50f57SSean Wang 6898efaa653SRené van Dorst #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 6908efaa653SRené van Dorst MTK_GMAC2_RGMII | MTK_SHARED_INT | MTK_TRGMII_MT7621_CLK) 6918efaa653SRené van Dorst 6927093f9d8SSean Wang #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 6937093f9d8SSean Wang MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 6947093f9d8SSean Wang MTK_MUX_GDM1_TO_GMAC1_ESW | \ 6957093f9d8SSean Wang MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII) 6967093f9d8SSean Wang 6977093f9d8SSean Wang #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII) 6987093f9d8SSean Wang 6997093f9d8SSean Wang #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 7007093f9d8SSean Wang MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 7017093f9d8SSean Wang MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 7027093f9d8SSean Wang MTK_MUX_U3_GMAC2_TO_QPHY | \ 7037093f9d8SSean Wang MTK_MUX_GMAC12_TO_GEPHY_SGMII) 7047093f9d8SSean Wang 70542c03844SSean Wang /* struct mtk_eth_data - This is the structure holding all differences 7062ec50f57SSean Wang * among various plaforms 7079ffee4a8SSean Wang * @ana_rgc3: The offset for register ANA_RGC3 related to 7089ffee4a8SSean Wang * sgmiisys syscon 7092ec50f57SSean Wang * @caps Flags shown the extra capability for the SoC 7102ec50f57SSean Wang * @required_clks Flags shown the bitmap for required clocks on 7112ec50f57SSean Wang * the target SoC 712243dc5fbSSean Wang * @required_pctl A bool value to show whether the SoC requires 713243dc5fbSSean Wang * the extra setup for those pins used by GMAC. 7142ec50f57SSean Wang */ 7152ec50f57SSean Wang struct mtk_soc_data { 7169ffee4a8SSean Wang u32 ana_rgc3; 7172ec50f57SSean Wang u32 caps; 7182ec50f57SSean Wang u32 required_clks; 719243dc5fbSSean Wang bool required_pctl; 7202ec50f57SSean Wang }; 7212ec50f57SSean Wang 722656e7052SJohn Crispin /* currently no SoC has more than 2 macs */ 723656e7052SJohn Crispin #define MTK_MAX_DEVS 2 724656e7052SJohn Crispin 7259ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_AN BIT(31) 7269ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_MASK GENMASK(0, 2) 7279ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_1000 BIT(0) 7289ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_2500 BIT(1) 7299ffee4a8SSean Wang #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) 7309ffee4a8SSean Wang 7319ffee4a8SSean Wang /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 7329ffee4a8SSean Wang * characteristics 7339ffee4a8SSean Wang * @regmap: The register map pointing at the range used to setup 7349ffee4a8SSean Wang * SGMII modes 7359ffee4a8SSean Wang * @flags: The enum refers to which mode the sgmii wants to run on 7369ffee4a8SSean Wang * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 7379ffee4a8SSean Wang */ 7389ffee4a8SSean Wang 7399ffee4a8SSean Wang struct mtk_sgmii { 7409ffee4a8SSean Wang struct regmap *regmap[MTK_MAX_DEVS]; 7419ffee4a8SSean Wang u32 flags[MTK_MAX_DEVS]; 7429ffee4a8SSean Wang u32 ana_rgc3; 7439ffee4a8SSean Wang }; 7449ffee4a8SSean Wang 745656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 746656e7052SJohn Crispin * of the driver 747656e7052SJohn Crispin * @dev: The device pointer 748656e7052SJohn Crispin * @base: The mapped register i/o base 749656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 7505cce0322SJohn Crispin * @tx_irq__lock: Make sure that IRQ register operations are atomic 7515cce0322SJohn Crispin * @rx_irq__lock: Make sure that IRQ register operations are atomic 752656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 753656e7052SJohn Crispin * dummy for NAPI to work 754656e7052SJohn Crispin * @netdev: The netdev instances 755656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 756656e7052SJohn Crispin * @irq: The IRQ that we are using 757656e7052SJohn Crispin * @msg_enable: Ethtool msg level 758656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 759656e7052SJohn Crispin * MII modes 7607093f9d8SSean Wang * @infra: The register map pointing at the range used to setup 7617093f9d8SSean Wang * SGMII and GePHY path 762656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 763656e7052SJohn Crispin * GMAC port drive/slew values 764656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 7650c07ce7fSJohn Crispin * @tx_ring: Pointer to the memory holding info about the TX ring 7660c07ce7fSJohn Crispin * @rx_ring: Pointer to the memory holding info about the RX ring 7676427dc1dSJohn Crispin * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 76880673029SJohn Crispin * @tx_napi: The TX NAPI struct 76980673029SJohn Crispin * @rx_napi: The RX NAPI struct 770656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 771605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 772656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 773549e5495SSean Wang * @clks: clock array for all clocks required 774656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 7757c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 77642c03844SSean Wang * @state: Initialization and runtime state of the device 7772ec50f57SSean Wang * @soc: Holding specific data among vaious SoCs 778656e7052SJohn Crispin */ 779656e7052SJohn Crispin 780656e7052SJohn Crispin struct mtk_eth { 781656e7052SJohn Crispin struct device *dev; 782656e7052SJohn Crispin void __iomem *base; 783656e7052SJohn Crispin spinlock_t page_lock; 7845cce0322SJohn Crispin spinlock_t tx_irq_lock; 7855cce0322SJohn Crispin spinlock_t rx_irq_lock; 786656e7052SJohn Crispin struct net_device dummy_dev; 787656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 788656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 78980673029SJohn Crispin int irq[3]; 790656e7052SJohn Crispin u32 msg_enable; 791656e7052SJohn Crispin unsigned long sysclk; 792656e7052SJohn Crispin struct regmap *ethsys; 7937093f9d8SSean Wang struct regmap *infra; 7949ffee4a8SSean Wang struct mtk_sgmii *sgmii; 795656e7052SJohn Crispin struct regmap *pctl; 796ee406810SNelson Chang bool hwlro; 797c6d4e63eSElena Reshetova refcount_t dma_refcnt; 798656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 799ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 8006427dc1dSJohn Crispin struct mtk_rx_ring rx_ring_qdma; 80180673029SJohn Crispin struct napi_struct tx_napi; 802656e7052SJohn Crispin struct napi_struct rx_napi; 803656e7052SJohn Crispin struct mtk_tx_dma *scratch_ring; 804605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 805656e7052SJohn Crispin void *scratch_head; 806549e5495SSean Wang struct clk *clks[MTK_CLK_MAX]; 807549e5495SSean Wang 808656e7052SJohn Crispin struct mii_bus *mii_bus; 8097c78b4adSJohn Crispin struct work_struct pending_work; 8109ea4d311SSean Wang unsigned long state; 8112ec50f57SSean Wang 8122ec50f57SSean Wang const struct mtk_soc_data *soc; 813656e7052SJohn Crispin }; 814656e7052SJohn Crispin 815656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 816656e7052SJohn Crispin * SoC 817656e7052SJohn Crispin * @id: The number of the MAC 8189ea4d311SSean Wang * @ge_mode: Interface mode kept for setup restoring 819656e7052SJohn Crispin * @of_node: Our devicetree node 820656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 821656e7052SJohn Crispin * @hw_stats: Packet statistics counter 822572de608SSean Wang * @trgmii Indicate if the MAC uses TRGMII connected to internal 823572de608SSean Wang switch 824656e7052SJohn Crispin */ 825656e7052SJohn Crispin struct mtk_mac { 826656e7052SJohn Crispin int id; 8279ea4d311SSean Wang int ge_mode; 828656e7052SJohn Crispin struct device_node *of_node; 829656e7052SJohn Crispin struct mtk_eth *hw; 830656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 831ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 832ee406810SNelson Chang int hwlro_ip_cnt; 833572de608SSean Wang bool trgmii; 834656e7052SJohn Crispin }; 835656e7052SJohn Crispin 836656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 837656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 838656e7052SJohn Crispin 839656e7052SJohn Crispin /* read the hardware status register */ 840656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 841656e7052SJohn Crispin 842656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 843656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 844656e7052SJohn Crispin 8459ffee4a8SSean Wang int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 8469ffee4a8SSean Wang u32 ana_rgc3); 8479ffee4a8SSean Wang int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); 8489ffee4a8SSean Wang int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id); 8497093f9d8SSean Wang int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode); 8509ffee4a8SSean Wang 851656e7052SJohn Crispin #endif /* MTK_ETH_H */ 852