18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28e8e69d6SThomas Gleixner /* 3656e7052SJohn Crispin * 4656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7656e7052SJohn Crispin */ 8656e7052SJohn Crispin 9656e7052SJohn Crispin #ifndef MTK_ETH_H 10656e7052SJohn Crispin #define MTK_ETH_H 11656e7052SJohn Crispin 129ffee4a8SSean Wang #include <linux/dma-mapping.h> 139ffee4a8SSean Wang #include <linux/netdevice.h> 149ffee4a8SSean Wang #include <linux/of_net.h> 159ffee4a8SSean Wang #include <linux/u64_stats_sync.h> 16c6d4e63eSElena Reshetova #include <linux/refcount.h> 17b8fc9f30SRené van Dorst #include <linux/phylink.h> 18c6d4e63eSElena Reshetova 19656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 20656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 214fd59792SDENG Qingfang #define MTK_MAX_RX_LENGTH_2K 2048 22656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 23656e7052SJohn Crispin #define MTK_DMA_SIZE 256 24656e7052SJohn Crispin #define MTK_NAPI_WEIGHT 64 25656e7052SJohn Crispin #define MTK_MAC_COUNT 2 264fd59792SDENG Qingfang #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 27656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 28656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 29656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 30656e7052SJohn Crispin NETIF_MSG_PROBE | \ 31656e7052SJohn Crispin NETIF_MSG_LINK | \ 32656e7052SJohn Crispin NETIF_MSG_TIMER | \ 33656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 34656e7052SJohn Crispin NETIF_MSG_IFUP | \ 35656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 36656e7052SJohn Crispin NETIF_MSG_TX_ERR) 37656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 38656e7052SJohn Crispin NETIF_F_RXCSUM | \ 39656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 40656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_RX | \ 41656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 42656e7052SJohn Crispin NETIF_F_TSO6 | \ 43656e7052SJohn Crispin NETIF_F_IPV6_CSUM) 44296c9120SStefan Roese #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 4508df5fa6SStefan Roese #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 46ee406810SNelson Chang 47ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4 48ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8 49ee406810SNelson Chang 50ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 51ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2 52ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 53ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 54ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 55ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 56ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64 57ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000 58ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000 59ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 60656e7052SJohn Crispin 61656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 62656e7052SJohn Crispin #define MTK_RST_GL 0x04 63656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 64656e7052SJohn Crispin 65656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 66656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 67656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 68656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 69656e7052SJohn Crispin 70ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */ 71ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 72ee406810SNelson Chang 73656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 74656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 75656e7052SJohn Crispin 7687e3df49SSean Wang /* CDMP Ingress Control Register */ 7787e3df49SSean Wang #define MTK_CDMQ_IG_CTRL 0x1400 7887e3df49SSean Wang #define MTK_CDMQ_STAG_EN BIT(0) 7987e3df49SSean Wang 80656e7052SJohn Crispin /* CDMP Exgress Control Register */ 81656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 82656e7052SJohn Crispin 83656e7052SJohn Crispin /* GDM Exgress Control Register */ 84656e7052SJohn Crispin #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 85*d5c53da2SFelix Fietkau #define MTK_GDMA_SPECIAL_TAG BIT(24) 86656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 87656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 88656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 898d3f4a95SMarkLee #define MTK_GDMA_TO_PDMA 0x0 908d66a818SMarkLee #define MTK_GDMA_DROP_ALL 0x7777 91656e7052SJohn Crispin 92656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 93656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 94656e7052SJohn Crispin 95656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 96656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 97656e7052SJohn Crispin 98bacfd110SNelson Chang /* PDMA RX Base Pointer Register */ 99bacfd110SNelson Chang #define MTK_PRX_BASE_PTR0 0x900 100ee406810SNelson Chang #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 101bacfd110SNelson Chang 102bacfd110SNelson Chang /* PDMA RX Maximum Count Register */ 103bacfd110SNelson Chang #define MTK_PRX_MAX_CNT0 0x904 104ee406810SNelson Chang #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 105bacfd110SNelson Chang 106bacfd110SNelson Chang /* PDMA RX CPU Pointer Register */ 107bacfd110SNelson Chang #define MTK_PRX_CRX_IDX0 0x908 108ee406810SNelson Chang #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 109ee406810SNelson Chang 110ee406810SNelson Chang /* PDMA HW LRO Control Registers */ 111ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980 112ee406810SNelson Chang #define MTK_LRO_EN BIT(0) 113ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7) 114ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 115ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 116ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 117ee406810SNelson Chang 118ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984 119ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988 120ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c 121ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15) 122ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 123bacfd110SNelson Chang 124bacfd110SNelson Chang /* PDMA Global Configuration Register */ 125bacfd110SNelson Chang #define MTK_PDMA_GLO_CFG 0xa04 126bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10) 127296c9120SStefan Roese #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 128bacfd110SNelson Chang 129bacfd110SNelson Chang /* PDMA Reset Index Register */ 130bacfd110SNelson Chang #define MTK_PDMA_RST_IDX 0xa08 131bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16) 132ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 133bacfd110SNelson Chang 134bacfd110SNelson Chang /* PDMA Delay Interrupt Register */ 135bacfd110SNelson Chang #define MTK_PDMA_DELAY_INT 0xa0c 136671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_EN BIT(15) 137671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT 4 138671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 139671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PTIME 4 140671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_DELAY \ 141671d41e6SJohn Crispin (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ 142671d41e6SJohn Crispin (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) 143bacfd110SNelson Chang 144bacfd110SNelson Chang /* PDMA Interrupt Status Register */ 145bacfd110SNelson Chang #define MTK_PDMA_INT_STATUS 0xa20 146bacfd110SNelson Chang 147bacfd110SNelson Chang /* PDMA Interrupt Mask Register */ 148bacfd110SNelson Chang #define MTK_PDMA_INT_MASK 0xa28 149bacfd110SNelson Chang 150ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */ 151ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 152ee406810SNelson Chang 15380673029SJohn Crispin /* PDMA Interrupt grouping registers */ 15480673029SJohn Crispin #define MTK_PDMA_INT_GRP1 0xa50 15580673029SJohn Crispin #define MTK_PDMA_INT_GRP2 0xa54 15680673029SJohn Crispin 157ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */ 158ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 159ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 160ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9) 161ee406810SNelson Chang 162ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */ 163ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 164ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 165ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 166ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 167ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 168ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 169ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 170ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 171ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 172ee406810SNelson Chang #define MTK_RING_VLD BIT(8) 173ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 174ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 175ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 176ee406810SNelson Chang 177656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 178656e7052SJohn Crispin #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 179656e7052SJohn Crispin #define QDMA_RES_THRES 4 180656e7052SJohn Crispin 181656e7052SJohn Crispin /* QDMA TX Queue Scheduler Registers */ 182656e7052SJohn Crispin #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 183656e7052SJohn Crispin 184656e7052SJohn Crispin /* QDMA RX Base Pointer Register */ 185656e7052SJohn Crispin #define MTK_QRX_BASE_PTR0 0x1900 186656e7052SJohn Crispin 187656e7052SJohn Crispin /* QDMA RX Maximum Count Register */ 188656e7052SJohn Crispin #define MTK_QRX_MAX_CNT0 0x1904 189656e7052SJohn Crispin 190656e7052SJohn Crispin /* QDMA RX CPU Pointer Register */ 191656e7052SJohn Crispin #define MTK_QRX_CRX_IDX0 0x1908 192656e7052SJohn Crispin 193656e7052SJohn Crispin /* QDMA RX DMA Pointer Register */ 194656e7052SJohn Crispin #define MTK_QRX_DRX_IDX0 0x190C 195656e7052SJohn Crispin 196656e7052SJohn Crispin /* QDMA Global Configuration Register */ 197656e7052SJohn Crispin #define MTK_QDMA_GLO_CFG 0x1A04 198656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 199656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 2006675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 201656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 202656e7052SJohn Crispin #define MTK_DMA_SIZE_16DWORDS (2 << 4) 203656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 204656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 205656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 206656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 207656e7052SJohn Crispin #define MTK_DMA_BUSY_TIMEOUT HZ 208656e7052SJohn Crispin 209656e7052SJohn Crispin /* QDMA Reset Index Register */ 210656e7052SJohn Crispin #define MTK_QDMA_RST_IDX 0x1A08 211656e7052SJohn Crispin 212656e7052SJohn Crispin /* QDMA Delay Interrupt Register */ 213656e7052SJohn Crispin #define MTK_QDMA_DELAY_INT 0x1A0C 214656e7052SJohn Crispin 215656e7052SJohn Crispin /* QDMA Flow Control Register */ 216656e7052SJohn Crispin #define MTK_QDMA_FC_THRES 0x1A10 217656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 218656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 219656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 220656e7052SJohn Crispin 221656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 22245487403SStefan Roese #define MTK_QDMA_INT_STATUS 0x1A18 223671d41e6SJohn Crispin #define MTK_RX_DONE_DLY BIT(30) 224bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19) 225bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18) 226656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 227656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 228656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 229656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 230656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 231656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 232671d41e6SJohn Crispin #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 233656e7052SJohn Crispin #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 234656e7052SJohn Crispin MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 235656e7052SJohn Crispin 23680673029SJohn Crispin /* QDMA Interrupt grouping registers */ 23780673029SJohn Crispin #define MTK_QDMA_INT_GRP1 0x1a20 23880673029SJohn Crispin #define MTK_QDMA_INT_GRP2 0x1a24 23980673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0) 24080673029SJohn Crispin 241656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 242656e7052SJohn Crispin #define MTK_QDMA_INT_MASK 0x1A1C 243656e7052SJohn Crispin 244656e7052SJohn Crispin /* QDMA Interrupt Mask Register */ 245656e7052SJohn Crispin #define MTK_QDMA_HRED2 0x1A44 246656e7052SJohn Crispin 247656e7052SJohn Crispin /* QDMA TX Forward CPU Pointer Register */ 248656e7052SJohn Crispin #define MTK_QTX_CTX_PTR 0x1B00 249656e7052SJohn Crispin 250656e7052SJohn Crispin /* QDMA TX Forward DMA Pointer Register */ 251656e7052SJohn Crispin #define MTK_QTX_DTX_PTR 0x1B04 252656e7052SJohn Crispin 253656e7052SJohn Crispin /* QDMA TX Release CPU Pointer Register */ 254656e7052SJohn Crispin #define MTK_QTX_CRX_PTR 0x1B10 255656e7052SJohn Crispin 256656e7052SJohn Crispin /* QDMA TX Release DMA Pointer Register */ 257656e7052SJohn Crispin #define MTK_QTX_DRX_PTR 0x1B14 258656e7052SJohn Crispin 259656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 260656e7052SJohn Crispin #define MTK_QDMA_FQ_HEAD 0x1B20 261656e7052SJohn Crispin 262656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 263656e7052SJohn Crispin #define MTK_QDMA_FQ_TAIL 0x1B24 264656e7052SJohn Crispin 265656e7052SJohn Crispin /* QDMA FQ Free Page Counter Register */ 266656e7052SJohn Crispin #define MTK_QDMA_FQ_CNT 0x1B28 267656e7052SJohn Crispin 268656e7052SJohn Crispin /* QDMA FQ Free Page Buffer Length Register */ 269656e7052SJohn Crispin #define MTK_QDMA_FQ_BLEN 0x1B2C 270656e7052SJohn Crispin 271656e7052SJohn Crispin /* GMA1 Received Good Byte Count Register */ 272656e7052SJohn Crispin #define MTK_GDM1_TX_GBCNT 0x2400 273656e7052SJohn Crispin #define MTK_STAT_OFFSET 0x40 274656e7052SJohn Crispin 275656e7052SJohn Crispin /* QDMA descriptor txd4 */ 276656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 277656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 278656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 279656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 280656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 281656e7052SJohn Crispin 282656e7052SJohn Crispin /* QDMA descriptor txd3 */ 283656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 284656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 285656e7052SJohn Crispin #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 286296c9120SStefan Roese #define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN) 287656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 288656e7052SJohn Crispin #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 289656e7052SJohn Crispin 290296c9120SStefan Roese /* PDMA on MT7628 */ 291296c9120SStefan Roese #define TX_DMA_DONE BIT(31) 292296c9120SStefan Roese #define TX_DMA_LS1 BIT(14) 293296c9120SStefan Roese #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 294296c9120SStefan Roese 295656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 296656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 297296c9120SStefan Roese #define RX_DMA_LSO BIT(30) 298656e7052SJohn Crispin #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 299656e7052SJohn Crispin #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 300656e7052SJohn Crispin 301656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 302656e7052SJohn Crispin #define RX_DMA_VID(_x) ((_x) & 0xfff) 303656e7052SJohn Crispin 304656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 305656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 306296c9120SStefan Roese #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 307656e7052SJohn Crispin #define RX_DMA_FPORT_SHIFT 19 308656e7052SJohn Crispin #define RX_DMA_FPORT_MASK 0x7 309*d5c53da2SFelix Fietkau #define RX_DMA_SPECIAL_TAG BIT(22) 310656e7052SJohn Crispin 311656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 312656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 313656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 314656e7052SJohn Crispin #define PHY_IAC_READ BIT(19) 315656e7052SJohn Crispin #define PHY_IAC_WRITE BIT(18) 316656e7052SJohn Crispin #define PHY_IAC_START BIT(16) 317656e7052SJohn Crispin #define PHY_IAC_ADDR_SHIFT 20 318656e7052SJohn Crispin #define PHY_IAC_REG_SHIFT 25 319656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 320656e7052SJohn Crispin 32142c03844SSean Wang #define MTK_MAC_MISC 0x1000c 32242c03844SSean Wang #define MTK_MUX_TO_ESW BIT(0) 32342c03844SSean Wang 324656e7052SJohn Crispin /* Mac control registers */ 325656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 3264fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 3274fd59792SDENG Qingfang #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 3284fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1518 0x0 3294fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1536 0x1 3304fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1552 0x2 3314fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_2048 0x3 332656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 333656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 334656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 335656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 336656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 337656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 338656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 339656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 340656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 341656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 342656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 343656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 344b8fc9f30SRené van Dorst #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 345b8fc9f30SRené van Dorst 346b8fc9f30SRené van Dorst /* Mac status registers */ 347b8fc9f30SRené van Dorst #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 348b8fc9f30SRené van Dorst #define MAC_MSR_EEE1G BIT(7) 349b8fc9f30SRené van Dorst #define MAC_MSR_EEE100M BIT(6) 350b8fc9f30SRené van Dorst #define MAC_MSR_RX_FC BIT(5) 351b8fc9f30SRené van Dorst #define MAC_MSR_TX_FC BIT(4) 352b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_1000 BIT(3) 353b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_100 BIT(2) 354b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 355b8fc9f30SRené van Dorst #define MAC_MSR_DPX BIT(1) 356b8fc9f30SRené van Dorst #define MAC_MSR_LINK BIT(0) 357656e7052SJohn Crispin 358f430dea7SSean Wang /* TRGMII RXC control register */ 359f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300 360f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 361f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 362f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 363a5d75538SRené van Dorst #define RXC_RST BIT(31) 364f430dea7SSean Wang #define RXC_DQSISEL BIT(30) 365f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 366f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 367f430dea7SSean Wang 368a5d75538SRené van Dorst #define NUM_TRGMII_CTRL 5 369a5d75538SRené van Dorst 370f430dea7SSean Wang /* TRGMII RXC control register */ 371f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340 372f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 373f430dea7SSean Wang #define TXC_INV BIT(30) 374f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 375f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 376f430dea7SSean Wang 377a5d75538SRené van Dorst /* TRGMII TX Drive Strength */ 378a5d75538SRené van Dorst #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 379a5d75538SRené van Dorst #define TD_DM_DRVP(x) ((x) & 0xf) 380a5d75538SRené van Dorst #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 381a5d75538SRené van Dorst 382f430dea7SSean Wang /* TRGMII Interface mode register */ 383f430dea7SSean Wang #define INTF_MODE 0x10390 384f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0) 385f430dea7SSean Wang #define TRGMII_MODE BIT(1) 386f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2) 387f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 388f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0 389f430dea7SSean Wang 390656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 391656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 392656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 393656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 394656e7052SJohn Crispin 395b95b6d99SNelson Chang /* ethernet subsystem chip id register */ 396b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0 397b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4 398983e1a6cSNelson Chang #define MT7623_ETH 7623 39942c03844SSean Wang #define MT7622_ETH 7622 400889bcbdeSBjørn Mork #define MT7621_ETH 7621 401b95b6d99SNelson Chang 4028efaa653SRené van Dorst /* ethernet system control register */ 4038efaa653SRené van Dorst #define ETHSYS_SYSCFG 0x10 4048efaa653SRené van Dorst #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 4058efaa653SRené van Dorst 406656e7052SJohn Crispin /* ethernet subsystem config register */ 407656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 408656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 409656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 4107093f9d8SSean Wang #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 4117093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 4127093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 4137093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 4147093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 4157093f9d8SSean Wang 416656e7052SJohn Crispin 417f430dea7SSean Wang /* ethernet subsystem clock register */ 418f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c 419f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 4208efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 4218efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 4228efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 423f430dea7SSean Wang 4242a8307aaSSean Wang /* ethernet reset control register */ 4252a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34 4262a8307aaSSean Wang #define RSTCTRL_FE BIT(6) 4272a8307aaSSean Wang #define RSTCTRL_PPE BIT(31) 4282a8307aaSSean Wang 42942c03844SSean Wang /* SGMII subsystem config registers */ 43042c03844SSean Wang /* Register to auto-negotiation restart */ 43142c03844SSean Wang #define SGMSYS_PCS_CONTROL_1 0x0 43242c03844SSean Wang #define SGMII_AN_RESTART BIT(9) 4337e538372SRené van Dorst #define SGMII_ISOLATE BIT(10) 4347e538372SRené van Dorst #define SGMII_AN_ENABLE BIT(12) 4357e538372SRené van Dorst #define SGMII_LINK_STATYS BIT(18) 4367e538372SRené van Dorst #define SGMII_AN_ABILITY BIT(19) 4377e538372SRené van Dorst #define SGMII_AN_COMPLETE BIT(21) 4387e538372SRené van Dorst #define SGMII_PCS_FAULT BIT(23) 4397e538372SRené van Dorst #define SGMII_AN_EXPANSION_CLR BIT(30) 44042c03844SSean Wang 44142c03844SSean Wang /* Register to programmable link timer, the unit in 2 * 8ns */ 44242c03844SSean Wang #define SGMSYS_PCS_LINK_TIMER 0x18 44342c03844SSean Wang #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 44442c03844SSean Wang 44542c03844SSean Wang /* Register to control remote fault */ 44642c03844SSean Wang #define SGMSYS_SGMII_MODE 0x20 4477e538372SRené van Dorst #define SGMII_IF_MODE_BIT0 BIT(0) 4487e538372SRené van Dorst #define SGMII_SPEED_DUPLEX_AN BIT(1) 4497e538372SRené van Dorst #define SGMII_SPEED_10 0x0 4507e538372SRené van Dorst #define SGMII_SPEED_100 BIT(2) 4517e538372SRené van Dorst #define SGMII_SPEED_1000 BIT(3) 4527e538372SRené van Dorst #define SGMII_DUPLEX_FULL BIT(4) 4537e538372SRené van Dorst #define SGMII_IF_MODE_BIT5 BIT(5) 45442c03844SSean Wang #define SGMII_REMOTE_FAULT_DIS BIT(8) 4557e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_VAL BIT(9) 4567e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_EN BIT(10) 4577e538372SRené van Dorst #define SGMII_SEND_AN_ERROR_EN BIT(11) 4587e538372SRené van Dorst #define SGMII_IF_MODE_MASK GENMASK(5, 1) 4597e538372SRené van Dorst 4607e538372SRené van Dorst /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 4617e538372SRené van Dorst #define SGMSYS_ANA_RG_CS3 0x2028 4627e538372SRené van Dorst #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 4637e538372SRené van Dorst #define RG_PHY_SPEED_1_25G 0x0 4647e538372SRené van Dorst #define RG_PHY_SPEED_3_125G BIT(2) 46542c03844SSean Wang 46642c03844SSean Wang /* Register to power up QPHY */ 46742c03844SSean Wang #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 46842c03844SSean Wang #define SGMII_PHYA_PWD BIT(4) 46942c03844SSean Wang 4707093f9d8SSean Wang /* Infrasys subsystem config registers */ 4717093f9d8SSean Wang #define INFRA_MISC2 0x70c 4727093f9d8SSean Wang #define CO_QPHY_SEL BIT(0) 4737093f9d8SSean Wang #define GEPHY_MAC_SEL BIT(1) 4747093f9d8SSean Wang 475296c9120SStefan Roese /* MT7628/88 specific stuff */ 476296c9120SStefan Roese #define MT7628_PDMA_OFFSET 0x0800 477296c9120SStefan Roese #define MT7628_SDM_OFFSET 0x0c00 478296c9120SStefan Roese 479296c9120SStefan Roese #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 480296c9120SStefan Roese #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 481296c9120SStefan Roese #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 482296c9120SStefan Roese #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 483296c9120SStefan Roese #define MT7628_PST_DTX_IDX0 BIT(0) 484296c9120SStefan Roese 485296c9120SStefan Roese #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 486296c9120SStefan Roese #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 487296c9120SStefan Roese 488656e7052SJohn Crispin struct mtk_rx_dma { 489656e7052SJohn Crispin unsigned int rxd1; 490656e7052SJohn Crispin unsigned int rxd2; 491656e7052SJohn Crispin unsigned int rxd3; 492656e7052SJohn Crispin unsigned int rxd4; 493656e7052SJohn Crispin } __packed __aligned(4); 494656e7052SJohn Crispin 495656e7052SJohn Crispin struct mtk_tx_dma { 496656e7052SJohn Crispin unsigned int txd1; 497656e7052SJohn Crispin unsigned int txd2; 498656e7052SJohn Crispin unsigned int txd3; 499656e7052SJohn Crispin unsigned int txd4; 500656e7052SJohn Crispin } __packed __aligned(4); 501656e7052SJohn Crispin 502656e7052SJohn Crispin struct mtk_eth; 503656e7052SJohn Crispin struct mtk_mac; 504656e7052SJohn Crispin 505656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 506656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 507656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 508656e7052SJohn Crispin * @syncp: the refcount 509656e7052SJohn Crispin * 510656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 511656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 512656e7052SJohn Crispin * counters and store them in this struct. 513656e7052SJohn Crispin */ 514656e7052SJohn Crispin struct mtk_hw_stats { 515656e7052SJohn Crispin u64 tx_bytes; 516656e7052SJohn Crispin u64 tx_packets; 517656e7052SJohn Crispin u64 tx_skip; 518656e7052SJohn Crispin u64 tx_collisions; 519656e7052SJohn Crispin u64 rx_bytes; 520656e7052SJohn Crispin u64 rx_packets; 521656e7052SJohn Crispin u64 rx_overflow; 522656e7052SJohn Crispin u64 rx_fcs_errors; 523656e7052SJohn Crispin u64 rx_short_errors; 524656e7052SJohn Crispin u64 rx_long_errors; 525656e7052SJohn Crispin u64 rx_checksum_errors; 526656e7052SJohn Crispin u64 rx_flow_control_packets; 527656e7052SJohn Crispin 528656e7052SJohn Crispin spinlock_t stats_lock; 529656e7052SJohn Crispin u32 reg_offset; 530656e7052SJohn Crispin struct u64_stats_sync syncp; 531656e7052SJohn Crispin }; 532656e7052SJohn Crispin 533656e7052SJohn Crispin enum mtk_tx_flags { 534134d2152SSean Wang /* PDMA descriptor can point at 1-2 segments. This enum allows us to 535134d2152SSean Wang * track how memory was allocated so that it can be freed properly. 536134d2152SSean Wang */ 537656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 538656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 539134d2152SSean Wang 540134d2152SSean Wang /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 541134d2152SSean Wang * SKB out instead of looking up through hardware TX descriptor. 542134d2152SSean Wang */ 543134d2152SSean Wang MTK_TX_FLAGS_FPORT0 = 0x04, 544134d2152SSean Wang MTK_TX_FLAGS_FPORT1 = 0x08, 545656e7052SJohn Crispin }; 546656e7052SJohn Crispin 547549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the 548549e5495SSean Wang * clock in the order 549549e5495SSean Wang */ 550549e5495SSean Wang enum mtk_clks_map { 551549e5495SSean Wang MTK_CLK_ETHIF, 552d438e298SSean Wang MTK_CLK_SGMIITOP, 553549e5495SSean Wang MTK_CLK_ESW, 55442c03844SSean Wang MTK_CLK_GP0, 555549e5495SSean Wang MTK_CLK_GP1, 556549e5495SSean Wang MTK_CLK_GP2, 557d438e298SSean Wang MTK_CLK_FE, 558f430dea7SSean Wang MTK_CLK_TRGPLL, 55942c03844SSean Wang MTK_CLK_SGMII_TX_250M, 56042c03844SSean Wang MTK_CLK_SGMII_RX_250M, 56142c03844SSean Wang MTK_CLK_SGMII_CDR_REF, 56242c03844SSean Wang MTK_CLK_SGMII_CDR_FB, 563d438e298SSean Wang MTK_CLK_SGMII2_TX_250M, 564d438e298SSean Wang MTK_CLK_SGMII2_RX_250M, 565d438e298SSean Wang MTK_CLK_SGMII2_CDR_REF, 566d438e298SSean Wang MTK_CLK_SGMII2_CDR_FB, 56742c03844SSean Wang MTK_CLK_SGMII_CK, 56842c03844SSean Wang MTK_CLK_ETH2PLL, 569549e5495SSean Wang MTK_CLK_MAX 570549e5495SSean Wang }; 571549e5495SSean Wang 5722ec50f57SSean Wang #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 5732ec50f57SSean Wang BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 5742ec50f57SSean Wang BIT(MTK_CLK_TRGPLL)) 57542c03844SSean Wang #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 57642c03844SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 57742c03844SSean Wang BIT(MTK_CLK_GP2) | \ 57842c03844SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 57942c03844SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 58042c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 58142c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 58242c03844SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 58342c03844SSean Wang BIT(MTK_CLK_ETH2PLL)) 584889bcbdeSBjørn Mork #define MT7621_CLKS_BITMAP (0) 585296c9120SStefan Roese #define MT7628_CLKS_BITMAP (0) 586d438e298SSean Wang #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 587d438e298SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 588d438e298SSean Wang BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 589d438e298SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 590d438e298SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 591d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 592d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 593d438e298SSean Wang BIT(MTK_CLK_SGMII2_TX_250M) | \ 594d438e298SSean Wang BIT(MTK_CLK_SGMII2_RX_250M) | \ 595d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_REF) | \ 596d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_FB) | \ 597d438e298SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 598d438e298SSean Wang BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 599889bcbdeSBjørn Mork 6009ea4d311SSean Wang enum mtk_dev_state { 601dce6fa42SSean Wang MTK_HW_INIT, 602dce6fa42SSean Wang MTK_RESETTING 6039ea4d311SSean Wang }; 6049ea4d311SSean Wang 605656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 606656e7052SJohn Crispin * by the TX descriptor s 607656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 608656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 609656e7052SJohn Crispin * @dma_len0: The length of the first segment 610656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 611656e7052SJohn Crispin * @dma_len1: The length of the second segment 612656e7052SJohn Crispin */ 613656e7052SJohn Crispin struct mtk_tx_buf { 614656e7052SJohn Crispin struct sk_buff *skb; 615656e7052SJohn Crispin u32 flags; 616656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 617656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 618656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 619656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 620656e7052SJohn Crispin }; 621656e7052SJohn Crispin 622656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 623656e7052SJohn Crispin * @dma: The descriptor ring 624656e7052SJohn Crispin * @buf: The memory pointed at by the ring 625656e7052SJohn Crispin * @phys: The physical addr of tx_buf 626656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 627656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 628656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 629656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 630656e7052SJohn Crispin * are present 631656e7052SJohn Crispin */ 632656e7052SJohn Crispin struct mtk_tx_ring { 633656e7052SJohn Crispin struct mtk_tx_dma *dma; 634656e7052SJohn Crispin struct mtk_tx_buf *buf; 635656e7052SJohn Crispin dma_addr_t phys; 636656e7052SJohn Crispin struct mtk_tx_dma *next_free; 637656e7052SJohn Crispin struct mtk_tx_dma *last_free; 638656e7052SJohn Crispin u16 thresh; 639656e7052SJohn Crispin atomic_t free_count; 640296c9120SStefan Roese int dma_size; 641296c9120SStefan Roese struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 642296c9120SStefan Roese dma_addr_t phys_pdma; 643296c9120SStefan Roese int cpu_idx; 644656e7052SJohn Crispin }; 645656e7052SJohn Crispin 646ee406810SNelson Chang /* PDMA rx ring mode */ 647ee406810SNelson Chang enum mtk_rx_flags { 648ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0, 649ee406810SNelson Chang MTK_RX_FLAGS_HWLRO, 6506427dc1dSJohn Crispin MTK_RX_FLAGS_QDMA, 651ee406810SNelson Chang }; 652ee406810SNelson Chang 653656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 654656e7052SJohn Crispin * @dma: The descriptor ring 655656e7052SJohn Crispin * @data: The memory pointed at by the ring 656656e7052SJohn Crispin * @phys: The physical addr of rx_buf 657656e7052SJohn Crispin * @frag_size: How big can each fragment be 658656e7052SJohn Crispin * @buf_size: The size of each packet buffer 659656e7052SJohn Crispin * @calc_idx: The current head of ring 660656e7052SJohn Crispin */ 661656e7052SJohn Crispin struct mtk_rx_ring { 662656e7052SJohn Crispin struct mtk_rx_dma *dma; 663656e7052SJohn Crispin u8 **data; 664656e7052SJohn Crispin dma_addr_t phys; 665656e7052SJohn Crispin u16 frag_size; 666656e7052SJohn Crispin u16 buf_size; 667ee406810SNelson Chang u16 dma_size; 668ee406810SNelson Chang bool calc_idx_update; 669656e7052SJohn Crispin u16 calc_idx; 670ee406810SNelson Chang u32 crx_idx_reg; 671656e7052SJohn Crispin }; 672656e7052SJohn Crispin 673e2c74694SRené van Dorst enum mkt_eth_capabilities { 674e2c74694SRené van Dorst MTK_RGMII_BIT = 0, 675e2c74694SRené van Dorst MTK_TRGMII_BIT, 676e2c74694SRené van Dorst MTK_SGMII_BIT, 677e2c74694SRené van Dorst MTK_ESW_BIT, 678e2c74694SRené van Dorst MTK_GEPHY_BIT, 679e2c74694SRené van Dorst MTK_MUX_BIT, 680e2c74694SRené van Dorst MTK_INFRA_BIT, 681e2c74694SRené van Dorst MTK_SHARED_SGMII_BIT, 682e2c74694SRené van Dorst MTK_HWLRO_BIT, 683e2c74694SRené van Dorst MTK_SHARED_INT_BIT, 684e2c74694SRené van Dorst MTK_TRGMII_MT7621_CLK_BIT, 685296c9120SStefan Roese MTK_QDMA_BIT, 686296c9120SStefan Roese MTK_SOC_MT7628_BIT, 6877093f9d8SSean Wang 688e2c74694SRené van Dorst /* MUX BITS*/ 689e2c74694SRené van Dorst MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 690e2c74694SRené van Dorst MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 691e2c74694SRené van Dorst MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 692e2c74694SRené van Dorst MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 693e2c74694SRené van Dorst MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 694e2c74694SRené van Dorst 695e2c74694SRené van Dorst /* PATH BITS */ 696e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_RGMII_BIT, 697e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_TRGMII_BIT, 698e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_SGMII_BIT, 699e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_RGMII_BIT, 700e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_SGMII_BIT, 701e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_GEPHY_BIT, 702e2c74694SRené van Dorst MTK_ETH_PATH_GDM1_ESW_BIT, 7037093f9d8SSean Wang }; 7047093f9d8SSean Wang 7057093f9d8SSean Wang /* Supported hardware group on SoCs */ 706e2c74694SRené van Dorst #define MTK_RGMII BIT(MTK_RGMII_BIT) 707e2c74694SRené van Dorst #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 708e2c74694SRené van Dorst #define MTK_SGMII BIT(MTK_SGMII_BIT) 709e2c74694SRené van Dorst #define MTK_ESW BIT(MTK_ESW_BIT) 710e2c74694SRené van Dorst #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 711e2c74694SRené van Dorst #define MTK_MUX BIT(MTK_MUX_BIT) 712e2c74694SRené van Dorst #define MTK_INFRA BIT(MTK_INFRA_BIT) 713e2c74694SRené van Dorst #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 714e2c74694SRené van Dorst #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 715e2c74694SRené van Dorst #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 716e2c74694SRené van Dorst #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 717296c9120SStefan Roese #define MTK_QDMA BIT(MTK_QDMA_BIT) 718296c9120SStefan Roese #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 719e2c74694SRené van Dorst 720e2c74694SRené van Dorst #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 721e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 722e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 723e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 724e2c74694SRené van Dorst #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 725e2c74694SRené van Dorst BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 726e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 727e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 728e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 729e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 7307093f9d8SSean Wang 7317093f9d8SSean Wang /* Supported path present on SoCs */ 732e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 733e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 734e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 735e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 736e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 737e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 738e2c74694SRené van Dorst #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 7397093f9d8SSean Wang 740e2c74694SRené van Dorst #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 741e2c74694SRené van Dorst #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 742e2c74694SRené van Dorst #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 743e2c74694SRené van Dorst #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 744e2c74694SRené van Dorst #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 745e2c74694SRené van Dorst #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 746e2c74694SRené van Dorst #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 7477093f9d8SSean Wang 7487093f9d8SSean Wang /* MUXes present on SoCs */ 7497093f9d8SSean Wang /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 750e2c74694SRené van Dorst #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 7517093f9d8SSean Wang 7527093f9d8SSean Wang /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 7537093f9d8SSean Wang #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 754e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 7557093f9d8SSean Wang 7567093f9d8SSean Wang /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 7577093f9d8SSean Wang #define MTK_MUX_U3_GMAC2_TO_QPHY \ 758e2c74694SRené van Dorst (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 7597093f9d8SSean Wang 7607093f9d8SSean Wang /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 7617093f9d8SSean Wang #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 762e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 7637093f9d8SSean Wang MTK_SHARED_SGMII) 7647093f9d8SSean Wang 7657093f9d8SSean Wang /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 7667093f9d8SSean Wang #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 767e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 7687093f9d8SSean Wang 7692ec50f57SSean Wang #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 7702ec50f57SSean Wang 7718efaa653SRené van Dorst #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 772296c9120SStefan Roese MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 773296c9120SStefan Roese MTK_TRGMII_MT7621_CLK | MTK_QDMA) 7748efaa653SRené van Dorst 7757093f9d8SSean Wang #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 7767093f9d8SSean Wang MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 7777093f9d8SSean Wang MTK_MUX_GDM1_TO_GMAC1_ESW | \ 778296c9120SStefan Roese MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 7797093f9d8SSean Wang 780296c9120SStefan Roese #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 781296c9120SStefan Roese MTK_QDMA) 782296c9120SStefan Roese 783296c9120SStefan Roese #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 7847093f9d8SSean Wang 7857093f9d8SSean Wang #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 7867093f9d8SSean Wang MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 7877093f9d8SSean Wang MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 7887093f9d8SSean Wang MTK_MUX_U3_GMAC2_TO_QPHY | \ 789296c9120SStefan Roese MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 7907093f9d8SSean Wang 79142c03844SSean Wang /* struct mtk_eth_data - This is the structure holding all differences 7922ec50f57SSean Wang * among various plaforms 7939ffee4a8SSean Wang * @ana_rgc3: The offset for register ANA_RGC3 related to 7949ffee4a8SSean Wang * sgmiisys syscon 7952ec50f57SSean Wang * @caps Flags shown the extra capability for the SoC 796296c9120SStefan Roese * @hw_features Flags shown HW features 7972ec50f57SSean Wang * @required_clks Flags shown the bitmap for required clocks on 7982ec50f57SSean Wang * the target SoC 799243dc5fbSSean Wang * @required_pctl A bool value to show whether the SoC requires 800243dc5fbSSean Wang * the extra setup for those pins used by GMAC. 8012ec50f57SSean Wang */ 8022ec50f57SSean Wang struct mtk_soc_data { 8039ffee4a8SSean Wang u32 ana_rgc3; 8042ec50f57SSean Wang u32 caps; 8052ec50f57SSean Wang u32 required_clks; 806243dc5fbSSean Wang bool required_pctl; 807296c9120SStefan Roese netdev_features_t hw_features; 8082ec50f57SSean Wang }; 8092ec50f57SSean Wang 810656e7052SJohn Crispin /* currently no SoC has more than 2 macs */ 811656e7052SJohn Crispin #define MTK_MAX_DEVS 2 812656e7052SJohn Crispin 8139ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_AN BIT(31) 814937a9440SJoe Perches #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) 8159ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_1000 BIT(0) 8169ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_2500 BIT(1) 8179ffee4a8SSean Wang #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) 8189ffee4a8SSean Wang 8199ffee4a8SSean Wang /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 8209ffee4a8SSean Wang * characteristics 8219ffee4a8SSean Wang * @regmap: The register map pointing at the range used to setup 8229ffee4a8SSean Wang * SGMII modes 8239ffee4a8SSean Wang * @flags: The enum refers to which mode the sgmii wants to run on 8249ffee4a8SSean Wang * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 8259ffee4a8SSean Wang */ 8269ffee4a8SSean Wang 8279ffee4a8SSean Wang struct mtk_sgmii { 8289ffee4a8SSean Wang struct regmap *regmap[MTK_MAX_DEVS]; 8299ffee4a8SSean Wang u32 flags[MTK_MAX_DEVS]; 8309ffee4a8SSean Wang u32 ana_rgc3; 8319ffee4a8SSean Wang }; 8329ffee4a8SSean Wang 833656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 834656e7052SJohn Crispin * of the driver 835656e7052SJohn Crispin * @dev: The device pointer 836656e7052SJohn Crispin * @base: The mapped register i/o base 837656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 8385cce0322SJohn Crispin * @tx_irq__lock: Make sure that IRQ register operations are atomic 8395cce0322SJohn Crispin * @rx_irq__lock: Make sure that IRQ register operations are atomic 840656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 841656e7052SJohn Crispin * dummy for NAPI to work 842656e7052SJohn Crispin * @netdev: The netdev instances 843656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 844656e7052SJohn Crispin * @irq: The IRQ that we are using 845656e7052SJohn Crispin * @msg_enable: Ethtool msg level 846656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 847656e7052SJohn Crispin * MII modes 8487093f9d8SSean Wang * @infra: The register map pointing at the range used to setup 8497093f9d8SSean Wang * SGMII and GePHY path 850656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 851656e7052SJohn Crispin * GMAC port drive/slew values 852656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 8530c07ce7fSJohn Crispin * @tx_ring: Pointer to the memory holding info about the TX ring 8540c07ce7fSJohn Crispin * @rx_ring: Pointer to the memory holding info about the RX ring 8556427dc1dSJohn Crispin * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 85680673029SJohn Crispin * @tx_napi: The TX NAPI struct 85780673029SJohn Crispin * @rx_napi: The RX NAPI struct 858656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 859605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 860656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 861549e5495SSean Wang * @clks: clock array for all clocks required 862656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 8637c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 86442c03844SSean Wang * @state: Initialization and runtime state of the device 8652ec50f57SSean Wang * @soc: Holding specific data among vaious SoCs 866656e7052SJohn Crispin */ 867656e7052SJohn Crispin 868656e7052SJohn Crispin struct mtk_eth { 869656e7052SJohn Crispin struct device *dev; 870656e7052SJohn Crispin void __iomem *base; 871656e7052SJohn Crispin spinlock_t page_lock; 8725cce0322SJohn Crispin spinlock_t tx_irq_lock; 8735cce0322SJohn Crispin spinlock_t rx_irq_lock; 874656e7052SJohn Crispin struct net_device dummy_dev; 875656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 876656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 87780673029SJohn Crispin int irq[3]; 878656e7052SJohn Crispin u32 msg_enable; 879656e7052SJohn Crispin unsigned long sysclk; 880656e7052SJohn Crispin struct regmap *ethsys; 8817093f9d8SSean Wang struct regmap *infra; 8829ffee4a8SSean Wang struct mtk_sgmii *sgmii; 883656e7052SJohn Crispin struct regmap *pctl; 884ee406810SNelson Chang bool hwlro; 885c6d4e63eSElena Reshetova refcount_t dma_refcnt; 886656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 887ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 8886427dc1dSJohn Crispin struct mtk_rx_ring rx_ring_qdma; 88980673029SJohn Crispin struct napi_struct tx_napi; 890656e7052SJohn Crispin struct napi_struct rx_napi; 891656e7052SJohn Crispin struct mtk_tx_dma *scratch_ring; 892605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 893656e7052SJohn Crispin void *scratch_head; 894549e5495SSean Wang struct clk *clks[MTK_CLK_MAX]; 895549e5495SSean Wang 896656e7052SJohn Crispin struct mii_bus *mii_bus; 8977c78b4adSJohn Crispin struct work_struct pending_work; 8989ea4d311SSean Wang unsigned long state; 8992ec50f57SSean Wang 9002ec50f57SSean Wang const struct mtk_soc_data *soc; 901296c9120SStefan Roese 902296c9120SStefan Roese u32 tx_int_mask_reg; 903296c9120SStefan Roese u32 tx_int_status_reg; 904296c9120SStefan Roese u32 rx_dma_l4_valid; 905296c9120SStefan Roese int ip_align; 906656e7052SJohn Crispin }; 907656e7052SJohn Crispin 908656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 909656e7052SJohn Crispin * SoC 910656e7052SJohn Crispin * @id: The number of the MAC 911b8fc9f30SRené van Dorst * @interface: Interface mode kept for detecting change in hw settings 912656e7052SJohn Crispin * @of_node: Our devicetree node 913656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 914656e7052SJohn Crispin * @hw_stats: Packet statistics counter 915656e7052SJohn Crispin */ 916656e7052SJohn Crispin struct mtk_mac { 917656e7052SJohn Crispin int id; 918b8fc9f30SRené van Dorst phy_interface_t interface; 919b8fc9f30SRené van Dorst unsigned int mode; 920b8fc9f30SRené van Dorst int speed; 921656e7052SJohn Crispin struct device_node *of_node; 922b8fc9f30SRené van Dorst struct phylink *phylink; 923b8fc9f30SRené van Dorst struct phylink_config phylink_config; 924656e7052SJohn Crispin struct mtk_eth *hw; 925656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 926ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 927ee406810SNelson Chang int hwlro_ip_cnt; 928656e7052SJohn Crispin }; 929656e7052SJohn Crispin 930656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 931656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 932656e7052SJohn Crispin 933656e7052SJohn Crispin /* read the hardware status register */ 934656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 935656e7052SJohn Crispin 936656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 937656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 938656e7052SJohn Crispin 9399ffee4a8SSean Wang int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 9409ffee4a8SSean Wang u32 ana_rgc3); 9419ffee4a8SSean Wang int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); 9427e538372SRené van Dorst int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, 9437e538372SRené van Dorst const struct phylink_link_state *state); 9447e538372SRené van Dorst void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); 9457e538372SRené van Dorst 9467e538372SRené van Dorst int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 9477e538372SRené van Dorst int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 9487e538372SRené van Dorst int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 9499ffee4a8SSean Wang 950656e7052SJohn Crispin #endif /* MTK_ETH_H */ 951