18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28e8e69d6SThomas Gleixner /* 3656e7052SJohn Crispin * 4656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7656e7052SJohn Crispin */ 8656e7052SJohn Crispin 9656e7052SJohn Crispin #ifndef MTK_ETH_H 10656e7052SJohn Crispin #define MTK_ETH_H 11656e7052SJohn Crispin 129ffee4a8SSean Wang #include <linux/dma-mapping.h> 139ffee4a8SSean Wang #include <linux/netdevice.h> 149ffee4a8SSean Wang #include <linux/of_net.h> 159ffee4a8SSean Wang #include <linux/u64_stats_sync.h> 16c6d4e63eSElena Reshetova #include <linux/refcount.h> 17b8fc9f30SRené van Dorst #include <linux/phylink.h> 18502e84e2SFelix Fietkau #include <linux/rhashtable.h> 19e9229ffdSFelix Fietkau #include <linux/dim.h> 20bc5e93e0SRussell King (Oracle) #include <linux/bitfield.h> 2123233e57SLorenzo Bianconi #include <net/page_pool.h> 2223233e57SLorenzo Bianconi #include <linux/bpf_trace.h> 23ba37b7caSFelix Fietkau #include "mtk_ppe.h" 24c6d4e63eSElena Reshetova 25656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 26656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 274fd59792SDENG Qingfang #define MTK_MAX_RX_LENGTH_2K 2048 28656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 29160d3a9bSLorenzo Bianconi #define MTK_TX_DMA_BUF_LEN_V2 0xffff 306b4423b2SFelix Fietkau #define MTK_DMA_SIZE 512 31656e7052SJohn Crispin #define MTK_MAC_COUNT 2 324fd59792SDENG Qingfang #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 33656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 34656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 35656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 36656e7052SJohn Crispin NETIF_MSG_PROBE | \ 37656e7052SJohn Crispin NETIF_MSG_LINK | \ 38656e7052SJohn Crispin NETIF_MSG_TIMER | \ 39656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 40656e7052SJohn Crispin NETIF_MSG_IFUP | \ 41656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 42656e7052SJohn Crispin NETIF_MSG_TX_ERR) 43656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 44656e7052SJohn Crispin NETIF_F_RXCSUM | \ 45656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 46656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_RX | \ 47656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 48656e7052SJohn Crispin NETIF_F_TSO6 | \ 49502e84e2SFelix Fietkau NETIF_F_IPV6_CSUM |\ 50502e84e2SFelix Fietkau NETIF_F_HW_TC) 51296c9120SStefan Roese #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 5208df5fa6SStefan Roese #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 53ee406810SNelson Chang 5423233e57SLorenzo Bianconi #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM 5523233e57SLorenzo Bianconi #define MTK_PP_PAD (MTK_PP_HEADROOM + \ 5623233e57SLorenzo Bianconi SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 5723233e57SLorenzo Bianconi #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD) 5823233e57SLorenzo Bianconi 598cb42714SLorenzo Bianconi #define MTK_QRX_OFFSET 0x10 608cb42714SLorenzo Bianconi 61ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4 62ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8 63ee406810SNelson Chang 64ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 65ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2 66ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 67ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 68ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 69ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 70ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64 71ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000 72ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000 73ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 74656e7052SJohn Crispin 75656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 76656e7052SJohn Crispin #define MTK_RST_GL 0x04 77656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 78656e7052SJohn Crispin 79656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 80656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 81656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 82656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 83656e7052SJohn Crispin 84ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */ 85ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 86ee406810SNelson Chang 87656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 88656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 89656e7052SJohn Crispin 9087e3df49SSean Wang /* CDMP Ingress Control Register */ 9187e3df49SSean Wang #define MTK_CDMQ_IG_CTRL 0x1400 9287e3df49SSean Wang #define MTK_CDMQ_STAG_EN BIT(0) 9387e3df49SSean Wang 94160d3a9bSLorenzo Bianconi /* CDMP Ingress Control Register */ 95160d3a9bSLorenzo Bianconi #define MTK_CDMP_IG_CTRL 0x400 96160d3a9bSLorenzo Bianconi #define MTK_CDMP_STAG_EN BIT(0) 97160d3a9bSLorenzo Bianconi 98656e7052SJohn Crispin /* CDMP Exgress Control Register */ 99656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 100656e7052SJohn Crispin 101656e7052SJohn Crispin /* GDM Exgress Control Register */ 102656e7052SJohn Crispin #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 103d5c53da2SFelix Fietkau #define MTK_GDMA_SPECIAL_TAG BIT(24) 104656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 105656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 106656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 1078d3f4a95SMarkLee #define MTK_GDMA_TO_PDMA 0x0 1088d66a818SMarkLee #define MTK_GDMA_DROP_ALL 0x7777 109656e7052SJohn Crispin 110656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 111656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 112656e7052SJohn Crispin 113656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 114656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 115656e7052SJohn Crispin 116160d3a9bSLorenzo Bianconi /* FE global misc reg*/ 117160d3a9bSLorenzo Bianconi #define MTK_FE_GLO_MISC 0x124 118160d3a9bSLorenzo Bianconi 119160d3a9bSLorenzo Bianconi /* PSE Free Queue Flow Control */ 120160d3a9bSLorenzo Bianconi #define PSE_FQFC_CFG1 0x100 121160d3a9bSLorenzo Bianconi #define PSE_FQFC_CFG2 0x104 122160d3a9bSLorenzo Bianconi #define PSE_DROP_CFG 0x108 123160d3a9bSLorenzo Bianconi 124160d3a9bSLorenzo Bianconi /* PSE Input Queue Reservation Register*/ 125160d3a9bSLorenzo Bianconi #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 126160d3a9bSLorenzo Bianconi 127160d3a9bSLorenzo Bianconi /* PSE Output Queue Threshold Register*/ 128160d3a9bSLorenzo Bianconi #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 129160d3a9bSLorenzo Bianconi 130160d3a9bSLorenzo Bianconi /* GDM and CDM Threshold */ 131160d3a9bSLorenzo Bianconi #define MTK_GDM2_THRES 0x1530 132160d3a9bSLorenzo Bianconi #define MTK_CDMW0_THRES 0x164c 133160d3a9bSLorenzo Bianconi #define MTK_CDMW1_THRES 0x1650 134160d3a9bSLorenzo Bianconi #define MTK_CDME0_THRES 0x1654 135160d3a9bSLorenzo Bianconi #define MTK_CDME1_THRES 0x1658 136160d3a9bSLorenzo Bianconi #define MTK_CDMM_THRES 0x165c 137160d3a9bSLorenzo Bianconi 138ee406810SNelson Chang /* PDMA HW LRO Control Registers */ 139ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980 140ee406810SNelson Chang #define MTK_LRO_EN BIT(0) 141ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7) 142160d3a9bSLorenzo Bianconi #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 143ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 144ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 145160d3a9bSLorenzo Bianconi #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 146ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 147160d3a9bSLorenzo Bianconi #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 148ee406810SNelson Chang 149ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984 150ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988 151ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c 152ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15) 153ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 154bacfd110SNelson Chang 1558cb42714SLorenzo Bianconi #define MTK_RX_DMA_LRO_EN BIT(8) 156bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10) 157296c9120SStefan Roese #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 158bacfd110SNelson Chang 1598cb42714SLorenzo Bianconi /* PDMA Global Configuration Register */ 1608cb42714SLorenzo Bianconi #define MTK_PDMA_LRO_SDL 0x3000 1618cb42714SLorenzo Bianconi #define MTK_RX_CFG_SDL_OFFSET 16 1628cb42714SLorenzo Bianconi 163bacfd110SNelson Chang /* PDMA Reset Index Register */ 164bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16) 165ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 166bacfd110SNelson Chang 167bacfd110SNelson Chang /* PDMA Delay Interrupt Register */ 168e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 169671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_EN BIT(15) 170671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 171e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 172e9229ffdSFelix Fietkau 173e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 174e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_EN BIT(31) 175e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 176e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 177e9229ffdSFelix Fietkau 178e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PINT_MASK 0x7f 179e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PTIME_MASK 0xff 180bacfd110SNelson Chang 181ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */ 182ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 183ee406810SNelson Chang 184ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */ 185ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 186ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 187ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9) 188ee406810SNelson Chang 189ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */ 190ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 191ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 192ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 193ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 194ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 195ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 196ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 197ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 198ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 199ee406810SNelson Chang #define MTK_RING_VLD BIT(8) 200ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 201ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 202ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 203ee406810SNelson Chang 204656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 205656e7052SJohn Crispin #define QDMA_RES_THRES 4 206656e7052SJohn Crispin 207656e7052SJohn Crispin /* QDMA Global Configuration Register */ 208656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 209656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 2106675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 211656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 21259555a8dSFelix Fietkau #define MTK_TX_BT_32DWORDS (3 << 4) 213656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 214656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 215656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 216656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 2173bc8e0afSIlya Lipnitskiy #define MTK_DMA_BUSY_TIMEOUT_US 1000000 218656e7052SJohn Crispin 219160d3a9bSLorenzo Bianconi /* QDMA V2 Global Configuration Register */ 220160d3a9bSLorenzo Bianconi #define MTK_CHK_DDONE_EN BIT(28) 221160d3a9bSLorenzo Bianconi #define MTK_DMAD_WR_WDONE BIT(26) 222160d3a9bSLorenzo Bianconi #define MTK_WCOMP_EN BIT(24) 223160d3a9bSLorenzo Bianconi #define MTK_RESV_BUF (0x40 << 16) 224160d3a9bSLorenzo Bianconi #define MTK_MUTLI_CNT (0x4 << 12) 225160d3a9bSLorenzo Bianconi 226656e7052SJohn Crispin /* QDMA Flow Control Register */ 227656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 228656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 229656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 230656e7052SJohn Crispin 231656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 232671d41e6SJohn Crispin #define MTK_RX_DONE_DLY BIT(30) 233e9229ffdSFelix Fietkau #define MTK_TX_DONE_DLY BIT(28) 234bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19) 235bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18) 236656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 237656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 238656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 239656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 240656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 241656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 242671d41e6SJohn Crispin #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 243e9229ffdSFelix Fietkau #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 244656e7052SJohn Crispin 245160d3a9bSLorenzo Bianconi #define MTK_RX_DONE_INT_V2 BIT(14) 246160d3a9bSLorenzo Bianconi 24780673029SJohn Crispin /* QDMA Interrupt grouping registers */ 24880673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0) 24980673029SJohn Crispin 250656e7052SJohn Crispin #define MTK_STAT_OFFSET 0x40 251656e7052SJohn Crispin 252160d3a9bSLorenzo Bianconi /* QDMA TX NUM */ 253160d3a9bSLorenzo Bianconi #define MTK_QDMA_TX_NUM 16 254160d3a9bSLorenzo Bianconi #define MTK_QDMA_TX_MASK (MTK_QDMA_TX_NUM - 1) 255160d3a9bSLorenzo Bianconi #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 256160d3a9bSLorenzo Bianconi #define MTK_QDMA_GMAC2_QID 8 257160d3a9bSLorenzo Bianconi 258160d3a9bSLorenzo Bianconi #define MTK_TX_DMA_BUF_SHIFT 8 259160d3a9bSLorenzo Bianconi 260160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd6 */ 261160d3a9bSLorenzo Bianconi #define TX_DMA_INS_VLAN_V2 BIT(16) 262160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd5 */ 263160d3a9bSLorenzo Bianconi #define TX_DMA_CHKSUM_V2 (0x7 << 28) 264160d3a9bSLorenzo Bianconi #define TX_DMA_TSO_V2 BIT(31) 265160d3a9bSLorenzo Bianconi 266160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd4 */ 267160d3a9bSLorenzo Bianconi #define TX_DMA_FPORT_SHIFT_V2 8 268160d3a9bSLorenzo Bianconi #define TX_DMA_FPORT_MASK_V2 0xf 269160d3a9bSLorenzo Bianconi #define TX_DMA_SWC_V2 BIT(30) 270160d3a9bSLorenzo Bianconi 271656e7052SJohn Crispin /* QDMA descriptor txd4 */ 272656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 273656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 274656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 275656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 276656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 277656e7052SJohn Crispin 278656e7052SJohn Crispin /* QDMA descriptor txd3 */ 279656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 280656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 281160d3a9bSLorenzo Bianconi #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 282160d3a9bSLorenzo Bianconi #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) 283656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 284656e7052SJohn Crispin 285296c9120SStefan Roese /* PDMA on MT7628 */ 286296c9120SStefan Roese #define TX_DMA_DONE BIT(31) 287296c9120SStefan Roese #define TX_DMA_LS1 BIT(14) 288296c9120SStefan Roese #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 289296c9120SStefan Roese 290656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 291656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 292296c9120SStefan Roese #define RX_DMA_LSO BIT(30) 293160d3a9bSLorenzo Bianconi #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 294160d3a9bSLorenzo Bianconi #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) 2953f57d8c4SFelix Fietkau #define RX_DMA_VTAG BIT(15) 296656e7052SJohn Crispin 297656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 298160d3a9bSLorenzo Bianconi #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 299160d3a9bSLorenzo Bianconi #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 300160d3a9bSLorenzo Bianconi #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 301656e7052SJohn Crispin 302656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 303ba37b7caSFelix Fietkau #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 304ba37b7caSFelix Fietkau #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 305ba37b7caSFelix Fietkau #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 306ba37b7caSFelix Fietkau #define MTK_RXD4_ALG GENMASK(31, 22) 307ba37b7caSFelix Fietkau 308ba37b7caSFelix Fietkau /* QDMA descriptor rxd4 */ 309656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 310296c9120SStefan Roese #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 311d5c53da2SFelix Fietkau #define RX_DMA_SPECIAL_TAG BIT(22) 312656e7052SJohn Crispin 3130cf731f9SLorenzo Bianconi /* PDMA descriptor rxd5 */ 3140cf731f9SLorenzo Bianconi #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) 3150cf731f9SLorenzo Bianconi #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) 3160cf731f9SLorenzo Bianconi #define MTK_RXD5_SRC_PORT GENMASK(29, 26) 3170cf731f9SLorenzo Bianconi 318c9da02bfSDaniel Golle #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7) 319c9da02bfSDaniel Golle #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf) 320160d3a9bSLorenzo Bianconi 321160d3a9bSLorenzo Bianconi /* PDMA V2 descriptor rxd3 */ 322160d3a9bSLorenzo Bianconi #define RX_DMA_VTAG_V2 BIT(0) 323160d3a9bSLorenzo Bianconi #define RX_DMA_L4_VALID_V2 BIT(2) 324160d3a9bSLorenzo Bianconi 325656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 326656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 327656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 328eda80b24SDaniel Golle #define PHY_IAC_REG_MASK GENMASK(29, 25) 329eda80b24SDaniel Golle #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 330eda80b24SDaniel Golle #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 331eda80b24SDaniel Golle #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 332eda80b24SDaniel Golle #define PHY_IAC_CMD_MASK GENMASK(19, 18) 333e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 334eda80b24SDaniel Golle #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 335eda80b24SDaniel Golle #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 336e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 337eda80b24SDaniel Golle #define PHY_IAC_START_MASK GENMASK(17, 16) 338e2e7f6e2SDaniel Golle #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 339eda80b24SDaniel Golle #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 340eda80b24SDaniel Golle #define PHY_IAC_DATA_MASK GENMASK(15, 0) 341eda80b24SDaniel Golle #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 342656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 343656e7052SJohn Crispin 34442c03844SSean Wang #define MTK_MAC_MISC 0x1000c 34542c03844SSean Wang #define MTK_MUX_TO_ESW BIT(0) 34642c03844SSean Wang 347656e7052SJohn Crispin /* Mac control registers */ 348656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 3494fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 3504fd59792SDENG Qingfang #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 3514fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1518 0x0 3524fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1536 0x1 3534fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1552 0x2 3544fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_2048 0x3 355656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 356656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 357656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 358656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 359656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 360656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 361656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 362656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 363656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 364656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 365656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 366656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 367b8fc9f30SRené van Dorst #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 368b8fc9f30SRené van Dorst 369b8fc9f30SRené van Dorst /* Mac status registers */ 370b8fc9f30SRené van Dorst #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 371b8fc9f30SRené van Dorst #define MAC_MSR_EEE1G BIT(7) 372b8fc9f30SRené van Dorst #define MAC_MSR_EEE100M BIT(6) 373b8fc9f30SRené van Dorst #define MAC_MSR_RX_FC BIT(5) 374b8fc9f30SRené van Dorst #define MAC_MSR_TX_FC BIT(4) 375b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_1000 BIT(3) 376b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_100 BIT(2) 377b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 378b8fc9f30SRené van Dorst #define MAC_MSR_DPX BIT(1) 379b8fc9f30SRené van Dorst #define MAC_MSR_LINK BIT(0) 380656e7052SJohn Crispin 381f430dea7SSean Wang /* TRGMII RXC control register */ 382f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300 383f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 384f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 385f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 386a5d75538SRené van Dorst #define RXC_RST BIT(31) 387f430dea7SSean Wang #define RXC_DQSISEL BIT(30) 388f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 389f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 390f430dea7SSean Wang 391a5d75538SRené van Dorst #define NUM_TRGMII_CTRL 5 392a5d75538SRené van Dorst 393f430dea7SSean Wang /* TRGMII RXC control register */ 394f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340 395f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 396f430dea7SSean Wang #define TXC_INV BIT(30) 397f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 398f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 399f430dea7SSean Wang 400a5d75538SRené van Dorst /* TRGMII TX Drive Strength */ 401a5d75538SRené van Dorst #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 402a5d75538SRené van Dorst #define TD_DM_DRVP(x) ((x) & 0xf) 403a5d75538SRené van Dorst #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 404a5d75538SRené van Dorst 405f430dea7SSean Wang /* TRGMII Interface mode register */ 406f430dea7SSean Wang #define INTF_MODE 0x10390 407f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0) 408f430dea7SSean Wang #define TRGMII_MODE BIT(1) 409f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2) 410f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 411f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0 412f430dea7SSean Wang 413656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 414656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 415656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 416656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 417656e7052SJohn Crispin 418b95b6d99SNelson Chang /* ethernet subsystem chip id register */ 419b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0 420b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4 421983e1a6cSNelson Chang #define MT7623_ETH 7623 42242c03844SSean Wang #define MT7622_ETH 7622 423889bcbdeSBjørn Mork #define MT7621_ETH 7621 424b95b6d99SNelson Chang 4258efaa653SRené van Dorst /* ethernet system control register */ 4268efaa653SRené van Dorst #define ETHSYS_SYSCFG 0x10 4278efaa653SRené van Dorst #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 4288efaa653SRené van Dorst 429656e7052SJohn Crispin /* ethernet subsystem config register */ 430656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 431656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 432656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 4337093f9d8SSean Wang #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 4347093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 4357093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 4367093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 4377093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 4387093f9d8SSean Wang 439656e7052SJohn Crispin 440f430dea7SSean Wang /* ethernet subsystem clock register */ 441f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c 442f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 4438efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 4448efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 4458efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 446f430dea7SSean Wang 4472a8307aaSSean Wang /* ethernet reset control register */ 4482a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34 4492a8307aaSSean Wang #define RSTCTRL_FE BIT(6) 4502a8307aaSSean Wang #define RSTCTRL_PPE BIT(31) 451160d3a9bSLorenzo Bianconi #define RSTCTRL_PPE1 BIT(30) 452160d3a9bSLorenzo Bianconi #define RSTCTRL_ETH BIT(23) 453160d3a9bSLorenzo Bianconi 454160d3a9bSLorenzo Bianconi /* ethernet reset check idle register */ 455160d3a9bSLorenzo Bianconi #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 456160d3a9bSLorenzo Bianconi 457160d3a9bSLorenzo Bianconi /* ethernet reset control register */ 458160d3a9bSLorenzo Bianconi #define ETHSYS_RSTCTRL 0x34 459160d3a9bSLorenzo Bianconi #define RSTCTRL_FE BIT(6) 460160d3a9bSLorenzo Bianconi #define RSTCTRL_PPE BIT(31) 4612a8307aaSSean Wang 462d776a57eSFelix Fietkau /* ethernet dma channel agent map */ 463d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP 0x408 464d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 465d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 466d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 467d776a57eSFelix Fietkau 46842c03844SSean Wang /* SGMII subsystem config registers */ 469*b6a709cbSRussell King (Oracle) /* BMCR (low 16) BMSR (high 16) */ 47042c03844SSean Wang #define SGMSYS_PCS_CONTROL_1 0x0 471*b6a709cbSRussell King (Oracle) #define SGMII_BMCR GENMASK(15, 0) 472*b6a709cbSRussell King (Oracle) #define SGMII_BMSR GENMASK(31, 16) 47342c03844SSean Wang #define SGMII_AN_RESTART BIT(9) 4747e538372SRené van Dorst #define SGMII_ISOLATE BIT(10) 4757e538372SRené van Dorst #define SGMII_AN_ENABLE BIT(12) 4767e538372SRené van Dorst #define SGMII_LINK_STATYS BIT(18) 4777e538372SRené van Dorst #define SGMII_AN_ABILITY BIT(19) 4787e538372SRené van Dorst #define SGMII_AN_COMPLETE BIT(21) 4797e538372SRené van Dorst #define SGMII_PCS_FAULT BIT(23) 4807e538372SRené van Dorst #define SGMII_AN_EXPANSION_CLR BIT(30) 48142c03844SSean Wang 482*b6a709cbSRussell King (Oracle) #define SGMSYS_PCS_ADVERTISE 0x8 483*b6a709cbSRussell King (Oracle) #define SGMII_ADVERTISE GENMASK(15, 0) 484*b6a709cbSRussell King (Oracle) #define SGMII_LPA GENMASK(31, 16) 485*b6a709cbSRussell King (Oracle) 48642c03844SSean Wang /* Register to programmable link timer, the unit in 2 * 8ns */ 48742c03844SSean Wang #define SGMSYS_PCS_LINK_TIMER 0x18 488*b6a709cbSRussell King (Oracle) #define SGMII_LINK_TIMER_MASK GENMASK(19, 0) 489*b6a709cbSRussell King (Oracle) #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & SGMII_LINK_TIMER_MASK) 49042c03844SSean Wang 49142c03844SSean Wang /* Register to control remote fault */ 49242c03844SSean Wang #define SGMSYS_SGMII_MODE 0x20 493*b6a709cbSRussell King (Oracle) #define SGMII_IF_MODE_SGMII BIT(0) 4947e538372SRené van Dorst #define SGMII_SPEED_DUPLEX_AN BIT(1) 495bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_MASK GENMASK(3, 2) 496bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) 497bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) 498bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) 4997e538372SRené van Dorst #define SGMII_DUPLEX_FULL BIT(4) 5007e538372SRené van Dorst #define SGMII_IF_MODE_BIT5 BIT(5) 50142c03844SSean Wang #define SGMII_REMOTE_FAULT_DIS BIT(8) 5027e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_VAL BIT(9) 5037e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_EN BIT(10) 5047e538372SRené van Dorst #define SGMII_SEND_AN_ERROR_EN BIT(11) 5057e538372SRené van Dorst #define SGMII_IF_MODE_MASK GENMASK(5, 1) 5067e538372SRené van Dorst 5077e538372SRené van Dorst /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 5087e538372SRené van Dorst #define SGMSYS_ANA_RG_CS3 0x2028 5097e538372SRené van Dorst #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 5107e538372SRené van Dorst #define RG_PHY_SPEED_1_25G 0x0 5117e538372SRené van Dorst #define RG_PHY_SPEED_3_125G BIT(2) 51242c03844SSean Wang 51342c03844SSean Wang /* Register to power up QPHY */ 51442c03844SSean Wang #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 51542c03844SSean Wang #define SGMII_PHYA_PWD BIT(4) 51642c03844SSean Wang 5177093f9d8SSean Wang /* Infrasys subsystem config registers */ 5187093f9d8SSean Wang #define INFRA_MISC2 0x70c 5197093f9d8SSean Wang #define CO_QPHY_SEL BIT(0) 5207093f9d8SSean Wang #define GEPHY_MAC_SEL BIT(1) 5217093f9d8SSean Wang 522296c9120SStefan Roese /* MT7628/88 specific stuff */ 523296c9120SStefan Roese #define MT7628_PDMA_OFFSET 0x0800 524296c9120SStefan Roese #define MT7628_SDM_OFFSET 0x0c00 525296c9120SStefan Roese 526296c9120SStefan Roese #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 527296c9120SStefan Roese #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 528296c9120SStefan Roese #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 529296c9120SStefan Roese #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 530296c9120SStefan Roese #define MT7628_PST_DTX_IDX0 BIT(0) 531296c9120SStefan Roese 532296c9120SStefan Roese #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 533296c9120SStefan Roese #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 534296c9120SStefan Roese 535ad79fd2cSStefan Roese /* Counter / stat register */ 536ad79fd2cSStefan Roese #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 537ad79fd2cSStefan Roese #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 538ad79fd2cSStefan Roese #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 539ad79fd2cSStefan Roese #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 540ad79fd2cSStefan Roese #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 541ad79fd2cSStefan Roese 542656e7052SJohn Crispin struct mtk_rx_dma { 543656e7052SJohn Crispin unsigned int rxd1; 544656e7052SJohn Crispin unsigned int rxd2; 545656e7052SJohn Crispin unsigned int rxd3; 546656e7052SJohn Crispin unsigned int rxd4; 547656e7052SJohn Crispin } __packed __aligned(4); 548656e7052SJohn Crispin 549160d3a9bSLorenzo Bianconi struct mtk_rx_dma_v2 { 550160d3a9bSLorenzo Bianconi unsigned int rxd1; 551160d3a9bSLorenzo Bianconi unsigned int rxd2; 552160d3a9bSLorenzo Bianconi unsigned int rxd3; 553160d3a9bSLorenzo Bianconi unsigned int rxd4; 554160d3a9bSLorenzo Bianconi unsigned int rxd5; 555160d3a9bSLorenzo Bianconi unsigned int rxd6; 556160d3a9bSLorenzo Bianconi unsigned int rxd7; 557160d3a9bSLorenzo Bianconi unsigned int rxd8; 558160d3a9bSLorenzo Bianconi } __packed __aligned(4); 559160d3a9bSLorenzo Bianconi 560656e7052SJohn Crispin struct mtk_tx_dma { 561656e7052SJohn Crispin unsigned int txd1; 562656e7052SJohn Crispin unsigned int txd2; 563656e7052SJohn Crispin unsigned int txd3; 564656e7052SJohn Crispin unsigned int txd4; 565656e7052SJohn Crispin } __packed __aligned(4); 566656e7052SJohn Crispin 567160d3a9bSLorenzo Bianconi struct mtk_tx_dma_v2 { 568160d3a9bSLorenzo Bianconi unsigned int txd1; 569160d3a9bSLorenzo Bianconi unsigned int txd2; 570160d3a9bSLorenzo Bianconi unsigned int txd3; 571160d3a9bSLorenzo Bianconi unsigned int txd4; 572160d3a9bSLorenzo Bianconi unsigned int txd5; 573160d3a9bSLorenzo Bianconi unsigned int txd6; 574160d3a9bSLorenzo Bianconi unsigned int txd7; 575160d3a9bSLorenzo Bianconi unsigned int txd8; 576160d3a9bSLorenzo Bianconi } __packed __aligned(4); 577160d3a9bSLorenzo Bianconi 578656e7052SJohn Crispin struct mtk_eth; 579656e7052SJohn Crispin struct mtk_mac; 580656e7052SJohn Crispin 581916a6ee8SLorenzo Bianconi struct mtk_xdp_stats { 582916a6ee8SLorenzo Bianconi u64 rx_xdp_redirect; 583916a6ee8SLorenzo Bianconi u64 rx_xdp_pass; 584916a6ee8SLorenzo Bianconi u64 rx_xdp_drop; 585916a6ee8SLorenzo Bianconi u64 rx_xdp_tx; 586916a6ee8SLorenzo Bianconi u64 rx_xdp_tx_errors; 587916a6ee8SLorenzo Bianconi u64 tx_xdp_xmit; 588916a6ee8SLorenzo Bianconi u64 tx_xdp_xmit_errors; 589916a6ee8SLorenzo Bianconi }; 590916a6ee8SLorenzo Bianconi 591656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 592656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 593656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 594656e7052SJohn Crispin * @syncp: the refcount 595656e7052SJohn Crispin * 596656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 597656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 598656e7052SJohn Crispin * counters and store them in this struct. 599656e7052SJohn Crispin */ 600656e7052SJohn Crispin struct mtk_hw_stats { 601656e7052SJohn Crispin u64 tx_bytes; 602656e7052SJohn Crispin u64 tx_packets; 603656e7052SJohn Crispin u64 tx_skip; 604656e7052SJohn Crispin u64 tx_collisions; 605656e7052SJohn Crispin u64 rx_bytes; 606656e7052SJohn Crispin u64 rx_packets; 607656e7052SJohn Crispin u64 rx_overflow; 608656e7052SJohn Crispin u64 rx_fcs_errors; 609656e7052SJohn Crispin u64 rx_short_errors; 610656e7052SJohn Crispin u64 rx_long_errors; 611656e7052SJohn Crispin u64 rx_checksum_errors; 612656e7052SJohn Crispin u64 rx_flow_control_packets; 613656e7052SJohn Crispin 614916a6ee8SLorenzo Bianconi struct mtk_xdp_stats xdp_stats; 615916a6ee8SLorenzo Bianconi 616656e7052SJohn Crispin spinlock_t stats_lock; 617656e7052SJohn Crispin u32 reg_offset; 618656e7052SJohn Crispin struct u64_stats_sync syncp; 619656e7052SJohn Crispin }; 620656e7052SJohn Crispin 621656e7052SJohn Crispin enum mtk_tx_flags { 622134d2152SSean Wang /* PDMA descriptor can point at 1-2 segments. This enum allows us to 623134d2152SSean Wang * track how memory was allocated so that it can be freed properly. 624134d2152SSean Wang */ 625656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 626656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 627134d2152SSean Wang 628134d2152SSean Wang /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 629134d2152SSean Wang * SKB out instead of looking up through hardware TX descriptor. 630134d2152SSean Wang */ 631134d2152SSean Wang MTK_TX_FLAGS_FPORT0 = 0x04, 632134d2152SSean Wang MTK_TX_FLAGS_FPORT1 = 0x08, 633656e7052SJohn Crispin }; 634656e7052SJohn Crispin 635549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the 636549e5495SSean Wang * clock in the order 637549e5495SSean Wang */ 638549e5495SSean Wang enum mtk_clks_map { 639549e5495SSean Wang MTK_CLK_ETHIF, 640d438e298SSean Wang MTK_CLK_SGMIITOP, 641549e5495SSean Wang MTK_CLK_ESW, 64242c03844SSean Wang MTK_CLK_GP0, 643549e5495SSean Wang MTK_CLK_GP1, 644549e5495SSean Wang MTK_CLK_GP2, 645d438e298SSean Wang MTK_CLK_FE, 646f430dea7SSean Wang MTK_CLK_TRGPLL, 64742c03844SSean Wang MTK_CLK_SGMII_TX_250M, 64842c03844SSean Wang MTK_CLK_SGMII_RX_250M, 64942c03844SSean Wang MTK_CLK_SGMII_CDR_REF, 65042c03844SSean Wang MTK_CLK_SGMII_CDR_FB, 651d438e298SSean Wang MTK_CLK_SGMII2_TX_250M, 652d438e298SSean Wang MTK_CLK_SGMII2_RX_250M, 653d438e298SSean Wang MTK_CLK_SGMII2_CDR_REF, 654d438e298SSean Wang MTK_CLK_SGMII2_CDR_FB, 65542c03844SSean Wang MTK_CLK_SGMII_CK, 65642c03844SSean Wang MTK_CLK_ETH2PLL, 657197c9e9bSLorenzo Bianconi MTK_CLK_WOCPU0, 658197c9e9bSLorenzo Bianconi MTK_CLK_WOCPU1, 659197c9e9bSLorenzo Bianconi MTK_CLK_NETSYS0, 660197c9e9bSLorenzo Bianconi MTK_CLK_NETSYS1, 661549e5495SSean Wang MTK_CLK_MAX 662549e5495SSean Wang }; 663549e5495SSean Wang 6642ec50f57SSean Wang #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 6652ec50f57SSean Wang BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 6662ec50f57SSean Wang BIT(MTK_CLK_TRGPLL)) 66742c03844SSean Wang #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 66842c03844SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 66942c03844SSean Wang BIT(MTK_CLK_GP2) | \ 67042c03844SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 67142c03844SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 67242c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 67342c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 67442c03844SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 67542c03844SSean Wang BIT(MTK_CLK_ETH2PLL)) 676889bcbdeSBjørn Mork #define MT7621_CLKS_BITMAP (0) 677296c9120SStefan Roese #define MT7628_CLKS_BITMAP (0) 678d438e298SSean Wang #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 679d438e298SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 680d438e298SSean Wang BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 681d438e298SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 682d438e298SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 683d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 684d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 685d438e298SSean Wang BIT(MTK_CLK_SGMII2_TX_250M) | \ 686d438e298SSean Wang BIT(MTK_CLK_SGMII2_RX_250M) | \ 687d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_REF) | \ 688d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_FB) | \ 689d438e298SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 690d438e298SSean Wang BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 691197c9e9bSLorenzo Bianconi #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ 692197c9e9bSLorenzo Bianconi BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ 693197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII_TX_250M) | \ 694197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII_RX_250M) | \ 695197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII_CDR_REF) | \ 696197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII_CDR_FB) | \ 697197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII2_TX_250M) | \ 698197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII2_RX_250M) | \ 699197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII2_CDR_REF) | \ 700197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII2_CDR_FB)) 701889bcbdeSBjørn Mork 7029ea4d311SSean Wang enum mtk_dev_state { 703dce6fa42SSean Wang MTK_HW_INIT, 704dce6fa42SSean Wang MTK_RESETTING 7059ea4d311SSean Wang }; 7069ea4d311SSean Wang 7075886d26fSLorenzo Bianconi enum mtk_tx_buf_type { 7085886d26fSLorenzo Bianconi MTK_TYPE_SKB, 7095886d26fSLorenzo Bianconi MTK_TYPE_XDP_TX, 7105886d26fSLorenzo Bianconi MTK_TYPE_XDP_NDO, 7115886d26fSLorenzo Bianconi }; 7125886d26fSLorenzo Bianconi 713656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 714656e7052SJohn Crispin * by the TX descriptor s 715656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 716656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 717656e7052SJohn Crispin * @dma_len0: The length of the first segment 718656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 719656e7052SJohn Crispin * @dma_len1: The length of the second segment 720656e7052SJohn Crispin */ 721656e7052SJohn Crispin struct mtk_tx_buf { 7225886d26fSLorenzo Bianconi enum mtk_tx_buf_type type; 7235886d26fSLorenzo Bianconi void *data; 7245886d26fSLorenzo Bianconi 725656e7052SJohn Crispin u32 flags; 726656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 727656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 728656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 729656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 730656e7052SJohn Crispin }; 731656e7052SJohn Crispin 732656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 733656e7052SJohn Crispin * @dma: The descriptor ring 734656e7052SJohn Crispin * @buf: The memory pointed at by the ring 735656e7052SJohn Crispin * @phys: The physical addr of tx_buf 736656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 737656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 7384e6bf609SFelix Fietkau * @last_free_ptr: Hardware pointer value of the last free descriptor 739656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 740656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 741656e7052SJohn Crispin * are present 742656e7052SJohn Crispin */ 743656e7052SJohn Crispin struct mtk_tx_ring { 7447173eca8SLorenzo Bianconi void *dma; 745656e7052SJohn Crispin struct mtk_tx_buf *buf; 746656e7052SJohn Crispin dma_addr_t phys; 747656e7052SJohn Crispin struct mtk_tx_dma *next_free; 748656e7052SJohn Crispin struct mtk_tx_dma *last_free; 7494e6bf609SFelix Fietkau u32 last_free_ptr; 750656e7052SJohn Crispin u16 thresh; 751656e7052SJohn Crispin atomic_t free_count; 752296c9120SStefan Roese int dma_size; 753296c9120SStefan Roese struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 754296c9120SStefan Roese dma_addr_t phys_pdma; 755296c9120SStefan Roese int cpu_idx; 756656e7052SJohn Crispin }; 757656e7052SJohn Crispin 758ee406810SNelson Chang /* PDMA rx ring mode */ 759ee406810SNelson Chang enum mtk_rx_flags { 760ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0, 761ee406810SNelson Chang MTK_RX_FLAGS_HWLRO, 7626427dc1dSJohn Crispin MTK_RX_FLAGS_QDMA, 763ee406810SNelson Chang }; 764ee406810SNelson Chang 765656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 766656e7052SJohn Crispin * @dma: The descriptor ring 767656e7052SJohn Crispin * @data: The memory pointed at by the ring 768656e7052SJohn Crispin * @phys: The physical addr of rx_buf 769656e7052SJohn Crispin * @frag_size: How big can each fragment be 770656e7052SJohn Crispin * @buf_size: The size of each packet buffer 771656e7052SJohn Crispin * @calc_idx: The current head of ring 772656e7052SJohn Crispin */ 773656e7052SJohn Crispin struct mtk_rx_ring { 7747173eca8SLorenzo Bianconi void *dma; 775656e7052SJohn Crispin u8 **data; 776656e7052SJohn Crispin dma_addr_t phys; 777656e7052SJohn Crispin u16 frag_size; 778656e7052SJohn Crispin u16 buf_size; 779ee406810SNelson Chang u16 dma_size; 780ee406810SNelson Chang bool calc_idx_update; 781656e7052SJohn Crispin u16 calc_idx; 782ee406810SNelson Chang u32 crx_idx_reg; 78323233e57SLorenzo Bianconi /* page_pool */ 78423233e57SLorenzo Bianconi struct page_pool *page_pool; 78523233e57SLorenzo Bianconi struct xdp_rxq_info xdp_q; 786656e7052SJohn Crispin }; 787656e7052SJohn Crispin 788e2c74694SRené van Dorst enum mkt_eth_capabilities { 789e2c74694SRené van Dorst MTK_RGMII_BIT = 0, 790e2c74694SRené van Dorst MTK_TRGMII_BIT, 791e2c74694SRené van Dorst MTK_SGMII_BIT, 792e2c74694SRené van Dorst MTK_ESW_BIT, 793e2c74694SRené van Dorst MTK_GEPHY_BIT, 794e2c74694SRené van Dorst MTK_MUX_BIT, 795e2c74694SRené van Dorst MTK_INFRA_BIT, 796e2c74694SRené van Dorst MTK_SHARED_SGMII_BIT, 797e2c74694SRené van Dorst MTK_HWLRO_BIT, 798e2c74694SRené van Dorst MTK_SHARED_INT_BIT, 799e2c74694SRené van Dorst MTK_TRGMII_MT7621_CLK_BIT, 800296c9120SStefan Roese MTK_QDMA_BIT, 801160d3a9bSLorenzo Bianconi MTK_NETSYS_V2_BIT, 802296c9120SStefan Roese MTK_SOC_MT7628_BIT, 803160d3a9bSLorenzo Bianconi MTK_RSTCTRL_PPE1_BIT, 8047093f9d8SSean Wang 805e2c74694SRené van Dorst /* MUX BITS*/ 806e2c74694SRené van Dorst MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 807e2c74694SRené van Dorst MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 808e2c74694SRené van Dorst MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 809e2c74694SRené van Dorst MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 810e2c74694SRené van Dorst MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 811e2c74694SRené van Dorst 812e2c74694SRené van Dorst /* PATH BITS */ 813e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_RGMII_BIT, 814e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_TRGMII_BIT, 815e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_SGMII_BIT, 816e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_RGMII_BIT, 817e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_SGMII_BIT, 818e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_GEPHY_BIT, 819e2c74694SRené van Dorst MTK_ETH_PATH_GDM1_ESW_BIT, 8207093f9d8SSean Wang }; 8217093f9d8SSean Wang 8227093f9d8SSean Wang /* Supported hardware group on SoCs */ 823e2c74694SRené van Dorst #define MTK_RGMII BIT(MTK_RGMII_BIT) 824e2c74694SRené van Dorst #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 825e2c74694SRené van Dorst #define MTK_SGMII BIT(MTK_SGMII_BIT) 826e2c74694SRené van Dorst #define MTK_ESW BIT(MTK_ESW_BIT) 827e2c74694SRené van Dorst #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 828e2c74694SRené van Dorst #define MTK_MUX BIT(MTK_MUX_BIT) 829e2c74694SRené van Dorst #define MTK_INFRA BIT(MTK_INFRA_BIT) 830e2c74694SRené van Dorst #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 831e2c74694SRené van Dorst #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 832e2c74694SRené van Dorst #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 833e2c74694SRené van Dorst #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 834296c9120SStefan Roese #define MTK_QDMA BIT(MTK_QDMA_BIT) 835160d3a9bSLorenzo Bianconi #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) 836296c9120SStefan Roese #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 837160d3a9bSLorenzo Bianconi #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) 838e2c74694SRené van Dorst 839e2c74694SRené van Dorst #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 840e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 841e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 842e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 843e2c74694SRené van Dorst #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 844e2c74694SRené van Dorst BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 845e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 846e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 847e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 848e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 8497093f9d8SSean Wang 8507093f9d8SSean Wang /* Supported path present on SoCs */ 851e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 852e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 853e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 854e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 855e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 856e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 857e2c74694SRené van Dorst #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 8587093f9d8SSean Wang 859e2c74694SRené van Dorst #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 860e2c74694SRené van Dorst #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 861e2c74694SRené van Dorst #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 862e2c74694SRené van Dorst #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 863e2c74694SRené van Dorst #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 864e2c74694SRené van Dorst #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 865e2c74694SRené van Dorst #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 8667093f9d8SSean Wang 8677093f9d8SSean Wang /* MUXes present on SoCs */ 8687093f9d8SSean Wang /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 869e2c74694SRené van Dorst #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 8707093f9d8SSean Wang 8717093f9d8SSean Wang /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 8727093f9d8SSean Wang #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 873e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 8747093f9d8SSean Wang 8757093f9d8SSean Wang /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 8767093f9d8SSean Wang #define MTK_MUX_U3_GMAC2_TO_QPHY \ 877e2c74694SRené van Dorst (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 8787093f9d8SSean Wang 8797093f9d8SSean Wang /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 8807093f9d8SSean Wang #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 881e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 8827093f9d8SSean Wang MTK_SHARED_SGMII) 8837093f9d8SSean Wang 8847093f9d8SSean Wang /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 8857093f9d8SSean Wang #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 886e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 8877093f9d8SSean Wang 8882ec50f57SSean Wang #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 8892ec50f57SSean Wang 8908efaa653SRené van Dorst #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 891296c9120SStefan Roese MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 892296c9120SStefan Roese MTK_TRGMII_MT7621_CLK | MTK_QDMA) 8938efaa653SRené van Dorst 8947093f9d8SSean Wang #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 8957093f9d8SSean Wang MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 8967093f9d8SSean Wang MTK_MUX_GDM1_TO_GMAC1_ESW | \ 897296c9120SStefan Roese MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 8987093f9d8SSean Wang 899296c9120SStefan Roese #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 900296c9120SStefan Roese MTK_QDMA) 901296c9120SStefan Roese 902296c9120SStefan Roese #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 9037093f9d8SSean Wang 9047093f9d8SSean Wang #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 9057093f9d8SSean Wang MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 9067093f9d8SSean Wang MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 9077093f9d8SSean Wang MTK_MUX_U3_GMAC2_TO_QPHY | \ 908296c9120SStefan Roese MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 9097093f9d8SSean Wang 910197c9e9bSLorenzo Bianconi #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 911197c9e9bSLorenzo Bianconi MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 912197c9e9bSLorenzo Bianconi MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) 913197c9e9bSLorenzo Bianconi 914731f3fd6SLorenzo Bianconi struct mtk_tx_dma_desc_info { 915731f3fd6SLorenzo Bianconi dma_addr_t addr; 916731f3fd6SLorenzo Bianconi u32 size; 917731f3fd6SLorenzo Bianconi u16 vlan_tci; 918160d3a9bSLorenzo Bianconi u16 qid; 919731f3fd6SLorenzo Bianconi u8 gso:1; 920731f3fd6SLorenzo Bianconi u8 csum:1; 921731f3fd6SLorenzo Bianconi u8 vlan:1; 922731f3fd6SLorenzo Bianconi u8 first:1; 923731f3fd6SLorenzo Bianconi u8 last:1; 924731f3fd6SLorenzo Bianconi }; 925731f3fd6SLorenzo Bianconi 9268cb42714SLorenzo Bianconi struct mtk_reg_map { 9278cb42714SLorenzo Bianconi u32 tx_irq_mask; 9288cb42714SLorenzo Bianconi u32 tx_irq_status; 9298cb42714SLorenzo Bianconi struct { 9308cb42714SLorenzo Bianconi u32 rx_ptr; /* rx base pointer */ 9318cb42714SLorenzo Bianconi u32 rx_cnt_cfg; /* rx max count configuration */ 9328cb42714SLorenzo Bianconi u32 pcrx_ptr; /* rx cpu pointer */ 9338cb42714SLorenzo Bianconi u32 glo_cfg; /* global configuration */ 9348cb42714SLorenzo Bianconi u32 rst_idx; /* reset index */ 9358cb42714SLorenzo Bianconi u32 delay_irq; /* delay interrupt */ 9368cb42714SLorenzo Bianconi u32 irq_status; /* interrupt status */ 9378cb42714SLorenzo Bianconi u32 irq_mask; /* interrupt mask */ 9388cb42714SLorenzo Bianconi u32 int_grp; 9398cb42714SLorenzo Bianconi } pdma; 9408cb42714SLorenzo Bianconi struct { 9418cb42714SLorenzo Bianconi u32 qtx_cfg; /* tx queue configuration */ 9428cb42714SLorenzo Bianconi u32 rx_ptr; /* rx base pointer */ 9438cb42714SLorenzo Bianconi u32 rx_cnt_cfg; /* rx max count configuration */ 9448cb42714SLorenzo Bianconi u32 qcrx_ptr; /* rx cpu pointer */ 9458cb42714SLorenzo Bianconi u32 glo_cfg; /* global configuration */ 9468cb42714SLorenzo Bianconi u32 rst_idx; /* reset index */ 9478cb42714SLorenzo Bianconi u32 delay_irq; /* delay interrupt */ 9488cb42714SLorenzo Bianconi u32 fc_th; /* flow control */ 9498cb42714SLorenzo Bianconi u32 int_grp; 9508cb42714SLorenzo Bianconi u32 hred; /* interrupt mask */ 9518cb42714SLorenzo Bianconi u32 ctx_ptr; /* tx acquire cpu pointer */ 9528cb42714SLorenzo Bianconi u32 dtx_ptr; /* tx acquire dma pointer */ 9538cb42714SLorenzo Bianconi u32 crx_ptr; /* tx release cpu pointer */ 9548cb42714SLorenzo Bianconi u32 drx_ptr; /* tx release dma pointer */ 9558cb42714SLorenzo Bianconi u32 fq_head; /* fq head pointer */ 9568cb42714SLorenzo Bianconi u32 fq_tail; /* fq tail pointer */ 9578cb42714SLorenzo Bianconi u32 fq_count; /* fq free page count */ 9588cb42714SLorenzo Bianconi u32 fq_blen; /* fq free page buffer length */ 9598cb42714SLorenzo Bianconi } qdma; 9608cb42714SLorenzo Bianconi u32 gdm1_cnt; 961329bce51SLorenzo Bianconi u32 gdma_to_ppe; 962329bce51SLorenzo Bianconi u32 ppe_base; 9630c1d3fb9SLorenzo Bianconi u32 wdma_base[2]; 9648cb42714SLorenzo Bianconi }; 9658cb42714SLorenzo Bianconi 96642c03844SSean Wang /* struct mtk_eth_data - This is the structure holding all differences 9672ec50f57SSean Wang * among various plaforms 9688cb42714SLorenzo Bianconi * @reg_map Soc register map. 9699ffee4a8SSean Wang * @ana_rgc3: The offset for register ANA_RGC3 related to 9709ffee4a8SSean Wang * sgmiisys syscon 9712ec50f57SSean Wang * @caps Flags shown the extra capability for the SoC 972296c9120SStefan Roese * @hw_features Flags shown HW features 9732ec50f57SSean Wang * @required_clks Flags shown the bitmap for required clocks on 9742ec50f57SSean Wang * the target SoC 975243dc5fbSSean Wang * @required_pctl A bool value to show whether the SoC requires 976243dc5fbSSean Wang * the extra setup for those pins used by GMAC. 977ba2fc48cSLorenzo Bianconi * @hash_offset Flow table hash offset. 9789d8cb4c0SLorenzo Bianconi * @foe_entry_size Foe table entry size. 979eb067347SLorenzo Bianconi * @txd_size Tx DMA descriptor size. 980670ff7daSLorenzo Bianconi * @rxd_size Rx DMA descriptor size. 981160d3a9bSLorenzo Bianconi * @rx_irq_done_mask Rx irq done register mask. 982160d3a9bSLorenzo Bianconi * @rx_dma_l4_valid Rx DMA valid register mask. 983160d3a9bSLorenzo Bianconi * @dma_max_len Max DMA tx/rx buffer length. 984160d3a9bSLorenzo Bianconi * @dma_len_offset Tx/Rx DMA length field offset. 9852ec50f57SSean Wang */ 9862ec50f57SSean Wang struct mtk_soc_data { 9878cb42714SLorenzo Bianconi const struct mtk_reg_map *reg_map; 9889ffee4a8SSean Wang u32 ana_rgc3; 9892ec50f57SSean Wang u32 caps; 9902ec50f57SSean Wang u32 required_clks; 991243dc5fbSSean Wang bool required_pctl; 992ba37b7caSFelix Fietkau u8 offload_version; 993ba2fc48cSLorenzo Bianconi u8 hash_offset; 9949d8cb4c0SLorenzo Bianconi u16 foe_entry_size; 995296c9120SStefan Roese netdev_features_t hw_features; 996eb067347SLorenzo Bianconi struct { 997eb067347SLorenzo Bianconi u32 txd_size; 998670ff7daSLorenzo Bianconi u32 rxd_size; 999160d3a9bSLorenzo Bianconi u32 rx_irq_done_mask; 1000160d3a9bSLorenzo Bianconi u32 rx_dma_l4_valid; 1001160d3a9bSLorenzo Bianconi u32 dma_max_len; 1002160d3a9bSLorenzo Bianconi u32 dma_len_offset; 1003eb067347SLorenzo Bianconi } txrx; 10042ec50f57SSean Wang }; 10052ec50f57SSean Wang 1006656e7052SJohn Crispin /* currently no SoC has more than 2 macs */ 1007656e7052SJohn Crispin #define MTK_MAX_DEVS 2 1008656e7052SJohn Crispin 1009901f3fbeSRussell King (Oracle) /* struct mtk_pcs - This structure holds each sgmii regmap and associated 1010901f3fbeSRussell King (Oracle) * data 10119ffee4a8SSean Wang * @regmap: The register map pointing at the range used to setup 10129ffee4a8SSean Wang * SGMII modes 10139ffee4a8SSean Wang * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 101414a44ab0SRussell King (Oracle) * @pcs: Phylink PCS structure 10159ffee4a8SSean Wang */ 1016901f3fbeSRussell King (Oracle) struct mtk_pcs { 1017901f3fbeSRussell King (Oracle) struct regmap *regmap; 10189ffee4a8SSean Wang u32 ana_rgc3; 101914a44ab0SRussell King (Oracle) struct phylink_pcs pcs; 10209ffee4a8SSean Wang }; 10219ffee4a8SSean Wang 1022901f3fbeSRussell King (Oracle) /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 1023901f3fbeSRussell King (Oracle) * characteristics 1024901f3fbeSRussell King (Oracle) * @pcs Array of individual PCS structures 1025901f3fbeSRussell King (Oracle) */ 1026901f3fbeSRussell King (Oracle) struct mtk_sgmii { 1027901f3fbeSRussell King (Oracle) struct mtk_pcs pcs[MTK_MAX_DEVS]; 1028901f3fbeSRussell King (Oracle) }; 1029901f3fbeSRussell King (Oracle) 1030656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 1031656e7052SJohn Crispin * of the driver 1032656e7052SJohn Crispin * @dev: The device pointer 1033d776a57eSFelix Fietkau * @dev: The device pointer used for dma mapping/alloc 1034656e7052SJohn Crispin * @base: The mapped register i/o base 1035656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 10365cce0322SJohn Crispin * @tx_irq__lock: Make sure that IRQ register operations are atomic 10375cce0322SJohn Crispin * @rx_irq__lock: Make sure that IRQ register operations are atomic 1038e9229ffdSFelix Fietkau * @dim_lock: Make sure that Net DIM operations are atomic 1039656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 1040656e7052SJohn Crispin * dummy for NAPI to work 1041656e7052SJohn Crispin * @netdev: The netdev instances 1042656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 1043656e7052SJohn Crispin * @irq: The IRQ that we are using 1044656e7052SJohn Crispin * @msg_enable: Ethtool msg level 1045656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 1046656e7052SJohn Crispin * MII modes 10477093f9d8SSean Wang * @infra: The register map pointing at the range used to setup 10487093f9d8SSean Wang * SGMII and GePHY path 1049656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 1050656e7052SJohn Crispin * GMAC port drive/slew values 1051656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 10520c07ce7fSJohn Crispin * @tx_ring: Pointer to the memory holding info about the TX ring 10530c07ce7fSJohn Crispin * @rx_ring: Pointer to the memory holding info about the RX ring 10546427dc1dSJohn Crispin * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 105580673029SJohn Crispin * @tx_napi: The TX NAPI struct 105680673029SJohn Crispin * @rx_napi: The RX NAPI struct 1057e9229ffdSFelix Fietkau * @rx_events: Net DIM RX event counter 1058e9229ffdSFelix Fietkau * @rx_packets: Net DIM RX packet counter 1059e9229ffdSFelix Fietkau * @rx_bytes: Net DIM RX byte counter 1060e9229ffdSFelix Fietkau * @rx_dim: Net DIM RX context 1061e9229ffdSFelix Fietkau * @tx_events: Net DIM TX event counter 1062e9229ffdSFelix Fietkau * @tx_packets: Net DIM TX packet counter 1063e9229ffdSFelix Fietkau * @tx_bytes: Net DIM TX byte counter 1064e9229ffdSFelix Fietkau * @tx_dim: Net DIM TX context 1065656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1066605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 1067656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 1068549e5495SSean Wang * @clks: clock array for all clocks required 1069656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 10707c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 107142c03844SSean Wang * @state: Initialization and runtime state of the device 10722ec50f57SSean Wang * @soc: Holding specific data among vaious SoCs 1073656e7052SJohn Crispin */ 1074656e7052SJohn Crispin 1075656e7052SJohn Crispin struct mtk_eth { 1076656e7052SJohn Crispin struct device *dev; 1077d776a57eSFelix Fietkau struct device *dma_dev; 1078656e7052SJohn Crispin void __iomem *base; 1079656e7052SJohn Crispin spinlock_t page_lock; 10805cce0322SJohn Crispin spinlock_t tx_irq_lock; 10815cce0322SJohn Crispin spinlock_t rx_irq_lock; 1082656e7052SJohn Crispin struct net_device dummy_dev; 1083656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 1084656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 108580673029SJohn Crispin int irq[3]; 1086656e7052SJohn Crispin u32 msg_enable; 1087656e7052SJohn Crispin unsigned long sysclk; 1088656e7052SJohn Crispin struct regmap *ethsys; 10897093f9d8SSean Wang struct regmap *infra; 10909ffee4a8SSean Wang struct mtk_sgmii *sgmii; 1091656e7052SJohn Crispin struct regmap *pctl; 1092ee406810SNelson Chang bool hwlro; 1093c6d4e63eSElena Reshetova refcount_t dma_refcnt; 1094656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 1095ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 10966427dc1dSJohn Crispin struct mtk_rx_ring rx_ring_qdma; 109780673029SJohn Crispin struct napi_struct tx_napi; 1098656e7052SJohn Crispin struct napi_struct rx_napi; 10994d642690SLorenzo Bianconi void *scratch_ring; 1100605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 1101656e7052SJohn Crispin void *scratch_head; 1102549e5495SSean Wang struct clk *clks[MTK_CLK_MAX]; 1103549e5495SSean Wang 1104656e7052SJohn Crispin struct mii_bus *mii_bus; 11057c78b4adSJohn Crispin struct work_struct pending_work; 11069ea4d311SSean Wang unsigned long state; 11072ec50f57SSean Wang 11082ec50f57SSean Wang const struct mtk_soc_data *soc; 1109296c9120SStefan Roese 1110e9229ffdSFelix Fietkau spinlock_t dim_lock; 1111e9229ffdSFelix Fietkau 1112e9229ffdSFelix Fietkau u32 rx_events; 1113e9229ffdSFelix Fietkau u32 rx_packets; 1114e9229ffdSFelix Fietkau u32 rx_bytes; 1115e9229ffdSFelix Fietkau struct dim rx_dim; 1116e9229ffdSFelix Fietkau 1117e9229ffdSFelix Fietkau u32 tx_events; 1118e9229ffdSFelix Fietkau u32 tx_packets; 1119e9229ffdSFelix Fietkau u32 tx_bytes; 1120e9229ffdSFelix Fietkau struct dim tx_dim; 1121e9229ffdSFelix Fietkau 1122296c9120SStefan Roese int ip_align; 1123ba37b7caSFelix Fietkau 11244ff1a3fcSLorenzo Bianconi struct mtk_ppe *ppe[2]; 1125502e84e2SFelix Fietkau struct rhashtable flow_table; 11267c26c20dSLorenzo Bianconi 11277c26c20dSLorenzo Bianconi struct bpf_prog __rcu *prog; 1128656e7052SJohn Crispin }; 1129656e7052SJohn Crispin 1130656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 1131656e7052SJohn Crispin * SoC 1132656e7052SJohn Crispin * @id: The number of the MAC 1133b8fc9f30SRené van Dorst * @interface: Interface mode kept for detecting change in hw settings 1134656e7052SJohn Crispin * @of_node: Our devicetree node 1135656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 1136656e7052SJohn Crispin * @hw_stats: Packet statistics counter 1137656e7052SJohn Crispin */ 1138656e7052SJohn Crispin struct mtk_mac { 1139656e7052SJohn Crispin int id; 1140b8fc9f30SRené van Dorst phy_interface_t interface; 1141b8fc9f30SRené van Dorst int speed; 1142656e7052SJohn Crispin struct device_node *of_node; 1143b8fc9f30SRené van Dorst struct phylink *phylink; 1144b8fc9f30SRené van Dorst struct phylink_config phylink_config; 1145656e7052SJohn Crispin struct mtk_eth *hw; 1146656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 1147ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1148ee406810SNelson Chang int hwlro_ip_cnt; 114921089867SRussell King (Oracle) unsigned int syscfg0; 1150656e7052SJohn Crispin }; 1151656e7052SJohn Crispin 1152656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1153656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 1154656e7052SJohn Crispin 11559d8cb4c0SLorenzo Bianconi static inline struct mtk_foe_entry * 11569d8cb4c0SLorenzo Bianconi mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 11579d8cb4c0SLorenzo Bianconi { 11589d8cb4c0SLorenzo Bianconi const struct mtk_soc_data *soc = ppe->eth->soc; 11599d8cb4c0SLorenzo Bianconi 11609d8cb4c0SLorenzo Bianconi return ppe->foe_table + hash * soc->foe_entry_size; 11619d8cb4c0SLorenzo Bianconi } 11629d8cb4c0SLorenzo Bianconi 116303a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 116403a3180eSLorenzo Bianconi { 116503a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 116603a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_TIMESTAMP_V2; 116703a3180eSLorenzo Bianconi 116803a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_TIMESTAMP; 116903a3180eSLorenzo Bianconi } 117003a3180eSLorenzo Bianconi 117103a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 117203a3180eSLorenzo Bianconi { 117303a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 117403a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_PPPOE_V2; 117503a3180eSLorenzo Bianconi 117603a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_PPPOE; 117703a3180eSLorenzo Bianconi } 117803a3180eSLorenzo Bianconi 117903a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 118003a3180eSLorenzo Bianconi { 118103a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 118203a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_TAG_V2; 118303a3180eSLorenzo Bianconi 118403a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_TAG; 118503a3180eSLorenzo Bianconi } 118603a3180eSLorenzo Bianconi 118703a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 118803a3180eSLorenzo Bianconi { 118903a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 119003a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; 119103a3180eSLorenzo Bianconi 119203a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_LAYER; 119303a3180eSLorenzo Bianconi } 119403a3180eSLorenzo Bianconi 119503a3180eSLorenzo Bianconi static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 119603a3180eSLorenzo Bianconi { 119703a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 119803a3180eSLorenzo Bianconi return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 119903a3180eSLorenzo Bianconi 120003a3180eSLorenzo Bianconi return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 120103a3180eSLorenzo Bianconi } 120203a3180eSLorenzo Bianconi 120303a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 120403a3180eSLorenzo Bianconi { 120503a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 120603a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 120703a3180eSLorenzo Bianconi 120803a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 120903a3180eSLorenzo Bianconi } 121003a3180eSLorenzo Bianconi 121103a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 121203a3180eSLorenzo Bianconi { 121303a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 121403a3180eSLorenzo Bianconi return MTK_FOE_IB1_PACKET_TYPE_V2; 121503a3180eSLorenzo Bianconi 121603a3180eSLorenzo Bianconi return MTK_FOE_IB1_PACKET_TYPE; 121703a3180eSLorenzo Bianconi } 121803a3180eSLorenzo Bianconi 121903a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 122003a3180eSLorenzo Bianconi { 122103a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 122203a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); 122303a3180eSLorenzo Bianconi 122403a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); 122503a3180eSLorenzo Bianconi } 122603a3180eSLorenzo Bianconi 122703a3180eSLorenzo Bianconi static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) 122803a3180eSLorenzo Bianconi { 122903a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 123003a3180eSLorenzo Bianconi return MTK_FOE_IB2_MULTICAST_V2; 123103a3180eSLorenzo Bianconi 123203a3180eSLorenzo Bianconi return MTK_FOE_IB2_MULTICAST; 123303a3180eSLorenzo Bianconi } 123403a3180eSLorenzo Bianconi 1235656e7052SJohn Crispin /* read the hardware status register */ 1236656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 1237656e7052SJohn Crispin 1238656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1239656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1240656e7052SJohn Crispin 124114a44ab0SRussell King (Oracle) struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id); 12429ffee4a8SSean Wang int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 12439ffee4a8SSean Wang u32 ana_rgc3); 12447e538372SRené van Dorst 12457e538372SRené van Dorst int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 12467e538372SRené van Dorst int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 12477e538372SRené van Dorst int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 12489ffee4a8SSean Wang 1249502e84e2SFelix Fietkau int mtk_eth_offload_init(struct mtk_eth *eth); 1250502e84e2SFelix Fietkau int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1251502e84e2SFelix Fietkau void *type_data); 1252d776a57eSFelix Fietkau void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1253502e84e2SFelix Fietkau 1254502e84e2SFelix Fietkau 1255656e7052SJohn Crispin #endif /* MTK_ETH_H */ 1256