1656e7052SJohn Crispin /* This program is free software; you can redistribute it and/or modify 2656e7052SJohn Crispin * it under the terms of the GNU General Public License as published by 3656e7052SJohn Crispin * the Free Software Foundation; version 2 of the License 4656e7052SJohn Crispin * 5656e7052SJohn Crispin * This program is distributed in the hope that it will be useful, 6656e7052SJohn Crispin * but WITHOUT ANY WARRANTY; without even the implied warranty of 7656e7052SJohn Crispin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8656e7052SJohn Crispin * GNU General Public License for more details. 9656e7052SJohn Crispin * 10656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13656e7052SJohn Crispin */ 14656e7052SJohn Crispin 15656e7052SJohn Crispin #ifndef MTK_ETH_H 16656e7052SJohn Crispin #define MTK_ETH_H 17656e7052SJohn Crispin 18656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 19656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 20656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 21656e7052SJohn Crispin #define MTK_DMA_SIZE 256 22656e7052SJohn Crispin #define MTK_NAPI_WEIGHT 64 23656e7052SJohn Crispin #define MTK_MAC_COUNT 2 24656e7052SJohn Crispin #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 25656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 26656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 27656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 28656e7052SJohn Crispin NETIF_MSG_PROBE | \ 29656e7052SJohn Crispin NETIF_MSG_LINK | \ 30656e7052SJohn Crispin NETIF_MSG_TIMER | \ 31656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 32656e7052SJohn Crispin NETIF_MSG_IFUP | \ 33656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 34656e7052SJohn Crispin NETIF_MSG_TX_ERR) 35656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 36656e7052SJohn Crispin NETIF_F_RXCSUM | \ 37656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 38656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_RX | \ 39656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 40656e7052SJohn Crispin NETIF_F_TSO6 | \ 41656e7052SJohn Crispin NETIF_F_IPV6_CSUM) 42ee406810SNelson Chang #define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 43ee406810SNelson Chang 44ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4 45ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8 46ee406810SNelson Chang 47ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 48ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2 49ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 50ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 51ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 52ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 53ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64 54ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000 55ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000 56ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 57656e7052SJohn Crispin 58656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 59656e7052SJohn Crispin #define MTK_RST_GL 0x04 60656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 61656e7052SJohn Crispin 62656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 63656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 64656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 65656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 66656e7052SJohn Crispin 67ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */ 68ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 69ee406810SNelson Chang 70656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 71656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 72656e7052SJohn Crispin 73656e7052SJohn Crispin /* CDMP Exgress Control Register */ 74656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 75656e7052SJohn Crispin 76656e7052SJohn Crispin /* GDM Exgress Control Register */ 77656e7052SJohn Crispin #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 78656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 79656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 80656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 81656e7052SJohn Crispin 82656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 83656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 84656e7052SJohn Crispin 85656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 86656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 87656e7052SJohn Crispin 88bacfd110SNelson Chang /* PDMA RX Base Pointer Register */ 89bacfd110SNelson Chang #define MTK_PRX_BASE_PTR0 0x900 90ee406810SNelson Chang #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 91bacfd110SNelson Chang 92bacfd110SNelson Chang /* PDMA RX Maximum Count Register */ 93bacfd110SNelson Chang #define MTK_PRX_MAX_CNT0 0x904 94ee406810SNelson Chang #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 95bacfd110SNelson Chang 96bacfd110SNelson Chang /* PDMA RX CPU Pointer Register */ 97bacfd110SNelson Chang #define MTK_PRX_CRX_IDX0 0x908 98ee406810SNelson Chang #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 99ee406810SNelson Chang 100ee406810SNelson Chang /* PDMA HW LRO Control Registers */ 101ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980 102ee406810SNelson Chang #define MTK_LRO_EN BIT(0) 103ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7) 104ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 105ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 106ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 107ee406810SNelson Chang 108ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984 109ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988 110ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c 111ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15) 112ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 113bacfd110SNelson Chang 114bacfd110SNelson Chang /* PDMA Global Configuration Register */ 115bacfd110SNelson Chang #define MTK_PDMA_GLO_CFG 0xa04 116bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10) 117bacfd110SNelson Chang 118bacfd110SNelson Chang /* PDMA Reset Index Register */ 119bacfd110SNelson Chang #define MTK_PDMA_RST_IDX 0xa08 120bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16) 121ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 122bacfd110SNelson Chang 123bacfd110SNelson Chang /* PDMA Delay Interrupt Register */ 124bacfd110SNelson Chang #define MTK_PDMA_DELAY_INT 0xa0c 125bacfd110SNelson Chang 126bacfd110SNelson Chang /* PDMA Interrupt Status Register */ 127bacfd110SNelson Chang #define MTK_PDMA_INT_STATUS 0xa20 128bacfd110SNelson Chang 129bacfd110SNelson Chang /* PDMA Interrupt Mask Register */ 130bacfd110SNelson Chang #define MTK_PDMA_INT_MASK 0xa28 131bacfd110SNelson Chang 132ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */ 133ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 134ee406810SNelson Chang 13580673029SJohn Crispin /* PDMA Interrupt grouping registers */ 13680673029SJohn Crispin #define MTK_PDMA_INT_GRP1 0xa50 13780673029SJohn Crispin #define MTK_PDMA_INT_GRP2 0xa54 13880673029SJohn Crispin 139ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */ 140ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 141ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 142ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9) 143ee406810SNelson Chang 144ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */ 145ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 146ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 147ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 148ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 149ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 150ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 151ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 152ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 153ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 154ee406810SNelson Chang #define MTK_RING_VLD BIT(8) 155ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 156ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 157ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 158ee406810SNelson Chang 159656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 160656e7052SJohn Crispin #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 161656e7052SJohn Crispin #define QDMA_RES_THRES 4 162656e7052SJohn Crispin 163656e7052SJohn Crispin /* QDMA TX Queue Scheduler Registers */ 164656e7052SJohn Crispin #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 165656e7052SJohn Crispin 166656e7052SJohn Crispin /* QDMA RX Base Pointer Register */ 167656e7052SJohn Crispin #define MTK_QRX_BASE_PTR0 0x1900 168656e7052SJohn Crispin 169656e7052SJohn Crispin /* QDMA RX Maximum Count Register */ 170656e7052SJohn Crispin #define MTK_QRX_MAX_CNT0 0x1904 171656e7052SJohn Crispin 172656e7052SJohn Crispin /* QDMA RX CPU Pointer Register */ 173656e7052SJohn Crispin #define MTK_QRX_CRX_IDX0 0x1908 174656e7052SJohn Crispin 175656e7052SJohn Crispin /* QDMA RX DMA Pointer Register */ 176656e7052SJohn Crispin #define MTK_QRX_DRX_IDX0 0x190C 177656e7052SJohn Crispin 178656e7052SJohn Crispin /* QDMA Global Configuration Register */ 179656e7052SJohn Crispin #define MTK_QDMA_GLO_CFG 0x1A04 180656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 181656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 1826675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 183656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 184656e7052SJohn Crispin #define MTK_DMA_SIZE_16DWORDS (2 << 4) 185656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 186656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 187656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 188656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 189656e7052SJohn Crispin #define MTK_DMA_BUSY_TIMEOUT HZ 190656e7052SJohn Crispin 191656e7052SJohn Crispin /* QDMA Reset Index Register */ 192656e7052SJohn Crispin #define MTK_QDMA_RST_IDX 0x1A08 193656e7052SJohn Crispin 194656e7052SJohn Crispin /* QDMA Delay Interrupt Register */ 195656e7052SJohn Crispin #define MTK_QDMA_DELAY_INT 0x1A0C 196656e7052SJohn Crispin 197656e7052SJohn Crispin /* QDMA Flow Control Register */ 198656e7052SJohn Crispin #define MTK_QDMA_FC_THRES 0x1A10 199656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 200656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 201656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 202656e7052SJohn Crispin 203656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 204656e7052SJohn Crispin #define MTK_QMTK_INT_STATUS 0x1A18 205bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19) 206bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18) 207656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 208656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 209656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 210656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 211656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 212656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 213bacfd110SNelson Chang #define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1 | \ 214bacfd110SNelson Chang MTK_RX_DONE_INT2 | MTK_RX_DONE_INT3) 215656e7052SJohn Crispin #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 216656e7052SJohn Crispin MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 217656e7052SJohn Crispin 21880673029SJohn Crispin /* QDMA Interrupt grouping registers */ 21980673029SJohn Crispin #define MTK_QDMA_INT_GRP1 0x1a20 22080673029SJohn Crispin #define MTK_QDMA_INT_GRP2 0x1a24 22180673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0) 22280673029SJohn Crispin 223656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 224656e7052SJohn Crispin #define MTK_QDMA_INT_MASK 0x1A1C 225656e7052SJohn Crispin 226656e7052SJohn Crispin /* QDMA Interrupt Mask Register */ 227656e7052SJohn Crispin #define MTK_QDMA_HRED2 0x1A44 228656e7052SJohn Crispin 229656e7052SJohn Crispin /* QDMA TX Forward CPU Pointer Register */ 230656e7052SJohn Crispin #define MTK_QTX_CTX_PTR 0x1B00 231656e7052SJohn Crispin 232656e7052SJohn Crispin /* QDMA TX Forward DMA Pointer Register */ 233656e7052SJohn Crispin #define MTK_QTX_DTX_PTR 0x1B04 234656e7052SJohn Crispin 235656e7052SJohn Crispin /* QDMA TX Release CPU Pointer Register */ 236656e7052SJohn Crispin #define MTK_QTX_CRX_PTR 0x1B10 237656e7052SJohn Crispin 238656e7052SJohn Crispin /* QDMA TX Release DMA Pointer Register */ 239656e7052SJohn Crispin #define MTK_QTX_DRX_PTR 0x1B14 240656e7052SJohn Crispin 241656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 242656e7052SJohn Crispin #define MTK_QDMA_FQ_HEAD 0x1B20 243656e7052SJohn Crispin 244656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 245656e7052SJohn Crispin #define MTK_QDMA_FQ_TAIL 0x1B24 246656e7052SJohn Crispin 247656e7052SJohn Crispin /* QDMA FQ Free Page Counter Register */ 248656e7052SJohn Crispin #define MTK_QDMA_FQ_CNT 0x1B28 249656e7052SJohn Crispin 250656e7052SJohn Crispin /* QDMA FQ Free Page Buffer Length Register */ 251656e7052SJohn Crispin #define MTK_QDMA_FQ_BLEN 0x1B2C 252656e7052SJohn Crispin 253656e7052SJohn Crispin /* GMA1 Received Good Byte Count Register */ 254656e7052SJohn Crispin #define MTK_GDM1_TX_GBCNT 0x2400 255656e7052SJohn Crispin #define MTK_STAT_OFFSET 0x40 256656e7052SJohn Crispin 257656e7052SJohn Crispin /* QDMA descriptor txd4 */ 258656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 259656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 260656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 261656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 262656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 263656e7052SJohn Crispin 264656e7052SJohn Crispin /* QDMA descriptor txd3 */ 265656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 266656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 267656e7052SJohn Crispin #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 268656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 269656e7052SJohn Crispin #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 270656e7052SJohn Crispin 271656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 272656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 273656e7052SJohn Crispin #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 274656e7052SJohn Crispin #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 275656e7052SJohn Crispin 276656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 277656e7052SJohn Crispin #define RX_DMA_VID(_x) ((_x) & 0xfff) 278656e7052SJohn Crispin 279656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 280656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 281656e7052SJohn Crispin #define RX_DMA_FPORT_SHIFT 19 282656e7052SJohn Crispin #define RX_DMA_FPORT_MASK 0x7 283656e7052SJohn Crispin 284656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 285656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 286656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 287656e7052SJohn Crispin #define PHY_IAC_READ BIT(19) 288656e7052SJohn Crispin #define PHY_IAC_WRITE BIT(18) 289656e7052SJohn Crispin #define PHY_IAC_START BIT(16) 290656e7052SJohn Crispin #define PHY_IAC_ADDR_SHIFT 20 291656e7052SJohn Crispin #define PHY_IAC_REG_SHIFT 25 292656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 293656e7052SJohn Crispin 294656e7052SJohn Crispin /* Mac control registers */ 295656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 296656e7052SJohn Crispin #define MAC_MCR_MAX_RX_1536 BIT(24) 297656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 298656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 299656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 300656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 301656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 302656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 303656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 304656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 305656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 306656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 307656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 308656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 309656e7052SJohn Crispin #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ 310656e7052SJohn Crispin MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ 311656e7052SJohn Crispin MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ 312656e7052SJohn Crispin MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ 313656e7052SJohn Crispin MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ 314656e7052SJohn Crispin MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) 315656e7052SJohn Crispin 316f430dea7SSean Wang /* TRGMII RXC control register */ 317f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300 318f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 319f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 320f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 321f430dea7SSean Wang #define RXC_DQSISEL BIT(30) 322f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 323f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 324f430dea7SSean Wang 325f430dea7SSean Wang /* TRGMII RXC control register */ 326f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340 327f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 328f430dea7SSean Wang #define TXC_INV BIT(30) 329f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 330f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 331f430dea7SSean Wang 332f430dea7SSean Wang /* TRGMII Interface mode register */ 333f430dea7SSean Wang #define INTF_MODE 0x10390 334f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0) 335f430dea7SSean Wang #define TRGMII_MODE BIT(1) 336f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2) 337f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 338f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0 339f430dea7SSean Wang 340656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 341656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 342656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 343656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 344656e7052SJohn Crispin 345b95b6d99SNelson Chang /* ethernet subsystem chip id register */ 346b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0 347b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4 348983e1a6cSNelson Chang #define MT7623_ETH 7623 349b95b6d99SNelson Chang 350656e7052SJohn Crispin /* ethernet subsystem config register */ 351656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 352656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 353656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 354656e7052SJohn Crispin 355f430dea7SSean Wang /* ethernet subsystem clock register */ 356f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c 357f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 358f430dea7SSean Wang 3592a8307aaSSean Wang /* ethernet reset control register */ 3602a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34 3612a8307aaSSean Wang #define RSTCTRL_FE BIT(6) 3622a8307aaSSean Wang #define RSTCTRL_PPE BIT(31) 3632a8307aaSSean Wang 364656e7052SJohn Crispin struct mtk_rx_dma { 365656e7052SJohn Crispin unsigned int rxd1; 366656e7052SJohn Crispin unsigned int rxd2; 367656e7052SJohn Crispin unsigned int rxd3; 368656e7052SJohn Crispin unsigned int rxd4; 369656e7052SJohn Crispin } __packed __aligned(4); 370656e7052SJohn Crispin 371656e7052SJohn Crispin struct mtk_tx_dma { 372656e7052SJohn Crispin unsigned int txd1; 373656e7052SJohn Crispin unsigned int txd2; 374656e7052SJohn Crispin unsigned int txd3; 375656e7052SJohn Crispin unsigned int txd4; 376656e7052SJohn Crispin } __packed __aligned(4); 377656e7052SJohn Crispin 378656e7052SJohn Crispin struct mtk_eth; 379656e7052SJohn Crispin struct mtk_mac; 380656e7052SJohn Crispin 381656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 382656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 383656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 384656e7052SJohn Crispin * @syncp: the refcount 385656e7052SJohn Crispin * 386656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 387656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 388656e7052SJohn Crispin * counters and store them in this struct. 389656e7052SJohn Crispin */ 390656e7052SJohn Crispin struct mtk_hw_stats { 391656e7052SJohn Crispin u64 tx_bytes; 392656e7052SJohn Crispin u64 tx_packets; 393656e7052SJohn Crispin u64 tx_skip; 394656e7052SJohn Crispin u64 tx_collisions; 395656e7052SJohn Crispin u64 rx_bytes; 396656e7052SJohn Crispin u64 rx_packets; 397656e7052SJohn Crispin u64 rx_overflow; 398656e7052SJohn Crispin u64 rx_fcs_errors; 399656e7052SJohn Crispin u64 rx_short_errors; 400656e7052SJohn Crispin u64 rx_long_errors; 401656e7052SJohn Crispin u64 rx_checksum_errors; 402656e7052SJohn Crispin u64 rx_flow_control_packets; 403656e7052SJohn Crispin 404656e7052SJohn Crispin spinlock_t stats_lock; 405656e7052SJohn Crispin u32 reg_offset; 406656e7052SJohn Crispin struct u64_stats_sync syncp; 407656e7052SJohn Crispin }; 408656e7052SJohn Crispin 409656e7052SJohn Crispin /* PDMA descriptor can point at 1-2 segments. This enum allows us to track how 410656e7052SJohn Crispin * memory was allocated so that it can be freed properly 411656e7052SJohn Crispin */ 412656e7052SJohn Crispin enum mtk_tx_flags { 413656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 414656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 415656e7052SJohn Crispin }; 416656e7052SJohn Crispin 417549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the 418549e5495SSean Wang * clock in the order 419549e5495SSean Wang */ 420549e5495SSean Wang enum mtk_clks_map { 421549e5495SSean Wang MTK_CLK_ETHIF, 422549e5495SSean Wang MTK_CLK_ESW, 423549e5495SSean Wang MTK_CLK_GP1, 424549e5495SSean Wang MTK_CLK_GP2, 425f430dea7SSean Wang MTK_CLK_TRGPLL, 426549e5495SSean Wang MTK_CLK_MAX 427549e5495SSean Wang }; 428549e5495SSean Wang 4299ea4d311SSean Wang enum mtk_dev_state { 430dce6fa42SSean Wang MTK_HW_INIT, 431dce6fa42SSean Wang MTK_RESETTING 4329ea4d311SSean Wang }; 4339ea4d311SSean Wang 434656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 435656e7052SJohn Crispin * by the TX descriptor s 436656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 437656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 438656e7052SJohn Crispin * @dma_len0: The length of the first segment 439656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 440656e7052SJohn Crispin * @dma_len1: The length of the second segment 441656e7052SJohn Crispin */ 442656e7052SJohn Crispin struct mtk_tx_buf { 443656e7052SJohn Crispin struct sk_buff *skb; 444656e7052SJohn Crispin u32 flags; 445656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 446656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 447656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 448656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 449656e7052SJohn Crispin }; 450656e7052SJohn Crispin 451656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 452656e7052SJohn Crispin * @dma: The descriptor ring 453656e7052SJohn Crispin * @buf: The memory pointed at by the ring 454656e7052SJohn Crispin * @phys: The physical addr of tx_buf 455656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 456656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 457656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 458656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 459656e7052SJohn Crispin * are present 460656e7052SJohn Crispin */ 461656e7052SJohn Crispin struct mtk_tx_ring { 462656e7052SJohn Crispin struct mtk_tx_dma *dma; 463656e7052SJohn Crispin struct mtk_tx_buf *buf; 464656e7052SJohn Crispin dma_addr_t phys; 465656e7052SJohn Crispin struct mtk_tx_dma *next_free; 466656e7052SJohn Crispin struct mtk_tx_dma *last_free; 467656e7052SJohn Crispin u16 thresh; 468656e7052SJohn Crispin atomic_t free_count; 469656e7052SJohn Crispin }; 470656e7052SJohn Crispin 471ee406810SNelson Chang /* PDMA rx ring mode */ 472ee406810SNelson Chang enum mtk_rx_flags { 473ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0, 474ee406810SNelson Chang MTK_RX_FLAGS_HWLRO, 475ee406810SNelson Chang }; 476ee406810SNelson Chang 477656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 478656e7052SJohn Crispin * @dma: The descriptor ring 479656e7052SJohn Crispin * @data: The memory pointed at by the ring 480656e7052SJohn Crispin * @phys: The physical addr of rx_buf 481656e7052SJohn Crispin * @frag_size: How big can each fragment be 482656e7052SJohn Crispin * @buf_size: The size of each packet buffer 483656e7052SJohn Crispin * @calc_idx: The current head of ring 484656e7052SJohn Crispin */ 485656e7052SJohn Crispin struct mtk_rx_ring { 486656e7052SJohn Crispin struct mtk_rx_dma *dma; 487656e7052SJohn Crispin u8 **data; 488656e7052SJohn Crispin dma_addr_t phys; 489656e7052SJohn Crispin u16 frag_size; 490656e7052SJohn Crispin u16 buf_size; 491ee406810SNelson Chang u16 dma_size; 492ee406810SNelson Chang bool calc_idx_update; 493656e7052SJohn Crispin u16 calc_idx; 494ee406810SNelson Chang u32 crx_idx_reg; 495656e7052SJohn Crispin }; 496656e7052SJohn Crispin 497656e7052SJohn Crispin /* currently no SoC has more than 2 macs */ 498656e7052SJohn Crispin #define MTK_MAX_DEVS 2 499656e7052SJohn Crispin 500656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 501656e7052SJohn Crispin * of the driver 502656e7052SJohn Crispin * @dev: The device pointer 503656e7052SJohn Crispin * @base: The mapped register i/o base 504656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 505656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 506656e7052SJohn Crispin * dummy for NAPI to work 507656e7052SJohn Crispin * @netdev: The netdev instances 508656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 509656e7052SJohn Crispin * @irq: The IRQ that we are using 510656e7052SJohn Crispin * @msg_enable: Ethtool msg level 511656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 512656e7052SJohn Crispin * MII modes 513656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 514656e7052SJohn Crispin * GMAC port drive/slew values 515656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 516656e7052SJohn Crispin * @tx_ring: Pointer to the memore holding info about the TX ring 517656e7052SJohn Crispin * @rx_ring: Pointer to the memore holding info about the RX ring 51880673029SJohn Crispin * @tx_napi: The TX NAPI struct 51980673029SJohn Crispin * @rx_napi: The RX NAPI struct 520656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 521605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 522656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 523549e5495SSean Wang * @clks: clock array for all clocks required 524656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 5257c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 5269ea4d311SSean Wang * @state Initialization and runtime state of the device. 527656e7052SJohn Crispin */ 528656e7052SJohn Crispin 529656e7052SJohn Crispin struct mtk_eth { 530656e7052SJohn Crispin struct device *dev; 531656e7052SJohn Crispin void __iomem *base; 532656e7052SJohn Crispin spinlock_t page_lock; 5337bc9ccecSJohn Crispin spinlock_t irq_lock; 534656e7052SJohn Crispin struct net_device dummy_dev; 535656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 536656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 53780673029SJohn Crispin int irq[3]; 538656e7052SJohn Crispin u32 msg_enable; 539656e7052SJohn Crispin unsigned long sysclk; 540656e7052SJohn Crispin struct regmap *ethsys; 541656e7052SJohn Crispin struct regmap *pctl; 542b95b6d99SNelson Chang u32 chip_id; 543ee406810SNelson Chang bool hwlro; 544656e7052SJohn Crispin atomic_t dma_refcnt; 545656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 546ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 54780673029SJohn Crispin struct napi_struct tx_napi; 548656e7052SJohn Crispin struct napi_struct rx_napi; 549656e7052SJohn Crispin struct mtk_tx_dma *scratch_ring; 550605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 551656e7052SJohn Crispin void *scratch_head; 552549e5495SSean Wang struct clk *clks[MTK_CLK_MAX]; 553549e5495SSean Wang 554656e7052SJohn Crispin struct mii_bus *mii_bus; 5557c78b4adSJohn Crispin struct work_struct pending_work; 5569ea4d311SSean Wang unsigned long state; 557656e7052SJohn Crispin }; 558656e7052SJohn Crispin 559656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 560656e7052SJohn Crispin * SoC 561656e7052SJohn Crispin * @id: The number of the MAC 5629ea4d311SSean Wang * @ge_mode: Interface mode kept for setup restoring 563656e7052SJohn Crispin * @of_node: Our devicetree node 564656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 565656e7052SJohn Crispin * @hw_stats: Packet statistics counter 566572de608SSean Wang * @trgmii Indicate if the MAC uses TRGMII connected to internal 567572de608SSean Wang switch 568656e7052SJohn Crispin */ 569656e7052SJohn Crispin struct mtk_mac { 570656e7052SJohn Crispin int id; 5719ea4d311SSean Wang int ge_mode; 572656e7052SJohn Crispin struct device_node *of_node; 573656e7052SJohn Crispin struct mtk_eth *hw; 574656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 575ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 576ee406810SNelson Chang int hwlro_ip_cnt; 577572de608SSean Wang bool trgmii; 578656e7052SJohn Crispin }; 579656e7052SJohn Crispin 580656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 581656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 582656e7052SJohn Crispin 583656e7052SJohn Crispin /* read the hardware status register */ 584656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 585656e7052SJohn Crispin 586656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 587656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 588656e7052SJohn Crispin 589656e7052SJohn Crispin #endif /* MTK_ETH_H */ 590