18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28e8e69d6SThomas Gleixner /* 3656e7052SJohn Crispin * 4656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7656e7052SJohn Crispin */ 8656e7052SJohn Crispin 9656e7052SJohn Crispin #ifndef MTK_ETH_H 10656e7052SJohn Crispin #define MTK_ETH_H 11656e7052SJohn Crispin 129ffee4a8SSean Wang #include <linux/dma-mapping.h> 139ffee4a8SSean Wang #include <linux/netdevice.h> 149ffee4a8SSean Wang #include <linux/of_net.h> 159ffee4a8SSean Wang #include <linux/u64_stats_sync.h> 16c6d4e63eSElena Reshetova #include <linux/refcount.h> 17b8fc9f30SRené van Dorst #include <linux/phylink.h> 18502e84e2SFelix Fietkau #include <linux/rhashtable.h> 19e9229ffdSFelix Fietkau #include <linux/dim.h> 20bc5e93e0SRussell King (Oracle) #include <linux/bitfield.h> 2123233e57SLorenzo Bianconi #include <net/page_pool.h> 2223233e57SLorenzo Bianconi #include <linux/bpf_trace.h> 23ba37b7caSFelix Fietkau #include "mtk_ppe.h" 24c6d4e63eSElena Reshetova 252d7605a7SFelix Fietkau #define MTK_MAX_DSA_PORTS 7 262d7605a7SFelix Fietkau #define MTK_DSA_PORT_MASK GENMASK(2, 0) 272d7605a7SFelix Fietkau 28f63959c7SFelix Fietkau #define MTK_QDMA_NUM_QUEUES 16 29656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 30656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 314fd59792SDENG Qingfang #define MTK_MAX_RX_LENGTH_2K 2048 32656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 33160d3a9bSLorenzo Bianconi #define MTK_TX_DMA_BUF_LEN_V2 0xffff 34c30e0b9bSFelix Fietkau #define MTK_QDMA_RING_SIZE 2048 356b4423b2SFelix Fietkau #define MTK_DMA_SIZE 512 36656e7052SJohn Crispin #define MTK_MAC_COUNT 2 374fd59792SDENG Qingfang #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 38656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 39656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 40656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 41656e7052SJohn Crispin NETIF_MSG_PROBE | \ 42656e7052SJohn Crispin NETIF_MSG_LINK | \ 43656e7052SJohn Crispin NETIF_MSG_TIMER | \ 44656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 45656e7052SJohn Crispin NETIF_MSG_IFUP | \ 46656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 47656e7052SJohn Crispin NETIF_MSG_TX_ERR) 48656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 49656e7052SJohn Crispin NETIF_F_RXCSUM | \ 50656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 51656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_RX | \ 52656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 53656e7052SJohn Crispin NETIF_F_TSO6 | \ 54502e84e2SFelix Fietkau NETIF_F_IPV6_CSUM |\ 55502e84e2SFelix Fietkau NETIF_F_HW_TC) 56296c9120SStefan Roese #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 5708df5fa6SStefan Roese #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 58ee406810SNelson Chang 5923233e57SLorenzo Bianconi #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM 6023233e57SLorenzo Bianconi #define MTK_PP_PAD (MTK_PP_HEADROOM + \ 6123233e57SLorenzo Bianconi SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 6223233e57SLorenzo Bianconi #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD) 6323233e57SLorenzo Bianconi 648cb42714SLorenzo Bianconi #define MTK_QRX_OFFSET 0x10 658cb42714SLorenzo Bianconi 66ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4 67ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8 68ee406810SNelson Chang 69ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 70ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2 71ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 72ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 73ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 74ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 75ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64 76ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000 77ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000 78ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 79656e7052SJohn Crispin 8006127504SLorenzo Bianconi /* Frame Engine Global Configuration */ 8106127504SLorenzo Bianconi #define MTK_FE_GLO_CFG 0x00 8206127504SLorenzo Bianconi #define MTK_FE_LINK_DOWN_P3 BIT(11) 8306127504SLorenzo Bianconi #define MTK_FE_LINK_DOWN_P4 BIT(12) 8406127504SLorenzo Bianconi 85656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 86656e7052SJohn Crispin #define MTK_RST_GL 0x04 87656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 88656e7052SJohn Crispin 89656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 90656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 9106127504SLorenzo Bianconi #define MTK_FE_INT_ENABLE 0x0c 9206127504SLorenzo Bianconi #define MTK_FE_INT_FQ_EMPTY BIT(8) 9306127504SLorenzo Bianconi #define MTK_FE_INT_TSO_FAIL BIT(12) 9406127504SLorenzo Bianconi #define MTK_FE_INT_TSO_ILLEGAL BIT(13) 9506127504SLorenzo Bianconi #define MTK_FE_INT_TSO_ALIGN BIT(14) 9606127504SLorenzo Bianconi #define MTK_FE_INT_RFIFO_OV BIT(18) 9706127504SLorenzo Bianconi #define MTK_FE_INT_RFIFO_UF BIT(19) 98656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 99656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 100656e7052SJohn Crispin 101ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */ 102ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 103ee406810SNelson Chang 104656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 105656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 106656e7052SJohn Crispin 10787e3df49SSean Wang /* CDMP Ingress Control Register */ 10887e3df49SSean Wang #define MTK_CDMQ_IG_CTRL 0x1400 10987e3df49SSean Wang #define MTK_CDMQ_STAG_EN BIT(0) 11087e3df49SSean Wang 1112d7605a7SFelix Fietkau /* CDMQ Exgress Control Register */ 1122d7605a7SFelix Fietkau #define MTK_CDMQ_EG_CTRL 0x1404 1132d7605a7SFelix Fietkau 114160d3a9bSLorenzo Bianconi /* CDMP Ingress Control Register */ 115160d3a9bSLorenzo Bianconi #define MTK_CDMP_IG_CTRL 0x400 116160d3a9bSLorenzo Bianconi #define MTK_CDMP_STAG_EN BIT(0) 117160d3a9bSLorenzo Bianconi 118656e7052SJohn Crispin /* CDMP Exgress Control Register */ 119656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 120656e7052SJohn Crispin 121656e7052SJohn Crispin /* GDM Exgress Control Register */ 122656e7052SJohn Crispin #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 123d5c53da2SFelix Fietkau #define MTK_GDMA_SPECIAL_TAG BIT(24) 124656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 125656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 126656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 1278d3f4a95SMarkLee #define MTK_GDMA_TO_PDMA 0x0 1288d66a818SMarkLee #define MTK_GDMA_DROP_ALL 0x7777 129656e7052SJohn Crispin 130656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 131656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 132656e7052SJohn Crispin 133656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 134656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 135656e7052SJohn Crispin 136160d3a9bSLorenzo Bianconi /* FE global misc reg*/ 137160d3a9bSLorenzo Bianconi #define MTK_FE_GLO_MISC 0x124 138160d3a9bSLorenzo Bianconi 139160d3a9bSLorenzo Bianconi /* PSE Free Queue Flow Control */ 140160d3a9bSLorenzo Bianconi #define PSE_FQFC_CFG1 0x100 141160d3a9bSLorenzo Bianconi #define PSE_FQFC_CFG2 0x104 142160d3a9bSLorenzo Bianconi #define PSE_DROP_CFG 0x108 143f4b2fa2cSFelix Fietkau #define PSE_PPE0_DROP 0x110 144160d3a9bSLorenzo Bianconi 145160d3a9bSLorenzo Bianconi /* PSE Input Queue Reservation Register*/ 146160d3a9bSLorenzo Bianconi #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 147160d3a9bSLorenzo Bianconi 148160d3a9bSLorenzo Bianconi /* PSE Output Queue Threshold Register*/ 149160d3a9bSLorenzo Bianconi #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 150160d3a9bSLorenzo Bianconi 151160d3a9bSLorenzo Bianconi /* GDM and CDM Threshold */ 152160d3a9bSLorenzo Bianconi #define MTK_GDM2_THRES 0x1530 153160d3a9bSLorenzo Bianconi #define MTK_CDMW0_THRES 0x164c 154160d3a9bSLorenzo Bianconi #define MTK_CDMW1_THRES 0x1650 155160d3a9bSLorenzo Bianconi #define MTK_CDME0_THRES 0x1654 156160d3a9bSLorenzo Bianconi #define MTK_CDME1_THRES 0x1658 157160d3a9bSLorenzo Bianconi #define MTK_CDMM_THRES 0x165c 158160d3a9bSLorenzo Bianconi 159ee406810SNelson Chang /* PDMA HW LRO Control Registers */ 160ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980 161ee406810SNelson Chang #define MTK_LRO_EN BIT(0) 162ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7) 163160d3a9bSLorenzo Bianconi #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 164ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 165ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 166160d3a9bSLorenzo Bianconi #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 167ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 168160d3a9bSLorenzo Bianconi #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 169ee406810SNelson Chang 170ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984 171ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988 172ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c 173ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15) 174ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 175bacfd110SNelson Chang 1768cb42714SLorenzo Bianconi #define MTK_RX_DMA_LRO_EN BIT(8) 177bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10) 178296c9120SStefan Roese #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 179bacfd110SNelson Chang 1808cb42714SLorenzo Bianconi /* PDMA Global Configuration Register */ 1818cb42714SLorenzo Bianconi #define MTK_PDMA_LRO_SDL 0x3000 1828cb42714SLorenzo Bianconi #define MTK_RX_CFG_SDL_OFFSET 16 1838cb42714SLorenzo Bianconi 184bacfd110SNelson Chang /* PDMA Reset Index Register */ 185bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16) 186ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 187bacfd110SNelson Chang 188bacfd110SNelson Chang /* PDMA Delay Interrupt Register */ 189e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 190671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_EN BIT(15) 191671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 192e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 193e9229ffdSFelix Fietkau 194e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 195e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_EN BIT(31) 196e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 197e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 198e9229ffdSFelix Fietkau 199e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PINT_MASK 0x7f 200e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PTIME_MASK 0xff 201bacfd110SNelson Chang 202ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */ 203ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 204ee406810SNelson Chang 205ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */ 206ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 207ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 208ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9) 209ee406810SNelson Chang 210ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */ 211ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 212ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 213ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 214ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 215ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 216ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 217ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 218ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 219ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 220ee406810SNelson Chang #define MTK_RING_VLD BIT(8) 221ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 222ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 223ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 224ee406810SNelson Chang 225656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 226f63959c7SFelix Fietkau #define MTK_QTX_OFFSET 0x10 227656e7052SJohn Crispin #define QDMA_RES_THRES 4 228656e7052SJohn Crispin 229f63959c7SFelix Fietkau /* QDMA Tx Queue Scheduler Configuration Registers */ 230f63959c7SFelix Fietkau #define MTK_QTX_SCH_TX_SEL BIT(31) 231f63959c7SFelix Fietkau #define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30) 232f63959c7SFelix Fietkau 233f63959c7SFelix Fietkau #define MTK_QTX_SCH_LEAKY_BUCKET_EN BIT(30) 234f63959c7SFelix Fietkau #define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28) 235f63959c7SFelix Fietkau #define MTK_QTX_SCH_MIN_RATE_EN BIT(27) 236f63959c7SFelix Fietkau #define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20) 237f63959c7SFelix Fietkau #define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16) 238f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12) 239f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_EN BIT(11) 240f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4) 241f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0) 242f63959c7SFelix Fietkau 243f63959c7SFelix Fietkau /* QDMA TX Scheduler Rate Control Register */ 244f63959c7SFelix Fietkau #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15) 245f63959c7SFelix Fietkau 246656e7052SJohn Crispin /* QDMA Global Configuration Register */ 247656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 248656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 2496675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 250656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 25159555a8dSFelix Fietkau #define MTK_TX_BT_32DWORDS (3 << 4) 252656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 253656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 254656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 255656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 2563bc8e0afSIlya Lipnitskiy #define MTK_DMA_BUSY_TIMEOUT_US 1000000 257656e7052SJohn Crispin 258160d3a9bSLorenzo Bianconi /* QDMA V2 Global Configuration Register */ 259160d3a9bSLorenzo Bianconi #define MTK_CHK_DDONE_EN BIT(28) 260160d3a9bSLorenzo Bianconi #define MTK_DMAD_WR_WDONE BIT(26) 261160d3a9bSLorenzo Bianconi #define MTK_WCOMP_EN BIT(24) 262160d3a9bSLorenzo Bianconi #define MTK_RESV_BUF (0x40 << 16) 263160d3a9bSLorenzo Bianconi #define MTK_MUTLI_CNT (0x4 << 12) 264f63959c7SFelix Fietkau #define MTK_LEAKY_BUCKET_EN BIT(11) 265160d3a9bSLorenzo Bianconi 266656e7052SJohn Crispin /* QDMA Flow Control Register */ 267656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 268656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 269656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 270656e7052SJohn Crispin 271656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 272671d41e6SJohn Crispin #define MTK_RX_DONE_DLY BIT(30) 273e9229ffdSFelix Fietkau #define MTK_TX_DONE_DLY BIT(28) 274bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19) 275bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18) 276656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 277656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 278656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 279656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 280656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 281656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 282671d41e6SJohn Crispin #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 283e9229ffdSFelix Fietkau #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 284656e7052SJohn Crispin 285160d3a9bSLorenzo Bianconi #define MTK_RX_DONE_INT_V2 BIT(14) 286160d3a9bSLorenzo Bianconi 287*93b2591aSLorenzo Bianconi #define MTK_CDM_TXFIFO_RDY BIT(7) 288*93b2591aSLorenzo Bianconi 28980673029SJohn Crispin /* QDMA Interrupt grouping registers */ 29080673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0) 29180673029SJohn Crispin 292656e7052SJohn Crispin #define MTK_STAT_OFFSET 0x40 293656e7052SJohn Crispin 294160d3a9bSLorenzo Bianconi /* QDMA TX NUM */ 295160d3a9bSLorenzo Bianconi #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 296160d3a9bSLorenzo Bianconi #define MTK_QDMA_GMAC2_QID 8 297160d3a9bSLorenzo Bianconi 298160d3a9bSLorenzo Bianconi #define MTK_TX_DMA_BUF_SHIFT 8 299160d3a9bSLorenzo Bianconi 300160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd6 */ 301160d3a9bSLorenzo Bianconi #define TX_DMA_INS_VLAN_V2 BIT(16) 302160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd5 */ 303160d3a9bSLorenzo Bianconi #define TX_DMA_CHKSUM_V2 (0x7 << 28) 304160d3a9bSLorenzo Bianconi #define TX_DMA_TSO_V2 BIT(31) 305160d3a9bSLorenzo Bianconi 306160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd4 */ 307160d3a9bSLorenzo Bianconi #define TX_DMA_FPORT_SHIFT_V2 8 308160d3a9bSLorenzo Bianconi #define TX_DMA_FPORT_MASK_V2 0xf 309160d3a9bSLorenzo Bianconi #define TX_DMA_SWC_V2 BIT(30) 310160d3a9bSLorenzo Bianconi 311656e7052SJohn Crispin /* QDMA descriptor txd4 */ 312656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 313656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 314656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 315656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 316656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 317656e7052SJohn Crispin 318656e7052SJohn Crispin /* QDMA descriptor txd3 */ 319656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 320656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 321160d3a9bSLorenzo Bianconi #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 322160d3a9bSLorenzo Bianconi #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) 323656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 324f63959c7SFelix Fietkau #define TX_DMA_PQID GENMASK(3, 0) 325656e7052SJohn Crispin 326296c9120SStefan Roese /* PDMA on MT7628 */ 327296c9120SStefan Roese #define TX_DMA_DONE BIT(31) 328296c9120SStefan Roese #define TX_DMA_LS1 BIT(14) 329296c9120SStefan Roese #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 330296c9120SStefan Roese 331656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 332656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 333296c9120SStefan Roese #define RX_DMA_LSO BIT(30) 334160d3a9bSLorenzo Bianconi #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 335160d3a9bSLorenzo Bianconi #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) 3363f57d8c4SFelix Fietkau #define RX_DMA_VTAG BIT(15) 337656e7052SJohn Crispin 338656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 339160d3a9bSLorenzo Bianconi #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 340160d3a9bSLorenzo Bianconi #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 341160d3a9bSLorenzo Bianconi #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 342656e7052SJohn Crispin 343656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 344ba37b7caSFelix Fietkau #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 345ba37b7caSFelix Fietkau #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 346ba37b7caSFelix Fietkau #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 347ba37b7caSFelix Fietkau #define MTK_RXD4_ALG GENMASK(31, 22) 348ba37b7caSFelix Fietkau 349ba37b7caSFelix Fietkau /* QDMA descriptor rxd4 */ 350656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 351296c9120SStefan Roese #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 352d5c53da2SFelix Fietkau #define RX_DMA_SPECIAL_TAG BIT(22) 353656e7052SJohn Crispin 3540cf731f9SLorenzo Bianconi /* PDMA descriptor rxd5 */ 3550cf731f9SLorenzo Bianconi #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) 3560cf731f9SLorenzo Bianconi #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) 3570cf731f9SLorenzo Bianconi #define MTK_RXD5_SRC_PORT GENMASK(29, 26) 3580cf731f9SLorenzo Bianconi 359c9da02bfSDaniel Golle #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7) 360c9da02bfSDaniel Golle #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf) 361160d3a9bSLorenzo Bianconi 362160d3a9bSLorenzo Bianconi /* PDMA V2 descriptor rxd3 */ 363160d3a9bSLorenzo Bianconi #define RX_DMA_VTAG_V2 BIT(0) 364160d3a9bSLorenzo Bianconi #define RX_DMA_L4_VALID_V2 BIT(2) 365160d3a9bSLorenzo Bianconi 366656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 367656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 368656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 369eda80b24SDaniel Golle #define PHY_IAC_REG_MASK GENMASK(29, 25) 370eda80b24SDaniel Golle #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 371eda80b24SDaniel Golle #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 372eda80b24SDaniel Golle #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 373eda80b24SDaniel Golle #define PHY_IAC_CMD_MASK GENMASK(19, 18) 374e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 375eda80b24SDaniel Golle #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 376eda80b24SDaniel Golle #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 377e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 378eda80b24SDaniel Golle #define PHY_IAC_START_MASK GENMASK(17, 16) 379e2e7f6e2SDaniel Golle #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 380eda80b24SDaniel Golle #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 381eda80b24SDaniel Golle #define PHY_IAC_DATA_MASK GENMASK(15, 0) 382eda80b24SDaniel Golle #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 383656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 384656e7052SJohn Crispin 38542c03844SSean Wang #define MTK_MAC_MISC 0x1000c 38642c03844SSean Wang #define MTK_MUX_TO_ESW BIT(0) 38742c03844SSean Wang 388656e7052SJohn Crispin /* Mac control registers */ 389656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 3904fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 3914fd59792SDENG Qingfang #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 3924fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1518 0x0 3934fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1536 0x1 3944fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1552 0x2 3954fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_2048 0x3 396656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 397656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 398656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 399656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 400656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 401656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 402656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 403656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 404656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 405656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 406656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 407656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 408b8fc9f30SRené van Dorst #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 409b8fc9f30SRené van Dorst 410b8fc9f30SRené van Dorst /* Mac status registers */ 411b8fc9f30SRené van Dorst #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 412b8fc9f30SRené van Dorst #define MAC_MSR_EEE1G BIT(7) 413b8fc9f30SRené van Dorst #define MAC_MSR_EEE100M BIT(6) 414b8fc9f30SRené van Dorst #define MAC_MSR_RX_FC BIT(5) 415b8fc9f30SRené van Dorst #define MAC_MSR_TX_FC BIT(4) 416b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_1000 BIT(3) 417b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_100 BIT(2) 418b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 419b8fc9f30SRené van Dorst #define MAC_MSR_DPX BIT(1) 420b8fc9f30SRené van Dorst #define MAC_MSR_LINK BIT(0) 421656e7052SJohn Crispin 422f430dea7SSean Wang /* TRGMII RXC control register */ 423f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300 424f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 425f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 426f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 427a5d75538SRené van Dorst #define RXC_RST BIT(31) 428f430dea7SSean Wang #define RXC_DQSISEL BIT(30) 429f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 430f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 431f430dea7SSean Wang 432a5d75538SRené van Dorst #define NUM_TRGMII_CTRL 5 433a5d75538SRené van Dorst 434f430dea7SSean Wang /* TRGMII RXC control register */ 435f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340 436f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 437f430dea7SSean Wang #define TXC_INV BIT(30) 438f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 439f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 440f430dea7SSean Wang 441a5d75538SRené van Dorst /* TRGMII TX Drive Strength */ 442a5d75538SRené van Dorst #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 443a5d75538SRené van Dorst #define TD_DM_DRVP(x) ((x) & 0xf) 444a5d75538SRené van Dorst #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 445a5d75538SRené van Dorst 446f430dea7SSean Wang /* TRGMII Interface mode register */ 447f430dea7SSean Wang #define INTF_MODE 0x10390 448f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0) 449f430dea7SSean Wang #define TRGMII_MODE BIT(1) 450f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2) 451f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 452f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0 453f430dea7SSean Wang 454656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 455656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 456656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 457656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 458656e7052SJohn Crispin 459b95b6d99SNelson Chang /* ethernet subsystem chip id register */ 460b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0 461b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4 462983e1a6cSNelson Chang #define MT7623_ETH 7623 46342c03844SSean Wang #define MT7622_ETH 7622 464889bcbdeSBjørn Mork #define MT7621_ETH 7621 465b95b6d99SNelson Chang 4668efaa653SRené van Dorst /* ethernet system control register */ 4678efaa653SRené van Dorst #define ETHSYS_SYSCFG 0x10 4688efaa653SRené van Dorst #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 4698efaa653SRené van Dorst 470656e7052SJohn Crispin /* ethernet subsystem config register */ 471656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 472656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 473656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 4747093f9d8SSean Wang #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 4757093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 4767093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 4777093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 4787093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 4797093f9d8SSean Wang 480656e7052SJohn Crispin 481f430dea7SSean Wang /* ethernet subsystem clock register */ 482f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c 483f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 4848efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 4858efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 4868efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 487f430dea7SSean Wang 4882a8307aaSSean Wang /* ethernet reset control register */ 4892a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34 4902a8307aaSSean Wang #define RSTCTRL_FE BIT(6) 491ef8c373bSLorenzo Bianconi #define RSTCTRL_PPE0 BIT(31) 492ef8c373bSLorenzo Bianconi #define RSTCTRL_PPE0_V2 BIT(30) 493ef8c373bSLorenzo Bianconi #define RSTCTRL_PPE1 BIT(31) 494160d3a9bSLorenzo Bianconi #define RSTCTRL_ETH BIT(23) 495160d3a9bSLorenzo Bianconi 496160d3a9bSLorenzo Bianconi /* ethernet reset check idle register */ 497160d3a9bSLorenzo Bianconi #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 498160d3a9bSLorenzo Bianconi 499d776a57eSFelix Fietkau /* ethernet dma channel agent map */ 500d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP 0x408 501d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 502d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 503d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 504d776a57eSFelix Fietkau 50542c03844SSean Wang /* SGMII subsystem config registers */ 506b6a709cbSRussell King (Oracle) /* BMCR (low 16) BMSR (high 16) */ 50742c03844SSean Wang #define SGMSYS_PCS_CONTROL_1 0x0 508b6a709cbSRussell King (Oracle) #define SGMII_BMCR GENMASK(15, 0) 509b6a709cbSRussell King (Oracle) #define SGMII_BMSR GENMASK(31, 16) 51042c03844SSean Wang #define SGMII_AN_RESTART BIT(9) 5117e538372SRené van Dorst #define SGMII_ISOLATE BIT(10) 5127e538372SRené van Dorst #define SGMII_AN_ENABLE BIT(12) 5137e538372SRené van Dorst #define SGMII_LINK_STATYS BIT(18) 5147e538372SRené van Dorst #define SGMII_AN_ABILITY BIT(19) 5157e538372SRené van Dorst #define SGMII_AN_COMPLETE BIT(21) 5167e538372SRené van Dorst #define SGMII_PCS_FAULT BIT(23) 5177e538372SRené van Dorst #define SGMII_AN_EXPANSION_CLR BIT(30) 51842c03844SSean Wang 519b6a709cbSRussell King (Oracle) #define SGMSYS_PCS_ADVERTISE 0x8 520b6a709cbSRussell King (Oracle) #define SGMII_ADVERTISE GENMASK(15, 0) 521b6a709cbSRussell King (Oracle) #define SGMII_LPA GENMASK(31, 16) 522b6a709cbSRussell King (Oracle) 52342c03844SSean Wang /* Register to programmable link timer, the unit in 2 * 8ns */ 52442c03844SSean Wang #define SGMSYS_PCS_LINK_TIMER 0x18 525b6a709cbSRussell King (Oracle) #define SGMII_LINK_TIMER_MASK GENMASK(19, 0) 526b6a709cbSRussell King (Oracle) #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & SGMII_LINK_TIMER_MASK) 52742c03844SSean Wang 52842c03844SSean Wang /* Register to control remote fault */ 52942c03844SSean Wang #define SGMSYS_SGMII_MODE 0x20 530b6a709cbSRussell King (Oracle) #define SGMII_IF_MODE_SGMII BIT(0) 5317e538372SRené van Dorst #define SGMII_SPEED_DUPLEX_AN BIT(1) 532bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_MASK GENMASK(3, 2) 533bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) 534bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) 535bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) 5367e538372SRené van Dorst #define SGMII_DUPLEX_FULL BIT(4) 5377e538372SRené van Dorst #define SGMII_IF_MODE_BIT5 BIT(5) 53842c03844SSean Wang #define SGMII_REMOTE_FAULT_DIS BIT(8) 5397e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_VAL BIT(9) 5407e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_EN BIT(10) 5417e538372SRené van Dorst #define SGMII_SEND_AN_ERROR_EN BIT(11) 5427e538372SRené van Dorst #define SGMII_IF_MODE_MASK GENMASK(5, 1) 5437e538372SRené van Dorst 5447e538372SRené van Dorst /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 5457e538372SRené van Dorst #define SGMSYS_ANA_RG_CS3 0x2028 5467e538372SRené van Dorst #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 5477e538372SRené van Dorst #define RG_PHY_SPEED_1_25G 0x0 5487e538372SRené van Dorst #define RG_PHY_SPEED_3_125G BIT(2) 54942c03844SSean Wang 55042c03844SSean Wang /* Register to power up QPHY */ 55142c03844SSean Wang #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 55242c03844SSean Wang #define SGMII_PHYA_PWD BIT(4) 55342c03844SSean Wang 5547093f9d8SSean Wang /* Infrasys subsystem config registers */ 5557093f9d8SSean Wang #define INFRA_MISC2 0x70c 5567093f9d8SSean Wang #define CO_QPHY_SEL BIT(0) 5577093f9d8SSean Wang #define GEPHY_MAC_SEL BIT(1) 5587093f9d8SSean Wang 559296c9120SStefan Roese /* MT7628/88 specific stuff */ 560296c9120SStefan Roese #define MT7628_PDMA_OFFSET 0x0800 561296c9120SStefan Roese #define MT7628_SDM_OFFSET 0x0c00 562296c9120SStefan Roese 563296c9120SStefan Roese #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 564296c9120SStefan Roese #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 565296c9120SStefan Roese #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 566296c9120SStefan Roese #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 567296c9120SStefan Roese #define MT7628_PST_DTX_IDX0 BIT(0) 568296c9120SStefan Roese 569296c9120SStefan Roese #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 570296c9120SStefan Roese #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 571296c9120SStefan Roese 572ad79fd2cSStefan Roese /* Counter / stat register */ 573ad79fd2cSStefan Roese #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 574ad79fd2cSStefan Roese #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 575ad79fd2cSStefan Roese #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 576ad79fd2cSStefan Roese #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 577ad79fd2cSStefan Roese #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 578ad79fd2cSStefan Roese 579*93b2591aSLorenzo Bianconi #define MTK_FE_CDM1_FSM 0x220 580*93b2591aSLorenzo Bianconi #define MTK_FE_CDM2_FSM 0x224 581*93b2591aSLorenzo Bianconi #define MTK_FE_CDM3_FSM 0x238 582*93b2591aSLorenzo Bianconi #define MTK_FE_CDM4_FSM 0x298 583*93b2591aSLorenzo Bianconi #define MTK_FE_CDM5_FSM 0x318 584*93b2591aSLorenzo Bianconi #define MTK_FE_CDM6_FSM 0x328 585*93b2591aSLorenzo Bianconi #define MTK_FE_GDM1_FSM 0x228 586*93b2591aSLorenzo Bianconi #define MTK_FE_GDM2_FSM 0x22C 587*93b2591aSLorenzo Bianconi 588*93b2591aSLorenzo Bianconi #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100)) 589*93b2591aSLorenzo Bianconi 590656e7052SJohn Crispin struct mtk_rx_dma { 591656e7052SJohn Crispin unsigned int rxd1; 592656e7052SJohn Crispin unsigned int rxd2; 593656e7052SJohn Crispin unsigned int rxd3; 594656e7052SJohn Crispin unsigned int rxd4; 595656e7052SJohn Crispin } __packed __aligned(4); 596656e7052SJohn Crispin 597160d3a9bSLorenzo Bianconi struct mtk_rx_dma_v2 { 598160d3a9bSLorenzo Bianconi unsigned int rxd1; 599160d3a9bSLorenzo Bianconi unsigned int rxd2; 600160d3a9bSLorenzo Bianconi unsigned int rxd3; 601160d3a9bSLorenzo Bianconi unsigned int rxd4; 602160d3a9bSLorenzo Bianconi unsigned int rxd5; 603160d3a9bSLorenzo Bianconi unsigned int rxd6; 604160d3a9bSLorenzo Bianconi unsigned int rxd7; 605160d3a9bSLorenzo Bianconi unsigned int rxd8; 606160d3a9bSLorenzo Bianconi } __packed __aligned(4); 607160d3a9bSLorenzo Bianconi 608656e7052SJohn Crispin struct mtk_tx_dma { 609656e7052SJohn Crispin unsigned int txd1; 610656e7052SJohn Crispin unsigned int txd2; 611656e7052SJohn Crispin unsigned int txd3; 612656e7052SJohn Crispin unsigned int txd4; 613656e7052SJohn Crispin } __packed __aligned(4); 614656e7052SJohn Crispin 615160d3a9bSLorenzo Bianconi struct mtk_tx_dma_v2 { 616160d3a9bSLorenzo Bianconi unsigned int txd1; 617160d3a9bSLorenzo Bianconi unsigned int txd2; 618160d3a9bSLorenzo Bianconi unsigned int txd3; 619160d3a9bSLorenzo Bianconi unsigned int txd4; 620160d3a9bSLorenzo Bianconi unsigned int txd5; 621160d3a9bSLorenzo Bianconi unsigned int txd6; 622160d3a9bSLorenzo Bianconi unsigned int txd7; 623160d3a9bSLorenzo Bianconi unsigned int txd8; 624160d3a9bSLorenzo Bianconi } __packed __aligned(4); 625160d3a9bSLorenzo Bianconi 626656e7052SJohn Crispin struct mtk_eth; 627656e7052SJohn Crispin struct mtk_mac; 628656e7052SJohn Crispin 629916a6ee8SLorenzo Bianconi struct mtk_xdp_stats { 630916a6ee8SLorenzo Bianconi u64 rx_xdp_redirect; 631916a6ee8SLorenzo Bianconi u64 rx_xdp_pass; 632916a6ee8SLorenzo Bianconi u64 rx_xdp_drop; 633916a6ee8SLorenzo Bianconi u64 rx_xdp_tx; 634916a6ee8SLorenzo Bianconi u64 rx_xdp_tx_errors; 635916a6ee8SLorenzo Bianconi u64 tx_xdp_xmit; 636916a6ee8SLorenzo Bianconi u64 tx_xdp_xmit_errors; 637916a6ee8SLorenzo Bianconi }; 638916a6ee8SLorenzo Bianconi 639656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 640656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 641656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 642656e7052SJohn Crispin * @syncp: the refcount 643656e7052SJohn Crispin * 644656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 645656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 646656e7052SJohn Crispin * counters and store them in this struct. 647656e7052SJohn Crispin */ 648656e7052SJohn Crispin struct mtk_hw_stats { 649656e7052SJohn Crispin u64 tx_bytes; 650656e7052SJohn Crispin u64 tx_packets; 651656e7052SJohn Crispin u64 tx_skip; 652656e7052SJohn Crispin u64 tx_collisions; 653656e7052SJohn Crispin u64 rx_bytes; 654656e7052SJohn Crispin u64 rx_packets; 655656e7052SJohn Crispin u64 rx_overflow; 656656e7052SJohn Crispin u64 rx_fcs_errors; 657656e7052SJohn Crispin u64 rx_short_errors; 658656e7052SJohn Crispin u64 rx_long_errors; 659656e7052SJohn Crispin u64 rx_checksum_errors; 660656e7052SJohn Crispin u64 rx_flow_control_packets; 661656e7052SJohn Crispin 662916a6ee8SLorenzo Bianconi struct mtk_xdp_stats xdp_stats; 663916a6ee8SLorenzo Bianconi 664656e7052SJohn Crispin spinlock_t stats_lock; 665656e7052SJohn Crispin u32 reg_offset; 666656e7052SJohn Crispin struct u64_stats_sync syncp; 667656e7052SJohn Crispin }; 668656e7052SJohn Crispin 669656e7052SJohn Crispin enum mtk_tx_flags { 670134d2152SSean Wang /* PDMA descriptor can point at 1-2 segments. This enum allows us to 671134d2152SSean Wang * track how memory was allocated so that it can be freed properly. 672134d2152SSean Wang */ 673656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 674656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 675134d2152SSean Wang 676134d2152SSean Wang /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 677134d2152SSean Wang * SKB out instead of looking up through hardware TX descriptor. 678134d2152SSean Wang */ 679134d2152SSean Wang MTK_TX_FLAGS_FPORT0 = 0x04, 680134d2152SSean Wang MTK_TX_FLAGS_FPORT1 = 0x08, 681656e7052SJohn Crispin }; 682656e7052SJohn Crispin 683549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the 684549e5495SSean Wang * clock in the order 685549e5495SSean Wang */ 686549e5495SSean Wang enum mtk_clks_map { 687549e5495SSean Wang MTK_CLK_ETHIF, 688d438e298SSean Wang MTK_CLK_SGMIITOP, 689549e5495SSean Wang MTK_CLK_ESW, 69042c03844SSean Wang MTK_CLK_GP0, 691549e5495SSean Wang MTK_CLK_GP1, 692549e5495SSean Wang MTK_CLK_GP2, 693d438e298SSean Wang MTK_CLK_FE, 694f430dea7SSean Wang MTK_CLK_TRGPLL, 69542c03844SSean Wang MTK_CLK_SGMII_TX_250M, 69642c03844SSean Wang MTK_CLK_SGMII_RX_250M, 69742c03844SSean Wang MTK_CLK_SGMII_CDR_REF, 69842c03844SSean Wang MTK_CLK_SGMII_CDR_FB, 699d438e298SSean Wang MTK_CLK_SGMII2_TX_250M, 700d438e298SSean Wang MTK_CLK_SGMII2_RX_250M, 701d438e298SSean Wang MTK_CLK_SGMII2_CDR_REF, 702d438e298SSean Wang MTK_CLK_SGMII2_CDR_FB, 70342c03844SSean Wang MTK_CLK_SGMII_CK, 70442c03844SSean Wang MTK_CLK_ETH2PLL, 705197c9e9bSLorenzo Bianconi MTK_CLK_WOCPU0, 706197c9e9bSLorenzo Bianconi MTK_CLK_WOCPU1, 707197c9e9bSLorenzo Bianconi MTK_CLK_NETSYS0, 708197c9e9bSLorenzo Bianconi MTK_CLK_NETSYS1, 709549e5495SSean Wang MTK_CLK_MAX 710549e5495SSean Wang }; 711549e5495SSean Wang 7122ec50f57SSean Wang #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 7132ec50f57SSean Wang BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 7142ec50f57SSean Wang BIT(MTK_CLK_TRGPLL)) 71542c03844SSean Wang #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 71642c03844SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 71742c03844SSean Wang BIT(MTK_CLK_GP2) | \ 71842c03844SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 71942c03844SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 72042c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 72142c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 72242c03844SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 72342c03844SSean Wang BIT(MTK_CLK_ETH2PLL)) 724889bcbdeSBjørn Mork #define MT7621_CLKS_BITMAP (0) 725296c9120SStefan Roese #define MT7628_CLKS_BITMAP (0) 726d438e298SSean Wang #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 727d438e298SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 728d438e298SSean Wang BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 729d438e298SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 730d438e298SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 731d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 732d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 733d438e298SSean Wang BIT(MTK_CLK_SGMII2_TX_250M) | \ 734d438e298SSean Wang BIT(MTK_CLK_SGMII2_RX_250M) | \ 735d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_REF) | \ 736d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_FB) | \ 737d438e298SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 738d438e298SSean Wang BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 739197c9e9bSLorenzo Bianconi #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ 740197c9e9bSLorenzo Bianconi BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ 741197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII_TX_250M) | \ 742197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII_RX_250M) | \ 743197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII_CDR_REF) | \ 744197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII_CDR_FB) | \ 745197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII2_TX_250M) | \ 746197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII2_RX_250M) | \ 747197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII2_CDR_REF) | \ 748197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII2_CDR_FB)) 749889bcbdeSBjørn Mork 7509ea4d311SSean Wang enum mtk_dev_state { 751dce6fa42SSean Wang MTK_HW_INIT, 752dce6fa42SSean Wang MTK_RESETTING 7539ea4d311SSean Wang }; 7549ea4d311SSean Wang 7555886d26fSLorenzo Bianconi enum mtk_tx_buf_type { 7565886d26fSLorenzo Bianconi MTK_TYPE_SKB, 7575886d26fSLorenzo Bianconi MTK_TYPE_XDP_TX, 7585886d26fSLorenzo Bianconi MTK_TYPE_XDP_NDO, 7595886d26fSLorenzo Bianconi }; 7605886d26fSLorenzo Bianconi 761656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 762656e7052SJohn Crispin * by the TX descriptor s 763656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 764656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 765656e7052SJohn Crispin * @dma_len0: The length of the first segment 766656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 767656e7052SJohn Crispin * @dma_len1: The length of the second segment 768656e7052SJohn Crispin */ 769656e7052SJohn Crispin struct mtk_tx_buf { 7705886d26fSLorenzo Bianconi enum mtk_tx_buf_type type; 7715886d26fSLorenzo Bianconi void *data; 7725886d26fSLorenzo Bianconi 773656e7052SJohn Crispin u32 flags; 774656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 775656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 776656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 777656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 778656e7052SJohn Crispin }; 779656e7052SJohn Crispin 780656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 781656e7052SJohn Crispin * @dma: The descriptor ring 782656e7052SJohn Crispin * @buf: The memory pointed at by the ring 783656e7052SJohn Crispin * @phys: The physical addr of tx_buf 784656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 785656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 7864e6bf609SFelix Fietkau * @last_free_ptr: Hardware pointer value of the last free descriptor 787656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 788656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 789656e7052SJohn Crispin * are present 790656e7052SJohn Crispin */ 791656e7052SJohn Crispin struct mtk_tx_ring { 7927173eca8SLorenzo Bianconi void *dma; 793656e7052SJohn Crispin struct mtk_tx_buf *buf; 794656e7052SJohn Crispin dma_addr_t phys; 795656e7052SJohn Crispin struct mtk_tx_dma *next_free; 796656e7052SJohn Crispin struct mtk_tx_dma *last_free; 7974e6bf609SFelix Fietkau u32 last_free_ptr; 798656e7052SJohn Crispin u16 thresh; 799656e7052SJohn Crispin atomic_t free_count; 800296c9120SStefan Roese int dma_size; 801296c9120SStefan Roese struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 802296c9120SStefan Roese dma_addr_t phys_pdma; 803296c9120SStefan Roese int cpu_idx; 804656e7052SJohn Crispin }; 805656e7052SJohn Crispin 806ee406810SNelson Chang /* PDMA rx ring mode */ 807ee406810SNelson Chang enum mtk_rx_flags { 808ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0, 809ee406810SNelson Chang MTK_RX_FLAGS_HWLRO, 8106427dc1dSJohn Crispin MTK_RX_FLAGS_QDMA, 811ee406810SNelson Chang }; 812ee406810SNelson Chang 813656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 814656e7052SJohn Crispin * @dma: The descriptor ring 815656e7052SJohn Crispin * @data: The memory pointed at by the ring 816656e7052SJohn Crispin * @phys: The physical addr of rx_buf 817656e7052SJohn Crispin * @frag_size: How big can each fragment be 818656e7052SJohn Crispin * @buf_size: The size of each packet buffer 819656e7052SJohn Crispin * @calc_idx: The current head of ring 820656e7052SJohn Crispin */ 821656e7052SJohn Crispin struct mtk_rx_ring { 8227173eca8SLorenzo Bianconi void *dma; 823656e7052SJohn Crispin u8 **data; 824656e7052SJohn Crispin dma_addr_t phys; 825656e7052SJohn Crispin u16 frag_size; 826656e7052SJohn Crispin u16 buf_size; 827ee406810SNelson Chang u16 dma_size; 828ee406810SNelson Chang bool calc_idx_update; 829656e7052SJohn Crispin u16 calc_idx; 830ee406810SNelson Chang u32 crx_idx_reg; 83123233e57SLorenzo Bianconi /* page_pool */ 83223233e57SLorenzo Bianconi struct page_pool *page_pool; 83323233e57SLorenzo Bianconi struct xdp_rxq_info xdp_q; 834656e7052SJohn Crispin }; 835656e7052SJohn Crispin 836e2c74694SRené van Dorst enum mkt_eth_capabilities { 837e2c74694SRené van Dorst MTK_RGMII_BIT = 0, 838e2c74694SRené van Dorst MTK_TRGMII_BIT, 839e2c74694SRené van Dorst MTK_SGMII_BIT, 840e2c74694SRené van Dorst MTK_ESW_BIT, 841e2c74694SRené van Dorst MTK_GEPHY_BIT, 842e2c74694SRené van Dorst MTK_MUX_BIT, 843e2c74694SRené van Dorst MTK_INFRA_BIT, 844e2c74694SRené van Dorst MTK_SHARED_SGMII_BIT, 845e2c74694SRené van Dorst MTK_HWLRO_BIT, 846e2c74694SRené van Dorst MTK_SHARED_INT_BIT, 847e2c74694SRené van Dorst MTK_TRGMII_MT7621_CLK_BIT, 848296c9120SStefan Roese MTK_QDMA_BIT, 849160d3a9bSLorenzo Bianconi MTK_NETSYS_V2_BIT, 850296c9120SStefan Roese MTK_SOC_MT7628_BIT, 851160d3a9bSLorenzo Bianconi MTK_RSTCTRL_PPE1_BIT, 8527093f9d8SSean Wang 853e2c74694SRené van Dorst /* MUX BITS*/ 854e2c74694SRené van Dorst MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 855e2c74694SRené van Dorst MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 856e2c74694SRené van Dorst MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 857e2c74694SRené van Dorst MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 858e2c74694SRené van Dorst MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 859e2c74694SRené van Dorst 860e2c74694SRené van Dorst /* PATH BITS */ 861e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_RGMII_BIT, 862e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_TRGMII_BIT, 863e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_SGMII_BIT, 864e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_RGMII_BIT, 865e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_SGMII_BIT, 866e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_GEPHY_BIT, 867e2c74694SRené van Dorst MTK_ETH_PATH_GDM1_ESW_BIT, 8687093f9d8SSean Wang }; 8697093f9d8SSean Wang 8707093f9d8SSean Wang /* Supported hardware group on SoCs */ 871e2c74694SRené van Dorst #define MTK_RGMII BIT(MTK_RGMII_BIT) 872e2c74694SRené van Dorst #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 873e2c74694SRené van Dorst #define MTK_SGMII BIT(MTK_SGMII_BIT) 874e2c74694SRené van Dorst #define MTK_ESW BIT(MTK_ESW_BIT) 875e2c74694SRené van Dorst #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 876e2c74694SRené van Dorst #define MTK_MUX BIT(MTK_MUX_BIT) 877e2c74694SRené van Dorst #define MTK_INFRA BIT(MTK_INFRA_BIT) 878e2c74694SRené van Dorst #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 879e2c74694SRené van Dorst #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 880e2c74694SRené van Dorst #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 881e2c74694SRené van Dorst #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 882296c9120SStefan Roese #define MTK_QDMA BIT(MTK_QDMA_BIT) 883160d3a9bSLorenzo Bianconi #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) 884296c9120SStefan Roese #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 885160d3a9bSLorenzo Bianconi #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) 886e2c74694SRené van Dorst 887e2c74694SRené van Dorst #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 888e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 889e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 890e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 891e2c74694SRené van Dorst #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 892e2c74694SRené van Dorst BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 893e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 894e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 895e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 896e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 8977093f9d8SSean Wang 8987093f9d8SSean Wang /* Supported path present on SoCs */ 899e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 900e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 901e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 902e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 903e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 904e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 905e2c74694SRené van Dorst #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 9067093f9d8SSean Wang 907e2c74694SRené van Dorst #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 908e2c74694SRené van Dorst #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 909e2c74694SRené van Dorst #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 910e2c74694SRené van Dorst #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 911e2c74694SRené van Dorst #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 912e2c74694SRené van Dorst #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 913e2c74694SRené van Dorst #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 9147093f9d8SSean Wang 9157093f9d8SSean Wang /* MUXes present on SoCs */ 9167093f9d8SSean Wang /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 917e2c74694SRené van Dorst #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 9187093f9d8SSean Wang 9197093f9d8SSean Wang /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 9207093f9d8SSean Wang #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 921e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 9227093f9d8SSean Wang 9237093f9d8SSean Wang /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 9247093f9d8SSean Wang #define MTK_MUX_U3_GMAC2_TO_QPHY \ 925e2c74694SRené van Dorst (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 9267093f9d8SSean Wang 9277093f9d8SSean Wang /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 9287093f9d8SSean Wang #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 929e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 9307093f9d8SSean Wang MTK_SHARED_SGMII) 9317093f9d8SSean Wang 9327093f9d8SSean Wang /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 9337093f9d8SSean Wang #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 934e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 9357093f9d8SSean Wang 9362ec50f57SSean Wang #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 9372ec50f57SSean Wang 9388efaa653SRené van Dorst #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 939296c9120SStefan Roese MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 940296c9120SStefan Roese MTK_TRGMII_MT7621_CLK | MTK_QDMA) 9418efaa653SRené van Dorst 9427093f9d8SSean Wang #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 9437093f9d8SSean Wang MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 9447093f9d8SSean Wang MTK_MUX_GDM1_TO_GMAC1_ESW | \ 945296c9120SStefan Roese MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 9467093f9d8SSean Wang 947296c9120SStefan Roese #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 948296c9120SStefan Roese MTK_QDMA) 949296c9120SStefan Roese 950296c9120SStefan Roese #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 9517093f9d8SSean Wang 9527093f9d8SSean Wang #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 9537093f9d8SSean Wang MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 9547093f9d8SSean Wang MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 9557093f9d8SSean Wang MTK_MUX_U3_GMAC2_TO_QPHY | \ 956296c9120SStefan Roese MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 9577093f9d8SSean Wang 958197c9e9bSLorenzo Bianconi #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 959197c9e9bSLorenzo Bianconi MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 960197c9e9bSLorenzo Bianconi MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) 961197c9e9bSLorenzo Bianconi 962731f3fd6SLorenzo Bianconi struct mtk_tx_dma_desc_info { 963731f3fd6SLorenzo Bianconi dma_addr_t addr; 964731f3fd6SLorenzo Bianconi u32 size; 965731f3fd6SLorenzo Bianconi u16 vlan_tci; 966160d3a9bSLorenzo Bianconi u16 qid; 967731f3fd6SLorenzo Bianconi u8 gso:1; 968731f3fd6SLorenzo Bianconi u8 csum:1; 969731f3fd6SLorenzo Bianconi u8 vlan:1; 970731f3fd6SLorenzo Bianconi u8 first:1; 971731f3fd6SLorenzo Bianconi u8 last:1; 972731f3fd6SLorenzo Bianconi }; 973731f3fd6SLorenzo Bianconi 9748cb42714SLorenzo Bianconi struct mtk_reg_map { 9758cb42714SLorenzo Bianconi u32 tx_irq_mask; 9768cb42714SLorenzo Bianconi u32 tx_irq_status; 9778cb42714SLorenzo Bianconi struct { 9788cb42714SLorenzo Bianconi u32 rx_ptr; /* rx base pointer */ 9798cb42714SLorenzo Bianconi u32 rx_cnt_cfg; /* rx max count configuration */ 9808cb42714SLorenzo Bianconi u32 pcrx_ptr; /* rx cpu pointer */ 9818cb42714SLorenzo Bianconi u32 glo_cfg; /* global configuration */ 9828cb42714SLorenzo Bianconi u32 rst_idx; /* reset index */ 9838cb42714SLorenzo Bianconi u32 delay_irq; /* delay interrupt */ 9848cb42714SLorenzo Bianconi u32 irq_status; /* interrupt status */ 9858cb42714SLorenzo Bianconi u32 irq_mask; /* interrupt mask */ 986*93b2591aSLorenzo Bianconi u32 adma_rx_dbg0; 9878cb42714SLorenzo Bianconi u32 int_grp; 9888cb42714SLorenzo Bianconi } pdma; 9898cb42714SLorenzo Bianconi struct { 9908cb42714SLorenzo Bianconi u32 qtx_cfg; /* tx queue configuration */ 991f63959c7SFelix Fietkau u32 qtx_sch; /* tx queue scheduler configuration */ 9928cb42714SLorenzo Bianconi u32 rx_ptr; /* rx base pointer */ 9938cb42714SLorenzo Bianconi u32 rx_cnt_cfg; /* rx max count configuration */ 9948cb42714SLorenzo Bianconi u32 qcrx_ptr; /* rx cpu pointer */ 9958cb42714SLorenzo Bianconi u32 glo_cfg; /* global configuration */ 9968cb42714SLorenzo Bianconi u32 rst_idx; /* reset index */ 9978cb42714SLorenzo Bianconi u32 delay_irq; /* delay interrupt */ 9988cb42714SLorenzo Bianconi u32 fc_th; /* flow control */ 9998cb42714SLorenzo Bianconi u32 int_grp; 10008cb42714SLorenzo Bianconi u32 hred; /* interrupt mask */ 10018cb42714SLorenzo Bianconi u32 ctx_ptr; /* tx acquire cpu pointer */ 10028cb42714SLorenzo Bianconi u32 dtx_ptr; /* tx acquire dma pointer */ 10038cb42714SLorenzo Bianconi u32 crx_ptr; /* tx release cpu pointer */ 10048cb42714SLorenzo Bianconi u32 drx_ptr; /* tx release dma pointer */ 10058cb42714SLorenzo Bianconi u32 fq_head; /* fq head pointer */ 10068cb42714SLorenzo Bianconi u32 fq_tail; /* fq tail pointer */ 10078cb42714SLorenzo Bianconi u32 fq_count; /* fq free page count */ 10088cb42714SLorenzo Bianconi u32 fq_blen; /* fq free page buffer length */ 1009f63959c7SFelix Fietkau u32 tx_sch_rate; /* tx scheduler rate control registers */ 10108cb42714SLorenzo Bianconi } qdma; 10118cb42714SLorenzo Bianconi u32 gdm1_cnt; 1012329bce51SLorenzo Bianconi u32 gdma_to_ppe; 1013329bce51SLorenzo Bianconi u32 ppe_base; 10140c1d3fb9SLorenzo Bianconi u32 wdma_base[2]; 1015*93b2591aSLorenzo Bianconi u32 pse_iq_sta; 1016*93b2591aSLorenzo Bianconi u32 pse_oq_sta; 10178cb42714SLorenzo Bianconi }; 10188cb42714SLorenzo Bianconi 101942c03844SSean Wang /* struct mtk_eth_data - This is the structure holding all differences 10202ec50f57SSean Wang * among various plaforms 10218cb42714SLorenzo Bianconi * @reg_map Soc register map. 10229ffee4a8SSean Wang * @ana_rgc3: The offset for register ANA_RGC3 related to 10239ffee4a8SSean Wang * sgmiisys syscon 10242ec50f57SSean Wang * @caps Flags shown the extra capability for the SoC 1025296c9120SStefan Roese * @hw_features Flags shown HW features 10262ec50f57SSean Wang * @required_clks Flags shown the bitmap for required clocks on 10272ec50f57SSean Wang * the target SoC 1028243dc5fbSSean Wang * @required_pctl A bool value to show whether the SoC requires 1029243dc5fbSSean Wang * the extra setup for those pins used by GMAC. 1030ba2fc48cSLorenzo Bianconi * @hash_offset Flow table hash offset. 10319d8cb4c0SLorenzo Bianconi * @foe_entry_size Foe table entry size. 1032eb067347SLorenzo Bianconi * @txd_size Tx DMA descriptor size. 1033670ff7daSLorenzo Bianconi * @rxd_size Rx DMA descriptor size. 1034160d3a9bSLorenzo Bianconi * @rx_irq_done_mask Rx irq done register mask. 1035160d3a9bSLorenzo Bianconi * @rx_dma_l4_valid Rx DMA valid register mask. 1036160d3a9bSLorenzo Bianconi * @dma_max_len Max DMA tx/rx buffer length. 1037160d3a9bSLorenzo Bianconi * @dma_len_offset Tx/Rx DMA length field offset. 10382ec50f57SSean Wang */ 10392ec50f57SSean Wang struct mtk_soc_data { 10408cb42714SLorenzo Bianconi const struct mtk_reg_map *reg_map; 10419ffee4a8SSean Wang u32 ana_rgc3; 10422ec50f57SSean Wang u32 caps; 10432ec50f57SSean Wang u32 required_clks; 1044243dc5fbSSean Wang bool required_pctl; 1045ba37b7caSFelix Fietkau u8 offload_version; 1046ba2fc48cSLorenzo Bianconi u8 hash_offset; 10479d8cb4c0SLorenzo Bianconi u16 foe_entry_size; 1048296c9120SStefan Roese netdev_features_t hw_features; 1049eb067347SLorenzo Bianconi struct { 1050eb067347SLorenzo Bianconi u32 txd_size; 1051670ff7daSLorenzo Bianconi u32 rxd_size; 1052160d3a9bSLorenzo Bianconi u32 rx_irq_done_mask; 1053160d3a9bSLorenzo Bianconi u32 rx_dma_l4_valid; 1054160d3a9bSLorenzo Bianconi u32 dma_max_len; 1055160d3a9bSLorenzo Bianconi u32 dma_len_offset; 1056eb067347SLorenzo Bianconi } txrx; 10572ec50f57SSean Wang }; 10582ec50f57SSean Wang 1059*93b2591aSLorenzo Bianconi #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) 1060*93b2591aSLorenzo Bianconi 1061656e7052SJohn Crispin /* currently no SoC has more than 2 macs */ 1062656e7052SJohn Crispin #define MTK_MAX_DEVS 2 1063656e7052SJohn Crispin 1064901f3fbeSRussell King (Oracle) /* struct mtk_pcs - This structure holds each sgmii regmap and associated 1065901f3fbeSRussell King (Oracle) * data 10669ffee4a8SSean Wang * @regmap: The register map pointing at the range used to setup 10679ffee4a8SSean Wang * SGMII modes 10689ffee4a8SSean Wang * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 106914a44ab0SRussell King (Oracle) * @pcs: Phylink PCS structure 10709ffee4a8SSean Wang */ 1071901f3fbeSRussell King (Oracle) struct mtk_pcs { 1072901f3fbeSRussell King (Oracle) struct regmap *regmap; 10739ffee4a8SSean Wang u32 ana_rgc3; 107414a44ab0SRussell King (Oracle) struct phylink_pcs pcs; 10759ffee4a8SSean Wang }; 10769ffee4a8SSean Wang 1077901f3fbeSRussell King (Oracle) /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 1078901f3fbeSRussell King (Oracle) * characteristics 1079901f3fbeSRussell King (Oracle) * @pcs Array of individual PCS structures 1080901f3fbeSRussell King (Oracle) */ 1081901f3fbeSRussell King (Oracle) struct mtk_sgmii { 1082901f3fbeSRussell King (Oracle) struct mtk_pcs pcs[MTK_MAX_DEVS]; 1083901f3fbeSRussell King (Oracle) }; 1084901f3fbeSRussell King (Oracle) 1085656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 1086656e7052SJohn Crispin * of the driver 1087656e7052SJohn Crispin * @dev: The device pointer 1088d776a57eSFelix Fietkau * @dev: The device pointer used for dma mapping/alloc 1089656e7052SJohn Crispin * @base: The mapped register i/o base 1090656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 10915cce0322SJohn Crispin * @tx_irq__lock: Make sure that IRQ register operations are atomic 10925cce0322SJohn Crispin * @rx_irq__lock: Make sure that IRQ register operations are atomic 1093e9229ffdSFelix Fietkau * @dim_lock: Make sure that Net DIM operations are atomic 1094656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 1095656e7052SJohn Crispin * dummy for NAPI to work 1096656e7052SJohn Crispin * @netdev: The netdev instances 1097656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 1098656e7052SJohn Crispin * @irq: The IRQ that we are using 1099656e7052SJohn Crispin * @msg_enable: Ethtool msg level 1100656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 1101656e7052SJohn Crispin * MII modes 11027093f9d8SSean Wang * @infra: The register map pointing at the range used to setup 11037093f9d8SSean Wang * SGMII and GePHY path 1104656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 1105656e7052SJohn Crispin * GMAC port drive/slew values 1106656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 11070c07ce7fSJohn Crispin * @tx_ring: Pointer to the memory holding info about the TX ring 11080c07ce7fSJohn Crispin * @rx_ring: Pointer to the memory holding info about the RX ring 11096427dc1dSJohn Crispin * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 111080673029SJohn Crispin * @tx_napi: The TX NAPI struct 111180673029SJohn Crispin * @rx_napi: The RX NAPI struct 1112e9229ffdSFelix Fietkau * @rx_events: Net DIM RX event counter 1113e9229ffdSFelix Fietkau * @rx_packets: Net DIM RX packet counter 1114e9229ffdSFelix Fietkau * @rx_bytes: Net DIM RX byte counter 1115e9229ffdSFelix Fietkau * @rx_dim: Net DIM RX context 1116e9229ffdSFelix Fietkau * @tx_events: Net DIM TX event counter 1117e9229ffdSFelix Fietkau * @tx_packets: Net DIM TX packet counter 1118e9229ffdSFelix Fietkau * @tx_bytes: Net DIM TX byte counter 1119e9229ffdSFelix Fietkau * @tx_dim: Net DIM TX context 1120656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1121605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 1122656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 1123549e5495SSean Wang * @clks: clock array for all clocks required 1124656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 11257c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 112642c03844SSean Wang * @state: Initialization and runtime state of the device 11272ec50f57SSean Wang * @soc: Holding specific data among vaious SoCs 1128656e7052SJohn Crispin */ 1129656e7052SJohn Crispin 1130656e7052SJohn Crispin struct mtk_eth { 1131656e7052SJohn Crispin struct device *dev; 1132d776a57eSFelix Fietkau struct device *dma_dev; 1133656e7052SJohn Crispin void __iomem *base; 1134656e7052SJohn Crispin spinlock_t page_lock; 11355cce0322SJohn Crispin spinlock_t tx_irq_lock; 11365cce0322SJohn Crispin spinlock_t rx_irq_lock; 1137656e7052SJohn Crispin struct net_device dummy_dev; 1138656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 1139656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 114080673029SJohn Crispin int irq[3]; 1141656e7052SJohn Crispin u32 msg_enable; 1142656e7052SJohn Crispin unsigned long sysclk; 1143656e7052SJohn Crispin struct regmap *ethsys; 11447093f9d8SSean Wang struct regmap *infra; 11459ffee4a8SSean Wang struct mtk_sgmii *sgmii; 1146656e7052SJohn Crispin struct regmap *pctl; 1147ee406810SNelson Chang bool hwlro; 1148c6d4e63eSElena Reshetova refcount_t dma_refcnt; 1149656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 1150ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 11516427dc1dSJohn Crispin struct mtk_rx_ring rx_ring_qdma; 115280673029SJohn Crispin struct napi_struct tx_napi; 1153656e7052SJohn Crispin struct napi_struct rx_napi; 11544d642690SLorenzo Bianconi void *scratch_ring; 1155605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 1156656e7052SJohn Crispin void *scratch_head; 1157549e5495SSean Wang struct clk *clks[MTK_CLK_MAX]; 1158549e5495SSean Wang 1159656e7052SJohn Crispin struct mii_bus *mii_bus; 11607c78b4adSJohn Crispin struct work_struct pending_work; 11619ea4d311SSean Wang unsigned long state; 11622ec50f57SSean Wang 11632ec50f57SSean Wang const struct mtk_soc_data *soc; 1164296c9120SStefan Roese 1165e9229ffdSFelix Fietkau spinlock_t dim_lock; 1166e9229ffdSFelix Fietkau 1167e9229ffdSFelix Fietkau u32 rx_events; 1168e9229ffdSFelix Fietkau u32 rx_packets; 1169e9229ffdSFelix Fietkau u32 rx_bytes; 1170e9229ffdSFelix Fietkau struct dim rx_dim; 1171e9229ffdSFelix Fietkau 1172e9229ffdSFelix Fietkau u32 tx_events; 1173e9229ffdSFelix Fietkau u32 tx_packets; 1174e9229ffdSFelix Fietkau u32 tx_bytes; 1175e9229ffdSFelix Fietkau struct dim tx_dim; 1176e9229ffdSFelix Fietkau 1177296c9120SStefan Roese int ip_align; 1178ba37b7caSFelix Fietkau 11792d7605a7SFelix Fietkau struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS]; 11802d7605a7SFelix Fietkau 11814ff1a3fcSLorenzo Bianconi struct mtk_ppe *ppe[2]; 1182502e84e2SFelix Fietkau struct rhashtable flow_table; 11837c26c20dSLorenzo Bianconi 11847c26c20dSLorenzo Bianconi struct bpf_prog __rcu *prog; 1185*93b2591aSLorenzo Bianconi 1186*93b2591aSLorenzo Bianconi struct { 1187*93b2591aSLorenzo Bianconi struct delayed_work monitor_work; 1188*93b2591aSLorenzo Bianconi u32 wdidx; 1189*93b2591aSLorenzo Bianconi u8 wdma_hang_count; 1190*93b2591aSLorenzo Bianconi u8 qdma_hang_count; 1191*93b2591aSLorenzo Bianconi u8 adma_hang_count; 1192*93b2591aSLorenzo Bianconi } reset; 1193656e7052SJohn Crispin }; 1194656e7052SJohn Crispin 1195656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 1196656e7052SJohn Crispin * SoC 1197656e7052SJohn Crispin * @id: The number of the MAC 1198b8fc9f30SRené van Dorst * @interface: Interface mode kept for detecting change in hw settings 1199656e7052SJohn Crispin * @of_node: Our devicetree node 1200656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 1201656e7052SJohn Crispin * @hw_stats: Packet statistics counter 1202656e7052SJohn Crispin */ 1203656e7052SJohn Crispin struct mtk_mac { 1204656e7052SJohn Crispin int id; 1205b8fc9f30SRené van Dorst phy_interface_t interface; 1206b8fc9f30SRené van Dorst int speed; 1207656e7052SJohn Crispin struct device_node *of_node; 1208b8fc9f30SRené van Dorst struct phylink *phylink; 1209b8fc9f30SRené van Dorst struct phylink_config phylink_config; 1210656e7052SJohn Crispin struct mtk_eth *hw; 1211656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 1212ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1213ee406810SNelson Chang int hwlro_ip_cnt; 121421089867SRussell King (Oracle) unsigned int syscfg0; 1215f63959c7SFelix Fietkau struct notifier_block device_notifier; 1216656e7052SJohn Crispin }; 1217656e7052SJohn Crispin 1218656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1219656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 1220656e7052SJohn Crispin 12219d8cb4c0SLorenzo Bianconi static inline struct mtk_foe_entry * 12229d8cb4c0SLorenzo Bianconi mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 12239d8cb4c0SLorenzo Bianconi { 12249d8cb4c0SLorenzo Bianconi const struct mtk_soc_data *soc = ppe->eth->soc; 12259d8cb4c0SLorenzo Bianconi 12269d8cb4c0SLorenzo Bianconi return ppe->foe_table + hash * soc->foe_entry_size; 12279d8cb4c0SLorenzo Bianconi } 12289d8cb4c0SLorenzo Bianconi 122903a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 123003a3180eSLorenzo Bianconi { 123103a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 123203a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_TIMESTAMP_V2; 123303a3180eSLorenzo Bianconi 123403a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_TIMESTAMP; 123503a3180eSLorenzo Bianconi } 123603a3180eSLorenzo Bianconi 123703a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 123803a3180eSLorenzo Bianconi { 123903a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 124003a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_PPPOE_V2; 124103a3180eSLorenzo Bianconi 124203a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_PPPOE; 124303a3180eSLorenzo Bianconi } 124403a3180eSLorenzo Bianconi 124503a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 124603a3180eSLorenzo Bianconi { 124703a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 124803a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_TAG_V2; 124903a3180eSLorenzo Bianconi 125003a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_TAG; 125103a3180eSLorenzo Bianconi } 125203a3180eSLorenzo Bianconi 125303a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 125403a3180eSLorenzo Bianconi { 125503a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 125603a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; 125703a3180eSLorenzo Bianconi 125803a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_LAYER; 125903a3180eSLorenzo Bianconi } 126003a3180eSLorenzo Bianconi 126103a3180eSLorenzo Bianconi static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 126203a3180eSLorenzo Bianconi { 126303a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 126403a3180eSLorenzo Bianconi return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 126503a3180eSLorenzo Bianconi 126603a3180eSLorenzo Bianconi return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 126703a3180eSLorenzo Bianconi } 126803a3180eSLorenzo Bianconi 126903a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 127003a3180eSLorenzo Bianconi { 127103a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 127203a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 127303a3180eSLorenzo Bianconi 127403a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 127503a3180eSLorenzo Bianconi } 127603a3180eSLorenzo Bianconi 127703a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 127803a3180eSLorenzo Bianconi { 127903a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 128003a3180eSLorenzo Bianconi return MTK_FOE_IB1_PACKET_TYPE_V2; 128103a3180eSLorenzo Bianconi 128203a3180eSLorenzo Bianconi return MTK_FOE_IB1_PACKET_TYPE; 128303a3180eSLorenzo Bianconi } 128403a3180eSLorenzo Bianconi 128503a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 128603a3180eSLorenzo Bianconi { 128703a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 128803a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); 128903a3180eSLorenzo Bianconi 129003a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); 129103a3180eSLorenzo Bianconi } 129203a3180eSLorenzo Bianconi 129303a3180eSLorenzo Bianconi static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) 129403a3180eSLorenzo Bianconi { 129503a3180eSLorenzo Bianconi if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 129603a3180eSLorenzo Bianconi return MTK_FOE_IB2_MULTICAST_V2; 129703a3180eSLorenzo Bianconi 129803a3180eSLorenzo Bianconi return MTK_FOE_IB2_MULTICAST; 129903a3180eSLorenzo Bianconi } 130003a3180eSLorenzo Bianconi 1301656e7052SJohn Crispin /* read the hardware status register */ 1302656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 1303656e7052SJohn Crispin 1304656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1305656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1306656e7052SJohn Crispin 130714a44ab0SRussell King (Oracle) struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id); 13089ffee4a8SSean Wang int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 13099ffee4a8SSean Wang u32 ana_rgc3); 13107e538372SRené van Dorst 13117e538372SRené van Dorst int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 13127e538372SRené van Dorst int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 13137e538372SRené van Dorst int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 13149ffee4a8SSean Wang 1315502e84e2SFelix Fietkau int mtk_eth_offload_init(struct mtk_eth *eth); 1316502e84e2SFelix Fietkau int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1317502e84e2SFelix Fietkau void *type_data); 1318d776a57eSFelix Fietkau void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1319502e84e2SFelix Fietkau 1320502e84e2SFelix Fietkau 1321656e7052SJohn Crispin #endif /* MTK_ETH_H */ 1322