18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28e8e69d6SThomas Gleixner /* 3656e7052SJohn Crispin * 4656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7656e7052SJohn Crispin */ 8656e7052SJohn Crispin 9656e7052SJohn Crispin #ifndef MTK_ETH_H 10656e7052SJohn Crispin #define MTK_ETH_H 11656e7052SJohn Crispin 129ffee4a8SSean Wang #include <linux/dma-mapping.h> 139ffee4a8SSean Wang #include <linux/netdevice.h> 149ffee4a8SSean Wang #include <linux/of_net.h> 159ffee4a8SSean Wang #include <linux/u64_stats_sync.h> 16c6d4e63eSElena Reshetova #include <linux/refcount.h> 17b8fc9f30SRené van Dorst #include <linux/phylink.h> 18502e84e2SFelix Fietkau #include <linux/rhashtable.h> 19e9229ffdSFelix Fietkau #include <linux/dim.h> 20bc5e93e0SRussell King (Oracle) #include <linux/bitfield.h> 21ba37b7caSFelix Fietkau #include "mtk_ppe.h" 22c6d4e63eSElena Reshetova 23656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 24656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 254fd59792SDENG Qingfang #define MTK_MAX_RX_LENGTH_2K 2048 26656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 276b4423b2SFelix Fietkau #define MTK_DMA_SIZE 512 28656e7052SJohn Crispin #define MTK_MAC_COUNT 2 294fd59792SDENG Qingfang #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 30656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 31656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 32656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 33656e7052SJohn Crispin NETIF_MSG_PROBE | \ 34656e7052SJohn Crispin NETIF_MSG_LINK | \ 35656e7052SJohn Crispin NETIF_MSG_TIMER | \ 36656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 37656e7052SJohn Crispin NETIF_MSG_IFUP | \ 38656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 39656e7052SJohn Crispin NETIF_MSG_TX_ERR) 40656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 41656e7052SJohn Crispin NETIF_F_RXCSUM | \ 42656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 43656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_RX | \ 44656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 45656e7052SJohn Crispin NETIF_F_TSO6 | \ 46502e84e2SFelix Fietkau NETIF_F_IPV6_CSUM |\ 47502e84e2SFelix Fietkau NETIF_F_HW_TC) 48296c9120SStefan Roese #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 4908df5fa6SStefan Roese #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 50ee406810SNelson Chang 51ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4 52ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8 53ee406810SNelson Chang 54ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 55ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2 56ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 57ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 58ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 59ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 60ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64 61ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000 62ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000 63ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 64656e7052SJohn Crispin 65656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 66656e7052SJohn Crispin #define MTK_RST_GL 0x04 67656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 68656e7052SJohn Crispin 69656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 70656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 71656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 72656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 73656e7052SJohn Crispin 74ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */ 75ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 76ee406810SNelson Chang 77656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 78656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 79656e7052SJohn Crispin 8087e3df49SSean Wang /* CDMP Ingress Control Register */ 8187e3df49SSean Wang #define MTK_CDMQ_IG_CTRL 0x1400 8287e3df49SSean Wang #define MTK_CDMQ_STAG_EN BIT(0) 8387e3df49SSean Wang 84656e7052SJohn Crispin /* CDMP Exgress Control Register */ 85656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 86656e7052SJohn Crispin 87656e7052SJohn Crispin /* GDM Exgress Control Register */ 88656e7052SJohn Crispin #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 89d5c53da2SFelix Fietkau #define MTK_GDMA_SPECIAL_TAG BIT(24) 90656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 91656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 92656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 938d3f4a95SMarkLee #define MTK_GDMA_TO_PDMA 0x0 94ba37b7caSFelix Fietkau #define MTK_GDMA_TO_PPE 0x4444 958d66a818SMarkLee #define MTK_GDMA_DROP_ALL 0x7777 96656e7052SJohn Crispin 97656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 98656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 99656e7052SJohn Crispin 100656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 101656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 102656e7052SJohn Crispin 103bacfd110SNelson Chang /* PDMA RX Base Pointer Register */ 104bacfd110SNelson Chang #define MTK_PRX_BASE_PTR0 0x900 105ee406810SNelson Chang #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 106bacfd110SNelson Chang 107bacfd110SNelson Chang /* PDMA RX Maximum Count Register */ 108bacfd110SNelson Chang #define MTK_PRX_MAX_CNT0 0x904 109ee406810SNelson Chang #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 110bacfd110SNelson Chang 111bacfd110SNelson Chang /* PDMA RX CPU Pointer Register */ 112bacfd110SNelson Chang #define MTK_PRX_CRX_IDX0 0x908 113ee406810SNelson Chang #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 114ee406810SNelson Chang 115ee406810SNelson Chang /* PDMA HW LRO Control Registers */ 116ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980 117ee406810SNelson Chang #define MTK_LRO_EN BIT(0) 118ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7) 119ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 120ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 121ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 122ee406810SNelson Chang 123ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984 124ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988 125ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c 126ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15) 127ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 128bacfd110SNelson Chang 129bacfd110SNelson Chang /* PDMA Global Configuration Register */ 130bacfd110SNelson Chang #define MTK_PDMA_GLO_CFG 0xa04 131bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10) 132296c9120SStefan Roese #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 133bacfd110SNelson Chang 134bacfd110SNelson Chang /* PDMA Reset Index Register */ 135bacfd110SNelson Chang #define MTK_PDMA_RST_IDX 0xa08 136bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16) 137ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 138bacfd110SNelson Chang 139bacfd110SNelson Chang /* PDMA Delay Interrupt Register */ 140bacfd110SNelson Chang #define MTK_PDMA_DELAY_INT 0xa0c 141e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 142671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_EN BIT(15) 143671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 144e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 145e9229ffdSFelix Fietkau 146e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 147e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_EN BIT(31) 148e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 149e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 150e9229ffdSFelix Fietkau 151e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PINT_MASK 0x7f 152e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PTIME_MASK 0xff 153bacfd110SNelson Chang 154bacfd110SNelson Chang /* PDMA Interrupt Status Register */ 155bacfd110SNelson Chang #define MTK_PDMA_INT_STATUS 0xa20 156bacfd110SNelson Chang 157bacfd110SNelson Chang /* PDMA Interrupt Mask Register */ 158bacfd110SNelson Chang #define MTK_PDMA_INT_MASK 0xa28 159bacfd110SNelson Chang 160ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */ 161ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 162ee406810SNelson Chang 16380673029SJohn Crispin /* PDMA Interrupt grouping registers */ 16480673029SJohn Crispin #define MTK_PDMA_INT_GRP1 0xa50 16580673029SJohn Crispin #define MTK_PDMA_INT_GRP2 0xa54 16680673029SJohn Crispin 167ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */ 168ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 169ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 170ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9) 171ee406810SNelson Chang 172ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */ 173ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 174ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 175ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 176ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 177ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 178ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 179ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 180ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 181ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 182ee406810SNelson Chang #define MTK_RING_VLD BIT(8) 183ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 184ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 185ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 186ee406810SNelson Chang 187656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 188656e7052SJohn Crispin #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 189656e7052SJohn Crispin #define QDMA_RES_THRES 4 190656e7052SJohn Crispin 191656e7052SJohn Crispin /* QDMA TX Queue Scheduler Registers */ 192656e7052SJohn Crispin #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 193656e7052SJohn Crispin 194656e7052SJohn Crispin /* QDMA RX Base Pointer Register */ 195656e7052SJohn Crispin #define MTK_QRX_BASE_PTR0 0x1900 196656e7052SJohn Crispin 197656e7052SJohn Crispin /* QDMA RX Maximum Count Register */ 198656e7052SJohn Crispin #define MTK_QRX_MAX_CNT0 0x1904 199656e7052SJohn Crispin 200656e7052SJohn Crispin /* QDMA RX CPU Pointer Register */ 201656e7052SJohn Crispin #define MTK_QRX_CRX_IDX0 0x1908 202656e7052SJohn Crispin 203656e7052SJohn Crispin /* QDMA RX DMA Pointer Register */ 204656e7052SJohn Crispin #define MTK_QRX_DRX_IDX0 0x190C 205656e7052SJohn Crispin 206656e7052SJohn Crispin /* QDMA Global Configuration Register */ 207656e7052SJohn Crispin #define MTK_QDMA_GLO_CFG 0x1A04 208656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 209656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 2106675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 211656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 21259555a8dSFelix Fietkau #define MTK_TX_BT_32DWORDS (3 << 4) 213656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 214656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 215656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 216656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 2173bc8e0afSIlya Lipnitskiy #define MTK_DMA_BUSY_TIMEOUT_US 1000000 218656e7052SJohn Crispin 219656e7052SJohn Crispin /* QDMA Reset Index Register */ 220656e7052SJohn Crispin #define MTK_QDMA_RST_IDX 0x1A08 221656e7052SJohn Crispin 222656e7052SJohn Crispin /* QDMA Delay Interrupt Register */ 223656e7052SJohn Crispin #define MTK_QDMA_DELAY_INT 0x1A0C 224656e7052SJohn Crispin 225656e7052SJohn Crispin /* QDMA Flow Control Register */ 226656e7052SJohn Crispin #define MTK_QDMA_FC_THRES 0x1A10 227656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 228656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 229656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 230656e7052SJohn Crispin 231656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 23245487403SStefan Roese #define MTK_QDMA_INT_STATUS 0x1A18 233671d41e6SJohn Crispin #define MTK_RX_DONE_DLY BIT(30) 234e9229ffdSFelix Fietkau #define MTK_TX_DONE_DLY BIT(28) 235bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19) 236bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18) 237656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 238656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 239656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 240656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 241656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 242656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 243671d41e6SJohn Crispin #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 244e9229ffdSFelix Fietkau #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 245656e7052SJohn Crispin 24680673029SJohn Crispin /* QDMA Interrupt grouping registers */ 24780673029SJohn Crispin #define MTK_QDMA_INT_GRP1 0x1a20 24880673029SJohn Crispin #define MTK_QDMA_INT_GRP2 0x1a24 24980673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0) 25080673029SJohn Crispin 251656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 252656e7052SJohn Crispin #define MTK_QDMA_INT_MASK 0x1A1C 253656e7052SJohn Crispin 254656e7052SJohn Crispin /* QDMA Interrupt Mask Register */ 255656e7052SJohn Crispin #define MTK_QDMA_HRED2 0x1A44 256656e7052SJohn Crispin 257656e7052SJohn Crispin /* QDMA TX Forward CPU Pointer Register */ 258656e7052SJohn Crispin #define MTK_QTX_CTX_PTR 0x1B00 259656e7052SJohn Crispin 260656e7052SJohn Crispin /* QDMA TX Forward DMA Pointer Register */ 261656e7052SJohn Crispin #define MTK_QTX_DTX_PTR 0x1B04 262656e7052SJohn Crispin 263656e7052SJohn Crispin /* QDMA TX Release CPU Pointer Register */ 264656e7052SJohn Crispin #define MTK_QTX_CRX_PTR 0x1B10 265656e7052SJohn Crispin 266656e7052SJohn Crispin /* QDMA TX Release DMA Pointer Register */ 267656e7052SJohn Crispin #define MTK_QTX_DRX_PTR 0x1B14 268656e7052SJohn Crispin 269656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 270656e7052SJohn Crispin #define MTK_QDMA_FQ_HEAD 0x1B20 271656e7052SJohn Crispin 272656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 273656e7052SJohn Crispin #define MTK_QDMA_FQ_TAIL 0x1B24 274656e7052SJohn Crispin 275656e7052SJohn Crispin /* QDMA FQ Free Page Counter Register */ 276656e7052SJohn Crispin #define MTK_QDMA_FQ_CNT 0x1B28 277656e7052SJohn Crispin 278656e7052SJohn Crispin /* QDMA FQ Free Page Buffer Length Register */ 279656e7052SJohn Crispin #define MTK_QDMA_FQ_BLEN 0x1B2C 280656e7052SJohn Crispin 281ad79fd2cSStefan Roese /* GMA1 counter / statics register */ 282ad79fd2cSStefan Roese #define MTK_GDM1_RX_GBCNT_L 0x2400 283ad79fd2cSStefan Roese #define MTK_GDM1_RX_GBCNT_H 0x2404 284ad79fd2cSStefan Roese #define MTK_GDM1_RX_GPCNT 0x2408 285ad79fd2cSStefan Roese #define MTK_GDM1_RX_OERCNT 0x2410 286ad79fd2cSStefan Roese #define MTK_GDM1_RX_FERCNT 0x2414 287ad79fd2cSStefan Roese #define MTK_GDM1_RX_SERCNT 0x2418 288ad79fd2cSStefan Roese #define MTK_GDM1_RX_LENCNT 0x241c 289ad79fd2cSStefan Roese #define MTK_GDM1_RX_CERCNT 0x2420 290ad79fd2cSStefan Roese #define MTK_GDM1_RX_FCCNT 0x2424 291ad79fd2cSStefan Roese #define MTK_GDM1_TX_SKIPCNT 0x2428 292ad79fd2cSStefan Roese #define MTK_GDM1_TX_COLCNT 0x242c 293ad79fd2cSStefan Roese #define MTK_GDM1_TX_GBCNT_L 0x2430 294ad79fd2cSStefan Roese #define MTK_GDM1_TX_GBCNT_H 0x2434 295ad79fd2cSStefan Roese #define MTK_GDM1_TX_GPCNT 0x2438 296656e7052SJohn Crispin #define MTK_STAT_OFFSET 0x40 297656e7052SJohn Crispin 298804775dfSFelix Fietkau #define MTK_WDMA0_BASE 0x2800 299804775dfSFelix Fietkau #define MTK_WDMA1_BASE 0x2c00 300804775dfSFelix Fietkau 301656e7052SJohn Crispin /* QDMA descriptor txd4 */ 302656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 303656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 304656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 305656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 306656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 307656e7052SJohn Crispin 308656e7052SJohn Crispin /* QDMA descriptor txd3 */ 309656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 310656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 311656e7052SJohn Crispin #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 312296c9120SStefan Roese #define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN) 313656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 314656e7052SJohn Crispin #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 315656e7052SJohn Crispin 316296c9120SStefan Roese /* PDMA on MT7628 */ 317296c9120SStefan Roese #define TX_DMA_DONE BIT(31) 318296c9120SStefan Roese #define TX_DMA_LS1 BIT(14) 319296c9120SStefan Roese #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 320296c9120SStefan Roese 321656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 322656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 323296c9120SStefan Roese #define RX_DMA_LSO BIT(30) 324656e7052SJohn Crispin #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 325656e7052SJohn Crispin #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 3263f57d8c4SFelix Fietkau #define RX_DMA_VTAG BIT(15) 327656e7052SJohn Crispin 328656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 329656e7052SJohn Crispin #define RX_DMA_VID(_x) ((_x) & 0xfff) 330656e7052SJohn Crispin 331656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 332ba37b7caSFelix Fietkau #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 333ba37b7caSFelix Fietkau #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 334ba37b7caSFelix Fietkau #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 335ba37b7caSFelix Fietkau #define MTK_RXD4_ALG GENMASK(31, 22) 336ba37b7caSFelix Fietkau 337ba37b7caSFelix Fietkau /* QDMA descriptor rxd4 */ 338656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 339296c9120SStefan Roese #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 340656e7052SJohn Crispin #define RX_DMA_FPORT_SHIFT 19 341656e7052SJohn Crispin #define RX_DMA_FPORT_MASK 0x7 342d5c53da2SFelix Fietkau #define RX_DMA_SPECIAL_TAG BIT(22) 343656e7052SJohn Crispin 344656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 345656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 346656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 347eda80b24SDaniel Golle #define PHY_IAC_REG_MASK GENMASK(29, 25) 348eda80b24SDaniel Golle #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 349eda80b24SDaniel Golle #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 350eda80b24SDaniel Golle #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 351eda80b24SDaniel Golle #define PHY_IAC_CMD_MASK GENMASK(19, 18) 352e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 353eda80b24SDaniel Golle #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 354eda80b24SDaniel Golle #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 355e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 356eda80b24SDaniel Golle #define PHY_IAC_START_MASK GENMASK(17, 16) 357e2e7f6e2SDaniel Golle #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 358eda80b24SDaniel Golle #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 359eda80b24SDaniel Golle #define PHY_IAC_DATA_MASK GENMASK(15, 0) 360eda80b24SDaniel Golle #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 361656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 362656e7052SJohn Crispin 36342c03844SSean Wang #define MTK_MAC_MISC 0x1000c 36442c03844SSean Wang #define MTK_MUX_TO_ESW BIT(0) 36542c03844SSean Wang 366656e7052SJohn Crispin /* Mac control registers */ 367656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 3684fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 3694fd59792SDENG Qingfang #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 3704fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1518 0x0 3714fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1536 0x1 3724fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1552 0x2 3734fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_2048 0x3 374656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 375656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 376656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 377656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 378656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 379656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 380656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 381656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 382656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 383656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 384656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 385656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 386b8fc9f30SRené van Dorst #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 387b8fc9f30SRené van Dorst 388b8fc9f30SRené van Dorst /* Mac status registers */ 389b8fc9f30SRené van Dorst #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 390b8fc9f30SRené van Dorst #define MAC_MSR_EEE1G BIT(7) 391b8fc9f30SRené van Dorst #define MAC_MSR_EEE100M BIT(6) 392b8fc9f30SRené van Dorst #define MAC_MSR_RX_FC BIT(5) 393b8fc9f30SRené van Dorst #define MAC_MSR_TX_FC BIT(4) 394b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_1000 BIT(3) 395b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_100 BIT(2) 396b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 397b8fc9f30SRené van Dorst #define MAC_MSR_DPX BIT(1) 398b8fc9f30SRené van Dorst #define MAC_MSR_LINK BIT(0) 399656e7052SJohn Crispin 400f430dea7SSean Wang /* TRGMII RXC control register */ 401f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300 402f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 403f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 404f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 405a5d75538SRené van Dorst #define RXC_RST BIT(31) 406f430dea7SSean Wang #define RXC_DQSISEL BIT(30) 407f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 408f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 409f430dea7SSean Wang 410a5d75538SRené van Dorst #define NUM_TRGMII_CTRL 5 411a5d75538SRené van Dorst 412f430dea7SSean Wang /* TRGMII RXC control register */ 413f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340 414f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 415f430dea7SSean Wang #define TXC_INV BIT(30) 416f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 417f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 418f430dea7SSean Wang 419a5d75538SRené van Dorst /* TRGMII TX Drive Strength */ 420a5d75538SRené van Dorst #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 421a5d75538SRené van Dorst #define TD_DM_DRVP(x) ((x) & 0xf) 422a5d75538SRené van Dorst #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 423a5d75538SRené van Dorst 424f430dea7SSean Wang /* TRGMII Interface mode register */ 425f430dea7SSean Wang #define INTF_MODE 0x10390 426f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0) 427f430dea7SSean Wang #define TRGMII_MODE BIT(1) 428f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2) 429f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 430f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0 431f430dea7SSean Wang 432656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 433656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 434656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 435656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 436656e7052SJohn Crispin 437b95b6d99SNelson Chang /* ethernet subsystem chip id register */ 438b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0 439b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4 440983e1a6cSNelson Chang #define MT7623_ETH 7623 44142c03844SSean Wang #define MT7622_ETH 7622 442889bcbdeSBjørn Mork #define MT7621_ETH 7621 443b95b6d99SNelson Chang 4448efaa653SRené van Dorst /* ethernet system control register */ 4458efaa653SRené van Dorst #define ETHSYS_SYSCFG 0x10 4468efaa653SRené van Dorst #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 4478efaa653SRené van Dorst 448656e7052SJohn Crispin /* ethernet subsystem config register */ 449656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 450656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 451656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 4527093f9d8SSean Wang #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 4537093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 4547093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 4557093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 4567093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 4577093f9d8SSean Wang 458656e7052SJohn Crispin 459f430dea7SSean Wang /* ethernet subsystem clock register */ 460f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c 461f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 4628efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 4638efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 4648efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 465f430dea7SSean Wang 4662a8307aaSSean Wang /* ethernet reset control register */ 4672a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34 4682a8307aaSSean Wang #define RSTCTRL_FE BIT(6) 4692a8307aaSSean Wang #define RSTCTRL_PPE BIT(31) 4702a8307aaSSean Wang 471d776a57eSFelix Fietkau /* ethernet dma channel agent map */ 472d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP 0x408 473d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 474d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 475d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 476d776a57eSFelix Fietkau 47742c03844SSean Wang /* SGMII subsystem config registers */ 47842c03844SSean Wang /* Register to auto-negotiation restart */ 47942c03844SSean Wang #define SGMSYS_PCS_CONTROL_1 0x0 48042c03844SSean Wang #define SGMII_AN_RESTART BIT(9) 4817e538372SRené van Dorst #define SGMII_ISOLATE BIT(10) 4827e538372SRené van Dorst #define SGMII_AN_ENABLE BIT(12) 4837e538372SRené van Dorst #define SGMII_LINK_STATYS BIT(18) 4847e538372SRené van Dorst #define SGMII_AN_ABILITY BIT(19) 4857e538372SRené van Dorst #define SGMII_AN_COMPLETE BIT(21) 4867e538372SRené van Dorst #define SGMII_PCS_FAULT BIT(23) 4877e538372SRené van Dorst #define SGMII_AN_EXPANSION_CLR BIT(30) 48842c03844SSean Wang 48942c03844SSean Wang /* Register to programmable link timer, the unit in 2 * 8ns */ 49042c03844SSean Wang #define SGMSYS_PCS_LINK_TIMER 0x18 49142c03844SSean Wang #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 49242c03844SSean Wang 49342c03844SSean Wang /* Register to control remote fault */ 49442c03844SSean Wang #define SGMSYS_SGMII_MODE 0x20 4957e538372SRené van Dorst #define SGMII_IF_MODE_BIT0 BIT(0) 4967e538372SRené van Dorst #define SGMII_SPEED_DUPLEX_AN BIT(1) 497bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_MASK GENMASK(3, 2) 498bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) 499bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) 500bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) 5017e538372SRené van Dorst #define SGMII_DUPLEX_FULL BIT(4) 5027e538372SRené van Dorst #define SGMII_IF_MODE_BIT5 BIT(5) 50342c03844SSean Wang #define SGMII_REMOTE_FAULT_DIS BIT(8) 5047e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_VAL BIT(9) 5057e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_EN BIT(10) 5067e538372SRené van Dorst #define SGMII_SEND_AN_ERROR_EN BIT(11) 5077e538372SRené van Dorst #define SGMII_IF_MODE_MASK GENMASK(5, 1) 5087e538372SRené van Dorst 5097e538372SRené van Dorst /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 5107e538372SRené van Dorst #define SGMSYS_ANA_RG_CS3 0x2028 5117e538372SRené van Dorst #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 5127e538372SRené van Dorst #define RG_PHY_SPEED_1_25G 0x0 5137e538372SRené van Dorst #define RG_PHY_SPEED_3_125G BIT(2) 51442c03844SSean Wang 51542c03844SSean Wang /* Register to power up QPHY */ 51642c03844SSean Wang #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 51742c03844SSean Wang #define SGMII_PHYA_PWD BIT(4) 51842c03844SSean Wang 5197093f9d8SSean Wang /* Infrasys subsystem config registers */ 5207093f9d8SSean Wang #define INFRA_MISC2 0x70c 5217093f9d8SSean Wang #define CO_QPHY_SEL BIT(0) 5227093f9d8SSean Wang #define GEPHY_MAC_SEL BIT(1) 5237093f9d8SSean Wang 524296c9120SStefan Roese /* MT7628/88 specific stuff */ 525296c9120SStefan Roese #define MT7628_PDMA_OFFSET 0x0800 526296c9120SStefan Roese #define MT7628_SDM_OFFSET 0x0c00 527296c9120SStefan Roese 528296c9120SStefan Roese #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 529296c9120SStefan Roese #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 530296c9120SStefan Roese #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 531296c9120SStefan Roese #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 532296c9120SStefan Roese #define MT7628_PST_DTX_IDX0 BIT(0) 533296c9120SStefan Roese 534296c9120SStefan Roese #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 535296c9120SStefan Roese #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 536296c9120SStefan Roese 537ad79fd2cSStefan Roese /* Counter / stat register */ 538ad79fd2cSStefan Roese #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 539ad79fd2cSStefan Roese #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 540ad79fd2cSStefan Roese #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 541ad79fd2cSStefan Roese #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 542ad79fd2cSStefan Roese #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 543ad79fd2cSStefan Roese 544656e7052SJohn Crispin struct mtk_rx_dma { 545656e7052SJohn Crispin unsigned int rxd1; 546656e7052SJohn Crispin unsigned int rxd2; 547656e7052SJohn Crispin unsigned int rxd3; 548656e7052SJohn Crispin unsigned int rxd4; 549656e7052SJohn Crispin } __packed __aligned(4); 550656e7052SJohn Crispin 551656e7052SJohn Crispin struct mtk_tx_dma { 552656e7052SJohn Crispin unsigned int txd1; 553656e7052SJohn Crispin unsigned int txd2; 554656e7052SJohn Crispin unsigned int txd3; 555656e7052SJohn Crispin unsigned int txd4; 556656e7052SJohn Crispin } __packed __aligned(4); 557656e7052SJohn Crispin 558656e7052SJohn Crispin struct mtk_eth; 559656e7052SJohn Crispin struct mtk_mac; 560656e7052SJohn Crispin 561656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 562656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 563656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 564656e7052SJohn Crispin * @syncp: the refcount 565656e7052SJohn Crispin * 566656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 567656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 568656e7052SJohn Crispin * counters and store them in this struct. 569656e7052SJohn Crispin */ 570656e7052SJohn Crispin struct mtk_hw_stats { 571656e7052SJohn Crispin u64 tx_bytes; 572656e7052SJohn Crispin u64 tx_packets; 573656e7052SJohn Crispin u64 tx_skip; 574656e7052SJohn Crispin u64 tx_collisions; 575656e7052SJohn Crispin u64 rx_bytes; 576656e7052SJohn Crispin u64 rx_packets; 577656e7052SJohn Crispin u64 rx_overflow; 578656e7052SJohn Crispin u64 rx_fcs_errors; 579656e7052SJohn Crispin u64 rx_short_errors; 580656e7052SJohn Crispin u64 rx_long_errors; 581656e7052SJohn Crispin u64 rx_checksum_errors; 582656e7052SJohn Crispin u64 rx_flow_control_packets; 583656e7052SJohn Crispin 584656e7052SJohn Crispin spinlock_t stats_lock; 585656e7052SJohn Crispin u32 reg_offset; 586656e7052SJohn Crispin struct u64_stats_sync syncp; 587656e7052SJohn Crispin }; 588656e7052SJohn Crispin 589656e7052SJohn Crispin enum mtk_tx_flags { 590134d2152SSean Wang /* PDMA descriptor can point at 1-2 segments. This enum allows us to 591134d2152SSean Wang * track how memory was allocated so that it can be freed properly. 592134d2152SSean Wang */ 593656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 594656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 595134d2152SSean Wang 596134d2152SSean Wang /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 597134d2152SSean Wang * SKB out instead of looking up through hardware TX descriptor. 598134d2152SSean Wang */ 599134d2152SSean Wang MTK_TX_FLAGS_FPORT0 = 0x04, 600134d2152SSean Wang MTK_TX_FLAGS_FPORT1 = 0x08, 601656e7052SJohn Crispin }; 602656e7052SJohn Crispin 603549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the 604549e5495SSean Wang * clock in the order 605549e5495SSean Wang */ 606549e5495SSean Wang enum mtk_clks_map { 607549e5495SSean Wang MTK_CLK_ETHIF, 608d438e298SSean Wang MTK_CLK_SGMIITOP, 609549e5495SSean Wang MTK_CLK_ESW, 61042c03844SSean Wang MTK_CLK_GP0, 611549e5495SSean Wang MTK_CLK_GP1, 612549e5495SSean Wang MTK_CLK_GP2, 613d438e298SSean Wang MTK_CLK_FE, 614f430dea7SSean Wang MTK_CLK_TRGPLL, 61542c03844SSean Wang MTK_CLK_SGMII_TX_250M, 61642c03844SSean Wang MTK_CLK_SGMII_RX_250M, 61742c03844SSean Wang MTK_CLK_SGMII_CDR_REF, 61842c03844SSean Wang MTK_CLK_SGMII_CDR_FB, 619d438e298SSean Wang MTK_CLK_SGMII2_TX_250M, 620d438e298SSean Wang MTK_CLK_SGMII2_RX_250M, 621d438e298SSean Wang MTK_CLK_SGMII2_CDR_REF, 622d438e298SSean Wang MTK_CLK_SGMII2_CDR_FB, 62342c03844SSean Wang MTK_CLK_SGMII_CK, 62442c03844SSean Wang MTK_CLK_ETH2PLL, 625549e5495SSean Wang MTK_CLK_MAX 626549e5495SSean Wang }; 627549e5495SSean Wang 6282ec50f57SSean Wang #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 6292ec50f57SSean Wang BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 6302ec50f57SSean Wang BIT(MTK_CLK_TRGPLL)) 63142c03844SSean Wang #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 63242c03844SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 63342c03844SSean Wang BIT(MTK_CLK_GP2) | \ 63442c03844SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 63542c03844SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 63642c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 63742c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 63842c03844SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 63942c03844SSean Wang BIT(MTK_CLK_ETH2PLL)) 640889bcbdeSBjørn Mork #define MT7621_CLKS_BITMAP (0) 641296c9120SStefan Roese #define MT7628_CLKS_BITMAP (0) 642d438e298SSean Wang #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 643d438e298SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 644d438e298SSean Wang BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 645d438e298SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 646d438e298SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 647d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 648d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 649d438e298SSean Wang BIT(MTK_CLK_SGMII2_TX_250M) | \ 650d438e298SSean Wang BIT(MTK_CLK_SGMII2_RX_250M) | \ 651d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_REF) | \ 652d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_FB) | \ 653d438e298SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 654d438e298SSean Wang BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 655889bcbdeSBjørn Mork 6569ea4d311SSean Wang enum mtk_dev_state { 657dce6fa42SSean Wang MTK_HW_INIT, 658dce6fa42SSean Wang MTK_RESETTING 6599ea4d311SSean Wang }; 6609ea4d311SSean Wang 661656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 662656e7052SJohn Crispin * by the TX descriptor s 663656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 664656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 665656e7052SJohn Crispin * @dma_len0: The length of the first segment 666656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 667656e7052SJohn Crispin * @dma_len1: The length of the second segment 668656e7052SJohn Crispin */ 669656e7052SJohn Crispin struct mtk_tx_buf { 670656e7052SJohn Crispin struct sk_buff *skb; 671656e7052SJohn Crispin u32 flags; 672656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 673656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 674656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 675656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 676656e7052SJohn Crispin }; 677656e7052SJohn Crispin 678656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 679656e7052SJohn Crispin * @dma: The descriptor ring 680656e7052SJohn Crispin * @buf: The memory pointed at by the ring 681656e7052SJohn Crispin * @phys: The physical addr of tx_buf 682656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 683656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 6844e6bf609SFelix Fietkau * @last_free_ptr: Hardware pointer value of the last free descriptor 685656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 686656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 687656e7052SJohn Crispin * are present 688656e7052SJohn Crispin */ 689656e7052SJohn Crispin struct mtk_tx_ring { 690656e7052SJohn Crispin struct mtk_tx_dma *dma; 691656e7052SJohn Crispin struct mtk_tx_buf *buf; 692656e7052SJohn Crispin dma_addr_t phys; 693656e7052SJohn Crispin struct mtk_tx_dma *next_free; 694656e7052SJohn Crispin struct mtk_tx_dma *last_free; 6954e6bf609SFelix Fietkau u32 last_free_ptr; 696656e7052SJohn Crispin u16 thresh; 697656e7052SJohn Crispin atomic_t free_count; 698296c9120SStefan Roese int dma_size; 699296c9120SStefan Roese struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 700296c9120SStefan Roese dma_addr_t phys_pdma; 701296c9120SStefan Roese int cpu_idx; 702656e7052SJohn Crispin }; 703656e7052SJohn Crispin 704ee406810SNelson Chang /* PDMA rx ring mode */ 705ee406810SNelson Chang enum mtk_rx_flags { 706ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0, 707ee406810SNelson Chang MTK_RX_FLAGS_HWLRO, 7086427dc1dSJohn Crispin MTK_RX_FLAGS_QDMA, 709ee406810SNelson Chang }; 710ee406810SNelson Chang 711656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 712656e7052SJohn Crispin * @dma: The descriptor ring 713656e7052SJohn Crispin * @data: The memory pointed at by the ring 714656e7052SJohn Crispin * @phys: The physical addr of rx_buf 715656e7052SJohn Crispin * @frag_size: How big can each fragment be 716656e7052SJohn Crispin * @buf_size: The size of each packet buffer 717656e7052SJohn Crispin * @calc_idx: The current head of ring 718656e7052SJohn Crispin */ 719656e7052SJohn Crispin struct mtk_rx_ring { 720656e7052SJohn Crispin struct mtk_rx_dma *dma; 721656e7052SJohn Crispin u8 **data; 722656e7052SJohn Crispin dma_addr_t phys; 723656e7052SJohn Crispin u16 frag_size; 724656e7052SJohn Crispin u16 buf_size; 725ee406810SNelson Chang u16 dma_size; 726ee406810SNelson Chang bool calc_idx_update; 727656e7052SJohn Crispin u16 calc_idx; 728ee406810SNelson Chang u32 crx_idx_reg; 729656e7052SJohn Crispin }; 730656e7052SJohn Crispin 731e2c74694SRené van Dorst enum mkt_eth_capabilities { 732e2c74694SRené van Dorst MTK_RGMII_BIT = 0, 733e2c74694SRené van Dorst MTK_TRGMII_BIT, 734e2c74694SRené van Dorst MTK_SGMII_BIT, 735e2c74694SRené van Dorst MTK_ESW_BIT, 736e2c74694SRené van Dorst MTK_GEPHY_BIT, 737e2c74694SRené van Dorst MTK_MUX_BIT, 738e2c74694SRené van Dorst MTK_INFRA_BIT, 739e2c74694SRené van Dorst MTK_SHARED_SGMII_BIT, 740e2c74694SRené van Dorst MTK_HWLRO_BIT, 741e2c74694SRené van Dorst MTK_SHARED_INT_BIT, 742e2c74694SRené van Dorst MTK_TRGMII_MT7621_CLK_BIT, 743296c9120SStefan Roese MTK_QDMA_BIT, 744296c9120SStefan Roese MTK_SOC_MT7628_BIT, 7457093f9d8SSean Wang 746e2c74694SRené van Dorst /* MUX BITS*/ 747e2c74694SRené van Dorst MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 748e2c74694SRené van Dorst MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 749e2c74694SRené van Dorst MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 750e2c74694SRené van Dorst MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 751e2c74694SRené van Dorst MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 752e2c74694SRené van Dorst 753e2c74694SRené van Dorst /* PATH BITS */ 754e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_RGMII_BIT, 755e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_TRGMII_BIT, 756e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_SGMII_BIT, 757e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_RGMII_BIT, 758e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_SGMII_BIT, 759e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_GEPHY_BIT, 760e2c74694SRené van Dorst MTK_ETH_PATH_GDM1_ESW_BIT, 7617093f9d8SSean Wang }; 7627093f9d8SSean Wang 7637093f9d8SSean Wang /* Supported hardware group on SoCs */ 764e2c74694SRené van Dorst #define MTK_RGMII BIT(MTK_RGMII_BIT) 765e2c74694SRené van Dorst #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 766e2c74694SRené van Dorst #define MTK_SGMII BIT(MTK_SGMII_BIT) 767e2c74694SRené van Dorst #define MTK_ESW BIT(MTK_ESW_BIT) 768e2c74694SRené van Dorst #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 769e2c74694SRené van Dorst #define MTK_MUX BIT(MTK_MUX_BIT) 770e2c74694SRené van Dorst #define MTK_INFRA BIT(MTK_INFRA_BIT) 771e2c74694SRené van Dorst #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 772e2c74694SRené van Dorst #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 773e2c74694SRené van Dorst #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 774e2c74694SRené van Dorst #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 775296c9120SStefan Roese #define MTK_QDMA BIT(MTK_QDMA_BIT) 776296c9120SStefan Roese #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 777e2c74694SRené van Dorst 778e2c74694SRené van Dorst #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 779e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 780e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 781e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 782e2c74694SRené van Dorst #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 783e2c74694SRené van Dorst BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 784e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 785e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 786e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 787e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 7887093f9d8SSean Wang 7897093f9d8SSean Wang /* Supported path present on SoCs */ 790e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 791e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 792e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 793e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 794e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 795e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 796e2c74694SRené van Dorst #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 7977093f9d8SSean Wang 798e2c74694SRené van Dorst #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 799e2c74694SRené van Dorst #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 800e2c74694SRené van Dorst #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 801e2c74694SRené van Dorst #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 802e2c74694SRené van Dorst #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 803e2c74694SRené van Dorst #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 804e2c74694SRené van Dorst #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 8057093f9d8SSean Wang 8067093f9d8SSean Wang /* MUXes present on SoCs */ 8077093f9d8SSean Wang /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 808e2c74694SRené van Dorst #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 8097093f9d8SSean Wang 8107093f9d8SSean Wang /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 8117093f9d8SSean Wang #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 812e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 8137093f9d8SSean Wang 8147093f9d8SSean Wang /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 8157093f9d8SSean Wang #define MTK_MUX_U3_GMAC2_TO_QPHY \ 816e2c74694SRené van Dorst (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 8177093f9d8SSean Wang 8187093f9d8SSean Wang /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 8197093f9d8SSean Wang #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 820e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 8217093f9d8SSean Wang MTK_SHARED_SGMII) 8227093f9d8SSean Wang 8237093f9d8SSean Wang /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 8247093f9d8SSean Wang #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 825e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 8267093f9d8SSean Wang 8272ec50f57SSean Wang #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 8282ec50f57SSean Wang 8298efaa653SRené van Dorst #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 830296c9120SStefan Roese MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 831296c9120SStefan Roese MTK_TRGMII_MT7621_CLK | MTK_QDMA) 8328efaa653SRené van Dorst 8337093f9d8SSean Wang #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 8347093f9d8SSean Wang MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 8357093f9d8SSean Wang MTK_MUX_GDM1_TO_GMAC1_ESW | \ 836296c9120SStefan Roese MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 8377093f9d8SSean Wang 838296c9120SStefan Roese #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 839296c9120SStefan Roese MTK_QDMA) 840296c9120SStefan Roese 841296c9120SStefan Roese #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 8427093f9d8SSean Wang 8437093f9d8SSean Wang #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 8447093f9d8SSean Wang MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 8457093f9d8SSean Wang MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 8467093f9d8SSean Wang MTK_MUX_U3_GMAC2_TO_QPHY | \ 847296c9120SStefan Roese MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 8487093f9d8SSean Wang 84942c03844SSean Wang /* struct mtk_eth_data - This is the structure holding all differences 8502ec50f57SSean Wang * among various plaforms 8519ffee4a8SSean Wang * @ana_rgc3: The offset for register ANA_RGC3 related to 8529ffee4a8SSean Wang * sgmiisys syscon 8532ec50f57SSean Wang * @caps Flags shown the extra capability for the SoC 854296c9120SStefan Roese * @hw_features Flags shown HW features 8552ec50f57SSean Wang * @required_clks Flags shown the bitmap for required clocks on 8562ec50f57SSean Wang * the target SoC 857243dc5fbSSean Wang * @required_pctl A bool value to show whether the SoC requires 858243dc5fbSSean Wang * the extra setup for those pins used by GMAC. 8592ec50f57SSean Wang */ 8602ec50f57SSean Wang struct mtk_soc_data { 8619ffee4a8SSean Wang u32 ana_rgc3; 8622ec50f57SSean Wang u32 caps; 8632ec50f57SSean Wang u32 required_clks; 864243dc5fbSSean Wang bool required_pctl; 865ba37b7caSFelix Fietkau u8 offload_version; 866296c9120SStefan Roese netdev_features_t hw_features; 8672ec50f57SSean Wang }; 8682ec50f57SSean Wang 869656e7052SJohn Crispin /* currently no SoC has more than 2 macs */ 870656e7052SJohn Crispin #define MTK_MAX_DEVS 2 871656e7052SJohn Crispin 872*901f3fbeSRussell King (Oracle) /* struct mtk_pcs - This structure holds each sgmii regmap and associated 873*901f3fbeSRussell King (Oracle) * data 8749ffee4a8SSean Wang * @regmap: The register map pointing at the range used to setup 8759ffee4a8SSean Wang * SGMII modes 8769ffee4a8SSean Wang * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 8779ffee4a8SSean Wang */ 878*901f3fbeSRussell King (Oracle) struct mtk_pcs { 879*901f3fbeSRussell King (Oracle) struct regmap *regmap; 8809ffee4a8SSean Wang u32 ana_rgc3; 8819ffee4a8SSean Wang }; 8829ffee4a8SSean Wang 883*901f3fbeSRussell King (Oracle) /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 884*901f3fbeSRussell King (Oracle) * characteristics 885*901f3fbeSRussell King (Oracle) * @pcs Array of individual PCS structures 886*901f3fbeSRussell King (Oracle) */ 887*901f3fbeSRussell King (Oracle) struct mtk_sgmii { 888*901f3fbeSRussell King (Oracle) struct mtk_pcs pcs[MTK_MAX_DEVS]; 889*901f3fbeSRussell King (Oracle) }; 890*901f3fbeSRussell King (Oracle) 891656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 892656e7052SJohn Crispin * of the driver 893656e7052SJohn Crispin * @dev: The device pointer 894d776a57eSFelix Fietkau * @dev: The device pointer used for dma mapping/alloc 895656e7052SJohn Crispin * @base: The mapped register i/o base 896656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 8975cce0322SJohn Crispin * @tx_irq__lock: Make sure that IRQ register operations are atomic 8985cce0322SJohn Crispin * @rx_irq__lock: Make sure that IRQ register operations are atomic 899e9229ffdSFelix Fietkau * @dim_lock: Make sure that Net DIM operations are atomic 900656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 901656e7052SJohn Crispin * dummy for NAPI to work 902656e7052SJohn Crispin * @netdev: The netdev instances 903656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 904656e7052SJohn Crispin * @irq: The IRQ that we are using 905656e7052SJohn Crispin * @msg_enable: Ethtool msg level 906656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 907656e7052SJohn Crispin * MII modes 9087093f9d8SSean Wang * @infra: The register map pointing at the range used to setup 9097093f9d8SSean Wang * SGMII and GePHY path 910656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 911656e7052SJohn Crispin * GMAC port drive/slew values 912656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 9130c07ce7fSJohn Crispin * @tx_ring: Pointer to the memory holding info about the TX ring 9140c07ce7fSJohn Crispin * @rx_ring: Pointer to the memory holding info about the RX ring 9156427dc1dSJohn Crispin * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 91680673029SJohn Crispin * @tx_napi: The TX NAPI struct 91780673029SJohn Crispin * @rx_napi: The RX NAPI struct 918e9229ffdSFelix Fietkau * @rx_events: Net DIM RX event counter 919e9229ffdSFelix Fietkau * @rx_packets: Net DIM RX packet counter 920e9229ffdSFelix Fietkau * @rx_bytes: Net DIM RX byte counter 921e9229ffdSFelix Fietkau * @rx_dim: Net DIM RX context 922e9229ffdSFelix Fietkau * @tx_events: Net DIM TX event counter 923e9229ffdSFelix Fietkau * @tx_packets: Net DIM TX packet counter 924e9229ffdSFelix Fietkau * @tx_bytes: Net DIM TX byte counter 925e9229ffdSFelix Fietkau * @tx_dim: Net DIM TX context 926656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 927605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 928656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 929549e5495SSean Wang * @clks: clock array for all clocks required 930656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 9317c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 93242c03844SSean Wang * @state: Initialization and runtime state of the device 9332ec50f57SSean Wang * @soc: Holding specific data among vaious SoCs 934656e7052SJohn Crispin */ 935656e7052SJohn Crispin 936656e7052SJohn Crispin struct mtk_eth { 937656e7052SJohn Crispin struct device *dev; 938d776a57eSFelix Fietkau struct device *dma_dev; 939656e7052SJohn Crispin void __iomem *base; 940656e7052SJohn Crispin spinlock_t page_lock; 9415cce0322SJohn Crispin spinlock_t tx_irq_lock; 9425cce0322SJohn Crispin spinlock_t rx_irq_lock; 943656e7052SJohn Crispin struct net_device dummy_dev; 944656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 945656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 94680673029SJohn Crispin int irq[3]; 947656e7052SJohn Crispin u32 msg_enable; 948656e7052SJohn Crispin unsigned long sysclk; 949656e7052SJohn Crispin struct regmap *ethsys; 9507093f9d8SSean Wang struct regmap *infra; 9519ffee4a8SSean Wang struct mtk_sgmii *sgmii; 952656e7052SJohn Crispin struct regmap *pctl; 953ee406810SNelson Chang bool hwlro; 954c6d4e63eSElena Reshetova refcount_t dma_refcnt; 955656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 956ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 9576427dc1dSJohn Crispin struct mtk_rx_ring rx_ring_qdma; 95880673029SJohn Crispin struct napi_struct tx_napi; 959656e7052SJohn Crispin struct napi_struct rx_napi; 960656e7052SJohn Crispin struct mtk_tx_dma *scratch_ring; 961605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 962656e7052SJohn Crispin void *scratch_head; 963549e5495SSean Wang struct clk *clks[MTK_CLK_MAX]; 964549e5495SSean Wang 965656e7052SJohn Crispin struct mii_bus *mii_bus; 9667c78b4adSJohn Crispin struct work_struct pending_work; 9679ea4d311SSean Wang unsigned long state; 9682ec50f57SSean Wang 9692ec50f57SSean Wang const struct mtk_soc_data *soc; 970296c9120SStefan Roese 971e9229ffdSFelix Fietkau spinlock_t dim_lock; 972e9229ffdSFelix Fietkau 973e9229ffdSFelix Fietkau u32 rx_events; 974e9229ffdSFelix Fietkau u32 rx_packets; 975e9229ffdSFelix Fietkau u32 rx_bytes; 976e9229ffdSFelix Fietkau struct dim rx_dim; 977e9229ffdSFelix Fietkau 978e9229ffdSFelix Fietkau u32 tx_events; 979e9229ffdSFelix Fietkau u32 tx_packets; 980e9229ffdSFelix Fietkau u32 tx_bytes; 981e9229ffdSFelix Fietkau struct dim tx_dim; 982e9229ffdSFelix Fietkau 983296c9120SStefan Roese u32 tx_int_mask_reg; 984296c9120SStefan Roese u32 tx_int_status_reg; 985296c9120SStefan Roese u32 rx_dma_l4_valid; 986296c9120SStefan Roese int ip_align; 987ba37b7caSFelix Fietkau 9881ccc723bSFelix Fietkau struct mtk_ppe *ppe; 989502e84e2SFelix Fietkau struct rhashtable flow_table; 990656e7052SJohn Crispin }; 991656e7052SJohn Crispin 992656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 993656e7052SJohn Crispin * SoC 994656e7052SJohn Crispin * @id: The number of the MAC 995b8fc9f30SRené van Dorst * @interface: Interface mode kept for detecting change in hw settings 996656e7052SJohn Crispin * @of_node: Our devicetree node 997656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 998656e7052SJohn Crispin * @hw_stats: Packet statistics counter 999656e7052SJohn Crispin */ 1000656e7052SJohn Crispin struct mtk_mac { 1001656e7052SJohn Crispin int id; 1002b8fc9f30SRené van Dorst phy_interface_t interface; 1003b8fc9f30SRené van Dorst int speed; 1004656e7052SJohn Crispin struct device_node *of_node; 1005b8fc9f30SRené van Dorst struct phylink *phylink; 1006b8fc9f30SRené van Dorst struct phylink_config phylink_config; 1007656e7052SJohn Crispin struct mtk_eth *hw; 1008656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 1009ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1010ee406810SNelson Chang int hwlro_ip_cnt; 101121089867SRussell King (Oracle) unsigned int syscfg0; 1012656e7052SJohn Crispin }; 1013656e7052SJohn Crispin 1014656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1015656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 1016656e7052SJohn Crispin 1017656e7052SJohn Crispin /* read the hardware status register */ 1018656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 1019656e7052SJohn Crispin 1020656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1021656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1022656e7052SJohn Crispin 10239ffee4a8SSean Wang int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 10249ffee4a8SSean Wang u32 ana_rgc3); 10251ec619eeSRussell King (Oracle) int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode, 10264ce5a0bdSRussell King (Oracle) phy_interface_t interface); 1027a4591873SRussell King void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex); 10287e538372SRené van Dorst void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); 10297e538372SRené van Dorst 10307e538372SRené van Dorst int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 10317e538372SRené van Dorst int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 10327e538372SRené van Dorst int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 10339ffee4a8SSean Wang 1034502e84e2SFelix Fietkau int mtk_eth_offload_init(struct mtk_eth *eth); 1035502e84e2SFelix Fietkau int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1036502e84e2SFelix Fietkau void *type_data); 1037d776a57eSFelix Fietkau void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1038502e84e2SFelix Fietkau 1039502e84e2SFelix Fietkau 1040656e7052SJohn Crispin #endif /* MTK_ETH_H */ 1041