18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28e8e69d6SThomas Gleixner /* 3656e7052SJohn Crispin * 4656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7656e7052SJohn Crispin */ 8656e7052SJohn Crispin 9656e7052SJohn Crispin #ifndef MTK_ETH_H 10656e7052SJohn Crispin #define MTK_ETH_H 11656e7052SJohn Crispin 12c6d4e63eSElena Reshetova #include <linux/refcount.h> 13c6d4e63eSElena Reshetova 14656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 15656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 16656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 17656e7052SJohn Crispin #define MTK_DMA_SIZE 256 18656e7052SJohn Crispin #define MTK_NAPI_WEIGHT 64 19656e7052SJohn Crispin #define MTK_MAC_COUNT 2 20656e7052SJohn Crispin #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 21656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 22656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 23656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 24656e7052SJohn Crispin NETIF_MSG_PROBE | \ 25656e7052SJohn Crispin NETIF_MSG_LINK | \ 26656e7052SJohn Crispin NETIF_MSG_TIMER | \ 27656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 28656e7052SJohn Crispin NETIF_MSG_IFUP | \ 29656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 30656e7052SJohn Crispin NETIF_MSG_TX_ERR) 31656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 32656e7052SJohn Crispin NETIF_F_RXCSUM | \ 33656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 34656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_RX | \ 35656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 36656e7052SJohn Crispin NETIF_F_TSO6 | \ 37656e7052SJohn Crispin NETIF_F_IPV6_CSUM) 38ee406810SNelson Chang #define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 39ee406810SNelson Chang 40ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4 41ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8 42ee406810SNelson Chang 43ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 44ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2 45ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 46ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 47ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 48ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 49ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64 50ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000 51ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000 52ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 53656e7052SJohn Crispin 54656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 55656e7052SJohn Crispin #define MTK_RST_GL 0x04 56656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 57656e7052SJohn Crispin 58656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 59656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 60656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 61656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 62656e7052SJohn Crispin 63ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */ 64ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 65ee406810SNelson Chang 66656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 67656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 68656e7052SJohn Crispin 6987e3df49SSean Wang /* CDMP Ingress Control Register */ 7087e3df49SSean Wang #define MTK_CDMQ_IG_CTRL 0x1400 7187e3df49SSean Wang #define MTK_CDMQ_STAG_EN BIT(0) 7287e3df49SSean Wang 73656e7052SJohn Crispin /* CDMP Exgress Control Register */ 74656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 75656e7052SJohn Crispin 76656e7052SJohn Crispin /* GDM Exgress Control Register */ 77656e7052SJohn Crispin #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 78656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 79656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 80656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 81656e7052SJohn Crispin 82656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 83656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 84656e7052SJohn Crispin 85656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 86656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 87656e7052SJohn Crispin 88bacfd110SNelson Chang /* PDMA RX Base Pointer Register */ 89bacfd110SNelson Chang #define MTK_PRX_BASE_PTR0 0x900 90ee406810SNelson Chang #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 91bacfd110SNelson Chang 92bacfd110SNelson Chang /* PDMA RX Maximum Count Register */ 93bacfd110SNelson Chang #define MTK_PRX_MAX_CNT0 0x904 94ee406810SNelson Chang #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 95bacfd110SNelson Chang 96bacfd110SNelson Chang /* PDMA RX CPU Pointer Register */ 97bacfd110SNelson Chang #define MTK_PRX_CRX_IDX0 0x908 98ee406810SNelson Chang #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 99ee406810SNelson Chang 100ee406810SNelson Chang /* PDMA HW LRO Control Registers */ 101ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980 102ee406810SNelson Chang #define MTK_LRO_EN BIT(0) 103ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7) 104ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 105ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 106ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 107ee406810SNelson Chang 108ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984 109ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988 110ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c 111ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15) 112ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 113bacfd110SNelson Chang 114bacfd110SNelson Chang /* PDMA Global Configuration Register */ 115bacfd110SNelson Chang #define MTK_PDMA_GLO_CFG 0xa04 116bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10) 117bacfd110SNelson Chang 118bacfd110SNelson Chang /* PDMA Reset Index Register */ 119bacfd110SNelson Chang #define MTK_PDMA_RST_IDX 0xa08 120bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16) 121ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 122bacfd110SNelson Chang 123bacfd110SNelson Chang /* PDMA Delay Interrupt Register */ 124bacfd110SNelson Chang #define MTK_PDMA_DELAY_INT 0xa0c 125671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_EN BIT(15) 126671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT 4 127671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 128671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PTIME 4 129671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_DELAY \ 130671d41e6SJohn Crispin (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ 131671d41e6SJohn Crispin (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) 132bacfd110SNelson Chang 133bacfd110SNelson Chang /* PDMA Interrupt Status Register */ 134bacfd110SNelson Chang #define MTK_PDMA_INT_STATUS 0xa20 135bacfd110SNelson Chang 136bacfd110SNelson Chang /* PDMA Interrupt Mask Register */ 137bacfd110SNelson Chang #define MTK_PDMA_INT_MASK 0xa28 138bacfd110SNelson Chang 139ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */ 140ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 141ee406810SNelson Chang 14280673029SJohn Crispin /* PDMA Interrupt grouping registers */ 14380673029SJohn Crispin #define MTK_PDMA_INT_GRP1 0xa50 14480673029SJohn Crispin #define MTK_PDMA_INT_GRP2 0xa54 14580673029SJohn Crispin 146ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */ 147ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 148ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 149ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9) 150ee406810SNelson Chang 151ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */ 152ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 153ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 154ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 155ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 156ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 157ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 158ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 159ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 160ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 161ee406810SNelson Chang #define MTK_RING_VLD BIT(8) 162ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 163ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 164ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 165ee406810SNelson Chang 166656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 167656e7052SJohn Crispin #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 168656e7052SJohn Crispin #define QDMA_RES_THRES 4 169656e7052SJohn Crispin 170656e7052SJohn Crispin /* QDMA TX Queue Scheduler Registers */ 171656e7052SJohn Crispin #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 172656e7052SJohn Crispin 173656e7052SJohn Crispin /* QDMA RX Base Pointer Register */ 174656e7052SJohn Crispin #define MTK_QRX_BASE_PTR0 0x1900 175656e7052SJohn Crispin 176656e7052SJohn Crispin /* QDMA RX Maximum Count Register */ 177656e7052SJohn Crispin #define MTK_QRX_MAX_CNT0 0x1904 178656e7052SJohn Crispin 179656e7052SJohn Crispin /* QDMA RX CPU Pointer Register */ 180656e7052SJohn Crispin #define MTK_QRX_CRX_IDX0 0x1908 181656e7052SJohn Crispin 182656e7052SJohn Crispin /* QDMA RX DMA Pointer Register */ 183656e7052SJohn Crispin #define MTK_QRX_DRX_IDX0 0x190C 184656e7052SJohn Crispin 185656e7052SJohn Crispin /* QDMA Global Configuration Register */ 186656e7052SJohn Crispin #define MTK_QDMA_GLO_CFG 0x1A04 187656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 188656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 1896675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 190656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 191656e7052SJohn Crispin #define MTK_DMA_SIZE_16DWORDS (2 << 4) 192656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 193656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 194656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 195656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 196656e7052SJohn Crispin #define MTK_DMA_BUSY_TIMEOUT HZ 197656e7052SJohn Crispin 198656e7052SJohn Crispin /* QDMA Reset Index Register */ 199656e7052SJohn Crispin #define MTK_QDMA_RST_IDX 0x1A08 200656e7052SJohn Crispin 201656e7052SJohn Crispin /* QDMA Delay Interrupt Register */ 202656e7052SJohn Crispin #define MTK_QDMA_DELAY_INT 0x1A0C 203656e7052SJohn Crispin 204656e7052SJohn Crispin /* QDMA Flow Control Register */ 205656e7052SJohn Crispin #define MTK_QDMA_FC_THRES 0x1A10 206656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 207656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 208656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 209656e7052SJohn Crispin 210656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 211656e7052SJohn Crispin #define MTK_QMTK_INT_STATUS 0x1A18 212671d41e6SJohn Crispin #define MTK_RX_DONE_DLY BIT(30) 213bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19) 214bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18) 215656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 216656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 217656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 218656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 219656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 220656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 221671d41e6SJohn Crispin #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 222656e7052SJohn Crispin #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 223656e7052SJohn Crispin MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 224656e7052SJohn Crispin 22580673029SJohn Crispin /* QDMA Interrupt grouping registers */ 22680673029SJohn Crispin #define MTK_QDMA_INT_GRP1 0x1a20 22780673029SJohn Crispin #define MTK_QDMA_INT_GRP2 0x1a24 22880673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0) 22980673029SJohn Crispin 230656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 231656e7052SJohn Crispin #define MTK_QDMA_INT_MASK 0x1A1C 232656e7052SJohn Crispin 233656e7052SJohn Crispin /* QDMA Interrupt Mask Register */ 234656e7052SJohn Crispin #define MTK_QDMA_HRED2 0x1A44 235656e7052SJohn Crispin 236656e7052SJohn Crispin /* QDMA TX Forward CPU Pointer Register */ 237656e7052SJohn Crispin #define MTK_QTX_CTX_PTR 0x1B00 238656e7052SJohn Crispin 239656e7052SJohn Crispin /* QDMA TX Forward DMA Pointer Register */ 240656e7052SJohn Crispin #define MTK_QTX_DTX_PTR 0x1B04 241656e7052SJohn Crispin 242656e7052SJohn Crispin /* QDMA TX Release CPU Pointer Register */ 243656e7052SJohn Crispin #define MTK_QTX_CRX_PTR 0x1B10 244656e7052SJohn Crispin 245656e7052SJohn Crispin /* QDMA TX Release DMA Pointer Register */ 246656e7052SJohn Crispin #define MTK_QTX_DRX_PTR 0x1B14 247656e7052SJohn Crispin 248656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 249656e7052SJohn Crispin #define MTK_QDMA_FQ_HEAD 0x1B20 250656e7052SJohn Crispin 251656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 252656e7052SJohn Crispin #define MTK_QDMA_FQ_TAIL 0x1B24 253656e7052SJohn Crispin 254656e7052SJohn Crispin /* QDMA FQ Free Page Counter Register */ 255656e7052SJohn Crispin #define MTK_QDMA_FQ_CNT 0x1B28 256656e7052SJohn Crispin 257656e7052SJohn Crispin /* QDMA FQ Free Page Buffer Length Register */ 258656e7052SJohn Crispin #define MTK_QDMA_FQ_BLEN 0x1B2C 259656e7052SJohn Crispin 260656e7052SJohn Crispin /* GMA1 Received Good Byte Count Register */ 261656e7052SJohn Crispin #define MTK_GDM1_TX_GBCNT 0x2400 262656e7052SJohn Crispin #define MTK_STAT_OFFSET 0x40 263656e7052SJohn Crispin 264656e7052SJohn Crispin /* QDMA descriptor txd4 */ 265656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 266656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 267656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 268656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 269656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 270656e7052SJohn Crispin 271656e7052SJohn Crispin /* QDMA descriptor txd3 */ 272656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 273656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 274656e7052SJohn Crispin #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 275656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 276656e7052SJohn Crispin #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 277656e7052SJohn Crispin 278656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 279656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 280656e7052SJohn Crispin #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 281656e7052SJohn Crispin #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 282656e7052SJohn Crispin 283656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 284656e7052SJohn Crispin #define RX_DMA_VID(_x) ((_x) & 0xfff) 285656e7052SJohn Crispin 286656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 287656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 288656e7052SJohn Crispin #define RX_DMA_FPORT_SHIFT 19 289656e7052SJohn Crispin #define RX_DMA_FPORT_MASK 0x7 290656e7052SJohn Crispin 291656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 292656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 293656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 294656e7052SJohn Crispin #define PHY_IAC_READ BIT(19) 295656e7052SJohn Crispin #define PHY_IAC_WRITE BIT(18) 296656e7052SJohn Crispin #define PHY_IAC_START BIT(16) 297656e7052SJohn Crispin #define PHY_IAC_ADDR_SHIFT 20 298656e7052SJohn Crispin #define PHY_IAC_REG_SHIFT 25 299656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 300656e7052SJohn Crispin 30142c03844SSean Wang #define MTK_MAC_MISC 0x1000c 30242c03844SSean Wang #define MTK_MUX_TO_ESW BIT(0) 30342c03844SSean Wang 304656e7052SJohn Crispin /* Mac control registers */ 305656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 306656e7052SJohn Crispin #define MAC_MCR_MAX_RX_1536 BIT(24) 307656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 308656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 309656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 310656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 311656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 312656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 313656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 314656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 315656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 316656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 317656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 318656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 319656e7052SJohn Crispin #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ 320656e7052SJohn Crispin MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ 321656e7052SJohn Crispin MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ 322656e7052SJohn Crispin MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ 323656e7052SJohn Crispin MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ 324656e7052SJohn Crispin MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) 325656e7052SJohn Crispin 326f430dea7SSean Wang /* TRGMII RXC control register */ 327f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300 328f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 329f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 330f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 331f430dea7SSean Wang #define RXC_DQSISEL BIT(30) 332f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 333f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 334f430dea7SSean Wang 335f430dea7SSean Wang /* TRGMII RXC control register */ 336f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340 337f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 338f430dea7SSean Wang #define TXC_INV BIT(30) 339f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 340f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 341f430dea7SSean Wang 342f430dea7SSean Wang /* TRGMII Interface mode register */ 343f430dea7SSean Wang #define INTF_MODE 0x10390 344f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0) 345f430dea7SSean Wang #define TRGMII_MODE BIT(1) 346f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2) 347f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 348f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0 349f430dea7SSean Wang 350656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 351656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 352656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 353656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 354656e7052SJohn Crispin 355b95b6d99SNelson Chang /* ethernet subsystem chip id register */ 356b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0 357b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4 358983e1a6cSNelson Chang #define MT7623_ETH 7623 35942c03844SSean Wang #define MT7622_ETH 7622 360889bcbdeSBjørn Mork #define MT7621_ETH 7621 361b95b6d99SNelson Chang 362656e7052SJohn Crispin /* ethernet subsystem config register */ 363656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 364656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 365656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 36642c03844SSean Wang #define SYSCFG0_SGMII_MASK (3 << 8) 36742c03844SSean Wang #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & GENMASK(9, 8)) 36842c03844SSean Wang #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & GENMASK(9, 8)) 369656e7052SJohn Crispin 370f430dea7SSean Wang /* ethernet subsystem clock register */ 371f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c 372f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 373f430dea7SSean Wang 3742a8307aaSSean Wang /* ethernet reset control register */ 3752a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34 3762a8307aaSSean Wang #define RSTCTRL_FE BIT(6) 3772a8307aaSSean Wang #define RSTCTRL_PPE BIT(31) 3782a8307aaSSean Wang 37942c03844SSean Wang /* SGMII subsystem config registers */ 38042c03844SSean Wang /* Register to auto-negotiation restart */ 38142c03844SSean Wang #define SGMSYS_PCS_CONTROL_1 0x0 38242c03844SSean Wang #define SGMII_AN_RESTART BIT(9) 38342c03844SSean Wang 38442c03844SSean Wang /* Register to programmable link timer, the unit in 2 * 8ns */ 38542c03844SSean Wang #define SGMSYS_PCS_LINK_TIMER 0x18 38642c03844SSean Wang #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 38742c03844SSean Wang 38842c03844SSean Wang /* Register to control remote fault */ 38942c03844SSean Wang #define SGMSYS_SGMII_MODE 0x20 39042c03844SSean Wang #define SGMII_REMOTE_FAULT_DIS BIT(8) 39142c03844SSean Wang 39242c03844SSean Wang /* Register to power up QPHY */ 39342c03844SSean Wang #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 39442c03844SSean Wang #define SGMII_PHYA_PWD BIT(4) 39542c03844SSean Wang 396656e7052SJohn Crispin struct mtk_rx_dma { 397656e7052SJohn Crispin unsigned int rxd1; 398656e7052SJohn Crispin unsigned int rxd2; 399656e7052SJohn Crispin unsigned int rxd3; 400656e7052SJohn Crispin unsigned int rxd4; 401656e7052SJohn Crispin } __packed __aligned(4); 402656e7052SJohn Crispin 403656e7052SJohn Crispin struct mtk_tx_dma { 404656e7052SJohn Crispin unsigned int txd1; 405656e7052SJohn Crispin unsigned int txd2; 406656e7052SJohn Crispin unsigned int txd3; 407656e7052SJohn Crispin unsigned int txd4; 408656e7052SJohn Crispin } __packed __aligned(4); 409656e7052SJohn Crispin 410656e7052SJohn Crispin struct mtk_eth; 411656e7052SJohn Crispin struct mtk_mac; 412656e7052SJohn Crispin 413656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 414656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 415656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 416656e7052SJohn Crispin * @syncp: the refcount 417656e7052SJohn Crispin * 418656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 419656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 420656e7052SJohn Crispin * counters and store them in this struct. 421656e7052SJohn Crispin */ 422656e7052SJohn Crispin struct mtk_hw_stats { 423656e7052SJohn Crispin u64 tx_bytes; 424656e7052SJohn Crispin u64 tx_packets; 425656e7052SJohn Crispin u64 tx_skip; 426656e7052SJohn Crispin u64 tx_collisions; 427656e7052SJohn Crispin u64 rx_bytes; 428656e7052SJohn Crispin u64 rx_packets; 429656e7052SJohn Crispin u64 rx_overflow; 430656e7052SJohn Crispin u64 rx_fcs_errors; 431656e7052SJohn Crispin u64 rx_short_errors; 432656e7052SJohn Crispin u64 rx_long_errors; 433656e7052SJohn Crispin u64 rx_checksum_errors; 434656e7052SJohn Crispin u64 rx_flow_control_packets; 435656e7052SJohn Crispin 436656e7052SJohn Crispin spinlock_t stats_lock; 437656e7052SJohn Crispin u32 reg_offset; 438656e7052SJohn Crispin struct u64_stats_sync syncp; 439656e7052SJohn Crispin }; 440656e7052SJohn Crispin 441656e7052SJohn Crispin enum mtk_tx_flags { 442134d2152SSean Wang /* PDMA descriptor can point at 1-2 segments. This enum allows us to 443134d2152SSean Wang * track how memory was allocated so that it can be freed properly. 444134d2152SSean Wang */ 445656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 446656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 447134d2152SSean Wang 448134d2152SSean Wang /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 449134d2152SSean Wang * SKB out instead of looking up through hardware TX descriptor. 450134d2152SSean Wang */ 451134d2152SSean Wang MTK_TX_FLAGS_FPORT0 = 0x04, 452134d2152SSean Wang MTK_TX_FLAGS_FPORT1 = 0x08, 453656e7052SJohn Crispin }; 454656e7052SJohn Crispin 455549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the 456549e5495SSean Wang * clock in the order 457549e5495SSean Wang */ 458549e5495SSean Wang enum mtk_clks_map { 459549e5495SSean Wang MTK_CLK_ETHIF, 460549e5495SSean Wang MTK_CLK_ESW, 46142c03844SSean Wang MTK_CLK_GP0, 462549e5495SSean Wang MTK_CLK_GP1, 463549e5495SSean Wang MTK_CLK_GP2, 464f430dea7SSean Wang MTK_CLK_TRGPLL, 46542c03844SSean Wang MTK_CLK_SGMII_TX_250M, 46642c03844SSean Wang MTK_CLK_SGMII_RX_250M, 46742c03844SSean Wang MTK_CLK_SGMII_CDR_REF, 46842c03844SSean Wang MTK_CLK_SGMII_CDR_FB, 46942c03844SSean Wang MTK_CLK_SGMII_CK, 47042c03844SSean Wang MTK_CLK_ETH2PLL, 471549e5495SSean Wang MTK_CLK_MAX 472549e5495SSean Wang }; 473549e5495SSean Wang 4742ec50f57SSean Wang #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 4752ec50f57SSean Wang BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 4762ec50f57SSean Wang BIT(MTK_CLK_TRGPLL)) 47742c03844SSean Wang #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 47842c03844SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 47942c03844SSean Wang BIT(MTK_CLK_GP2) | \ 48042c03844SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 48142c03844SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 48242c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 48342c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 48442c03844SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 48542c03844SSean Wang BIT(MTK_CLK_ETH2PLL)) 486889bcbdeSBjørn Mork #define MT7621_CLKS_BITMAP (0) 487889bcbdeSBjørn Mork 4889ea4d311SSean Wang enum mtk_dev_state { 489dce6fa42SSean Wang MTK_HW_INIT, 490dce6fa42SSean Wang MTK_RESETTING 4919ea4d311SSean Wang }; 4929ea4d311SSean Wang 493656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 494656e7052SJohn Crispin * by the TX descriptor s 495656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 496656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 497656e7052SJohn Crispin * @dma_len0: The length of the first segment 498656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 499656e7052SJohn Crispin * @dma_len1: The length of the second segment 500656e7052SJohn Crispin */ 501656e7052SJohn Crispin struct mtk_tx_buf { 502656e7052SJohn Crispin struct sk_buff *skb; 503656e7052SJohn Crispin u32 flags; 504656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 505656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 506656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 507656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 508656e7052SJohn Crispin }; 509656e7052SJohn Crispin 510656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 511656e7052SJohn Crispin * @dma: The descriptor ring 512656e7052SJohn Crispin * @buf: The memory pointed at by the ring 513656e7052SJohn Crispin * @phys: The physical addr of tx_buf 514656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 515656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 516656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 517656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 518656e7052SJohn Crispin * are present 519656e7052SJohn Crispin */ 520656e7052SJohn Crispin struct mtk_tx_ring { 521656e7052SJohn Crispin struct mtk_tx_dma *dma; 522656e7052SJohn Crispin struct mtk_tx_buf *buf; 523656e7052SJohn Crispin dma_addr_t phys; 524656e7052SJohn Crispin struct mtk_tx_dma *next_free; 525656e7052SJohn Crispin struct mtk_tx_dma *last_free; 526656e7052SJohn Crispin u16 thresh; 527656e7052SJohn Crispin atomic_t free_count; 528656e7052SJohn Crispin }; 529656e7052SJohn Crispin 530ee406810SNelson Chang /* PDMA rx ring mode */ 531ee406810SNelson Chang enum mtk_rx_flags { 532ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0, 533ee406810SNelson Chang MTK_RX_FLAGS_HWLRO, 5346427dc1dSJohn Crispin MTK_RX_FLAGS_QDMA, 535ee406810SNelson Chang }; 536ee406810SNelson Chang 537656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 538656e7052SJohn Crispin * @dma: The descriptor ring 539656e7052SJohn Crispin * @data: The memory pointed at by the ring 540656e7052SJohn Crispin * @phys: The physical addr of rx_buf 541656e7052SJohn Crispin * @frag_size: How big can each fragment be 542656e7052SJohn Crispin * @buf_size: The size of each packet buffer 543656e7052SJohn Crispin * @calc_idx: The current head of ring 544656e7052SJohn Crispin */ 545656e7052SJohn Crispin struct mtk_rx_ring { 546656e7052SJohn Crispin struct mtk_rx_dma *dma; 547656e7052SJohn Crispin u8 **data; 548656e7052SJohn Crispin dma_addr_t phys; 549656e7052SJohn Crispin u16 frag_size; 550656e7052SJohn Crispin u16 buf_size; 551ee406810SNelson Chang u16 dma_size; 552ee406810SNelson Chang bool calc_idx_update; 553656e7052SJohn Crispin u16 calc_idx; 554ee406810SNelson Chang u32 crx_idx_reg; 555656e7052SJohn Crispin }; 556656e7052SJohn Crispin 5572ec50f57SSean Wang #define MTK_TRGMII BIT(0) 5582ec50f57SSean Wang #define MTK_GMAC1_TRGMII (BIT(1) | MTK_TRGMII) 55942c03844SSean Wang #define MTK_ESW BIT(4) 56042c03844SSean Wang #define MTK_GMAC1_ESW (BIT(5) | MTK_ESW) 56142c03844SSean Wang #define MTK_SGMII BIT(8) 56242c03844SSean Wang #define MTK_GMAC1_SGMII (BIT(9) | MTK_SGMII) 56342c03844SSean Wang #define MTK_GMAC2_SGMII (BIT(10) | MTK_SGMII) 56442c03844SSean Wang #define MTK_DUAL_GMAC_SHARED_SGMII (BIT(11) | MTK_GMAC1_SGMII | \ 56542c03844SSean Wang MTK_GMAC2_SGMII) 5662d14ba72SSean Wang #define MTK_HWLRO BIT(12) 567889bcbdeSBjørn Mork #define MTK_SHARED_INT BIT(13) 5682ec50f57SSean Wang #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 5692ec50f57SSean Wang 57042c03844SSean Wang /* struct mtk_eth_data - This is the structure holding all differences 5712ec50f57SSean Wang * among various plaforms 5722ec50f57SSean Wang * @caps Flags shown the extra capability for the SoC 5732ec50f57SSean Wang * @required_clks Flags shown the bitmap for required clocks on 5742ec50f57SSean Wang * the target SoC 575243dc5fbSSean Wang * @required_pctl A bool value to show whether the SoC requires 576243dc5fbSSean Wang * the extra setup for those pins used by GMAC. 5772ec50f57SSean Wang */ 5782ec50f57SSean Wang struct mtk_soc_data { 5792ec50f57SSean Wang u32 caps; 5802ec50f57SSean Wang u32 required_clks; 581243dc5fbSSean Wang bool required_pctl; 5822ec50f57SSean Wang }; 5832ec50f57SSean Wang 584656e7052SJohn Crispin /* currently no SoC has more than 2 macs */ 585656e7052SJohn Crispin #define MTK_MAX_DEVS 2 586656e7052SJohn Crispin 587656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 588656e7052SJohn Crispin * of the driver 589656e7052SJohn Crispin * @dev: The device pointer 590656e7052SJohn Crispin * @base: The mapped register i/o base 591656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 5925cce0322SJohn Crispin * @tx_irq__lock: Make sure that IRQ register operations are atomic 5935cce0322SJohn Crispin * @rx_irq__lock: Make sure that IRQ register operations are atomic 594656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 595656e7052SJohn Crispin * dummy for NAPI to work 596656e7052SJohn Crispin * @netdev: The netdev instances 597656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 598656e7052SJohn Crispin * @irq: The IRQ that we are using 599656e7052SJohn Crispin * @msg_enable: Ethtool msg level 600656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 601656e7052SJohn Crispin * MII modes 60242c03844SSean Wang * @sgmiisys: The register map pointing at the range used to setup 60342c03844SSean Wang * SGMII modes 604656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 605656e7052SJohn Crispin * GMAC port drive/slew values 606656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 6070c07ce7fSJohn Crispin * @tx_ring: Pointer to the memory holding info about the TX ring 6080c07ce7fSJohn Crispin * @rx_ring: Pointer to the memory holding info about the RX ring 6096427dc1dSJohn Crispin * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 61080673029SJohn Crispin * @tx_napi: The TX NAPI struct 61180673029SJohn Crispin * @rx_napi: The RX NAPI struct 612656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 613605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 614656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 615549e5495SSean Wang * @clks: clock array for all clocks required 616656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 6177c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 61842c03844SSean Wang * @state: Initialization and runtime state of the device 6192ec50f57SSean Wang * @soc: Holding specific data among vaious SoCs 620656e7052SJohn Crispin */ 621656e7052SJohn Crispin 622656e7052SJohn Crispin struct mtk_eth { 623656e7052SJohn Crispin struct device *dev; 624656e7052SJohn Crispin void __iomem *base; 625656e7052SJohn Crispin spinlock_t page_lock; 6265cce0322SJohn Crispin spinlock_t tx_irq_lock; 6275cce0322SJohn Crispin spinlock_t rx_irq_lock; 628656e7052SJohn Crispin struct net_device dummy_dev; 629656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 630656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 63180673029SJohn Crispin int irq[3]; 632656e7052SJohn Crispin u32 msg_enable; 633656e7052SJohn Crispin unsigned long sysclk; 634656e7052SJohn Crispin struct regmap *ethsys; 63542c03844SSean Wang struct regmap *sgmiisys; 636656e7052SJohn Crispin struct regmap *pctl; 637ee406810SNelson Chang bool hwlro; 638c6d4e63eSElena Reshetova refcount_t dma_refcnt; 639656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 640ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 6416427dc1dSJohn Crispin struct mtk_rx_ring rx_ring_qdma; 64280673029SJohn Crispin struct napi_struct tx_napi; 643656e7052SJohn Crispin struct napi_struct rx_napi; 644656e7052SJohn Crispin struct mtk_tx_dma *scratch_ring; 645605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 646656e7052SJohn Crispin void *scratch_head; 647549e5495SSean Wang struct clk *clks[MTK_CLK_MAX]; 648549e5495SSean Wang 649656e7052SJohn Crispin struct mii_bus *mii_bus; 6507c78b4adSJohn Crispin struct work_struct pending_work; 6519ea4d311SSean Wang unsigned long state; 6522ec50f57SSean Wang 6532ec50f57SSean Wang const struct mtk_soc_data *soc; 654656e7052SJohn Crispin }; 655656e7052SJohn Crispin 656656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 657656e7052SJohn Crispin * SoC 658656e7052SJohn Crispin * @id: The number of the MAC 6599ea4d311SSean Wang * @ge_mode: Interface mode kept for setup restoring 660656e7052SJohn Crispin * @of_node: Our devicetree node 661656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 662656e7052SJohn Crispin * @hw_stats: Packet statistics counter 663572de608SSean Wang * @trgmii Indicate if the MAC uses TRGMII connected to internal 664572de608SSean Wang switch 665656e7052SJohn Crispin */ 666656e7052SJohn Crispin struct mtk_mac { 667656e7052SJohn Crispin int id; 6689ea4d311SSean Wang int ge_mode; 669656e7052SJohn Crispin struct device_node *of_node; 670656e7052SJohn Crispin struct mtk_eth *hw; 671656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 672ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 673ee406810SNelson Chang int hwlro_ip_cnt; 674572de608SSean Wang bool trgmii; 675656e7052SJohn Crispin }; 676656e7052SJohn Crispin 677656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 678656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 679656e7052SJohn Crispin 680656e7052SJohn Crispin /* read the hardware status register */ 681656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 682656e7052SJohn Crispin 683656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 684656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 685656e7052SJohn Crispin 686656e7052SJohn Crispin #endif /* MTK_ETH_H */ 687