18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28e8e69d6SThomas Gleixner /* 3656e7052SJohn Crispin * 4656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7656e7052SJohn Crispin */ 8656e7052SJohn Crispin 9656e7052SJohn Crispin #ifndef MTK_ETH_H 10656e7052SJohn Crispin #define MTK_ETH_H 11656e7052SJohn Crispin 129ffee4a8SSean Wang #include <linux/dma-mapping.h> 139ffee4a8SSean Wang #include <linux/netdevice.h> 149ffee4a8SSean Wang #include <linux/of_net.h> 159ffee4a8SSean Wang #include <linux/u64_stats_sync.h> 16c6d4e63eSElena Reshetova #include <linux/refcount.h> 17b8fc9f30SRené van Dorst #include <linux/phylink.h> 18502e84e2SFelix Fietkau #include <linux/rhashtable.h> 19e9229ffdSFelix Fietkau #include <linux/dim.h> 20bc5e93e0SRussell King (Oracle) #include <linux/bitfield.h> 21a9ca9f9cSYunsheng Lin #include <net/page_pool/types.h> 2223233e57SLorenzo Bianconi #include <linux/bpf_trace.h> 23ba37b7caSFelix Fietkau #include "mtk_ppe.h" 24c6d4e63eSElena Reshetova 252d7605a7SFelix Fietkau #define MTK_MAX_DSA_PORTS 7 262d7605a7SFelix Fietkau #define MTK_DSA_PORT_MASK GENMASK(2, 0) 272d7605a7SFelix Fietkau 28f63959c7SFelix Fietkau #define MTK_QDMA_NUM_QUEUES 16 29656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 30656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 314fd59792SDENG Qingfang #define MTK_MAX_RX_LENGTH_2K 2048 32656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 33160d3a9bSLorenzo Bianconi #define MTK_TX_DMA_BUF_LEN_V2 0xffff 34c30e0b9bSFelix Fietkau #define MTK_QDMA_RING_SIZE 2048 356b4423b2SFelix Fietkau #define MTK_DMA_SIZE 512 364fd59792SDENG Qingfang #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 37656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 38656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 39656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 40656e7052SJohn Crispin NETIF_MSG_PROBE | \ 41656e7052SJohn Crispin NETIF_MSG_LINK | \ 42656e7052SJohn Crispin NETIF_MSG_TIMER | \ 43656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 44656e7052SJohn Crispin NETIF_MSG_IFUP | \ 45656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 46656e7052SJohn Crispin NETIF_MSG_TX_ERR) 47656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 48656e7052SJohn Crispin NETIF_F_RXCSUM | \ 49656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 50656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 51656e7052SJohn Crispin NETIF_F_TSO6 | \ 52502e84e2SFelix Fietkau NETIF_F_IPV6_CSUM |\ 53502e84e2SFelix Fietkau NETIF_F_HW_TC) 54296c9120SStefan Roese #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 5508df5fa6SStefan Roese #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 56ee406810SNelson Chang 5723233e57SLorenzo Bianconi #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM 5823233e57SLorenzo Bianconi #define MTK_PP_PAD (MTK_PP_HEADROOM + \ 5923233e57SLorenzo Bianconi SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 6023233e57SLorenzo Bianconi #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD) 6123233e57SLorenzo Bianconi 628cb42714SLorenzo Bianconi #define MTK_QRX_OFFSET 0x10 638cb42714SLorenzo Bianconi 64ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4 65ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8 66ee406810SNelson Chang 67ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 68ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2 69ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 70ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 71ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 72ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 73ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64 74ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000 75ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000 76ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 77656e7052SJohn Crispin 7806127504SLorenzo Bianconi /* Frame Engine Global Configuration */ 79*88c1e6efSDaniel Golle #define MTK_FE_GLO_CFG(x) (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00) 80*88c1e6efSDaniel Golle #define MTK_FE_LINK_DOWN_P(x) BIT(((x) + 8) % 16) 8106127504SLorenzo Bianconi 82656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 83656e7052SJohn Crispin #define MTK_RST_GL 0x04 84656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 85656e7052SJohn Crispin 86656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 87656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 8806127504SLorenzo Bianconi #define MTK_FE_INT_ENABLE 0x0c 8906127504SLorenzo Bianconi #define MTK_FE_INT_FQ_EMPTY BIT(8) 9006127504SLorenzo Bianconi #define MTK_FE_INT_TSO_FAIL BIT(12) 9106127504SLorenzo Bianconi #define MTK_FE_INT_TSO_ILLEGAL BIT(13) 9206127504SLorenzo Bianconi #define MTK_FE_INT_TSO_ALIGN BIT(14) 9306127504SLorenzo Bianconi #define MTK_FE_INT_RFIFO_OV BIT(18) 9406127504SLorenzo Bianconi #define MTK_FE_INT_RFIFO_UF BIT(19) 95656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 96656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 97656e7052SJohn Crispin 98ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */ 99ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 100ee406810SNelson Chang 101656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 102656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 103656e7052SJohn Crispin 10487e3df49SSean Wang /* CDMP Ingress Control Register */ 10587e3df49SSean Wang #define MTK_CDMQ_IG_CTRL 0x1400 10687e3df49SSean Wang #define MTK_CDMQ_STAG_EN BIT(0) 10787e3df49SSean Wang 1082d7605a7SFelix Fietkau /* CDMQ Exgress Control Register */ 1092d7605a7SFelix Fietkau #define MTK_CDMQ_EG_CTRL 0x1404 1102d7605a7SFelix Fietkau 111160d3a9bSLorenzo Bianconi /* CDMP Ingress Control Register */ 112160d3a9bSLorenzo Bianconi #define MTK_CDMP_IG_CTRL 0x400 113160d3a9bSLorenzo Bianconi #define MTK_CDMP_STAG_EN BIT(0) 114160d3a9bSLorenzo Bianconi 115656e7052SJohn Crispin /* CDMP Exgress Control Register */ 116656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 117656e7052SJohn Crispin 118656e7052SJohn Crispin /* GDM Exgress Control Register */ 119445eb644SLorenzo Bianconi #define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 120445eb644SLorenzo Bianconi 0x540 : 0x500 + (_x * 0x1000); }) 121d5c53da2SFelix Fietkau #define MTK_GDMA_SPECIAL_TAG BIT(24) 122656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 123656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 124656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 1251953f134SLorenzo Bianconi #define MTK_GDMA_STRP_CRC BIT(16) 1268d3f4a95SMarkLee #define MTK_GDMA_TO_PDMA 0x0 1278d66a818SMarkLee #define MTK_GDMA_DROP_ALL 0x7777 128656e7052SJohn Crispin 129445eb644SLorenzo Bianconi /* GDM Egress Control Register */ 130445eb644SLorenzo Bianconi #define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 131445eb644SLorenzo Bianconi 0x544 : 0x504 + (_x * 0x1000); }) 132445eb644SLorenzo Bianconi #define MTK_GDMA_XGDM_SEL BIT(31) 133445eb644SLorenzo Bianconi 134656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 135cfb5677dSDaniel Golle #define MTK_GDMA_MAC_ADRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 136cfb5677dSDaniel Golle 0x548 : 0x508 + (_x * 0x1000); }) 137656e7052SJohn Crispin 138656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 139cfb5677dSDaniel Golle #define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 140cfb5677dSDaniel Golle 0x54C : 0x50C + (_x * 0x1000); }) 141656e7052SJohn Crispin 142160d3a9bSLorenzo Bianconi /* FE global misc reg*/ 143160d3a9bSLorenzo Bianconi #define MTK_FE_GLO_MISC 0x124 144160d3a9bSLorenzo Bianconi 145160d3a9bSLorenzo Bianconi /* PSE Free Queue Flow Control */ 146160d3a9bSLorenzo Bianconi #define PSE_FQFC_CFG1 0x100 147160d3a9bSLorenzo Bianconi #define PSE_FQFC_CFG2 0x104 148160d3a9bSLorenzo Bianconi #define PSE_DROP_CFG 0x108 149f4b2fa2cSFelix Fietkau #define PSE_PPE0_DROP 0x110 150160d3a9bSLorenzo Bianconi 151160d3a9bSLorenzo Bianconi /* PSE Input Queue Reservation Register*/ 152160d3a9bSLorenzo Bianconi #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 153160d3a9bSLorenzo Bianconi 154160d3a9bSLorenzo Bianconi /* PSE Output Queue Threshold Register*/ 155160d3a9bSLorenzo Bianconi #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 156160d3a9bSLorenzo Bianconi 157160d3a9bSLorenzo Bianconi /* GDM and CDM Threshold */ 158160d3a9bSLorenzo Bianconi #define MTK_GDM2_THRES 0x1530 159160d3a9bSLorenzo Bianconi #define MTK_CDMW0_THRES 0x164c 160160d3a9bSLorenzo Bianconi #define MTK_CDMW1_THRES 0x1650 161160d3a9bSLorenzo Bianconi #define MTK_CDME0_THRES 0x1654 162160d3a9bSLorenzo Bianconi #define MTK_CDME1_THRES 0x1658 163160d3a9bSLorenzo Bianconi #define MTK_CDMM_THRES 0x165c 164160d3a9bSLorenzo Bianconi 165ee406810SNelson Chang /* PDMA HW LRO Control Registers */ 166ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980 167ee406810SNelson Chang #define MTK_LRO_EN BIT(0) 168ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7) 169160d3a9bSLorenzo Bianconi #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 170ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 171ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 172160d3a9bSLorenzo Bianconi #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 173ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 174160d3a9bSLorenzo Bianconi #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 175ee406810SNelson Chang 176ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984 177ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988 178ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c 179ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15) 180ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 181bacfd110SNelson Chang 1828cb42714SLorenzo Bianconi #define MTK_RX_DMA_LRO_EN BIT(8) 183bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10) 184296c9120SStefan Roese #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 185bacfd110SNelson Chang 1868cb42714SLorenzo Bianconi /* PDMA Global Configuration Register */ 1878cb42714SLorenzo Bianconi #define MTK_PDMA_LRO_SDL 0x3000 1888cb42714SLorenzo Bianconi #define MTK_RX_CFG_SDL_OFFSET 16 1898cb42714SLorenzo Bianconi 190bacfd110SNelson Chang /* PDMA Reset Index Register */ 191bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16) 192ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 193bacfd110SNelson Chang 194bacfd110SNelson Chang /* PDMA Delay Interrupt Register */ 195e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 196671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_EN BIT(15) 197671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 198e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 199e9229ffdSFelix Fietkau 200e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 201e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_EN BIT(31) 202e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 203e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 204e9229ffdSFelix Fietkau 205e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PINT_MASK 0x7f 206e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PTIME_MASK 0xff 207bacfd110SNelson Chang 208ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */ 209ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 210ee406810SNelson Chang 211ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */ 212ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 213ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 214ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9) 215ee406810SNelson Chang 216ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */ 217ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 218ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 219ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 220ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 221ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 222ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 223ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 224ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 225ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 226ee406810SNelson Chang #define MTK_RING_VLD BIT(8) 227ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 228ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 229ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 230ee406810SNelson Chang 231656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 232f63959c7SFelix Fietkau #define MTK_QTX_OFFSET 0x10 233656e7052SJohn Crispin #define QDMA_RES_THRES 4 234656e7052SJohn Crispin 235f63959c7SFelix Fietkau /* QDMA Tx Queue Scheduler Configuration Registers */ 236f63959c7SFelix Fietkau #define MTK_QTX_SCH_TX_SEL BIT(31) 237f63959c7SFelix Fietkau #define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30) 238f63959c7SFelix Fietkau 239f63959c7SFelix Fietkau #define MTK_QTX_SCH_LEAKY_BUCKET_EN BIT(30) 240f63959c7SFelix Fietkau #define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28) 241f63959c7SFelix Fietkau #define MTK_QTX_SCH_MIN_RATE_EN BIT(27) 242f63959c7SFelix Fietkau #define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20) 243f63959c7SFelix Fietkau #define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16) 244f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12) 245f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_EN BIT(11) 246f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4) 247f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0) 248f63959c7SFelix Fietkau 249f63959c7SFelix Fietkau /* QDMA TX Scheduler Rate Control Register */ 250f63959c7SFelix Fietkau #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15) 251f63959c7SFelix Fietkau 252656e7052SJohn Crispin /* QDMA Global Configuration Register */ 253656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 254656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 2556675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 256656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 25759555a8dSFelix Fietkau #define MTK_TX_BT_32DWORDS (3 << 4) 258656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 259656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 260656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 261656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 2623bc8e0afSIlya Lipnitskiy #define MTK_DMA_BUSY_TIMEOUT_US 1000000 263656e7052SJohn Crispin 264160d3a9bSLorenzo Bianconi /* QDMA V2 Global Configuration Register */ 265160d3a9bSLorenzo Bianconi #define MTK_CHK_DDONE_EN BIT(28) 266160d3a9bSLorenzo Bianconi #define MTK_DMAD_WR_WDONE BIT(26) 267160d3a9bSLorenzo Bianconi #define MTK_WCOMP_EN BIT(24) 268160d3a9bSLorenzo Bianconi #define MTK_RESV_BUF (0x40 << 16) 269160d3a9bSLorenzo Bianconi #define MTK_MUTLI_CNT (0x4 << 12) 270f63959c7SFelix Fietkau #define MTK_LEAKY_BUCKET_EN BIT(11) 271160d3a9bSLorenzo Bianconi 272656e7052SJohn Crispin /* QDMA Flow Control Register */ 273656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 274656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 275656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 276656e7052SJohn Crispin 277656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 278671d41e6SJohn Crispin #define MTK_RX_DONE_DLY BIT(30) 279e9229ffdSFelix Fietkau #define MTK_TX_DONE_DLY BIT(28) 280bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19) 281bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18) 282656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 283656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 284656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 285656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 286656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 287656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 288671d41e6SJohn Crispin #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 289e9229ffdSFelix Fietkau #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 290656e7052SJohn Crispin 291160d3a9bSLorenzo Bianconi #define MTK_RX_DONE_INT_V2 BIT(14) 292160d3a9bSLorenzo Bianconi 29393b2591aSLorenzo Bianconi #define MTK_CDM_TXFIFO_RDY BIT(7) 29493b2591aSLorenzo Bianconi 29580673029SJohn Crispin /* QDMA Interrupt grouping registers */ 29680673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0) 29780673029SJohn Crispin 298160d3a9bSLorenzo Bianconi /* QDMA TX NUM */ 299160d3a9bSLorenzo Bianconi #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 300160d3a9bSLorenzo Bianconi #define MTK_QDMA_GMAC2_QID 8 301160d3a9bSLorenzo Bianconi 302160d3a9bSLorenzo Bianconi #define MTK_TX_DMA_BUF_SHIFT 8 303160d3a9bSLorenzo Bianconi 304160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd6 */ 305160d3a9bSLorenzo Bianconi #define TX_DMA_INS_VLAN_V2 BIT(16) 306160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd5 */ 307160d3a9bSLorenzo Bianconi #define TX_DMA_CHKSUM_V2 (0x7 << 28) 308160d3a9bSLorenzo Bianconi #define TX_DMA_TSO_V2 BIT(31) 309160d3a9bSLorenzo Bianconi 3101953f134SLorenzo Bianconi #define TX_DMA_SPTAG_V3 BIT(27) 3111953f134SLorenzo Bianconi 312160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd4 */ 313160d3a9bSLorenzo Bianconi #define TX_DMA_FPORT_SHIFT_V2 8 314160d3a9bSLorenzo Bianconi #define TX_DMA_FPORT_MASK_V2 0xf 315160d3a9bSLorenzo Bianconi #define TX_DMA_SWC_V2 BIT(30) 316160d3a9bSLorenzo Bianconi 317656e7052SJohn Crispin /* QDMA descriptor txd4 */ 318656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 319656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 320656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 321656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 322656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 323656e7052SJohn Crispin 324656e7052SJohn Crispin /* QDMA descriptor txd3 */ 325656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 326656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 327160d3a9bSLorenzo Bianconi #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 328160d3a9bSLorenzo Bianconi #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) 329656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 330f63959c7SFelix Fietkau #define TX_DMA_PQID GENMASK(3, 0) 331656e7052SJohn Crispin 332296c9120SStefan Roese /* PDMA on MT7628 */ 333296c9120SStefan Roese #define TX_DMA_DONE BIT(31) 334296c9120SStefan Roese #define TX_DMA_LS1 BIT(14) 335296c9120SStefan Roese #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 336296c9120SStefan Roese 337656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 338656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 339296c9120SStefan Roese #define RX_DMA_LSO BIT(30) 340160d3a9bSLorenzo Bianconi #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 341160d3a9bSLorenzo Bianconi #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) 3423f57d8c4SFelix Fietkau #define RX_DMA_VTAG BIT(15) 343656e7052SJohn Crispin 344656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 345160d3a9bSLorenzo Bianconi #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 346160d3a9bSLorenzo Bianconi #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 347160d3a9bSLorenzo Bianconi #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 348656e7052SJohn Crispin 349656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 350ba37b7caSFelix Fietkau #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 351ba37b7caSFelix Fietkau #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 352ba37b7caSFelix Fietkau #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 353ba37b7caSFelix Fietkau #define MTK_RXD4_ALG GENMASK(31, 22) 354ba37b7caSFelix Fietkau 355ba37b7caSFelix Fietkau /* QDMA descriptor rxd4 */ 356656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 357296c9120SStefan Roese #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 358d5c53da2SFelix Fietkau #define RX_DMA_SPECIAL_TAG BIT(22) 359656e7052SJohn Crispin 3600cf731f9SLorenzo Bianconi /* PDMA descriptor rxd5 */ 3610cf731f9SLorenzo Bianconi #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) 3620cf731f9SLorenzo Bianconi #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) 3630cf731f9SLorenzo Bianconi #define MTK_RXD5_SRC_PORT GENMASK(29, 26) 3640cf731f9SLorenzo Bianconi 365c9da02bfSDaniel Golle #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7) 366c9da02bfSDaniel Golle #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf) 367160d3a9bSLorenzo Bianconi 368160d3a9bSLorenzo Bianconi /* PDMA V2 descriptor rxd3 */ 369160d3a9bSLorenzo Bianconi #define RX_DMA_VTAG_V2 BIT(0) 370160d3a9bSLorenzo Bianconi #define RX_DMA_L4_VALID_V2 BIT(2) 371160d3a9bSLorenzo Bianconi 372c0a44003SDaniel Golle /* PHY Polling and SMI Master Control registers */ 373c0a44003SDaniel Golle #define MTK_PPSC 0x10000 374c0a44003SDaniel Golle #define PPSC_MDC_CFG GENMASK(29, 24) 375c0a44003SDaniel Golle #define PPSC_MDC_TURBO BIT(20) 376c0a44003SDaniel Golle #define MDC_MAX_FREQ 25000000 377c0a44003SDaniel Golle #define MDC_MAX_DIVIDER 63 378c0a44003SDaniel Golle 379656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 380656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 381656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 382eda80b24SDaniel Golle #define PHY_IAC_REG_MASK GENMASK(29, 25) 383eda80b24SDaniel Golle #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 384eda80b24SDaniel Golle #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 385eda80b24SDaniel Golle #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 386eda80b24SDaniel Golle #define PHY_IAC_CMD_MASK GENMASK(19, 18) 387e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 388eda80b24SDaniel Golle #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 389eda80b24SDaniel Golle #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 390e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 391eda80b24SDaniel Golle #define PHY_IAC_START_MASK GENMASK(17, 16) 392e2e7f6e2SDaniel Golle #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 393eda80b24SDaniel Golle #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 394eda80b24SDaniel Golle #define PHY_IAC_DATA_MASK GENMASK(15, 0) 395eda80b24SDaniel Golle #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 396656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 397656e7052SJohn Crispin 39842c03844SSean Wang #define MTK_MAC_MISC 0x1000c 399445eb644SLorenzo Bianconi #define MTK_MAC_MISC_V3 0x10010 40042c03844SSean Wang #define MTK_MUX_TO_ESW BIT(0) 401445eb644SLorenzo Bianconi #define MISC_MDC_TURBO BIT(4) 402445eb644SLorenzo Bianconi 403445eb644SLorenzo Bianconi /* XMAC status registers */ 404445eb644SLorenzo Bianconi #define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C) 405445eb644SLorenzo Bianconi #define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15)) 406445eb644SLorenzo Bianconi #define MTK_USXGMII_PCS_LINK BIT(8) 407445eb644SLorenzo Bianconi #define MTK_XGMAC_RX_FC BIT(5) 408445eb644SLorenzo Bianconi #define MTK_XGMAC_TX_FC BIT(4) 409445eb644SLorenzo Bianconi #define MTK_USXGMII_PCS_MODE GENMASK(3, 1) 410445eb644SLorenzo Bianconi #define MTK_XGMAC_LINK_STS BIT(0) 411445eb644SLorenzo Bianconi 412445eb644SLorenzo Bianconi /* GSW bridge registers */ 413445eb644SLorenzo Bianconi #define MTK_GSW_CFG (0x10080) 414445eb644SLorenzo Bianconi #define GSWTX_IPG_MASK GENMASK(19, 16) 415445eb644SLorenzo Bianconi #define GSWTX_IPG_SHIFT 16 416445eb644SLorenzo Bianconi #define GSWRX_IPG_MASK GENMASK(3, 0) 417445eb644SLorenzo Bianconi #define GSWRX_IPG_SHIFT 0 418445eb644SLorenzo Bianconi #define GSW_IPG_11 11 41942c03844SSean Wang 420656e7052SJohn Crispin /* Mac control registers */ 421656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 4224fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 4234fd59792SDENG Qingfang #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 4244fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1518 0x0 4254fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1536 0x1 4264fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1552 0x2 4274fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_2048 0x3 428656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 429656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 430656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 431656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 432193250acSDaniel Golle #define MAC_MCR_RX_FIFO_CLR_DIS BIT(12) 433656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 434656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 435656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 436656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 437656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 438656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 439656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 440656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 441b8fc9f30SRené van Dorst #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 442b8fc9f30SRené van Dorst 443b8fc9f30SRené van Dorst /* Mac status registers */ 444b8fc9f30SRené van Dorst #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 445b8fc9f30SRené van Dorst #define MAC_MSR_EEE1G BIT(7) 446b8fc9f30SRené van Dorst #define MAC_MSR_EEE100M BIT(6) 447b8fc9f30SRené van Dorst #define MAC_MSR_RX_FC BIT(5) 448b8fc9f30SRené van Dorst #define MAC_MSR_TX_FC BIT(4) 449b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_1000 BIT(3) 450b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_100 BIT(2) 451b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 452b8fc9f30SRené van Dorst #define MAC_MSR_DPX BIT(1) 453b8fc9f30SRené van Dorst #define MAC_MSR_LINK BIT(0) 454656e7052SJohn Crispin 455f430dea7SSean Wang /* TRGMII RXC control register */ 456f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300 457f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 458f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 459f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 460a5d75538SRené van Dorst #define RXC_RST BIT(31) 461f430dea7SSean Wang #define RXC_DQSISEL BIT(30) 462f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 463f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 464f430dea7SSean Wang 465a5d75538SRené van Dorst #define NUM_TRGMII_CTRL 5 466a5d75538SRené van Dorst 467f430dea7SSean Wang /* TRGMII RXC control register */ 468f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340 469f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 470f430dea7SSean Wang #define TXC_INV BIT(30) 471f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 472f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 473f430dea7SSean Wang 474a5d75538SRené van Dorst /* TRGMII TX Drive Strength */ 475a5d75538SRené van Dorst #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 476a5d75538SRené van Dorst #define TD_DM_DRVP(x) ((x) & 0xf) 477a5d75538SRené van Dorst #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 478a5d75538SRené van Dorst 479f430dea7SSean Wang /* TRGMII Interface mode register */ 480f430dea7SSean Wang #define INTF_MODE 0x10390 481f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0) 482f430dea7SSean Wang #define TRGMII_MODE BIT(1) 483f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2) 484f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 485f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0 486f430dea7SSean Wang 487656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 488656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 489656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 490656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 491656e7052SJohn Crispin 492b95b6d99SNelson Chang /* ethernet subsystem chip id register */ 493b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0 494b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4 495983e1a6cSNelson Chang #define MT7623_ETH 7623 49642c03844SSean Wang #define MT7622_ETH 7622 497889bcbdeSBjørn Mork #define MT7621_ETH 7621 498b95b6d99SNelson Chang 4998efaa653SRené van Dorst /* ethernet system control register */ 5008efaa653SRené van Dorst #define ETHSYS_SYSCFG 0x10 5018efaa653SRené van Dorst #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 5028efaa653SRené van Dorst 503656e7052SJohn Crispin /* ethernet subsystem config register */ 504656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 505656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 506656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 507cfb5677dSDaniel Golle #define SYSCFG0_SGMII_MASK GENMASK(9, 7) 5087093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 5097093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 5107093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 5117093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 5127093f9d8SSean Wang 513656e7052SJohn Crispin 514f430dea7SSean Wang /* ethernet subsystem clock register */ 515f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c 516f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 5178efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 5188efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 5198efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 520f430dea7SSean Wang 5212a8307aaSSean Wang /* ethernet reset control register */ 5222a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34 5232a8307aaSSean Wang #define RSTCTRL_FE BIT(6) 524*88c1e6efSDaniel Golle #define RSTCTRL_WDMA0 BIT(24) 525*88c1e6efSDaniel Golle #define RSTCTRL_WDMA1 BIT(25) 526*88c1e6efSDaniel Golle #define RSTCTRL_WDMA2 BIT(26) 527ef8c373bSLorenzo Bianconi #define RSTCTRL_PPE0 BIT(31) 528ef8c373bSLorenzo Bianconi #define RSTCTRL_PPE0_V2 BIT(30) 529ef8c373bSLorenzo Bianconi #define RSTCTRL_PPE1 BIT(31) 530*88c1e6efSDaniel Golle #define RSTCTRL_PPE0_V3 BIT(29) 531*88c1e6efSDaniel Golle #define RSTCTRL_PPE1_V3 BIT(30) 532*88c1e6efSDaniel Golle #define RSTCTRL_PPE2 BIT(31) 533160d3a9bSLorenzo Bianconi #define RSTCTRL_ETH BIT(23) 534160d3a9bSLorenzo Bianconi 535160d3a9bSLorenzo Bianconi /* ethernet reset check idle register */ 536160d3a9bSLorenzo Bianconi #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 537160d3a9bSLorenzo Bianconi 538d776a57eSFelix Fietkau /* ethernet dma channel agent map */ 539d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP 0x408 540d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 541d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 542d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 543d776a57eSFelix Fietkau 5447093f9d8SSean Wang /* Infrasys subsystem config registers */ 5457093f9d8SSean Wang #define INFRA_MISC2 0x70c 5467093f9d8SSean Wang #define CO_QPHY_SEL BIT(0) 5477093f9d8SSean Wang #define GEPHY_MAC_SEL BIT(1) 5487093f9d8SSean Wang 549f5d43dddSDaniel Golle /* Top misc registers */ 550f5d43dddSDaniel Golle #define USB_PHY_SWITCH_REG 0x218 551f5d43dddSDaniel Golle #define QPHY_SEL_MASK GENMASK(1, 0) 552f5d43dddSDaniel Golle #define SGMII_QPHY_SEL 0x2 553f5d43dddSDaniel Golle 554296c9120SStefan Roese /* MT7628/88 specific stuff */ 555296c9120SStefan Roese #define MT7628_PDMA_OFFSET 0x0800 556296c9120SStefan Roese #define MT7628_SDM_OFFSET 0x0c00 557296c9120SStefan Roese 558296c9120SStefan Roese #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 559296c9120SStefan Roese #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 560296c9120SStefan Roese #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 561296c9120SStefan Roese #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 562296c9120SStefan Roese #define MT7628_PST_DTX_IDX0 BIT(0) 563296c9120SStefan Roese 564296c9120SStefan Roese #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 565296c9120SStefan Roese #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 566296c9120SStefan Roese 567ad79fd2cSStefan Roese /* Counter / stat register */ 568ad79fd2cSStefan Roese #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 569ad79fd2cSStefan Roese #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 570ad79fd2cSStefan Roese #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 571ad79fd2cSStefan Roese #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 572ad79fd2cSStefan Roese #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 573ad79fd2cSStefan Roese 57493b2591aSLorenzo Bianconi #define MTK_FE_CDM1_FSM 0x220 57593b2591aSLorenzo Bianconi #define MTK_FE_CDM2_FSM 0x224 57693b2591aSLorenzo Bianconi #define MTK_FE_CDM3_FSM 0x238 57793b2591aSLorenzo Bianconi #define MTK_FE_CDM4_FSM 0x298 57893b2591aSLorenzo Bianconi #define MTK_FE_CDM5_FSM 0x318 57993b2591aSLorenzo Bianconi #define MTK_FE_CDM6_FSM 0x328 58093b2591aSLorenzo Bianconi #define MTK_FE_GDM1_FSM 0x228 58193b2591aSLorenzo Bianconi #define MTK_FE_GDM2_FSM 0x22C 58293b2591aSLorenzo Bianconi 58393b2591aSLorenzo Bianconi #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100)) 58493b2591aSLorenzo Bianconi 585656e7052SJohn Crispin struct mtk_rx_dma { 586656e7052SJohn Crispin unsigned int rxd1; 587656e7052SJohn Crispin unsigned int rxd2; 588656e7052SJohn Crispin unsigned int rxd3; 589656e7052SJohn Crispin unsigned int rxd4; 590656e7052SJohn Crispin } __packed __aligned(4); 591656e7052SJohn Crispin 592160d3a9bSLorenzo Bianconi struct mtk_rx_dma_v2 { 593160d3a9bSLorenzo Bianconi unsigned int rxd1; 594160d3a9bSLorenzo Bianconi unsigned int rxd2; 595160d3a9bSLorenzo Bianconi unsigned int rxd3; 596160d3a9bSLorenzo Bianconi unsigned int rxd4; 597160d3a9bSLorenzo Bianconi unsigned int rxd5; 598160d3a9bSLorenzo Bianconi unsigned int rxd6; 599160d3a9bSLorenzo Bianconi unsigned int rxd7; 600160d3a9bSLorenzo Bianconi unsigned int rxd8; 601160d3a9bSLorenzo Bianconi } __packed __aligned(4); 602160d3a9bSLorenzo Bianconi 603656e7052SJohn Crispin struct mtk_tx_dma { 604656e7052SJohn Crispin unsigned int txd1; 605656e7052SJohn Crispin unsigned int txd2; 606656e7052SJohn Crispin unsigned int txd3; 607656e7052SJohn Crispin unsigned int txd4; 608656e7052SJohn Crispin } __packed __aligned(4); 609656e7052SJohn Crispin 610160d3a9bSLorenzo Bianconi struct mtk_tx_dma_v2 { 611160d3a9bSLorenzo Bianconi unsigned int txd1; 612160d3a9bSLorenzo Bianconi unsigned int txd2; 613160d3a9bSLorenzo Bianconi unsigned int txd3; 614160d3a9bSLorenzo Bianconi unsigned int txd4; 615160d3a9bSLorenzo Bianconi unsigned int txd5; 616160d3a9bSLorenzo Bianconi unsigned int txd6; 617160d3a9bSLorenzo Bianconi unsigned int txd7; 618160d3a9bSLorenzo Bianconi unsigned int txd8; 619160d3a9bSLorenzo Bianconi } __packed __aligned(4); 620160d3a9bSLorenzo Bianconi 621656e7052SJohn Crispin struct mtk_eth; 622656e7052SJohn Crispin struct mtk_mac; 623656e7052SJohn Crispin 624916a6ee8SLorenzo Bianconi struct mtk_xdp_stats { 625916a6ee8SLorenzo Bianconi u64 rx_xdp_redirect; 626916a6ee8SLorenzo Bianconi u64 rx_xdp_pass; 627916a6ee8SLorenzo Bianconi u64 rx_xdp_drop; 628916a6ee8SLorenzo Bianconi u64 rx_xdp_tx; 629916a6ee8SLorenzo Bianconi u64 rx_xdp_tx_errors; 630916a6ee8SLorenzo Bianconi u64 tx_xdp_xmit; 631916a6ee8SLorenzo Bianconi u64 tx_xdp_xmit_errors; 632916a6ee8SLorenzo Bianconi }; 633916a6ee8SLorenzo Bianconi 634656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 635656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 636656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 637656e7052SJohn Crispin * @syncp: the refcount 638656e7052SJohn Crispin * 639656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 640656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 641656e7052SJohn Crispin * counters and store them in this struct. 642656e7052SJohn Crispin */ 643656e7052SJohn Crispin struct mtk_hw_stats { 644656e7052SJohn Crispin u64 tx_bytes; 645656e7052SJohn Crispin u64 tx_packets; 646656e7052SJohn Crispin u64 tx_skip; 647656e7052SJohn Crispin u64 tx_collisions; 648656e7052SJohn Crispin u64 rx_bytes; 649656e7052SJohn Crispin u64 rx_packets; 650656e7052SJohn Crispin u64 rx_overflow; 651656e7052SJohn Crispin u64 rx_fcs_errors; 652656e7052SJohn Crispin u64 rx_short_errors; 653656e7052SJohn Crispin u64 rx_long_errors; 654656e7052SJohn Crispin u64 rx_checksum_errors; 655656e7052SJohn Crispin u64 rx_flow_control_packets; 656656e7052SJohn Crispin 657916a6ee8SLorenzo Bianconi struct mtk_xdp_stats xdp_stats; 658916a6ee8SLorenzo Bianconi 659656e7052SJohn Crispin spinlock_t stats_lock; 660656e7052SJohn Crispin u32 reg_offset; 661656e7052SJohn Crispin struct u64_stats_sync syncp; 662656e7052SJohn Crispin }; 663656e7052SJohn Crispin 664656e7052SJohn Crispin enum mtk_tx_flags { 665134d2152SSean Wang /* PDMA descriptor can point at 1-2 segments. This enum allows us to 666134d2152SSean Wang * track how memory was allocated so that it can be freed properly. 667134d2152SSean Wang */ 668656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 669656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 670656e7052SJohn Crispin }; 671656e7052SJohn Crispin 672549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the 673549e5495SSean Wang * clock in the order 674549e5495SSean Wang */ 675549e5495SSean Wang enum mtk_clks_map { 676549e5495SSean Wang MTK_CLK_ETHIF, 677d438e298SSean Wang MTK_CLK_SGMIITOP, 678549e5495SSean Wang MTK_CLK_ESW, 67942c03844SSean Wang MTK_CLK_GP0, 680549e5495SSean Wang MTK_CLK_GP1, 681549e5495SSean Wang MTK_CLK_GP2, 682445eb644SLorenzo Bianconi MTK_CLK_GP3, 683445eb644SLorenzo Bianconi MTK_CLK_XGP1, 684445eb644SLorenzo Bianconi MTK_CLK_XGP2, 685445eb644SLorenzo Bianconi MTK_CLK_XGP3, 686445eb644SLorenzo Bianconi MTK_CLK_CRYPTO, 687d438e298SSean Wang MTK_CLK_FE, 688f430dea7SSean Wang MTK_CLK_TRGPLL, 68942c03844SSean Wang MTK_CLK_SGMII_TX_250M, 69042c03844SSean Wang MTK_CLK_SGMII_RX_250M, 69142c03844SSean Wang MTK_CLK_SGMII_CDR_REF, 69242c03844SSean Wang MTK_CLK_SGMII_CDR_FB, 693d438e298SSean Wang MTK_CLK_SGMII2_TX_250M, 694d438e298SSean Wang MTK_CLK_SGMII2_RX_250M, 695d438e298SSean Wang MTK_CLK_SGMII2_CDR_REF, 696d438e298SSean Wang MTK_CLK_SGMII2_CDR_FB, 69742c03844SSean Wang MTK_CLK_SGMII_CK, 69842c03844SSean Wang MTK_CLK_ETH2PLL, 699197c9e9bSLorenzo Bianconi MTK_CLK_WOCPU0, 700197c9e9bSLorenzo Bianconi MTK_CLK_WOCPU1, 701197c9e9bSLorenzo Bianconi MTK_CLK_NETSYS0, 702197c9e9bSLorenzo Bianconi MTK_CLK_NETSYS1, 703445eb644SLorenzo Bianconi MTK_CLK_ETHWARP_WOCPU2, 704445eb644SLorenzo Bianconi MTK_CLK_ETHWARP_WOCPU1, 705445eb644SLorenzo Bianconi MTK_CLK_ETHWARP_WOCPU0, 706445eb644SLorenzo Bianconi MTK_CLK_TOP_USXGMII_SBUS_0_SEL, 707445eb644SLorenzo Bianconi MTK_CLK_TOP_USXGMII_SBUS_1_SEL, 708445eb644SLorenzo Bianconi MTK_CLK_TOP_SGM_0_SEL, 709445eb644SLorenzo Bianconi MTK_CLK_TOP_SGM_1_SEL, 710445eb644SLorenzo Bianconi MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL, 711445eb644SLorenzo Bianconi MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL, 712445eb644SLorenzo Bianconi MTK_CLK_TOP_ETH_GMII_SEL, 713445eb644SLorenzo Bianconi MTK_CLK_TOP_ETH_REFCK_50M_SEL, 714445eb644SLorenzo Bianconi MTK_CLK_TOP_ETH_SYS_200M_SEL, 715445eb644SLorenzo Bianconi MTK_CLK_TOP_ETH_SYS_SEL, 716445eb644SLorenzo Bianconi MTK_CLK_TOP_ETH_XGMII_SEL, 717445eb644SLorenzo Bianconi MTK_CLK_TOP_ETH_MII_SEL, 718445eb644SLorenzo Bianconi MTK_CLK_TOP_NETSYS_SEL, 719445eb644SLorenzo Bianconi MTK_CLK_TOP_NETSYS_500M_SEL, 720445eb644SLorenzo Bianconi MTK_CLK_TOP_NETSYS_PAO_2X_SEL, 721445eb644SLorenzo Bianconi MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, 722445eb644SLorenzo Bianconi MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, 723445eb644SLorenzo Bianconi MTK_CLK_TOP_NETSYS_WARP_SEL, 724549e5495SSean Wang MTK_CLK_MAX 725549e5495SSean Wang }; 726549e5495SSean Wang 727c75e416cSDaniel Golle #define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 728c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ 729c75e416cSDaniel Golle BIT_ULL(MTK_CLK_TRGPLL)) 730c75e416cSDaniel Golle #define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 731c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ 732c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP2) | \ 733c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 734c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 735c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 736c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 737c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CK) | \ 738c75e416cSDaniel Golle BIT_ULL(MTK_CLK_ETH2PLL)) 739889bcbdeSBjørn Mork #define MT7621_CLKS_BITMAP (0) 740296c9120SStefan Roese #define MT7628_CLKS_BITMAP (0) 741c75e416cSDaniel Golle #define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 742c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ 743c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \ 744c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 745c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 746c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 747c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 748c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 749c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 750c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 751c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ 752c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CK) | \ 753c75e416cSDaniel Golle BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP)) 754c75e416cSDaniel Golle #define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ 755c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP1) | \ 756c75e416cSDaniel Golle BIT_ULL(MTK_CLK_WOCPU0) | \ 757c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 758c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 759c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 760c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 761c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 762c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 763c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 764c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ 765c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CK)) 766c75e416cSDaniel Golle #define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ 767c75e416cSDaniel Golle BIT_ULL(MTK_CLK_GP1) | \ 768c75e416cSDaniel Golle BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \ 769c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 770c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 771c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 772c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 773c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 774c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 775c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 776c75e416cSDaniel Golle BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) 777445eb644SLorenzo Bianconi #define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ 778445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ 779445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ 780445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \ 781445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_CRYPTO) | \ 782445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 783445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 784445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 785445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 786445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \ 787445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \ 788445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \ 789445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \ 790445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \ 791445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \ 792445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \ 793445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \ 794445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \ 795445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ 796445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ 797445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ 798445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ 799445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ 800445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ 801445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ 802445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ 803445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ 804445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ 805445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ 806445eb644SLorenzo Bianconi BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL)) 807889bcbdeSBjørn Mork 8089ea4d311SSean Wang enum mtk_dev_state { 809dce6fa42SSean Wang MTK_HW_INIT, 810dce6fa42SSean Wang MTK_RESETTING 8119ea4d311SSean Wang }; 8129ea4d311SSean Wang 8131953f134SLorenzo Bianconi /* PSE Port Definition */ 8141953f134SLorenzo Bianconi enum mtk_pse_port { 8151953f134SLorenzo Bianconi PSE_ADMA_PORT = 0, 8161953f134SLorenzo Bianconi PSE_GDM1_PORT, 8171953f134SLorenzo Bianconi PSE_GDM2_PORT, 8181953f134SLorenzo Bianconi PSE_PPE0_PORT, 8191953f134SLorenzo Bianconi PSE_PPE1_PORT, 8201953f134SLorenzo Bianconi PSE_QDMA_TX_PORT, 8211953f134SLorenzo Bianconi PSE_QDMA_RX_PORT, 8221953f134SLorenzo Bianconi PSE_DROP_PORT, 8231953f134SLorenzo Bianconi PSE_WDMA0_PORT, 8241953f134SLorenzo Bianconi PSE_WDMA1_PORT, 8251953f134SLorenzo Bianconi PSE_TDMA_PORT, 8261953f134SLorenzo Bianconi PSE_NONE_PORT, 8271953f134SLorenzo Bianconi PSE_PPE2_PORT, 8281953f134SLorenzo Bianconi PSE_WDMA2_PORT, 8291953f134SLorenzo Bianconi PSE_EIP197_PORT, 8301953f134SLorenzo Bianconi PSE_GDM3_PORT, 8311953f134SLorenzo Bianconi PSE_PORT_MAX 8321953f134SLorenzo Bianconi }; 8331953f134SLorenzo Bianconi 8341953f134SLorenzo Bianconi /* GMAC Identifier */ 8351953f134SLorenzo Bianconi enum mtk_gmac_id { 8361953f134SLorenzo Bianconi MTK_GMAC1_ID = 0, 8371953f134SLorenzo Bianconi MTK_GMAC2_ID, 8381953f134SLorenzo Bianconi MTK_GMAC3_ID, 8391953f134SLorenzo Bianconi MTK_GMAC_ID_MAX 8401953f134SLorenzo Bianconi }; 8411953f134SLorenzo Bianconi 8425886d26fSLorenzo Bianconi enum mtk_tx_buf_type { 8435886d26fSLorenzo Bianconi MTK_TYPE_SKB, 8445886d26fSLorenzo Bianconi MTK_TYPE_XDP_TX, 8455886d26fSLorenzo Bianconi MTK_TYPE_XDP_NDO, 8465886d26fSLorenzo Bianconi }; 8475886d26fSLorenzo Bianconi 848656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 849656e7052SJohn Crispin * by the TX descriptor s 850656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 851656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 852656e7052SJohn Crispin * @dma_len0: The length of the first segment 853656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 854656e7052SJohn Crispin * @dma_len1: The length of the second segment 855656e7052SJohn Crispin */ 856656e7052SJohn Crispin struct mtk_tx_buf { 8575886d26fSLorenzo Bianconi enum mtk_tx_buf_type type; 8585886d26fSLorenzo Bianconi void *data; 8595886d26fSLorenzo Bianconi 8601953f134SLorenzo Bianconi u16 mac_id; 8611953f134SLorenzo Bianconi u16 flags; 862656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 863656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 864656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 865656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 866656e7052SJohn Crispin }; 867656e7052SJohn Crispin 868656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 869656e7052SJohn Crispin * @dma: The descriptor ring 870656e7052SJohn Crispin * @buf: The memory pointed at by the ring 871656e7052SJohn Crispin * @phys: The physical addr of tx_buf 872656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 873656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 8744e6bf609SFelix Fietkau * @last_free_ptr: Hardware pointer value of the last free descriptor 875656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 876656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 877656e7052SJohn Crispin * are present 878656e7052SJohn Crispin */ 879656e7052SJohn Crispin struct mtk_tx_ring { 8807173eca8SLorenzo Bianconi void *dma; 881656e7052SJohn Crispin struct mtk_tx_buf *buf; 882656e7052SJohn Crispin dma_addr_t phys; 883656e7052SJohn Crispin struct mtk_tx_dma *next_free; 884656e7052SJohn Crispin struct mtk_tx_dma *last_free; 8854e6bf609SFelix Fietkau u32 last_free_ptr; 886656e7052SJohn Crispin u16 thresh; 887656e7052SJohn Crispin atomic_t free_count; 888296c9120SStefan Roese int dma_size; 889296c9120SStefan Roese struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 890296c9120SStefan Roese dma_addr_t phys_pdma; 891296c9120SStefan Roese int cpu_idx; 892656e7052SJohn Crispin }; 893656e7052SJohn Crispin 894ee406810SNelson Chang /* PDMA rx ring mode */ 895ee406810SNelson Chang enum mtk_rx_flags { 896ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0, 897ee406810SNelson Chang MTK_RX_FLAGS_HWLRO, 8986427dc1dSJohn Crispin MTK_RX_FLAGS_QDMA, 899ee406810SNelson Chang }; 900ee406810SNelson Chang 901656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 902656e7052SJohn Crispin * @dma: The descriptor ring 903656e7052SJohn Crispin * @data: The memory pointed at by the ring 904656e7052SJohn Crispin * @phys: The physical addr of rx_buf 905656e7052SJohn Crispin * @frag_size: How big can each fragment be 906656e7052SJohn Crispin * @buf_size: The size of each packet buffer 907656e7052SJohn Crispin * @calc_idx: The current head of ring 908656e7052SJohn Crispin */ 909656e7052SJohn Crispin struct mtk_rx_ring { 9107173eca8SLorenzo Bianconi void *dma; 911656e7052SJohn Crispin u8 **data; 912656e7052SJohn Crispin dma_addr_t phys; 913656e7052SJohn Crispin u16 frag_size; 914656e7052SJohn Crispin u16 buf_size; 915ee406810SNelson Chang u16 dma_size; 916ee406810SNelson Chang bool calc_idx_update; 917656e7052SJohn Crispin u16 calc_idx; 918ee406810SNelson Chang u32 crx_idx_reg; 91923233e57SLorenzo Bianconi /* page_pool */ 92023233e57SLorenzo Bianconi struct page_pool *page_pool; 92123233e57SLorenzo Bianconi struct xdp_rxq_info xdp_q; 922656e7052SJohn Crispin }; 923656e7052SJohn Crispin 924e2c74694SRené van Dorst enum mkt_eth_capabilities { 925e2c74694SRené van Dorst MTK_RGMII_BIT = 0, 926e2c74694SRené van Dorst MTK_TRGMII_BIT, 927e2c74694SRené van Dorst MTK_SGMII_BIT, 928e2c74694SRené van Dorst MTK_ESW_BIT, 929e2c74694SRené van Dorst MTK_GEPHY_BIT, 930e2c74694SRené van Dorst MTK_MUX_BIT, 931e2c74694SRené van Dorst MTK_INFRA_BIT, 932e2c74694SRené van Dorst MTK_SHARED_SGMII_BIT, 933e2c74694SRené van Dorst MTK_HWLRO_BIT, 934e2c74694SRené van Dorst MTK_SHARED_INT_BIT, 935e2c74694SRené van Dorst MTK_TRGMII_MT7621_CLK_BIT, 936296c9120SStefan Roese MTK_QDMA_BIT, 937296c9120SStefan Roese MTK_SOC_MT7628_BIT, 938160d3a9bSLorenzo Bianconi MTK_RSTCTRL_PPE1_BIT, 939*88c1e6efSDaniel Golle MTK_RSTCTRL_PPE2_BIT, 940f5d43dddSDaniel Golle MTK_U3_COPHY_V2_BIT, 9417093f9d8SSean Wang 942e2c74694SRené van Dorst /* MUX BITS*/ 943e2c74694SRené van Dorst MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 944e2c74694SRené van Dorst MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 945e2c74694SRené van Dorst MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 946e2c74694SRené van Dorst MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 947e2c74694SRené van Dorst MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 948e2c74694SRené van Dorst 949e2c74694SRené van Dorst /* PATH BITS */ 950e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_RGMII_BIT, 951e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_TRGMII_BIT, 952e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_SGMII_BIT, 953e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_RGMII_BIT, 954e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_SGMII_BIT, 955e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_GEPHY_BIT, 956e2c74694SRené van Dorst MTK_ETH_PATH_GDM1_ESW_BIT, 9577093f9d8SSean Wang }; 9587093f9d8SSean Wang 9597093f9d8SSean Wang /* Supported hardware group on SoCs */ 96051a4df60SLorenzo Bianconi #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) 96151a4df60SLorenzo Bianconi #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) 96251a4df60SLorenzo Bianconi #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) 96351a4df60SLorenzo Bianconi #define MTK_ESW BIT_ULL(MTK_ESW_BIT) 96451a4df60SLorenzo Bianconi #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) 96551a4df60SLorenzo Bianconi #define MTK_MUX BIT_ULL(MTK_MUX_BIT) 96651a4df60SLorenzo Bianconi #define MTK_INFRA BIT_ULL(MTK_INFRA_BIT) 96751a4df60SLorenzo Bianconi #define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT) 96851a4df60SLorenzo Bianconi #define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT) 96951a4df60SLorenzo Bianconi #define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT) 97051a4df60SLorenzo Bianconi #define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT) 97151a4df60SLorenzo Bianconi #define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) 97251a4df60SLorenzo Bianconi #define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) 97351a4df60SLorenzo Bianconi #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) 974*88c1e6efSDaniel Golle #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT) 97551a4df60SLorenzo Bianconi #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) 976e2c74694SRené van Dorst 977e2c74694SRené van Dorst #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 97851a4df60SLorenzo Bianconi BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 979e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 98051a4df60SLorenzo Bianconi BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 981e2c74694SRené van Dorst #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 98251a4df60SLorenzo Bianconi BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 983e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 98451a4df60SLorenzo Bianconi BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 985e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 98651a4df60SLorenzo Bianconi BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 9877093f9d8SSean Wang 9887093f9d8SSean Wang /* Supported path present on SoCs */ 98951a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) 99051a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 99151a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) 99251a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) 99351a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) 99451a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 99551a4df60SLorenzo Bianconi #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) 9967093f9d8SSean Wang 997e2c74694SRené van Dorst #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 998e2c74694SRené van Dorst #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 999e2c74694SRené van Dorst #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 1000e2c74694SRené van Dorst #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 1001e2c74694SRené van Dorst #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 1002e2c74694SRené van Dorst #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 1003e2c74694SRené van Dorst #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 10047093f9d8SSean Wang 10057093f9d8SSean Wang /* MUXes present on SoCs */ 10067093f9d8SSean Wang /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 1007e2c74694SRené van Dorst #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 10087093f9d8SSean Wang 10097093f9d8SSean Wang /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 10107093f9d8SSean Wang #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 1011e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 10127093f9d8SSean Wang 10137093f9d8SSean Wang /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 10147093f9d8SSean Wang #define MTK_MUX_U3_GMAC2_TO_QPHY \ 1015e2c74694SRené van Dorst (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 10167093f9d8SSean Wang 10177093f9d8SSean Wang /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 10187093f9d8SSean Wang #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 1019e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 10207093f9d8SSean Wang MTK_SHARED_SGMII) 10217093f9d8SSean Wang 10227093f9d8SSean Wang /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 10237093f9d8SSean Wang #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 1024e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 10257093f9d8SSean Wang 10262ec50f57SSean Wang #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 10272ec50f57SSean Wang 10288efaa653SRené van Dorst #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 1029296c9120SStefan Roese MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 1030296c9120SStefan Roese MTK_TRGMII_MT7621_CLK | MTK_QDMA) 10318efaa653SRené van Dorst 10327093f9d8SSean Wang #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 10337093f9d8SSean Wang MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 10347093f9d8SSean Wang MTK_MUX_GDM1_TO_GMAC1_ESW | \ 1035296c9120SStefan Roese MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 10367093f9d8SSean Wang 1037296c9120SStefan Roese #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 1038296c9120SStefan Roese MTK_QDMA) 1039296c9120SStefan Roese 1040296c9120SStefan Roese #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 10417093f9d8SSean Wang 10427093f9d8SSean Wang #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 10437093f9d8SSean Wang MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 10447093f9d8SSean Wang MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 10457093f9d8SSean Wang MTK_MUX_U3_GMAC2_TO_QPHY | \ 1046296c9120SStefan Roese MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 10477093f9d8SSean Wang 1048f5d43dddSDaniel Golle #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 1049f5d43dddSDaniel Golle MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 1050f5d43dddSDaniel Golle MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ 1051a008e2a8SLorenzo Bianconi MTK_RSTCTRL_PPE1) 1052f5d43dddSDaniel Golle 1053197c9e9bSLorenzo Bianconi #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 1054197c9e9bSLorenzo Bianconi MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 1055a008e2a8SLorenzo Bianconi MTK_RSTCTRL_PPE1) 1056197c9e9bSLorenzo Bianconi 1057*88c1e6efSDaniel Golle #define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \ 1058*88c1e6efSDaniel Golle MTK_RSTCTRL_PPE2) 1059445eb644SLorenzo Bianconi 1060731f3fd6SLorenzo Bianconi struct mtk_tx_dma_desc_info { 1061731f3fd6SLorenzo Bianconi dma_addr_t addr; 1062731f3fd6SLorenzo Bianconi u32 size; 1063731f3fd6SLorenzo Bianconi u16 vlan_tci; 1064160d3a9bSLorenzo Bianconi u16 qid; 1065731f3fd6SLorenzo Bianconi u8 gso:1; 1066731f3fd6SLorenzo Bianconi u8 csum:1; 1067731f3fd6SLorenzo Bianconi u8 vlan:1; 1068731f3fd6SLorenzo Bianconi u8 first:1; 1069731f3fd6SLorenzo Bianconi u8 last:1; 1070731f3fd6SLorenzo Bianconi }; 1071731f3fd6SLorenzo Bianconi 10728cb42714SLorenzo Bianconi struct mtk_reg_map { 10738cb42714SLorenzo Bianconi u32 tx_irq_mask; 10748cb42714SLorenzo Bianconi u32 tx_irq_status; 10758cb42714SLorenzo Bianconi struct { 10768cb42714SLorenzo Bianconi u32 rx_ptr; /* rx base pointer */ 10778cb42714SLorenzo Bianconi u32 rx_cnt_cfg; /* rx max count configuration */ 10788cb42714SLorenzo Bianconi u32 pcrx_ptr; /* rx cpu pointer */ 10798cb42714SLorenzo Bianconi u32 glo_cfg; /* global configuration */ 10808cb42714SLorenzo Bianconi u32 rst_idx; /* reset index */ 10818cb42714SLorenzo Bianconi u32 delay_irq; /* delay interrupt */ 10828cb42714SLorenzo Bianconi u32 irq_status; /* interrupt status */ 10838cb42714SLorenzo Bianconi u32 irq_mask; /* interrupt mask */ 108493b2591aSLorenzo Bianconi u32 adma_rx_dbg0; 10858cb42714SLorenzo Bianconi u32 int_grp; 10868cb42714SLorenzo Bianconi } pdma; 10878cb42714SLorenzo Bianconi struct { 10888cb42714SLorenzo Bianconi u32 qtx_cfg; /* tx queue configuration */ 1089f63959c7SFelix Fietkau u32 qtx_sch; /* tx queue scheduler configuration */ 10908cb42714SLorenzo Bianconi u32 rx_ptr; /* rx base pointer */ 10918cb42714SLorenzo Bianconi u32 rx_cnt_cfg; /* rx max count configuration */ 10928cb42714SLorenzo Bianconi u32 qcrx_ptr; /* rx cpu pointer */ 10938cb42714SLorenzo Bianconi u32 glo_cfg; /* global configuration */ 10948cb42714SLorenzo Bianconi u32 rst_idx; /* reset index */ 10958cb42714SLorenzo Bianconi u32 delay_irq; /* delay interrupt */ 10968cb42714SLorenzo Bianconi u32 fc_th; /* flow control */ 10978cb42714SLorenzo Bianconi u32 int_grp; 10988cb42714SLorenzo Bianconi u32 hred; /* interrupt mask */ 10998cb42714SLorenzo Bianconi u32 ctx_ptr; /* tx acquire cpu pointer */ 11008cb42714SLorenzo Bianconi u32 dtx_ptr; /* tx acquire dma pointer */ 11018cb42714SLorenzo Bianconi u32 crx_ptr; /* tx release cpu pointer */ 11028cb42714SLorenzo Bianconi u32 drx_ptr; /* tx release dma pointer */ 11038cb42714SLorenzo Bianconi u32 fq_head; /* fq head pointer */ 11048cb42714SLorenzo Bianconi u32 fq_tail; /* fq tail pointer */ 11058cb42714SLorenzo Bianconi u32 fq_count; /* fq free page count */ 11068cb42714SLorenzo Bianconi u32 fq_blen; /* fq free page buffer length */ 1107f63959c7SFelix Fietkau u32 tx_sch_rate; /* tx scheduler rate control registers */ 11088cb42714SLorenzo Bianconi } qdma; 11098cb42714SLorenzo Bianconi u32 gdm1_cnt; 1110329bce51SLorenzo Bianconi u32 gdma_to_ppe; 1111329bce51SLorenzo Bianconi u32 ppe_base; 11120c1d3fb9SLorenzo Bianconi u32 wdma_base[2]; 111393b2591aSLorenzo Bianconi u32 pse_iq_sta; 111493b2591aSLorenzo Bianconi u32 pse_oq_sta; 11158cb42714SLorenzo Bianconi }; 11168cb42714SLorenzo Bianconi 111742c03844SSean Wang /* struct mtk_eth_data - This is the structure holding all differences 11182ec50f57SSean Wang * among various plaforms 11198cb42714SLorenzo Bianconi * @reg_map Soc register map. 11209ffee4a8SSean Wang * @ana_rgc3: The offset for register ANA_RGC3 related to 11219ffee4a8SSean Wang * sgmiisys syscon 11222ec50f57SSean Wang * @caps Flags shown the extra capability for the SoC 1123296c9120SStefan Roese * @hw_features Flags shown HW features 11242ec50f57SSean Wang * @required_clks Flags shown the bitmap for required clocks on 11252ec50f57SSean Wang * the target SoC 1126243dc5fbSSean Wang * @required_pctl A bool value to show whether the SoC requires 1127243dc5fbSSean Wang * the extra setup for those pins used by GMAC. 1128ba2fc48cSLorenzo Bianconi * @hash_offset Flow table hash offset. 1129a008e2a8SLorenzo Bianconi * @version SoC version. 11309d8cb4c0SLorenzo Bianconi * @foe_entry_size Foe table entry size. 11313fbe4d8cSDaniel Golle * @has_accounting Bool indicating support for accounting of 11323fbe4d8cSDaniel Golle * offloaded flows. 1133eb067347SLorenzo Bianconi * @txd_size Tx DMA descriptor size. 1134670ff7daSLorenzo Bianconi * @rxd_size Rx DMA descriptor size. 1135160d3a9bSLorenzo Bianconi * @rx_irq_done_mask Rx irq done register mask. 1136160d3a9bSLorenzo Bianconi * @rx_dma_l4_valid Rx DMA valid register mask. 1137160d3a9bSLorenzo Bianconi * @dma_max_len Max DMA tx/rx buffer length. 1138160d3a9bSLorenzo Bianconi * @dma_len_offset Tx/Rx DMA length field offset. 11392ec50f57SSean Wang */ 11402ec50f57SSean Wang struct mtk_soc_data { 11418cb42714SLorenzo Bianconi const struct mtk_reg_map *reg_map; 11429ffee4a8SSean Wang u32 ana_rgc3; 114351a4df60SLorenzo Bianconi u64 caps; 1144c75e416cSDaniel Golle u64 required_clks; 1145243dc5fbSSean Wang bool required_pctl; 1146ba37b7caSFelix Fietkau u8 offload_version; 1147ba2fc48cSLorenzo Bianconi u8 hash_offset; 1148a008e2a8SLorenzo Bianconi u8 version; 11499d8cb4c0SLorenzo Bianconi u16 foe_entry_size; 1150296c9120SStefan Roese netdev_features_t hw_features; 11513fbe4d8cSDaniel Golle bool has_accounting; 115276a4cb75SRussell King (Oracle) bool disable_pll_modes; 1153eb067347SLorenzo Bianconi struct { 1154eb067347SLorenzo Bianconi u32 txd_size; 1155670ff7daSLorenzo Bianconi u32 rxd_size; 1156160d3a9bSLorenzo Bianconi u32 rx_irq_done_mask; 1157160d3a9bSLorenzo Bianconi u32 rx_dma_l4_valid; 1158160d3a9bSLorenzo Bianconi u32 dma_max_len; 1159160d3a9bSLorenzo Bianconi u32 dma_len_offset; 1160eb067347SLorenzo Bianconi } txrx; 11612ec50f57SSean Wang }; 11622ec50f57SSean Wang 116393b2591aSLorenzo Bianconi #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) 116493b2591aSLorenzo Bianconi 11656ca26557SLorenzo Bianconi /* currently no SoC has more than 3 macs */ 11666ca26557SLorenzo Bianconi #define MTK_MAX_DEVS 3 1167656e7052SJohn Crispin 1168656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 1169656e7052SJohn Crispin * of the driver 1170656e7052SJohn Crispin * @dev: The device pointer 1171d776a57eSFelix Fietkau * @dev: The device pointer used for dma mapping/alloc 1172656e7052SJohn Crispin * @base: The mapped register i/o base 1173656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 11745cce0322SJohn Crispin * @tx_irq__lock: Make sure that IRQ register operations are atomic 11755cce0322SJohn Crispin * @rx_irq__lock: Make sure that IRQ register operations are atomic 1176e9229ffdSFelix Fietkau * @dim_lock: Make sure that Net DIM operations are atomic 1177656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 1178656e7052SJohn Crispin * dummy for NAPI to work 1179656e7052SJohn Crispin * @netdev: The netdev instances 1180656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 1181656e7052SJohn Crispin * @irq: The IRQ that we are using 1182656e7052SJohn Crispin * @msg_enable: Ethtool msg level 1183656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 1184656e7052SJohn Crispin * MII modes 11857093f9d8SSean Wang * @infra: The register map pointing at the range used to setup 11867093f9d8SSean Wang * SGMII and GePHY path 11872a3ec7aeSDaniel Golle * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances 1188656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 1189656e7052SJohn Crispin * GMAC port drive/slew values 1190656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 11910c07ce7fSJohn Crispin * @tx_ring: Pointer to the memory holding info about the TX ring 11920c07ce7fSJohn Crispin * @rx_ring: Pointer to the memory holding info about the RX ring 11936427dc1dSJohn Crispin * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 119480673029SJohn Crispin * @tx_napi: The TX NAPI struct 119580673029SJohn Crispin * @rx_napi: The RX NAPI struct 1196e9229ffdSFelix Fietkau * @rx_events: Net DIM RX event counter 1197e9229ffdSFelix Fietkau * @rx_packets: Net DIM RX packet counter 1198e9229ffdSFelix Fietkau * @rx_bytes: Net DIM RX byte counter 1199e9229ffdSFelix Fietkau * @rx_dim: Net DIM RX context 1200e9229ffdSFelix Fietkau * @tx_events: Net DIM TX event counter 1201e9229ffdSFelix Fietkau * @tx_packets: Net DIM TX packet counter 1202e9229ffdSFelix Fietkau * @tx_bytes: Net DIM TX byte counter 1203e9229ffdSFelix Fietkau * @tx_dim: Net DIM TX context 1204656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1205605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 1206656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 1207549e5495SSean Wang * @clks: clock array for all clocks required 1208656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 12097c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 121042c03844SSean Wang * @state: Initialization and runtime state of the device 12112ec50f57SSean Wang * @soc: Holding specific data among vaious SoCs 1212656e7052SJohn Crispin */ 1213656e7052SJohn Crispin 1214656e7052SJohn Crispin struct mtk_eth { 1215656e7052SJohn Crispin struct device *dev; 1216d776a57eSFelix Fietkau struct device *dma_dev; 1217656e7052SJohn Crispin void __iomem *base; 1218656e7052SJohn Crispin spinlock_t page_lock; 12195cce0322SJohn Crispin spinlock_t tx_irq_lock; 12205cce0322SJohn Crispin spinlock_t rx_irq_lock; 1221656e7052SJohn Crispin struct net_device dummy_dev; 1222656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 1223656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 122480673029SJohn Crispin int irq[3]; 1225656e7052SJohn Crispin u32 msg_enable; 1226656e7052SJohn Crispin unsigned long sysclk; 1227656e7052SJohn Crispin struct regmap *ethsys; 12287093f9d8SSean Wang struct regmap *infra; 12292a3ec7aeSDaniel Golle struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS]; 1230656e7052SJohn Crispin struct regmap *pctl; 1231ee406810SNelson Chang bool hwlro; 1232c6d4e63eSElena Reshetova refcount_t dma_refcnt; 1233656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 1234ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 12356427dc1dSJohn Crispin struct mtk_rx_ring rx_ring_qdma; 123680673029SJohn Crispin struct napi_struct tx_napi; 1237656e7052SJohn Crispin struct napi_struct rx_napi; 12384d642690SLorenzo Bianconi void *scratch_ring; 1239605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 1240656e7052SJohn Crispin void *scratch_head; 1241549e5495SSean Wang struct clk *clks[MTK_CLK_MAX]; 1242549e5495SSean Wang 1243656e7052SJohn Crispin struct mii_bus *mii_bus; 12447c78b4adSJohn Crispin struct work_struct pending_work; 12459ea4d311SSean Wang unsigned long state; 12462ec50f57SSean Wang 12472ec50f57SSean Wang const struct mtk_soc_data *soc; 1248296c9120SStefan Roese 1249e9229ffdSFelix Fietkau spinlock_t dim_lock; 1250e9229ffdSFelix Fietkau 1251e9229ffdSFelix Fietkau u32 rx_events; 1252e9229ffdSFelix Fietkau u32 rx_packets; 1253e9229ffdSFelix Fietkau u32 rx_bytes; 1254e9229ffdSFelix Fietkau struct dim rx_dim; 1255e9229ffdSFelix Fietkau 1256e9229ffdSFelix Fietkau u32 tx_events; 1257e9229ffdSFelix Fietkau u32 tx_packets; 1258e9229ffdSFelix Fietkau u32 tx_bytes; 1259e9229ffdSFelix Fietkau struct dim tx_dim; 1260e9229ffdSFelix Fietkau 1261296c9120SStefan Roese int ip_align; 1262ba37b7caSFelix Fietkau 12632d7605a7SFelix Fietkau struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS]; 12642d7605a7SFelix Fietkau 12654ff1a3fcSLorenzo Bianconi struct mtk_ppe *ppe[2]; 1266502e84e2SFelix Fietkau struct rhashtable flow_table; 12677c26c20dSLorenzo Bianconi 12687c26c20dSLorenzo Bianconi struct bpf_prog __rcu *prog; 126993b2591aSLorenzo Bianconi 127093b2591aSLorenzo Bianconi struct { 127193b2591aSLorenzo Bianconi struct delayed_work monitor_work; 127293b2591aSLorenzo Bianconi u32 wdidx; 127393b2591aSLorenzo Bianconi u8 wdma_hang_count; 127493b2591aSLorenzo Bianconi u8 qdma_hang_count; 127593b2591aSLorenzo Bianconi u8 adma_hang_count; 127693b2591aSLorenzo Bianconi } reset; 1277656e7052SJohn Crispin }; 1278656e7052SJohn Crispin 1279656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 1280656e7052SJohn Crispin * SoC 1281656e7052SJohn Crispin * @id: The number of the MAC 1282b8fc9f30SRené van Dorst * @interface: Interface mode kept for detecting change in hw settings 1283656e7052SJohn Crispin * @of_node: Our devicetree node 1284656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 1285656e7052SJohn Crispin * @hw_stats: Packet statistics counter 1286656e7052SJohn Crispin */ 1287656e7052SJohn Crispin struct mtk_mac { 1288656e7052SJohn Crispin int id; 1289b8fc9f30SRené van Dorst phy_interface_t interface; 1290b8fc9f30SRené van Dorst int speed; 1291656e7052SJohn Crispin struct device_node *of_node; 1292b8fc9f30SRené van Dorst struct phylink *phylink; 1293b8fc9f30SRené van Dorst struct phylink_config phylink_config; 1294656e7052SJohn Crispin struct mtk_eth *hw; 1295656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 1296ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1297ee406810SNelson Chang int hwlro_ip_cnt; 129821089867SRussell King (Oracle) unsigned int syscfg0; 1299f63959c7SFelix Fietkau struct notifier_block device_notifier; 1300656e7052SJohn Crispin }; 1301656e7052SJohn Crispin 1302656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1303656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 1304656e7052SJohn Crispin 1305a008e2a8SLorenzo Bianconi static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) 1306a008e2a8SLorenzo Bianconi { 1307a008e2a8SLorenzo Bianconi return eth->soc->version == 1; 1308a008e2a8SLorenzo Bianconi } 1309a008e2a8SLorenzo Bianconi 1310a008e2a8SLorenzo Bianconi static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth) 1311a008e2a8SLorenzo Bianconi { 1312a008e2a8SLorenzo Bianconi return eth->soc->version > 1; 1313a008e2a8SLorenzo Bianconi } 1314a008e2a8SLorenzo Bianconi 13151953f134SLorenzo Bianconi static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth) 13161953f134SLorenzo Bianconi { 13171953f134SLorenzo Bianconi return eth->soc->version > 2; 13181953f134SLorenzo Bianconi } 13191953f134SLorenzo Bianconi 13209d8cb4c0SLorenzo Bianconi static inline struct mtk_foe_entry * 13219d8cb4c0SLorenzo Bianconi mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 13229d8cb4c0SLorenzo Bianconi { 13239d8cb4c0SLorenzo Bianconi const struct mtk_soc_data *soc = ppe->eth->soc; 13249d8cb4c0SLorenzo Bianconi 13259d8cb4c0SLorenzo Bianconi return ppe->foe_table + hash * soc->foe_entry_size; 13269d8cb4c0SLorenzo Bianconi } 13279d8cb4c0SLorenzo Bianconi 132803a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 132903a3180eSLorenzo Bianconi { 1330a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 133103a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_TIMESTAMP_V2; 133203a3180eSLorenzo Bianconi 133303a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_TIMESTAMP; 133403a3180eSLorenzo Bianconi } 133503a3180eSLorenzo Bianconi 133603a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 133703a3180eSLorenzo Bianconi { 1338a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 133903a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_PPPOE_V2; 134003a3180eSLorenzo Bianconi 134103a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_PPPOE; 134203a3180eSLorenzo Bianconi } 134303a3180eSLorenzo Bianconi 134403a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 134503a3180eSLorenzo Bianconi { 1346a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 134703a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_TAG_V2; 134803a3180eSLorenzo Bianconi 134903a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_TAG; 135003a3180eSLorenzo Bianconi } 135103a3180eSLorenzo Bianconi 135203a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 135303a3180eSLorenzo Bianconi { 1354a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 135503a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; 135603a3180eSLorenzo Bianconi 135703a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_LAYER; 135803a3180eSLorenzo Bianconi } 135903a3180eSLorenzo Bianconi 136003a3180eSLorenzo Bianconi static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 136103a3180eSLorenzo Bianconi { 1362a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 136303a3180eSLorenzo Bianconi return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 136403a3180eSLorenzo Bianconi 136503a3180eSLorenzo Bianconi return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 136603a3180eSLorenzo Bianconi } 136703a3180eSLorenzo Bianconi 136803a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 136903a3180eSLorenzo Bianconi { 1370a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 137103a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 137203a3180eSLorenzo Bianconi 137303a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 137403a3180eSLorenzo Bianconi } 137503a3180eSLorenzo Bianconi 137603a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 137703a3180eSLorenzo Bianconi { 1378a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 137903a3180eSLorenzo Bianconi return MTK_FOE_IB1_PACKET_TYPE_V2; 138003a3180eSLorenzo Bianconi 138103a3180eSLorenzo Bianconi return MTK_FOE_IB1_PACKET_TYPE; 138203a3180eSLorenzo Bianconi } 138303a3180eSLorenzo Bianconi 138403a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 138503a3180eSLorenzo Bianconi { 1386a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 138703a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); 138803a3180eSLorenzo Bianconi 138903a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); 139003a3180eSLorenzo Bianconi } 139103a3180eSLorenzo Bianconi 139203a3180eSLorenzo Bianconi static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) 139303a3180eSLorenzo Bianconi { 1394a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 139503a3180eSLorenzo Bianconi return MTK_FOE_IB2_MULTICAST_V2; 139603a3180eSLorenzo Bianconi 139703a3180eSLorenzo Bianconi return MTK_FOE_IB2_MULTICAST; 139803a3180eSLorenzo Bianconi } 139903a3180eSLorenzo Bianconi 1400656e7052SJohn Crispin /* read the hardware status register */ 1401656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 1402656e7052SJohn Crispin 1403656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1404656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1405445eb644SLorenzo Bianconi u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg); 1406656e7052SJohn Crispin 14077e538372SRené van Dorst int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 14087e538372SRené van Dorst int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 14097e538372SRené van Dorst int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 14109ffee4a8SSean Wang 1411502e84e2SFelix Fietkau int mtk_eth_offload_init(struct mtk_eth *eth); 1412502e84e2SFelix Fietkau int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1413502e84e2SFelix Fietkau void *type_data); 141405f3ab77SFelix Fietkau int mtk_flow_offload_cmd(struct mtk_eth *eth, struct flow_cls_offload *cls, 141505f3ab77SFelix Fietkau int ppe_index); 141605f3ab77SFelix Fietkau void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list); 1417d776a57eSFelix Fietkau void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1418502e84e2SFelix Fietkau 1419502e84e2SFelix Fietkau 1420656e7052SJohn Crispin #endif /* MTK_ETH_H */ 1421