18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28e8e69d6SThomas Gleixner /* 3656e7052SJohn Crispin * 4656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7656e7052SJohn Crispin */ 8656e7052SJohn Crispin 9656e7052SJohn Crispin #ifndef MTK_ETH_H 10656e7052SJohn Crispin #define MTK_ETH_H 11656e7052SJohn Crispin 129ffee4a8SSean Wang #include <linux/dma-mapping.h> 139ffee4a8SSean Wang #include <linux/netdevice.h> 149ffee4a8SSean Wang #include <linux/of_net.h> 159ffee4a8SSean Wang #include <linux/u64_stats_sync.h> 16c6d4e63eSElena Reshetova #include <linux/refcount.h> 17b8fc9f30SRené van Dorst #include <linux/phylink.h> 18502e84e2SFelix Fietkau #include <linux/rhashtable.h> 19e9229ffdSFelix Fietkau #include <linux/dim.h> 20bc5e93e0SRussell King (Oracle) #include <linux/bitfield.h> 21ba37b7caSFelix Fietkau #include "mtk_ppe.h" 22c6d4e63eSElena Reshetova 23656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 24656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 254fd59792SDENG Qingfang #define MTK_MAX_RX_LENGTH_2K 2048 26656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 27160d3a9bSLorenzo Bianconi #define MTK_TX_DMA_BUF_LEN_V2 0xffff 286b4423b2SFelix Fietkau #define MTK_DMA_SIZE 512 29656e7052SJohn Crispin #define MTK_MAC_COUNT 2 304fd59792SDENG Qingfang #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 31656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 32656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 33656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 34656e7052SJohn Crispin NETIF_MSG_PROBE | \ 35656e7052SJohn Crispin NETIF_MSG_LINK | \ 36656e7052SJohn Crispin NETIF_MSG_TIMER | \ 37656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 38656e7052SJohn Crispin NETIF_MSG_IFUP | \ 39656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 40656e7052SJohn Crispin NETIF_MSG_TX_ERR) 41656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 42656e7052SJohn Crispin NETIF_F_RXCSUM | \ 43656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 44656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_RX | \ 45656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 46656e7052SJohn Crispin NETIF_F_TSO6 | \ 47502e84e2SFelix Fietkau NETIF_F_IPV6_CSUM |\ 48502e84e2SFelix Fietkau NETIF_F_HW_TC) 49296c9120SStefan Roese #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 5008df5fa6SStefan Roese #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 51ee406810SNelson Chang 528cb42714SLorenzo Bianconi #define MTK_QRX_OFFSET 0x10 538cb42714SLorenzo Bianconi 54ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4 55ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8 56ee406810SNelson Chang 57ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 58ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2 59ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 60ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 61ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 62ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 63ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64 64ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000 65ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000 66ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 67656e7052SJohn Crispin 68656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 69656e7052SJohn Crispin #define MTK_RST_GL 0x04 70656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 71656e7052SJohn Crispin 72656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 73656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 74656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 75656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 76656e7052SJohn Crispin 77ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */ 78ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 79ee406810SNelson Chang 80656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 81656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 82656e7052SJohn Crispin 8387e3df49SSean Wang /* CDMP Ingress Control Register */ 8487e3df49SSean Wang #define MTK_CDMQ_IG_CTRL 0x1400 8587e3df49SSean Wang #define MTK_CDMQ_STAG_EN BIT(0) 8687e3df49SSean Wang 87160d3a9bSLorenzo Bianconi /* CDMP Ingress Control Register */ 88160d3a9bSLorenzo Bianconi #define MTK_CDMP_IG_CTRL 0x400 89160d3a9bSLorenzo Bianconi #define MTK_CDMP_STAG_EN BIT(0) 90160d3a9bSLorenzo Bianconi 91656e7052SJohn Crispin /* CDMP Exgress Control Register */ 92656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 93656e7052SJohn Crispin 94656e7052SJohn Crispin /* GDM Exgress Control Register */ 95656e7052SJohn Crispin #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 96d5c53da2SFelix Fietkau #define MTK_GDMA_SPECIAL_TAG BIT(24) 97656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 98656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 99656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 1008d3f4a95SMarkLee #define MTK_GDMA_TO_PDMA 0x0 101ba37b7caSFelix Fietkau #define MTK_GDMA_TO_PPE 0x4444 1028d66a818SMarkLee #define MTK_GDMA_DROP_ALL 0x7777 103656e7052SJohn Crispin 104656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 105656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 106656e7052SJohn Crispin 107656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 108656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 109656e7052SJohn Crispin 110160d3a9bSLorenzo Bianconi /* FE global misc reg*/ 111160d3a9bSLorenzo Bianconi #define MTK_FE_GLO_MISC 0x124 112160d3a9bSLorenzo Bianconi 113160d3a9bSLorenzo Bianconi /* PSE Free Queue Flow Control */ 114160d3a9bSLorenzo Bianconi #define PSE_FQFC_CFG1 0x100 115160d3a9bSLorenzo Bianconi #define PSE_FQFC_CFG2 0x104 116160d3a9bSLorenzo Bianconi #define PSE_DROP_CFG 0x108 117160d3a9bSLorenzo Bianconi 118160d3a9bSLorenzo Bianconi /* PSE Input Queue Reservation Register*/ 119160d3a9bSLorenzo Bianconi #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 120160d3a9bSLorenzo Bianconi 121160d3a9bSLorenzo Bianconi /* PSE Output Queue Threshold Register*/ 122160d3a9bSLorenzo Bianconi #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 123160d3a9bSLorenzo Bianconi 124160d3a9bSLorenzo Bianconi /* GDM and CDM Threshold */ 125160d3a9bSLorenzo Bianconi #define MTK_GDM2_THRES 0x1530 126160d3a9bSLorenzo Bianconi #define MTK_CDMW0_THRES 0x164c 127160d3a9bSLorenzo Bianconi #define MTK_CDMW1_THRES 0x1650 128160d3a9bSLorenzo Bianconi #define MTK_CDME0_THRES 0x1654 129160d3a9bSLorenzo Bianconi #define MTK_CDME1_THRES 0x1658 130160d3a9bSLorenzo Bianconi #define MTK_CDMM_THRES 0x165c 131160d3a9bSLorenzo Bianconi 132ee406810SNelson Chang /* PDMA HW LRO Control Registers */ 133ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980 134ee406810SNelson Chang #define MTK_LRO_EN BIT(0) 135ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7) 136160d3a9bSLorenzo Bianconi #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 137ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 138ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 139160d3a9bSLorenzo Bianconi #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 140ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 141160d3a9bSLorenzo Bianconi #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 142ee406810SNelson Chang 143ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984 144ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988 145ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c 146ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15) 147ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 148bacfd110SNelson Chang 1498cb42714SLorenzo Bianconi #define MTK_RX_DMA_LRO_EN BIT(8) 150bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10) 151296c9120SStefan Roese #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 152bacfd110SNelson Chang 1538cb42714SLorenzo Bianconi /* PDMA Global Configuration Register */ 1548cb42714SLorenzo Bianconi #define MTK_PDMA_LRO_SDL 0x3000 1558cb42714SLorenzo Bianconi #define MTK_RX_CFG_SDL_OFFSET 16 1568cb42714SLorenzo Bianconi 157bacfd110SNelson Chang /* PDMA Reset Index Register */ 158bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16) 159ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 160bacfd110SNelson Chang 161bacfd110SNelson Chang /* PDMA Delay Interrupt Register */ 162e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 163671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_EN BIT(15) 164671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 165e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 166e9229ffdSFelix Fietkau 167e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 168e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_EN BIT(31) 169e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 170e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 171e9229ffdSFelix Fietkau 172e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PINT_MASK 0x7f 173e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PTIME_MASK 0xff 174bacfd110SNelson Chang 175ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */ 176ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 177ee406810SNelson Chang 178ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */ 179ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 180ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 181ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9) 182ee406810SNelson Chang 183ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */ 184ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 185ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 186ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 187ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 188ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 189ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 190ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 191ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 192ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 193ee406810SNelson Chang #define MTK_RING_VLD BIT(8) 194ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 195ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 196ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 197ee406810SNelson Chang 198656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 199656e7052SJohn Crispin #define QDMA_RES_THRES 4 200656e7052SJohn Crispin 201656e7052SJohn Crispin /* QDMA Global Configuration Register */ 202656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 203656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 2046675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 205656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 20659555a8dSFelix Fietkau #define MTK_TX_BT_32DWORDS (3 << 4) 207656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 208656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 209656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 210656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 2113bc8e0afSIlya Lipnitskiy #define MTK_DMA_BUSY_TIMEOUT_US 1000000 212656e7052SJohn Crispin 213160d3a9bSLorenzo Bianconi /* QDMA V2 Global Configuration Register */ 214160d3a9bSLorenzo Bianconi #define MTK_CHK_DDONE_EN BIT(28) 215160d3a9bSLorenzo Bianconi #define MTK_DMAD_WR_WDONE BIT(26) 216160d3a9bSLorenzo Bianconi #define MTK_WCOMP_EN BIT(24) 217160d3a9bSLorenzo Bianconi #define MTK_RESV_BUF (0x40 << 16) 218160d3a9bSLorenzo Bianconi #define MTK_MUTLI_CNT (0x4 << 12) 219160d3a9bSLorenzo Bianconi 220656e7052SJohn Crispin /* QDMA Flow Control Register */ 221656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 222656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 223656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 224656e7052SJohn Crispin 225656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 226671d41e6SJohn Crispin #define MTK_RX_DONE_DLY BIT(30) 227e9229ffdSFelix Fietkau #define MTK_TX_DONE_DLY BIT(28) 228bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19) 229bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18) 230656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 231656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 232656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 233656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 234656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 235656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 236671d41e6SJohn Crispin #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 237e9229ffdSFelix Fietkau #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 238656e7052SJohn Crispin 239160d3a9bSLorenzo Bianconi #define MTK_RX_DONE_INT_V2 BIT(14) 240160d3a9bSLorenzo Bianconi 24180673029SJohn Crispin /* QDMA Interrupt grouping registers */ 24280673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0) 24380673029SJohn Crispin 244656e7052SJohn Crispin #define MTK_STAT_OFFSET 0x40 245656e7052SJohn Crispin 246160d3a9bSLorenzo Bianconi /* QDMA TX NUM */ 247160d3a9bSLorenzo Bianconi #define MTK_QDMA_TX_NUM 16 248160d3a9bSLorenzo Bianconi #define MTK_QDMA_TX_MASK (MTK_QDMA_TX_NUM - 1) 249160d3a9bSLorenzo Bianconi #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 250160d3a9bSLorenzo Bianconi #define MTK_QDMA_GMAC2_QID 8 251160d3a9bSLorenzo Bianconi 252160d3a9bSLorenzo Bianconi #define MTK_TX_DMA_BUF_SHIFT 8 253160d3a9bSLorenzo Bianconi 254160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd6 */ 255160d3a9bSLorenzo Bianconi #define TX_DMA_INS_VLAN_V2 BIT(16) 256160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd5 */ 257160d3a9bSLorenzo Bianconi #define TX_DMA_CHKSUM_V2 (0x7 << 28) 258160d3a9bSLorenzo Bianconi #define TX_DMA_TSO_V2 BIT(31) 259160d3a9bSLorenzo Bianconi 260160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd4 */ 261160d3a9bSLorenzo Bianconi #define TX_DMA_FPORT_SHIFT_V2 8 262160d3a9bSLorenzo Bianconi #define TX_DMA_FPORT_MASK_V2 0xf 263160d3a9bSLorenzo Bianconi #define TX_DMA_SWC_V2 BIT(30) 264160d3a9bSLorenzo Bianconi 265804775dfSFelix Fietkau #define MTK_WDMA0_BASE 0x2800 266804775dfSFelix Fietkau #define MTK_WDMA1_BASE 0x2c00 267804775dfSFelix Fietkau 268656e7052SJohn Crispin /* QDMA descriptor txd4 */ 269656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 270656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 271656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 272656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 273656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 274656e7052SJohn Crispin 275656e7052SJohn Crispin /* QDMA descriptor txd3 */ 276656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 277656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 278160d3a9bSLorenzo Bianconi #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 279160d3a9bSLorenzo Bianconi #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) 280656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 281656e7052SJohn Crispin 282296c9120SStefan Roese /* PDMA on MT7628 */ 283296c9120SStefan Roese #define TX_DMA_DONE BIT(31) 284296c9120SStefan Roese #define TX_DMA_LS1 BIT(14) 285296c9120SStefan Roese #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 286296c9120SStefan Roese 287656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 288656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 289296c9120SStefan Roese #define RX_DMA_LSO BIT(30) 290160d3a9bSLorenzo Bianconi #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 291160d3a9bSLorenzo Bianconi #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) 2923f57d8c4SFelix Fietkau #define RX_DMA_VTAG BIT(15) 293656e7052SJohn Crispin 294656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 295160d3a9bSLorenzo Bianconi #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 296160d3a9bSLorenzo Bianconi #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 297160d3a9bSLorenzo Bianconi #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 298656e7052SJohn Crispin 299656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 300ba37b7caSFelix Fietkau #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 301ba37b7caSFelix Fietkau #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 302ba37b7caSFelix Fietkau #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 303ba37b7caSFelix Fietkau #define MTK_RXD4_ALG GENMASK(31, 22) 304ba37b7caSFelix Fietkau 305ba37b7caSFelix Fietkau /* QDMA descriptor rxd4 */ 306656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 307296c9120SStefan Roese #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 308d5c53da2SFelix Fietkau #define RX_DMA_SPECIAL_TAG BIT(22) 309656e7052SJohn Crispin 310160d3a9bSLorenzo Bianconi #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0xf) 311160d3a9bSLorenzo Bianconi #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0x7) 312160d3a9bSLorenzo Bianconi 313160d3a9bSLorenzo Bianconi /* PDMA V2 descriptor rxd3 */ 314160d3a9bSLorenzo Bianconi #define RX_DMA_VTAG_V2 BIT(0) 315160d3a9bSLorenzo Bianconi #define RX_DMA_L4_VALID_V2 BIT(2) 316160d3a9bSLorenzo Bianconi 317656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 318656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 319656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 320eda80b24SDaniel Golle #define PHY_IAC_REG_MASK GENMASK(29, 25) 321eda80b24SDaniel Golle #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 322eda80b24SDaniel Golle #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 323eda80b24SDaniel Golle #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 324eda80b24SDaniel Golle #define PHY_IAC_CMD_MASK GENMASK(19, 18) 325e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 326eda80b24SDaniel Golle #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 327eda80b24SDaniel Golle #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 328e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 329eda80b24SDaniel Golle #define PHY_IAC_START_MASK GENMASK(17, 16) 330e2e7f6e2SDaniel Golle #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 331eda80b24SDaniel Golle #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 332eda80b24SDaniel Golle #define PHY_IAC_DATA_MASK GENMASK(15, 0) 333eda80b24SDaniel Golle #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 334656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 335656e7052SJohn Crispin 33642c03844SSean Wang #define MTK_MAC_MISC 0x1000c 33742c03844SSean Wang #define MTK_MUX_TO_ESW BIT(0) 33842c03844SSean Wang 339656e7052SJohn Crispin /* Mac control registers */ 340656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 3414fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 3424fd59792SDENG Qingfang #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 3434fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1518 0x0 3444fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1536 0x1 3454fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1552 0x2 3464fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_2048 0x3 347656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 348656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 349656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 350656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 351656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 352656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 353656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 354656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 355656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 356656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 357656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 358656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 359b8fc9f30SRené van Dorst #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 360b8fc9f30SRené van Dorst 361b8fc9f30SRené van Dorst /* Mac status registers */ 362b8fc9f30SRené van Dorst #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 363b8fc9f30SRené van Dorst #define MAC_MSR_EEE1G BIT(7) 364b8fc9f30SRené van Dorst #define MAC_MSR_EEE100M BIT(6) 365b8fc9f30SRené van Dorst #define MAC_MSR_RX_FC BIT(5) 366b8fc9f30SRené van Dorst #define MAC_MSR_TX_FC BIT(4) 367b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_1000 BIT(3) 368b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_100 BIT(2) 369b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 370b8fc9f30SRené van Dorst #define MAC_MSR_DPX BIT(1) 371b8fc9f30SRené van Dorst #define MAC_MSR_LINK BIT(0) 372656e7052SJohn Crispin 373f430dea7SSean Wang /* TRGMII RXC control register */ 374f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300 375f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 376f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 377f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 378a5d75538SRené van Dorst #define RXC_RST BIT(31) 379f430dea7SSean Wang #define RXC_DQSISEL BIT(30) 380f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 381f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 382f430dea7SSean Wang 383a5d75538SRené van Dorst #define NUM_TRGMII_CTRL 5 384a5d75538SRené van Dorst 385f430dea7SSean Wang /* TRGMII RXC control register */ 386f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340 387f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 388f430dea7SSean Wang #define TXC_INV BIT(30) 389f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 390f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 391f430dea7SSean Wang 392a5d75538SRené van Dorst /* TRGMII TX Drive Strength */ 393a5d75538SRené van Dorst #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 394a5d75538SRené van Dorst #define TD_DM_DRVP(x) ((x) & 0xf) 395a5d75538SRené van Dorst #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 396a5d75538SRené van Dorst 397f430dea7SSean Wang /* TRGMII Interface mode register */ 398f430dea7SSean Wang #define INTF_MODE 0x10390 399f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0) 400f430dea7SSean Wang #define TRGMII_MODE BIT(1) 401f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2) 402f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 403f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0 404f430dea7SSean Wang 405656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 406656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 407656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 408656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 409656e7052SJohn Crispin 410b95b6d99SNelson Chang /* ethernet subsystem chip id register */ 411b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0 412b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4 413983e1a6cSNelson Chang #define MT7623_ETH 7623 41442c03844SSean Wang #define MT7622_ETH 7622 415889bcbdeSBjørn Mork #define MT7621_ETH 7621 416b95b6d99SNelson Chang 4178efaa653SRené van Dorst /* ethernet system control register */ 4188efaa653SRené van Dorst #define ETHSYS_SYSCFG 0x10 4198efaa653SRené van Dorst #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 4208efaa653SRené van Dorst 421656e7052SJohn Crispin /* ethernet subsystem config register */ 422656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 423656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 424656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 4257093f9d8SSean Wang #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 4267093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 4277093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 4287093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 4297093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 4307093f9d8SSean Wang 431656e7052SJohn Crispin 432f430dea7SSean Wang /* ethernet subsystem clock register */ 433f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c 434f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 4358efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 4368efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 4378efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 438f430dea7SSean Wang 4392a8307aaSSean Wang /* ethernet reset control register */ 4402a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34 4412a8307aaSSean Wang #define RSTCTRL_FE BIT(6) 4422a8307aaSSean Wang #define RSTCTRL_PPE BIT(31) 443160d3a9bSLorenzo Bianconi #define RSTCTRL_PPE1 BIT(30) 444160d3a9bSLorenzo Bianconi #define RSTCTRL_ETH BIT(23) 445160d3a9bSLorenzo Bianconi 446160d3a9bSLorenzo Bianconi /* ethernet reset check idle register */ 447160d3a9bSLorenzo Bianconi #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 448160d3a9bSLorenzo Bianconi 449160d3a9bSLorenzo Bianconi /* ethernet reset control register */ 450160d3a9bSLorenzo Bianconi #define ETHSYS_RSTCTRL 0x34 451160d3a9bSLorenzo Bianconi #define RSTCTRL_FE BIT(6) 452160d3a9bSLorenzo Bianconi #define RSTCTRL_PPE BIT(31) 4532a8307aaSSean Wang 454d776a57eSFelix Fietkau /* ethernet dma channel agent map */ 455d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP 0x408 456d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 457d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 458d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 459d776a57eSFelix Fietkau 46042c03844SSean Wang /* SGMII subsystem config registers */ 46142c03844SSean Wang /* Register to auto-negotiation restart */ 46242c03844SSean Wang #define SGMSYS_PCS_CONTROL_1 0x0 46342c03844SSean Wang #define SGMII_AN_RESTART BIT(9) 4647e538372SRené van Dorst #define SGMII_ISOLATE BIT(10) 4657e538372SRené van Dorst #define SGMII_AN_ENABLE BIT(12) 4667e538372SRené van Dorst #define SGMII_LINK_STATYS BIT(18) 4677e538372SRené van Dorst #define SGMII_AN_ABILITY BIT(19) 4687e538372SRené van Dorst #define SGMII_AN_COMPLETE BIT(21) 4697e538372SRené van Dorst #define SGMII_PCS_FAULT BIT(23) 4707e538372SRené van Dorst #define SGMII_AN_EXPANSION_CLR BIT(30) 47142c03844SSean Wang 47242c03844SSean Wang /* Register to programmable link timer, the unit in 2 * 8ns */ 47342c03844SSean Wang #define SGMSYS_PCS_LINK_TIMER 0x18 47442c03844SSean Wang #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 47542c03844SSean Wang 47642c03844SSean Wang /* Register to control remote fault */ 47742c03844SSean Wang #define SGMSYS_SGMII_MODE 0x20 4787e538372SRené van Dorst #define SGMII_IF_MODE_BIT0 BIT(0) 4797e538372SRené van Dorst #define SGMII_SPEED_DUPLEX_AN BIT(1) 480bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_MASK GENMASK(3, 2) 481bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) 482bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) 483bc5e93e0SRussell King (Oracle) #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) 4847e538372SRené van Dorst #define SGMII_DUPLEX_FULL BIT(4) 4857e538372SRené van Dorst #define SGMII_IF_MODE_BIT5 BIT(5) 48642c03844SSean Wang #define SGMII_REMOTE_FAULT_DIS BIT(8) 4877e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_VAL BIT(9) 4887e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_EN BIT(10) 4897e538372SRené van Dorst #define SGMII_SEND_AN_ERROR_EN BIT(11) 4907e538372SRené van Dorst #define SGMII_IF_MODE_MASK GENMASK(5, 1) 4917e538372SRené van Dorst 4927e538372SRené van Dorst /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 4937e538372SRené van Dorst #define SGMSYS_ANA_RG_CS3 0x2028 4947e538372SRené van Dorst #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 4957e538372SRené van Dorst #define RG_PHY_SPEED_1_25G 0x0 4967e538372SRené van Dorst #define RG_PHY_SPEED_3_125G BIT(2) 49742c03844SSean Wang 49842c03844SSean Wang /* Register to power up QPHY */ 49942c03844SSean Wang #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 50042c03844SSean Wang #define SGMII_PHYA_PWD BIT(4) 50142c03844SSean Wang 5027093f9d8SSean Wang /* Infrasys subsystem config registers */ 5037093f9d8SSean Wang #define INFRA_MISC2 0x70c 5047093f9d8SSean Wang #define CO_QPHY_SEL BIT(0) 5057093f9d8SSean Wang #define GEPHY_MAC_SEL BIT(1) 5067093f9d8SSean Wang 507296c9120SStefan Roese /* MT7628/88 specific stuff */ 508296c9120SStefan Roese #define MT7628_PDMA_OFFSET 0x0800 509296c9120SStefan Roese #define MT7628_SDM_OFFSET 0x0c00 510296c9120SStefan Roese 511296c9120SStefan Roese #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 512296c9120SStefan Roese #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 513296c9120SStefan Roese #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 514296c9120SStefan Roese #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 515296c9120SStefan Roese #define MT7628_PST_DTX_IDX0 BIT(0) 516296c9120SStefan Roese 517296c9120SStefan Roese #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 518296c9120SStefan Roese #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 519296c9120SStefan Roese 520ad79fd2cSStefan Roese /* Counter / stat register */ 521ad79fd2cSStefan Roese #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 522ad79fd2cSStefan Roese #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 523ad79fd2cSStefan Roese #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 524ad79fd2cSStefan Roese #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 525ad79fd2cSStefan Roese #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 526ad79fd2cSStefan Roese 527656e7052SJohn Crispin struct mtk_rx_dma { 528656e7052SJohn Crispin unsigned int rxd1; 529656e7052SJohn Crispin unsigned int rxd2; 530656e7052SJohn Crispin unsigned int rxd3; 531656e7052SJohn Crispin unsigned int rxd4; 532656e7052SJohn Crispin } __packed __aligned(4); 533656e7052SJohn Crispin 534160d3a9bSLorenzo Bianconi struct mtk_rx_dma_v2 { 535160d3a9bSLorenzo Bianconi unsigned int rxd1; 536160d3a9bSLorenzo Bianconi unsigned int rxd2; 537160d3a9bSLorenzo Bianconi unsigned int rxd3; 538160d3a9bSLorenzo Bianconi unsigned int rxd4; 539160d3a9bSLorenzo Bianconi unsigned int rxd5; 540160d3a9bSLorenzo Bianconi unsigned int rxd6; 541160d3a9bSLorenzo Bianconi unsigned int rxd7; 542160d3a9bSLorenzo Bianconi unsigned int rxd8; 543160d3a9bSLorenzo Bianconi } __packed __aligned(4); 544160d3a9bSLorenzo Bianconi 545656e7052SJohn Crispin struct mtk_tx_dma { 546656e7052SJohn Crispin unsigned int txd1; 547656e7052SJohn Crispin unsigned int txd2; 548656e7052SJohn Crispin unsigned int txd3; 549656e7052SJohn Crispin unsigned int txd4; 550656e7052SJohn Crispin } __packed __aligned(4); 551656e7052SJohn Crispin 552160d3a9bSLorenzo Bianconi struct mtk_tx_dma_v2 { 553160d3a9bSLorenzo Bianconi unsigned int txd1; 554160d3a9bSLorenzo Bianconi unsigned int txd2; 555160d3a9bSLorenzo Bianconi unsigned int txd3; 556160d3a9bSLorenzo Bianconi unsigned int txd4; 557160d3a9bSLorenzo Bianconi unsigned int txd5; 558160d3a9bSLorenzo Bianconi unsigned int txd6; 559160d3a9bSLorenzo Bianconi unsigned int txd7; 560160d3a9bSLorenzo Bianconi unsigned int txd8; 561160d3a9bSLorenzo Bianconi } __packed __aligned(4); 562160d3a9bSLorenzo Bianconi 563656e7052SJohn Crispin struct mtk_eth; 564656e7052SJohn Crispin struct mtk_mac; 565656e7052SJohn Crispin 566656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 567656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 568656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 569656e7052SJohn Crispin * @syncp: the refcount 570656e7052SJohn Crispin * 571656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 572656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 573656e7052SJohn Crispin * counters and store them in this struct. 574656e7052SJohn Crispin */ 575656e7052SJohn Crispin struct mtk_hw_stats { 576656e7052SJohn Crispin u64 tx_bytes; 577656e7052SJohn Crispin u64 tx_packets; 578656e7052SJohn Crispin u64 tx_skip; 579656e7052SJohn Crispin u64 tx_collisions; 580656e7052SJohn Crispin u64 rx_bytes; 581656e7052SJohn Crispin u64 rx_packets; 582656e7052SJohn Crispin u64 rx_overflow; 583656e7052SJohn Crispin u64 rx_fcs_errors; 584656e7052SJohn Crispin u64 rx_short_errors; 585656e7052SJohn Crispin u64 rx_long_errors; 586656e7052SJohn Crispin u64 rx_checksum_errors; 587656e7052SJohn Crispin u64 rx_flow_control_packets; 588656e7052SJohn Crispin 589656e7052SJohn Crispin spinlock_t stats_lock; 590656e7052SJohn Crispin u32 reg_offset; 591656e7052SJohn Crispin struct u64_stats_sync syncp; 592656e7052SJohn Crispin }; 593656e7052SJohn Crispin 594656e7052SJohn Crispin enum mtk_tx_flags { 595134d2152SSean Wang /* PDMA descriptor can point at 1-2 segments. This enum allows us to 596134d2152SSean Wang * track how memory was allocated so that it can be freed properly. 597134d2152SSean Wang */ 598656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 599656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 600134d2152SSean Wang 601134d2152SSean Wang /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 602134d2152SSean Wang * SKB out instead of looking up through hardware TX descriptor. 603134d2152SSean Wang */ 604134d2152SSean Wang MTK_TX_FLAGS_FPORT0 = 0x04, 605134d2152SSean Wang MTK_TX_FLAGS_FPORT1 = 0x08, 606656e7052SJohn Crispin }; 607656e7052SJohn Crispin 608549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the 609549e5495SSean Wang * clock in the order 610549e5495SSean Wang */ 611549e5495SSean Wang enum mtk_clks_map { 612549e5495SSean Wang MTK_CLK_ETHIF, 613d438e298SSean Wang MTK_CLK_SGMIITOP, 614549e5495SSean Wang MTK_CLK_ESW, 61542c03844SSean Wang MTK_CLK_GP0, 616549e5495SSean Wang MTK_CLK_GP1, 617549e5495SSean Wang MTK_CLK_GP2, 618d438e298SSean Wang MTK_CLK_FE, 619f430dea7SSean Wang MTK_CLK_TRGPLL, 62042c03844SSean Wang MTK_CLK_SGMII_TX_250M, 62142c03844SSean Wang MTK_CLK_SGMII_RX_250M, 62242c03844SSean Wang MTK_CLK_SGMII_CDR_REF, 62342c03844SSean Wang MTK_CLK_SGMII_CDR_FB, 624d438e298SSean Wang MTK_CLK_SGMII2_TX_250M, 625d438e298SSean Wang MTK_CLK_SGMII2_RX_250M, 626d438e298SSean Wang MTK_CLK_SGMII2_CDR_REF, 627d438e298SSean Wang MTK_CLK_SGMII2_CDR_FB, 62842c03844SSean Wang MTK_CLK_SGMII_CK, 62942c03844SSean Wang MTK_CLK_ETH2PLL, 630549e5495SSean Wang MTK_CLK_MAX 631549e5495SSean Wang }; 632549e5495SSean Wang 6332ec50f57SSean Wang #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 6342ec50f57SSean Wang BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 6352ec50f57SSean Wang BIT(MTK_CLK_TRGPLL)) 63642c03844SSean Wang #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 63742c03844SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 63842c03844SSean Wang BIT(MTK_CLK_GP2) | \ 63942c03844SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 64042c03844SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 64142c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 64242c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 64342c03844SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 64442c03844SSean Wang BIT(MTK_CLK_ETH2PLL)) 645889bcbdeSBjørn Mork #define MT7621_CLKS_BITMAP (0) 646296c9120SStefan Roese #define MT7628_CLKS_BITMAP (0) 647d438e298SSean Wang #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 648d438e298SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 649d438e298SSean Wang BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 650d438e298SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 651d438e298SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 652d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 653d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 654d438e298SSean Wang BIT(MTK_CLK_SGMII2_TX_250M) | \ 655d438e298SSean Wang BIT(MTK_CLK_SGMII2_RX_250M) | \ 656d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_REF) | \ 657d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_FB) | \ 658d438e298SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 659d438e298SSean Wang BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 660889bcbdeSBjørn Mork 6619ea4d311SSean Wang enum mtk_dev_state { 662dce6fa42SSean Wang MTK_HW_INIT, 663dce6fa42SSean Wang MTK_RESETTING 6649ea4d311SSean Wang }; 6659ea4d311SSean Wang 666656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 667656e7052SJohn Crispin * by the TX descriptor s 668656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 669656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 670656e7052SJohn Crispin * @dma_len0: The length of the first segment 671656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 672656e7052SJohn Crispin * @dma_len1: The length of the second segment 673656e7052SJohn Crispin */ 674656e7052SJohn Crispin struct mtk_tx_buf { 675656e7052SJohn Crispin struct sk_buff *skb; 676656e7052SJohn Crispin u32 flags; 677656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 678656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 679656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 680656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 681656e7052SJohn Crispin }; 682656e7052SJohn Crispin 683656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 684656e7052SJohn Crispin * @dma: The descriptor ring 685656e7052SJohn Crispin * @buf: The memory pointed at by the ring 686656e7052SJohn Crispin * @phys: The physical addr of tx_buf 687656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 688656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 6894e6bf609SFelix Fietkau * @last_free_ptr: Hardware pointer value of the last free descriptor 690656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 691656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 692656e7052SJohn Crispin * are present 693656e7052SJohn Crispin */ 694656e7052SJohn Crispin struct mtk_tx_ring { 695*7173eca8SLorenzo Bianconi void *dma; 696656e7052SJohn Crispin struct mtk_tx_buf *buf; 697656e7052SJohn Crispin dma_addr_t phys; 698656e7052SJohn Crispin struct mtk_tx_dma *next_free; 699656e7052SJohn Crispin struct mtk_tx_dma *last_free; 7004e6bf609SFelix Fietkau u32 last_free_ptr; 701656e7052SJohn Crispin u16 thresh; 702656e7052SJohn Crispin atomic_t free_count; 703296c9120SStefan Roese int dma_size; 704296c9120SStefan Roese struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 705296c9120SStefan Roese dma_addr_t phys_pdma; 706296c9120SStefan Roese int cpu_idx; 707656e7052SJohn Crispin }; 708656e7052SJohn Crispin 709ee406810SNelson Chang /* PDMA rx ring mode */ 710ee406810SNelson Chang enum mtk_rx_flags { 711ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0, 712ee406810SNelson Chang MTK_RX_FLAGS_HWLRO, 7136427dc1dSJohn Crispin MTK_RX_FLAGS_QDMA, 714ee406810SNelson Chang }; 715ee406810SNelson Chang 716656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 717656e7052SJohn Crispin * @dma: The descriptor ring 718656e7052SJohn Crispin * @data: The memory pointed at by the ring 719656e7052SJohn Crispin * @phys: The physical addr of rx_buf 720656e7052SJohn Crispin * @frag_size: How big can each fragment be 721656e7052SJohn Crispin * @buf_size: The size of each packet buffer 722656e7052SJohn Crispin * @calc_idx: The current head of ring 723656e7052SJohn Crispin */ 724656e7052SJohn Crispin struct mtk_rx_ring { 725*7173eca8SLorenzo Bianconi void *dma; 726656e7052SJohn Crispin u8 **data; 727656e7052SJohn Crispin dma_addr_t phys; 728656e7052SJohn Crispin u16 frag_size; 729656e7052SJohn Crispin u16 buf_size; 730ee406810SNelson Chang u16 dma_size; 731ee406810SNelson Chang bool calc_idx_update; 732656e7052SJohn Crispin u16 calc_idx; 733ee406810SNelson Chang u32 crx_idx_reg; 734656e7052SJohn Crispin }; 735656e7052SJohn Crispin 736e2c74694SRené van Dorst enum mkt_eth_capabilities { 737e2c74694SRené van Dorst MTK_RGMII_BIT = 0, 738e2c74694SRené van Dorst MTK_TRGMII_BIT, 739e2c74694SRené van Dorst MTK_SGMII_BIT, 740e2c74694SRené van Dorst MTK_ESW_BIT, 741e2c74694SRené van Dorst MTK_GEPHY_BIT, 742e2c74694SRené van Dorst MTK_MUX_BIT, 743e2c74694SRené van Dorst MTK_INFRA_BIT, 744e2c74694SRené van Dorst MTK_SHARED_SGMII_BIT, 745e2c74694SRené van Dorst MTK_HWLRO_BIT, 746e2c74694SRené van Dorst MTK_SHARED_INT_BIT, 747e2c74694SRené van Dorst MTK_TRGMII_MT7621_CLK_BIT, 748296c9120SStefan Roese MTK_QDMA_BIT, 749160d3a9bSLorenzo Bianconi MTK_NETSYS_V2_BIT, 750296c9120SStefan Roese MTK_SOC_MT7628_BIT, 751160d3a9bSLorenzo Bianconi MTK_RSTCTRL_PPE1_BIT, 7527093f9d8SSean Wang 753e2c74694SRené van Dorst /* MUX BITS*/ 754e2c74694SRené van Dorst MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 755e2c74694SRené van Dorst MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 756e2c74694SRené van Dorst MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 757e2c74694SRené van Dorst MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 758e2c74694SRené van Dorst MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 759e2c74694SRené van Dorst 760e2c74694SRené van Dorst /* PATH BITS */ 761e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_RGMII_BIT, 762e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_TRGMII_BIT, 763e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_SGMII_BIT, 764e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_RGMII_BIT, 765e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_SGMII_BIT, 766e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_GEPHY_BIT, 767e2c74694SRené van Dorst MTK_ETH_PATH_GDM1_ESW_BIT, 7687093f9d8SSean Wang }; 7697093f9d8SSean Wang 7707093f9d8SSean Wang /* Supported hardware group on SoCs */ 771e2c74694SRené van Dorst #define MTK_RGMII BIT(MTK_RGMII_BIT) 772e2c74694SRené van Dorst #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 773e2c74694SRené van Dorst #define MTK_SGMII BIT(MTK_SGMII_BIT) 774e2c74694SRené van Dorst #define MTK_ESW BIT(MTK_ESW_BIT) 775e2c74694SRené van Dorst #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 776e2c74694SRené van Dorst #define MTK_MUX BIT(MTK_MUX_BIT) 777e2c74694SRené van Dorst #define MTK_INFRA BIT(MTK_INFRA_BIT) 778e2c74694SRené van Dorst #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 779e2c74694SRené van Dorst #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 780e2c74694SRené van Dorst #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 781e2c74694SRené van Dorst #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 782296c9120SStefan Roese #define MTK_QDMA BIT(MTK_QDMA_BIT) 783160d3a9bSLorenzo Bianconi #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) 784296c9120SStefan Roese #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 785160d3a9bSLorenzo Bianconi #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) 786e2c74694SRené van Dorst 787e2c74694SRené van Dorst #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 788e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 789e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 790e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 791e2c74694SRené van Dorst #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 792e2c74694SRené van Dorst BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 793e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 794e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 795e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 796e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 7977093f9d8SSean Wang 7987093f9d8SSean Wang /* Supported path present on SoCs */ 799e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 800e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 801e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 802e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 803e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 804e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 805e2c74694SRené van Dorst #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 8067093f9d8SSean Wang 807e2c74694SRené van Dorst #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 808e2c74694SRené van Dorst #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 809e2c74694SRené van Dorst #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 810e2c74694SRené van Dorst #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 811e2c74694SRené van Dorst #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 812e2c74694SRené van Dorst #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 813e2c74694SRené van Dorst #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 8147093f9d8SSean Wang 8157093f9d8SSean Wang /* MUXes present on SoCs */ 8167093f9d8SSean Wang /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 817e2c74694SRené van Dorst #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 8187093f9d8SSean Wang 8197093f9d8SSean Wang /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 8207093f9d8SSean Wang #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 821e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 8227093f9d8SSean Wang 8237093f9d8SSean Wang /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 8247093f9d8SSean Wang #define MTK_MUX_U3_GMAC2_TO_QPHY \ 825e2c74694SRené van Dorst (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 8267093f9d8SSean Wang 8277093f9d8SSean Wang /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 8287093f9d8SSean Wang #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 829e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 8307093f9d8SSean Wang MTK_SHARED_SGMII) 8317093f9d8SSean Wang 8327093f9d8SSean Wang /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 8337093f9d8SSean Wang #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 834e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 8357093f9d8SSean Wang 8362ec50f57SSean Wang #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 8372ec50f57SSean Wang 8388efaa653SRené van Dorst #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 839296c9120SStefan Roese MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 840296c9120SStefan Roese MTK_TRGMII_MT7621_CLK | MTK_QDMA) 8418efaa653SRené van Dorst 8427093f9d8SSean Wang #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 8437093f9d8SSean Wang MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 8447093f9d8SSean Wang MTK_MUX_GDM1_TO_GMAC1_ESW | \ 845296c9120SStefan Roese MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 8467093f9d8SSean Wang 847296c9120SStefan Roese #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 848296c9120SStefan Roese MTK_QDMA) 849296c9120SStefan Roese 850296c9120SStefan Roese #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 8517093f9d8SSean Wang 8527093f9d8SSean Wang #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 8537093f9d8SSean Wang MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 8547093f9d8SSean Wang MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 8557093f9d8SSean Wang MTK_MUX_U3_GMAC2_TO_QPHY | \ 856296c9120SStefan Roese MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 8577093f9d8SSean Wang 858731f3fd6SLorenzo Bianconi struct mtk_tx_dma_desc_info { 859731f3fd6SLorenzo Bianconi dma_addr_t addr; 860731f3fd6SLorenzo Bianconi u32 size; 861731f3fd6SLorenzo Bianconi u16 vlan_tci; 862160d3a9bSLorenzo Bianconi u16 qid; 863731f3fd6SLorenzo Bianconi u8 gso:1; 864731f3fd6SLorenzo Bianconi u8 csum:1; 865731f3fd6SLorenzo Bianconi u8 vlan:1; 866731f3fd6SLorenzo Bianconi u8 first:1; 867731f3fd6SLorenzo Bianconi u8 last:1; 868731f3fd6SLorenzo Bianconi }; 869731f3fd6SLorenzo Bianconi 8708cb42714SLorenzo Bianconi struct mtk_reg_map { 8718cb42714SLorenzo Bianconi u32 tx_irq_mask; 8728cb42714SLorenzo Bianconi u32 tx_irq_status; 8738cb42714SLorenzo Bianconi struct { 8748cb42714SLorenzo Bianconi u32 rx_ptr; /* rx base pointer */ 8758cb42714SLorenzo Bianconi u32 rx_cnt_cfg; /* rx max count configuration */ 8768cb42714SLorenzo Bianconi u32 pcrx_ptr; /* rx cpu pointer */ 8778cb42714SLorenzo Bianconi u32 glo_cfg; /* global configuration */ 8788cb42714SLorenzo Bianconi u32 rst_idx; /* reset index */ 8798cb42714SLorenzo Bianconi u32 delay_irq; /* delay interrupt */ 8808cb42714SLorenzo Bianconi u32 irq_status; /* interrupt status */ 8818cb42714SLorenzo Bianconi u32 irq_mask; /* interrupt mask */ 8828cb42714SLorenzo Bianconi u32 int_grp; 8838cb42714SLorenzo Bianconi } pdma; 8848cb42714SLorenzo Bianconi struct { 8858cb42714SLorenzo Bianconi u32 qtx_cfg; /* tx queue configuration */ 8868cb42714SLorenzo Bianconi u32 rx_ptr; /* rx base pointer */ 8878cb42714SLorenzo Bianconi u32 rx_cnt_cfg; /* rx max count configuration */ 8888cb42714SLorenzo Bianconi u32 qcrx_ptr; /* rx cpu pointer */ 8898cb42714SLorenzo Bianconi u32 glo_cfg; /* global configuration */ 8908cb42714SLorenzo Bianconi u32 rst_idx; /* reset index */ 8918cb42714SLorenzo Bianconi u32 delay_irq; /* delay interrupt */ 8928cb42714SLorenzo Bianconi u32 fc_th; /* flow control */ 8938cb42714SLorenzo Bianconi u32 int_grp; 8948cb42714SLorenzo Bianconi u32 hred; /* interrupt mask */ 8958cb42714SLorenzo Bianconi u32 ctx_ptr; /* tx acquire cpu pointer */ 8968cb42714SLorenzo Bianconi u32 dtx_ptr; /* tx acquire dma pointer */ 8978cb42714SLorenzo Bianconi u32 crx_ptr; /* tx release cpu pointer */ 8988cb42714SLorenzo Bianconi u32 drx_ptr; /* tx release dma pointer */ 8998cb42714SLorenzo Bianconi u32 fq_head; /* fq head pointer */ 9008cb42714SLorenzo Bianconi u32 fq_tail; /* fq tail pointer */ 9018cb42714SLorenzo Bianconi u32 fq_count; /* fq free page count */ 9028cb42714SLorenzo Bianconi u32 fq_blen; /* fq free page buffer length */ 9038cb42714SLorenzo Bianconi } qdma; 9048cb42714SLorenzo Bianconi u32 gdm1_cnt; 9058cb42714SLorenzo Bianconi }; 9068cb42714SLorenzo Bianconi 90742c03844SSean Wang /* struct mtk_eth_data - This is the structure holding all differences 9082ec50f57SSean Wang * among various plaforms 9098cb42714SLorenzo Bianconi * @reg_map Soc register map. 9109ffee4a8SSean Wang * @ana_rgc3: The offset for register ANA_RGC3 related to 9119ffee4a8SSean Wang * sgmiisys syscon 9122ec50f57SSean Wang * @caps Flags shown the extra capability for the SoC 913296c9120SStefan Roese * @hw_features Flags shown HW features 9142ec50f57SSean Wang * @required_clks Flags shown the bitmap for required clocks on 9152ec50f57SSean Wang * the target SoC 916243dc5fbSSean Wang * @required_pctl A bool value to show whether the SoC requires 917243dc5fbSSean Wang * the extra setup for those pins used by GMAC. 918eb067347SLorenzo Bianconi * @txd_size Tx DMA descriptor size. 919670ff7daSLorenzo Bianconi * @rxd_size Rx DMA descriptor size. 920160d3a9bSLorenzo Bianconi * @rx_irq_done_mask Rx irq done register mask. 921160d3a9bSLorenzo Bianconi * @rx_dma_l4_valid Rx DMA valid register mask. 922160d3a9bSLorenzo Bianconi * @dma_max_len Max DMA tx/rx buffer length. 923160d3a9bSLorenzo Bianconi * @dma_len_offset Tx/Rx DMA length field offset. 9242ec50f57SSean Wang */ 9252ec50f57SSean Wang struct mtk_soc_data { 9268cb42714SLorenzo Bianconi const struct mtk_reg_map *reg_map; 9279ffee4a8SSean Wang u32 ana_rgc3; 9282ec50f57SSean Wang u32 caps; 9292ec50f57SSean Wang u32 required_clks; 930243dc5fbSSean Wang bool required_pctl; 931ba37b7caSFelix Fietkau u8 offload_version; 932296c9120SStefan Roese netdev_features_t hw_features; 933eb067347SLorenzo Bianconi struct { 934eb067347SLorenzo Bianconi u32 txd_size; 935670ff7daSLorenzo Bianconi u32 rxd_size; 936160d3a9bSLorenzo Bianconi u32 rx_irq_done_mask; 937160d3a9bSLorenzo Bianconi u32 rx_dma_l4_valid; 938160d3a9bSLorenzo Bianconi u32 dma_max_len; 939160d3a9bSLorenzo Bianconi u32 dma_len_offset; 940eb067347SLorenzo Bianconi } txrx; 9412ec50f57SSean Wang }; 9422ec50f57SSean Wang 943656e7052SJohn Crispin /* currently no SoC has more than 2 macs */ 944656e7052SJohn Crispin #define MTK_MAX_DEVS 2 945656e7052SJohn Crispin 946901f3fbeSRussell King (Oracle) /* struct mtk_pcs - This structure holds each sgmii regmap and associated 947901f3fbeSRussell King (Oracle) * data 9489ffee4a8SSean Wang * @regmap: The register map pointing at the range used to setup 9499ffee4a8SSean Wang * SGMII modes 9509ffee4a8SSean Wang * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 95114a44ab0SRussell King (Oracle) * @pcs: Phylink PCS structure 9529ffee4a8SSean Wang */ 953901f3fbeSRussell King (Oracle) struct mtk_pcs { 954901f3fbeSRussell King (Oracle) struct regmap *regmap; 9559ffee4a8SSean Wang u32 ana_rgc3; 95614a44ab0SRussell King (Oracle) struct phylink_pcs pcs; 9579ffee4a8SSean Wang }; 9589ffee4a8SSean Wang 959901f3fbeSRussell King (Oracle) /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 960901f3fbeSRussell King (Oracle) * characteristics 961901f3fbeSRussell King (Oracle) * @pcs Array of individual PCS structures 962901f3fbeSRussell King (Oracle) */ 963901f3fbeSRussell King (Oracle) struct mtk_sgmii { 964901f3fbeSRussell King (Oracle) struct mtk_pcs pcs[MTK_MAX_DEVS]; 965901f3fbeSRussell King (Oracle) }; 966901f3fbeSRussell King (Oracle) 967656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 968656e7052SJohn Crispin * of the driver 969656e7052SJohn Crispin * @dev: The device pointer 970d776a57eSFelix Fietkau * @dev: The device pointer used for dma mapping/alloc 971656e7052SJohn Crispin * @base: The mapped register i/o base 972656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 9735cce0322SJohn Crispin * @tx_irq__lock: Make sure that IRQ register operations are atomic 9745cce0322SJohn Crispin * @rx_irq__lock: Make sure that IRQ register operations are atomic 975e9229ffdSFelix Fietkau * @dim_lock: Make sure that Net DIM operations are atomic 976656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 977656e7052SJohn Crispin * dummy for NAPI to work 978656e7052SJohn Crispin * @netdev: The netdev instances 979656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 980656e7052SJohn Crispin * @irq: The IRQ that we are using 981656e7052SJohn Crispin * @msg_enable: Ethtool msg level 982656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 983656e7052SJohn Crispin * MII modes 9847093f9d8SSean Wang * @infra: The register map pointing at the range used to setup 9857093f9d8SSean Wang * SGMII and GePHY path 986656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 987656e7052SJohn Crispin * GMAC port drive/slew values 988656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 9890c07ce7fSJohn Crispin * @tx_ring: Pointer to the memory holding info about the TX ring 9900c07ce7fSJohn Crispin * @rx_ring: Pointer to the memory holding info about the RX ring 9916427dc1dSJohn Crispin * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 99280673029SJohn Crispin * @tx_napi: The TX NAPI struct 99380673029SJohn Crispin * @rx_napi: The RX NAPI struct 994e9229ffdSFelix Fietkau * @rx_events: Net DIM RX event counter 995e9229ffdSFelix Fietkau * @rx_packets: Net DIM RX packet counter 996e9229ffdSFelix Fietkau * @rx_bytes: Net DIM RX byte counter 997e9229ffdSFelix Fietkau * @rx_dim: Net DIM RX context 998e9229ffdSFelix Fietkau * @tx_events: Net DIM TX event counter 999e9229ffdSFelix Fietkau * @tx_packets: Net DIM TX packet counter 1000e9229ffdSFelix Fietkau * @tx_bytes: Net DIM TX byte counter 1001e9229ffdSFelix Fietkau * @tx_dim: Net DIM TX context 1002656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1003605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 1004656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 1005549e5495SSean Wang * @clks: clock array for all clocks required 1006656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 10077c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 100842c03844SSean Wang * @state: Initialization and runtime state of the device 10092ec50f57SSean Wang * @soc: Holding specific data among vaious SoCs 1010656e7052SJohn Crispin */ 1011656e7052SJohn Crispin 1012656e7052SJohn Crispin struct mtk_eth { 1013656e7052SJohn Crispin struct device *dev; 1014d776a57eSFelix Fietkau struct device *dma_dev; 1015656e7052SJohn Crispin void __iomem *base; 1016656e7052SJohn Crispin spinlock_t page_lock; 10175cce0322SJohn Crispin spinlock_t tx_irq_lock; 10185cce0322SJohn Crispin spinlock_t rx_irq_lock; 1019656e7052SJohn Crispin struct net_device dummy_dev; 1020656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 1021656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 102280673029SJohn Crispin int irq[3]; 1023656e7052SJohn Crispin u32 msg_enable; 1024656e7052SJohn Crispin unsigned long sysclk; 1025656e7052SJohn Crispin struct regmap *ethsys; 10267093f9d8SSean Wang struct regmap *infra; 10279ffee4a8SSean Wang struct mtk_sgmii *sgmii; 1028656e7052SJohn Crispin struct regmap *pctl; 1029ee406810SNelson Chang bool hwlro; 1030c6d4e63eSElena Reshetova refcount_t dma_refcnt; 1031656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 1032ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 10336427dc1dSJohn Crispin struct mtk_rx_ring rx_ring_qdma; 103480673029SJohn Crispin struct napi_struct tx_napi; 1035656e7052SJohn Crispin struct napi_struct rx_napi; 1036656e7052SJohn Crispin struct mtk_tx_dma *scratch_ring; 1037605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 1038656e7052SJohn Crispin void *scratch_head; 1039549e5495SSean Wang struct clk *clks[MTK_CLK_MAX]; 1040549e5495SSean Wang 1041656e7052SJohn Crispin struct mii_bus *mii_bus; 10427c78b4adSJohn Crispin struct work_struct pending_work; 10439ea4d311SSean Wang unsigned long state; 10442ec50f57SSean Wang 10452ec50f57SSean Wang const struct mtk_soc_data *soc; 1046296c9120SStefan Roese 1047e9229ffdSFelix Fietkau spinlock_t dim_lock; 1048e9229ffdSFelix Fietkau 1049e9229ffdSFelix Fietkau u32 rx_events; 1050e9229ffdSFelix Fietkau u32 rx_packets; 1051e9229ffdSFelix Fietkau u32 rx_bytes; 1052e9229ffdSFelix Fietkau struct dim rx_dim; 1053e9229ffdSFelix Fietkau 1054e9229ffdSFelix Fietkau u32 tx_events; 1055e9229ffdSFelix Fietkau u32 tx_packets; 1056e9229ffdSFelix Fietkau u32 tx_bytes; 1057e9229ffdSFelix Fietkau struct dim tx_dim; 1058e9229ffdSFelix Fietkau 1059296c9120SStefan Roese int ip_align; 1060ba37b7caSFelix Fietkau 10611ccc723bSFelix Fietkau struct mtk_ppe *ppe; 1062502e84e2SFelix Fietkau struct rhashtable flow_table; 1063656e7052SJohn Crispin }; 1064656e7052SJohn Crispin 1065656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 1066656e7052SJohn Crispin * SoC 1067656e7052SJohn Crispin * @id: The number of the MAC 1068b8fc9f30SRené van Dorst * @interface: Interface mode kept for detecting change in hw settings 1069656e7052SJohn Crispin * @of_node: Our devicetree node 1070656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 1071656e7052SJohn Crispin * @hw_stats: Packet statistics counter 1072656e7052SJohn Crispin */ 1073656e7052SJohn Crispin struct mtk_mac { 1074656e7052SJohn Crispin int id; 1075b8fc9f30SRené van Dorst phy_interface_t interface; 1076b8fc9f30SRené van Dorst int speed; 1077656e7052SJohn Crispin struct device_node *of_node; 1078b8fc9f30SRené van Dorst struct phylink *phylink; 1079b8fc9f30SRené van Dorst struct phylink_config phylink_config; 1080656e7052SJohn Crispin struct mtk_eth *hw; 1081656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 1082ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1083ee406810SNelson Chang int hwlro_ip_cnt; 108421089867SRussell King (Oracle) unsigned int syscfg0; 1085656e7052SJohn Crispin }; 1086656e7052SJohn Crispin 1087656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1088656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 1089656e7052SJohn Crispin 1090656e7052SJohn Crispin /* read the hardware status register */ 1091656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 1092656e7052SJohn Crispin 1093656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1094656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1095656e7052SJohn Crispin 109614a44ab0SRussell King (Oracle) struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id); 10979ffee4a8SSean Wang int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 10989ffee4a8SSean Wang u32 ana_rgc3); 10997e538372SRené van Dorst 11007e538372SRené van Dorst int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 11017e538372SRené van Dorst int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 11027e538372SRené van Dorst int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 11039ffee4a8SSean Wang 1104502e84e2SFelix Fietkau int mtk_eth_offload_init(struct mtk_eth *eth); 1105502e84e2SFelix Fietkau int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1106502e84e2SFelix Fietkau void *type_data); 1107d776a57eSFelix Fietkau void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1108502e84e2SFelix Fietkau 1109502e84e2SFelix Fietkau 1110656e7052SJohn Crispin #endif /* MTK_ETH_H */ 1111