18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28e8e69d6SThomas Gleixner /* 3656e7052SJohn Crispin * 4656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7656e7052SJohn Crispin */ 8656e7052SJohn Crispin 9656e7052SJohn Crispin #ifndef MTK_ETH_H 10656e7052SJohn Crispin #define MTK_ETH_H 11656e7052SJohn Crispin 129ffee4a8SSean Wang #include <linux/dma-mapping.h> 139ffee4a8SSean Wang #include <linux/netdevice.h> 149ffee4a8SSean Wang #include <linux/of_net.h> 159ffee4a8SSean Wang #include <linux/u64_stats_sync.h> 16c6d4e63eSElena Reshetova #include <linux/refcount.h> 17b8fc9f30SRené van Dorst #include <linux/phylink.h> 18502e84e2SFelix Fietkau #include <linux/rhashtable.h> 19e9229ffdSFelix Fietkau #include <linux/dim.h> 20bc5e93e0SRussell King (Oracle) #include <linux/bitfield.h> 2123233e57SLorenzo Bianconi #include <net/page_pool.h> 2223233e57SLorenzo Bianconi #include <linux/bpf_trace.h> 23ba37b7caSFelix Fietkau #include "mtk_ppe.h" 24c6d4e63eSElena Reshetova 252d7605a7SFelix Fietkau #define MTK_MAX_DSA_PORTS 7 262d7605a7SFelix Fietkau #define MTK_DSA_PORT_MASK GENMASK(2, 0) 272d7605a7SFelix Fietkau 28f63959c7SFelix Fietkau #define MTK_QDMA_NUM_QUEUES 16 29656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 30656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 314fd59792SDENG Qingfang #define MTK_MAX_RX_LENGTH_2K 2048 32656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 33160d3a9bSLorenzo Bianconi #define MTK_TX_DMA_BUF_LEN_V2 0xffff 34c30e0b9bSFelix Fietkau #define MTK_QDMA_RING_SIZE 2048 356b4423b2SFelix Fietkau #define MTK_DMA_SIZE 512 36656e7052SJohn Crispin #define MTK_MAC_COUNT 2 374fd59792SDENG Qingfang #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 38656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 39656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 40656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 41656e7052SJohn Crispin NETIF_MSG_PROBE | \ 42656e7052SJohn Crispin NETIF_MSG_LINK | \ 43656e7052SJohn Crispin NETIF_MSG_TIMER | \ 44656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 45656e7052SJohn Crispin NETIF_MSG_IFUP | \ 46656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 47656e7052SJohn Crispin NETIF_MSG_TX_ERR) 48656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 49656e7052SJohn Crispin NETIF_F_RXCSUM | \ 50656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 51656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 52656e7052SJohn Crispin NETIF_F_TSO6 | \ 53502e84e2SFelix Fietkau NETIF_F_IPV6_CSUM |\ 54502e84e2SFelix Fietkau NETIF_F_HW_TC) 55296c9120SStefan Roese #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 5608df5fa6SStefan Roese #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 57ee406810SNelson Chang 5823233e57SLorenzo Bianconi #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM 5923233e57SLorenzo Bianconi #define MTK_PP_PAD (MTK_PP_HEADROOM + \ 6023233e57SLorenzo Bianconi SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 6123233e57SLorenzo Bianconi #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD) 6223233e57SLorenzo Bianconi 638cb42714SLorenzo Bianconi #define MTK_QRX_OFFSET 0x10 648cb42714SLorenzo Bianconi 65ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4 66ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8 67ee406810SNelson Chang 68ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 69ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2 70ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 71ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 72ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 73ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 74ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64 75ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000 76ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000 77ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 78656e7052SJohn Crispin 7906127504SLorenzo Bianconi /* Frame Engine Global Configuration */ 8006127504SLorenzo Bianconi #define MTK_FE_GLO_CFG 0x00 8106127504SLorenzo Bianconi #define MTK_FE_LINK_DOWN_P3 BIT(11) 8206127504SLorenzo Bianconi #define MTK_FE_LINK_DOWN_P4 BIT(12) 8306127504SLorenzo Bianconi 84656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 85656e7052SJohn Crispin #define MTK_RST_GL 0x04 86656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 87656e7052SJohn Crispin 88656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 89656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 9006127504SLorenzo Bianconi #define MTK_FE_INT_ENABLE 0x0c 9106127504SLorenzo Bianconi #define MTK_FE_INT_FQ_EMPTY BIT(8) 9206127504SLorenzo Bianconi #define MTK_FE_INT_TSO_FAIL BIT(12) 9306127504SLorenzo Bianconi #define MTK_FE_INT_TSO_ILLEGAL BIT(13) 9406127504SLorenzo Bianconi #define MTK_FE_INT_TSO_ALIGN BIT(14) 9506127504SLorenzo Bianconi #define MTK_FE_INT_RFIFO_OV BIT(18) 9606127504SLorenzo Bianconi #define MTK_FE_INT_RFIFO_UF BIT(19) 97656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 98656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 99656e7052SJohn Crispin 100ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */ 101ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 102ee406810SNelson Chang 103656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 104656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 105656e7052SJohn Crispin 10687e3df49SSean Wang /* CDMP Ingress Control Register */ 10787e3df49SSean Wang #define MTK_CDMQ_IG_CTRL 0x1400 10887e3df49SSean Wang #define MTK_CDMQ_STAG_EN BIT(0) 10987e3df49SSean Wang 1102d7605a7SFelix Fietkau /* CDMQ Exgress Control Register */ 1112d7605a7SFelix Fietkau #define MTK_CDMQ_EG_CTRL 0x1404 1122d7605a7SFelix Fietkau 113160d3a9bSLorenzo Bianconi /* CDMP Ingress Control Register */ 114160d3a9bSLorenzo Bianconi #define MTK_CDMP_IG_CTRL 0x400 115160d3a9bSLorenzo Bianconi #define MTK_CDMP_STAG_EN BIT(0) 116160d3a9bSLorenzo Bianconi 117656e7052SJohn Crispin /* CDMP Exgress Control Register */ 118656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 119656e7052SJohn Crispin 120656e7052SJohn Crispin /* GDM Exgress Control Register */ 121656e7052SJohn Crispin #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 122d5c53da2SFelix Fietkau #define MTK_GDMA_SPECIAL_TAG BIT(24) 123656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 124656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 125656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 1268d3f4a95SMarkLee #define MTK_GDMA_TO_PDMA 0x0 1278d66a818SMarkLee #define MTK_GDMA_DROP_ALL 0x7777 128656e7052SJohn Crispin 129656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 130656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 131656e7052SJohn Crispin 132656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 133656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 134656e7052SJohn Crispin 135160d3a9bSLorenzo Bianconi /* FE global misc reg*/ 136160d3a9bSLorenzo Bianconi #define MTK_FE_GLO_MISC 0x124 137160d3a9bSLorenzo Bianconi 138160d3a9bSLorenzo Bianconi /* PSE Free Queue Flow Control */ 139160d3a9bSLorenzo Bianconi #define PSE_FQFC_CFG1 0x100 140160d3a9bSLorenzo Bianconi #define PSE_FQFC_CFG2 0x104 141160d3a9bSLorenzo Bianconi #define PSE_DROP_CFG 0x108 142f4b2fa2cSFelix Fietkau #define PSE_PPE0_DROP 0x110 143160d3a9bSLorenzo Bianconi 144160d3a9bSLorenzo Bianconi /* PSE Input Queue Reservation Register*/ 145160d3a9bSLorenzo Bianconi #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) 146160d3a9bSLorenzo Bianconi 147160d3a9bSLorenzo Bianconi /* PSE Output Queue Threshold Register*/ 148160d3a9bSLorenzo Bianconi #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2)) 149160d3a9bSLorenzo Bianconi 150160d3a9bSLorenzo Bianconi /* GDM and CDM Threshold */ 151160d3a9bSLorenzo Bianconi #define MTK_GDM2_THRES 0x1530 152160d3a9bSLorenzo Bianconi #define MTK_CDMW0_THRES 0x164c 153160d3a9bSLorenzo Bianconi #define MTK_CDMW1_THRES 0x1650 154160d3a9bSLorenzo Bianconi #define MTK_CDME0_THRES 0x1654 155160d3a9bSLorenzo Bianconi #define MTK_CDME1_THRES 0x1658 156160d3a9bSLorenzo Bianconi #define MTK_CDMM_THRES 0x165c 157160d3a9bSLorenzo Bianconi 158ee406810SNelson Chang /* PDMA HW LRO Control Registers */ 159ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980 160ee406810SNelson Chang #define MTK_LRO_EN BIT(0) 161ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7) 162160d3a9bSLorenzo Bianconi #define MTK_L3_CKS_UPD_EN_V2 BIT(19) 163ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 164ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 165160d3a9bSLorenzo Bianconi #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24) 166ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 167160d3a9bSLorenzo Bianconi #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28) 168ee406810SNelson Chang 169ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984 170ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988 171ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c 172ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15) 173ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 174bacfd110SNelson Chang 1758cb42714SLorenzo Bianconi #define MTK_RX_DMA_LRO_EN BIT(8) 176bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10) 177296c9120SStefan Roese #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 178bacfd110SNelson Chang 1798cb42714SLorenzo Bianconi /* PDMA Global Configuration Register */ 1808cb42714SLorenzo Bianconi #define MTK_PDMA_LRO_SDL 0x3000 1818cb42714SLorenzo Bianconi #define MTK_RX_CFG_SDL_OFFSET 16 1828cb42714SLorenzo Bianconi 183bacfd110SNelson Chang /* PDMA Reset Index Register */ 184bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16) 185ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 186bacfd110SNelson Chang 187bacfd110SNelson Chang /* PDMA Delay Interrupt Register */ 188e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 189671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_EN BIT(15) 190671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 191e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 192e9229ffdSFelix Fietkau 193e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 194e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_EN BIT(31) 195e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 196e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 197e9229ffdSFelix Fietkau 198e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PINT_MASK 0x7f 199e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PTIME_MASK 0xff 200bacfd110SNelson Chang 201ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */ 202ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 203ee406810SNelson Chang 204ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */ 205ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 206ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 207ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9) 208ee406810SNelson Chang 209ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */ 210ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 211ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 212ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 213ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 214ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 215ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 216ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 217ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 218ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 219ee406810SNelson Chang #define MTK_RING_VLD BIT(8) 220ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 221ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 222ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 223ee406810SNelson Chang 224656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 225f63959c7SFelix Fietkau #define MTK_QTX_OFFSET 0x10 226656e7052SJohn Crispin #define QDMA_RES_THRES 4 227656e7052SJohn Crispin 228f63959c7SFelix Fietkau /* QDMA Tx Queue Scheduler Configuration Registers */ 229f63959c7SFelix Fietkau #define MTK_QTX_SCH_TX_SEL BIT(31) 230f63959c7SFelix Fietkau #define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30) 231f63959c7SFelix Fietkau 232f63959c7SFelix Fietkau #define MTK_QTX_SCH_LEAKY_BUCKET_EN BIT(30) 233f63959c7SFelix Fietkau #define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28) 234f63959c7SFelix Fietkau #define MTK_QTX_SCH_MIN_RATE_EN BIT(27) 235f63959c7SFelix Fietkau #define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20) 236f63959c7SFelix Fietkau #define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16) 237f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12) 238f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_EN BIT(11) 239f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4) 240f63959c7SFelix Fietkau #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0) 241f63959c7SFelix Fietkau 242f63959c7SFelix Fietkau /* QDMA TX Scheduler Rate Control Register */ 243f63959c7SFelix Fietkau #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15) 244f63959c7SFelix Fietkau 245656e7052SJohn Crispin /* QDMA Global Configuration Register */ 246656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 247656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 2486675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 249656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 25059555a8dSFelix Fietkau #define MTK_TX_BT_32DWORDS (3 << 4) 251656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 252656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 253656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 254656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 2553bc8e0afSIlya Lipnitskiy #define MTK_DMA_BUSY_TIMEOUT_US 1000000 256656e7052SJohn Crispin 257160d3a9bSLorenzo Bianconi /* QDMA V2 Global Configuration Register */ 258160d3a9bSLorenzo Bianconi #define MTK_CHK_DDONE_EN BIT(28) 259160d3a9bSLorenzo Bianconi #define MTK_DMAD_WR_WDONE BIT(26) 260160d3a9bSLorenzo Bianconi #define MTK_WCOMP_EN BIT(24) 261160d3a9bSLorenzo Bianconi #define MTK_RESV_BUF (0x40 << 16) 262160d3a9bSLorenzo Bianconi #define MTK_MUTLI_CNT (0x4 << 12) 263f63959c7SFelix Fietkau #define MTK_LEAKY_BUCKET_EN BIT(11) 264160d3a9bSLorenzo Bianconi 265656e7052SJohn Crispin /* QDMA Flow Control Register */ 266656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 267656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 268656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 269656e7052SJohn Crispin 270656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 271671d41e6SJohn Crispin #define MTK_RX_DONE_DLY BIT(30) 272e9229ffdSFelix Fietkau #define MTK_TX_DONE_DLY BIT(28) 273bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19) 274bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18) 275656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 276656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 277656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 278656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 279656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 280656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 281671d41e6SJohn Crispin #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 282e9229ffdSFelix Fietkau #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 283656e7052SJohn Crispin 284160d3a9bSLorenzo Bianconi #define MTK_RX_DONE_INT_V2 BIT(14) 285160d3a9bSLorenzo Bianconi 28693b2591aSLorenzo Bianconi #define MTK_CDM_TXFIFO_RDY BIT(7) 28793b2591aSLorenzo Bianconi 28880673029SJohn Crispin /* QDMA Interrupt grouping registers */ 28980673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0) 29080673029SJohn Crispin 291656e7052SJohn Crispin #define MTK_STAT_OFFSET 0x40 292656e7052SJohn Crispin 293160d3a9bSLorenzo Bianconi /* QDMA TX NUM */ 294160d3a9bSLorenzo Bianconi #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 295160d3a9bSLorenzo Bianconi #define MTK_QDMA_GMAC2_QID 8 296160d3a9bSLorenzo Bianconi 297160d3a9bSLorenzo Bianconi #define MTK_TX_DMA_BUF_SHIFT 8 298160d3a9bSLorenzo Bianconi 299160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd6 */ 300160d3a9bSLorenzo Bianconi #define TX_DMA_INS_VLAN_V2 BIT(16) 301160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd5 */ 302160d3a9bSLorenzo Bianconi #define TX_DMA_CHKSUM_V2 (0x7 << 28) 303160d3a9bSLorenzo Bianconi #define TX_DMA_TSO_V2 BIT(31) 304160d3a9bSLorenzo Bianconi 305160d3a9bSLorenzo Bianconi /* QDMA V2 descriptor txd4 */ 306160d3a9bSLorenzo Bianconi #define TX_DMA_FPORT_SHIFT_V2 8 307160d3a9bSLorenzo Bianconi #define TX_DMA_FPORT_MASK_V2 0xf 308160d3a9bSLorenzo Bianconi #define TX_DMA_SWC_V2 BIT(30) 309160d3a9bSLorenzo Bianconi 310656e7052SJohn Crispin /* QDMA descriptor txd4 */ 311656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 312656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 313656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 314656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 315656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 316656e7052SJohn Crispin 317656e7052SJohn Crispin /* QDMA descriptor txd3 */ 318656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 319656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 320160d3a9bSLorenzo Bianconi #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 321160d3a9bSLorenzo Bianconi #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) 322656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 323f63959c7SFelix Fietkau #define TX_DMA_PQID GENMASK(3, 0) 324656e7052SJohn Crispin 325296c9120SStefan Roese /* PDMA on MT7628 */ 326296c9120SStefan Roese #define TX_DMA_DONE BIT(31) 327296c9120SStefan Roese #define TX_DMA_LS1 BIT(14) 328296c9120SStefan Roese #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 329296c9120SStefan Roese 330656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 331656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 332296c9120SStefan Roese #define RX_DMA_LSO BIT(30) 333160d3a9bSLorenzo Bianconi #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) 334160d3a9bSLorenzo Bianconi #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) 3353f57d8c4SFelix Fietkau #define RX_DMA_VTAG BIT(15) 336656e7052SJohn Crispin 337656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 338160d3a9bSLorenzo Bianconi #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK) 339160d3a9bSLorenzo Bianconi #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK)) 340160d3a9bSLorenzo Bianconi #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff) 341656e7052SJohn Crispin 342656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 343ba37b7caSFelix Fietkau #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 344ba37b7caSFelix Fietkau #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 345ba37b7caSFelix Fietkau #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 346ba37b7caSFelix Fietkau #define MTK_RXD4_ALG GENMASK(31, 22) 347ba37b7caSFelix Fietkau 348ba37b7caSFelix Fietkau /* QDMA descriptor rxd4 */ 349656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 350296c9120SStefan Roese #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 351d5c53da2SFelix Fietkau #define RX_DMA_SPECIAL_TAG BIT(22) 352656e7052SJohn Crispin 3530cf731f9SLorenzo Bianconi /* PDMA descriptor rxd5 */ 3540cf731f9SLorenzo Bianconi #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) 3550cf731f9SLorenzo Bianconi #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) 3560cf731f9SLorenzo Bianconi #define MTK_RXD5_SRC_PORT GENMASK(29, 26) 3570cf731f9SLorenzo Bianconi 358c9da02bfSDaniel Golle #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7) 359c9da02bfSDaniel Golle #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf) 360160d3a9bSLorenzo Bianconi 361160d3a9bSLorenzo Bianconi /* PDMA V2 descriptor rxd3 */ 362160d3a9bSLorenzo Bianconi #define RX_DMA_VTAG_V2 BIT(0) 363160d3a9bSLorenzo Bianconi #define RX_DMA_L4_VALID_V2 BIT(2) 364160d3a9bSLorenzo Bianconi 365c0a44003SDaniel Golle /* PHY Polling and SMI Master Control registers */ 366c0a44003SDaniel Golle #define MTK_PPSC 0x10000 367c0a44003SDaniel Golle #define PPSC_MDC_CFG GENMASK(29, 24) 368c0a44003SDaniel Golle #define PPSC_MDC_TURBO BIT(20) 369c0a44003SDaniel Golle #define MDC_MAX_FREQ 25000000 370c0a44003SDaniel Golle #define MDC_MAX_DIVIDER 63 371c0a44003SDaniel Golle 372656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 373656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 374656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 375eda80b24SDaniel Golle #define PHY_IAC_REG_MASK GENMASK(29, 25) 376eda80b24SDaniel Golle #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) 377eda80b24SDaniel Golle #define PHY_IAC_ADDR_MASK GENMASK(24, 20) 378eda80b24SDaniel Golle #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) 379eda80b24SDaniel Golle #define PHY_IAC_CMD_MASK GENMASK(19, 18) 380e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) 381eda80b24SDaniel Golle #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) 382eda80b24SDaniel Golle #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) 383e2e7f6e2SDaniel Golle #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) 384eda80b24SDaniel Golle #define PHY_IAC_START_MASK GENMASK(17, 16) 385e2e7f6e2SDaniel Golle #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) 386eda80b24SDaniel Golle #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) 387eda80b24SDaniel Golle #define PHY_IAC_DATA_MASK GENMASK(15, 0) 388eda80b24SDaniel Golle #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) 389656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 390656e7052SJohn Crispin 39142c03844SSean Wang #define MTK_MAC_MISC 0x1000c 39242c03844SSean Wang #define MTK_MUX_TO_ESW BIT(0) 39342c03844SSean Wang 394656e7052SJohn Crispin /* Mac control registers */ 395656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 3964fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 3974fd59792SDENG Qingfang #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 3984fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1518 0x0 3994fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1536 0x1 4004fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1552 0x2 4014fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_2048 0x3 402656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 403656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 404656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 405656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 406193250acSDaniel Golle #define MAC_MCR_RX_FIFO_CLR_DIS BIT(12) 407656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 408656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 409656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 410656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 411656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 412656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 413656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 414656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 415b8fc9f30SRené van Dorst #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 416b8fc9f30SRené van Dorst 417b8fc9f30SRené van Dorst /* Mac status registers */ 418b8fc9f30SRené van Dorst #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 419b8fc9f30SRené van Dorst #define MAC_MSR_EEE1G BIT(7) 420b8fc9f30SRené van Dorst #define MAC_MSR_EEE100M BIT(6) 421b8fc9f30SRené van Dorst #define MAC_MSR_RX_FC BIT(5) 422b8fc9f30SRené van Dorst #define MAC_MSR_TX_FC BIT(4) 423b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_1000 BIT(3) 424b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_100 BIT(2) 425b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 426b8fc9f30SRené van Dorst #define MAC_MSR_DPX BIT(1) 427b8fc9f30SRené van Dorst #define MAC_MSR_LINK BIT(0) 428656e7052SJohn Crispin 429f430dea7SSean Wang /* TRGMII RXC control register */ 430f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300 431f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 432f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 433f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 434a5d75538SRené van Dorst #define RXC_RST BIT(31) 435f430dea7SSean Wang #define RXC_DQSISEL BIT(30) 436f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 437f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 438f430dea7SSean Wang 439a5d75538SRené van Dorst #define NUM_TRGMII_CTRL 5 440a5d75538SRené van Dorst 441f430dea7SSean Wang /* TRGMII RXC control register */ 442f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340 443f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 444f430dea7SSean Wang #define TXC_INV BIT(30) 445f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 446f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 447f430dea7SSean Wang 448a5d75538SRené van Dorst /* TRGMII TX Drive Strength */ 449a5d75538SRené van Dorst #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 450a5d75538SRené van Dorst #define TD_DM_DRVP(x) ((x) & 0xf) 451a5d75538SRené van Dorst #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 452a5d75538SRené van Dorst 453f430dea7SSean Wang /* TRGMII Interface mode register */ 454f430dea7SSean Wang #define INTF_MODE 0x10390 455f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0) 456f430dea7SSean Wang #define TRGMII_MODE BIT(1) 457f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2) 458f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 459f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0 460f430dea7SSean Wang 461656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 462656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 463656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 464656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 465656e7052SJohn Crispin 466b95b6d99SNelson Chang /* ethernet subsystem chip id register */ 467b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0 468b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4 469983e1a6cSNelson Chang #define MT7623_ETH 7623 47042c03844SSean Wang #define MT7622_ETH 7622 471889bcbdeSBjørn Mork #define MT7621_ETH 7621 472b95b6d99SNelson Chang 4738efaa653SRené van Dorst /* ethernet system control register */ 4748efaa653SRené van Dorst #define ETHSYS_SYSCFG 0x10 4758efaa653SRené van Dorst #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 4768efaa653SRené van Dorst 477656e7052SJohn Crispin /* ethernet subsystem config register */ 478656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 479656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 480656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 4817093f9d8SSean Wang #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 4827093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 4837093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 4847093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 4857093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 4867093f9d8SSean Wang 487656e7052SJohn Crispin 488f430dea7SSean Wang /* ethernet subsystem clock register */ 489f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c 490f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 4918efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 4928efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 4938efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 494f430dea7SSean Wang 4952a8307aaSSean Wang /* ethernet reset control register */ 4962a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34 4972a8307aaSSean Wang #define RSTCTRL_FE BIT(6) 498ef8c373bSLorenzo Bianconi #define RSTCTRL_PPE0 BIT(31) 499ef8c373bSLorenzo Bianconi #define RSTCTRL_PPE0_V2 BIT(30) 500ef8c373bSLorenzo Bianconi #define RSTCTRL_PPE1 BIT(31) 501160d3a9bSLorenzo Bianconi #define RSTCTRL_ETH BIT(23) 502160d3a9bSLorenzo Bianconi 503160d3a9bSLorenzo Bianconi /* ethernet reset check idle register */ 504160d3a9bSLorenzo Bianconi #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28 505160d3a9bSLorenzo Bianconi 506d776a57eSFelix Fietkau /* ethernet dma channel agent map */ 507d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP 0x408 508d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PDMA BIT(0) 509d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) 510d776a57eSFelix Fietkau #define ETHSYS_DMA_AG_MAP_PPE BIT(2) 511d776a57eSFelix Fietkau 5127093f9d8SSean Wang /* Infrasys subsystem config registers */ 5137093f9d8SSean Wang #define INFRA_MISC2 0x70c 5147093f9d8SSean Wang #define CO_QPHY_SEL BIT(0) 5157093f9d8SSean Wang #define GEPHY_MAC_SEL BIT(1) 5167093f9d8SSean Wang 517f5d43dddSDaniel Golle /* Top misc registers */ 518f5d43dddSDaniel Golle #define USB_PHY_SWITCH_REG 0x218 519f5d43dddSDaniel Golle #define QPHY_SEL_MASK GENMASK(1, 0) 520f5d43dddSDaniel Golle #define SGMII_QPHY_SEL 0x2 521f5d43dddSDaniel Golle 522296c9120SStefan Roese /* MT7628/88 specific stuff */ 523296c9120SStefan Roese #define MT7628_PDMA_OFFSET 0x0800 524296c9120SStefan Roese #define MT7628_SDM_OFFSET 0x0c00 525296c9120SStefan Roese 526296c9120SStefan Roese #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 527296c9120SStefan Roese #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 528296c9120SStefan Roese #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 529296c9120SStefan Roese #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 530296c9120SStefan Roese #define MT7628_PST_DTX_IDX0 BIT(0) 531296c9120SStefan Roese 532296c9120SStefan Roese #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 533296c9120SStefan Roese #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 534296c9120SStefan Roese 535ad79fd2cSStefan Roese /* Counter / stat register */ 536ad79fd2cSStefan Roese #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) 537ad79fd2cSStefan Roese #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) 538ad79fd2cSStefan Roese #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) 539ad79fd2cSStefan Roese #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) 540ad79fd2cSStefan Roese #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) 541ad79fd2cSStefan Roese 54293b2591aSLorenzo Bianconi #define MTK_FE_CDM1_FSM 0x220 54393b2591aSLorenzo Bianconi #define MTK_FE_CDM2_FSM 0x224 54493b2591aSLorenzo Bianconi #define MTK_FE_CDM3_FSM 0x238 54593b2591aSLorenzo Bianconi #define MTK_FE_CDM4_FSM 0x298 54693b2591aSLorenzo Bianconi #define MTK_FE_CDM5_FSM 0x318 54793b2591aSLorenzo Bianconi #define MTK_FE_CDM6_FSM 0x328 54893b2591aSLorenzo Bianconi #define MTK_FE_GDM1_FSM 0x228 54993b2591aSLorenzo Bianconi #define MTK_FE_GDM2_FSM 0x22C 55093b2591aSLorenzo Bianconi 55193b2591aSLorenzo Bianconi #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100)) 55293b2591aSLorenzo Bianconi 553656e7052SJohn Crispin struct mtk_rx_dma { 554656e7052SJohn Crispin unsigned int rxd1; 555656e7052SJohn Crispin unsigned int rxd2; 556656e7052SJohn Crispin unsigned int rxd3; 557656e7052SJohn Crispin unsigned int rxd4; 558656e7052SJohn Crispin } __packed __aligned(4); 559656e7052SJohn Crispin 560160d3a9bSLorenzo Bianconi struct mtk_rx_dma_v2 { 561160d3a9bSLorenzo Bianconi unsigned int rxd1; 562160d3a9bSLorenzo Bianconi unsigned int rxd2; 563160d3a9bSLorenzo Bianconi unsigned int rxd3; 564160d3a9bSLorenzo Bianconi unsigned int rxd4; 565160d3a9bSLorenzo Bianconi unsigned int rxd5; 566160d3a9bSLorenzo Bianconi unsigned int rxd6; 567160d3a9bSLorenzo Bianconi unsigned int rxd7; 568160d3a9bSLorenzo Bianconi unsigned int rxd8; 569160d3a9bSLorenzo Bianconi } __packed __aligned(4); 570160d3a9bSLorenzo Bianconi 571656e7052SJohn Crispin struct mtk_tx_dma { 572656e7052SJohn Crispin unsigned int txd1; 573656e7052SJohn Crispin unsigned int txd2; 574656e7052SJohn Crispin unsigned int txd3; 575656e7052SJohn Crispin unsigned int txd4; 576656e7052SJohn Crispin } __packed __aligned(4); 577656e7052SJohn Crispin 578160d3a9bSLorenzo Bianconi struct mtk_tx_dma_v2 { 579160d3a9bSLorenzo Bianconi unsigned int txd1; 580160d3a9bSLorenzo Bianconi unsigned int txd2; 581160d3a9bSLorenzo Bianconi unsigned int txd3; 582160d3a9bSLorenzo Bianconi unsigned int txd4; 583160d3a9bSLorenzo Bianconi unsigned int txd5; 584160d3a9bSLorenzo Bianconi unsigned int txd6; 585160d3a9bSLorenzo Bianconi unsigned int txd7; 586160d3a9bSLorenzo Bianconi unsigned int txd8; 587160d3a9bSLorenzo Bianconi } __packed __aligned(4); 588160d3a9bSLorenzo Bianconi 589656e7052SJohn Crispin struct mtk_eth; 590656e7052SJohn Crispin struct mtk_mac; 591656e7052SJohn Crispin 592916a6ee8SLorenzo Bianconi struct mtk_xdp_stats { 593916a6ee8SLorenzo Bianconi u64 rx_xdp_redirect; 594916a6ee8SLorenzo Bianconi u64 rx_xdp_pass; 595916a6ee8SLorenzo Bianconi u64 rx_xdp_drop; 596916a6ee8SLorenzo Bianconi u64 rx_xdp_tx; 597916a6ee8SLorenzo Bianconi u64 rx_xdp_tx_errors; 598916a6ee8SLorenzo Bianconi u64 tx_xdp_xmit; 599916a6ee8SLorenzo Bianconi u64 tx_xdp_xmit_errors; 600916a6ee8SLorenzo Bianconi }; 601916a6ee8SLorenzo Bianconi 602656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 603656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 604656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 605656e7052SJohn Crispin * @syncp: the refcount 606656e7052SJohn Crispin * 607656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 608656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 609656e7052SJohn Crispin * counters and store them in this struct. 610656e7052SJohn Crispin */ 611656e7052SJohn Crispin struct mtk_hw_stats { 612656e7052SJohn Crispin u64 tx_bytes; 613656e7052SJohn Crispin u64 tx_packets; 614656e7052SJohn Crispin u64 tx_skip; 615656e7052SJohn Crispin u64 tx_collisions; 616656e7052SJohn Crispin u64 rx_bytes; 617656e7052SJohn Crispin u64 rx_packets; 618656e7052SJohn Crispin u64 rx_overflow; 619656e7052SJohn Crispin u64 rx_fcs_errors; 620656e7052SJohn Crispin u64 rx_short_errors; 621656e7052SJohn Crispin u64 rx_long_errors; 622656e7052SJohn Crispin u64 rx_checksum_errors; 623656e7052SJohn Crispin u64 rx_flow_control_packets; 624656e7052SJohn Crispin 625916a6ee8SLorenzo Bianconi struct mtk_xdp_stats xdp_stats; 626916a6ee8SLorenzo Bianconi 627656e7052SJohn Crispin spinlock_t stats_lock; 628656e7052SJohn Crispin u32 reg_offset; 629656e7052SJohn Crispin struct u64_stats_sync syncp; 630656e7052SJohn Crispin }; 631656e7052SJohn Crispin 632656e7052SJohn Crispin enum mtk_tx_flags { 633134d2152SSean Wang /* PDMA descriptor can point at 1-2 segments. This enum allows us to 634134d2152SSean Wang * track how memory was allocated so that it can be freed properly. 635134d2152SSean Wang */ 636656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 637656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 638134d2152SSean Wang 639134d2152SSean Wang /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 640134d2152SSean Wang * SKB out instead of looking up through hardware TX descriptor. 641134d2152SSean Wang */ 642134d2152SSean Wang MTK_TX_FLAGS_FPORT0 = 0x04, 643134d2152SSean Wang MTK_TX_FLAGS_FPORT1 = 0x08, 644656e7052SJohn Crispin }; 645656e7052SJohn Crispin 646549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the 647549e5495SSean Wang * clock in the order 648549e5495SSean Wang */ 649549e5495SSean Wang enum mtk_clks_map { 650549e5495SSean Wang MTK_CLK_ETHIF, 651d438e298SSean Wang MTK_CLK_SGMIITOP, 652549e5495SSean Wang MTK_CLK_ESW, 65342c03844SSean Wang MTK_CLK_GP0, 654549e5495SSean Wang MTK_CLK_GP1, 655549e5495SSean Wang MTK_CLK_GP2, 656d438e298SSean Wang MTK_CLK_FE, 657f430dea7SSean Wang MTK_CLK_TRGPLL, 65842c03844SSean Wang MTK_CLK_SGMII_TX_250M, 65942c03844SSean Wang MTK_CLK_SGMII_RX_250M, 66042c03844SSean Wang MTK_CLK_SGMII_CDR_REF, 66142c03844SSean Wang MTK_CLK_SGMII_CDR_FB, 662d438e298SSean Wang MTK_CLK_SGMII2_TX_250M, 663d438e298SSean Wang MTK_CLK_SGMII2_RX_250M, 664d438e298SSean Wang MTK_CLK_SGMII2_CDR_REF, 665d438e298SSean Wang MTK_CLK_SGMII2_CDR_FB, 66642c03844SSean Wang MTK_CLK_SGMII_CK, 66742c03844SSean Wang MTK_CLK_ETH2PLL, 668197c9e9bSLorenzo Bianconi MTK_CLK_WOCPU0, 669197c9e9bSLorenzo Bianconi MTK_CLK_WOCPU1, 670197c9e9bSLorenzo Bianconi MTK_CLK_NETSYS0, 671197c9e9bSLorenzo Bianconi MTK_CLK_NETSYS1, 672549e5495SSean Wang MTK_CLK_MAX 673549e5495SSean Wang }; 674549e5495SSean Wang 6752ec50f57SSean Wang #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 6762ec50f57SSean Wang BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 6772ec50f57SSean Wang BIT(MTK_CLK_TRGPLL)) 67842c03844SSean Wang #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 67942c03844SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 68042c03844SSean Wang BIT(MTK_CLK_GP2) | \ 68142c03844SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 68242c03844SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 68342c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 68442c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 68542c03844SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 68642c03844SSean Wang BIT(MTK_CLK_ETH2PLL)) 687889bcbdeSBjørn Mork #define MT7621_CLKS_BITMAP (0) 688296c9120SStefan Roese #define MT7628_CLKS_BITMAP (0) 689d438e298SSean Wang #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 690d438e298SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 691d438e298SSean Wang BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 692d438e298SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 693d438e298SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 694d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 695d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 696d438e298SSean Wang BIT(MTK_CLK_SGMII2_TX_250M) | \ 697d438e298SSean Wang BIT(MTK_CLK_SGMII2_RX_250M) | \ 698d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_REF) | \ 699d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_FB) | \ 700d438e298SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 701d438e298SSean Wang BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 702f5d43dddSDaniel Golle #define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ 703f5d43dddSDaniel Golle BIT(MTK_CLK_WOCPU0) | \ 704f5d43dddSDaniel Golle BIT(MTK_CLK_SGMII_TX_250M) | \ 705f5d43dddSDaniel Golle BIT(MTK_CLK_SGMII_RX_250M) | \ 706f5d43dddSDaniel Golle BIT(MTK_CLK_SGMII_CDR_REF) | \ 707f5d43dddSDaniel Golle BIT(MTK_CLK_SGMII_CDR_FB) | \ 708f5d43dddSDaniel Golle BIT(MTK_CLK_SGMII2_TX_250M) | \ 709f5d43dddSDaniel Golle BIT(MTK_CLK_SGMII2_RX_250M) | \ 710f5d43dddSDaniel Golle BIT(MTK_CLK_SGMII2_CDR_REF) | \ 711f5d43dddSDaniel Golle BIT(MTK_CLK_SGMII2_CDR_FB) | \ 712f5d43dddSDaniel Golle BIT(MTK_CLK_SGMII_CK)) 713197c9e9bSLorenzo Bianconi #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ 714197c9e9bSLorenzo Bianconi BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ 715197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII_TX_250M) | \ 716197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII_RX_250M) | \ 717197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII_CDR_REF) | \ 718197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII_CDR_FB) | \ 719197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII2_TX_250M) | \ 720197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII2_RX_250M) | \ 721197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII2_CDR_REF) | \ 722197c9e9bSLorenzo Bianconi BIT(MTK_CLK_SGMII2_CDR_FB)) 723889bcbdeSBjørn Mork 7249ea4d311SSean Wang enum mtk_dev_state { 725dce6fa42SSean Wang MTK_HW_INIT, 726dce6fa42SSean Wang MTK_RESETTING 7279ea4d311SSean Wang }; 7289ea4d311SSean Wang 7295886d26fSLorenzo Bianconi enum mtk_tx_buf_type { 7305886d26fSLorenzo Bianconi MTK_TYPE_SKB, 7315886d26fSLorenzo Bianconi MTK_TYPE_XDP_TX, 7325886d26fSLorenzo Bianconi MTK_TYPE_XDP_NDO, 7335886d26fSLorenzo Bianconi }; 7345886d26fSLorenzo Bianconi 735656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 736656e7052SJohn Crispin * by the TX descriptor s 737656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 738656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 739656e7052SJohn Crispin * @dma_len0: The length of the first segment 740656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 741656e7052SJohn Crispin * @dma_len1: The length of the second segment 742656e7052SJohn Crispin */ 743656e7052SJohn Crispin struct mtk_tx_buf { 7445886d26fSLorenzo Bianconi enum mtk_tx_buf_type type; 7455886d26fSLorenzo Bianconi void *data; 7465886d26fSLorenzo Bianconi 747656e7052SJohn Crispin u32 flags; 748656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 749656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 750656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 751656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 752656e7052SJohn Crispin }; 753656e7052SJohn Crispin 754656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 755656e7052SJohn Crispin * @dma: The descriptor ring 756656e7052SJohn Crispin * @buf: The memory pointed at by the ring 757656e7052SJohn Crispin * @phys: The physical addr of tx_buf 758656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 759656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 7604e6bf609SFelix Fietkau * @last_free_ptr: Hardware pointer value of the last free descriptor 761656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 762656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 763656e7052SJohn Crispin * are present 764656e7052SJohn Crispin */ 765656e7052SJohn Crispin struct mtk_tx_ring { 7667173eca8SLorenzo Bianconi void *dma; 767656e7052SJohn Crispin struct mtk_tx_buf *buf; 768656e7052SJohn Crispin dma_addr_t phys; 769656e7052SJohn Crispin struct mtk_tx_dma *next_free; 770656e7052SJohn Crispin struct mtk_tx_dma *last_free; 7714e6bf609SFelix Fietkau u32 last_free_ptr; 772656e7052SJohn Crispin u16 thresh; 773656e7052SJohn Crispin atomic_t free_count; 774296c9120SStefan Roese int dma_size; 775296c9120SStefan Roese struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 776296c9120SStefan Roese dma_addr_t phys_pdma; 777296c9120SStefan Roese int cpu_idx; 778656e7052SJohn Crispin }; 779656e7052SJohn Crispin 780ee406810SNelson Chang /* PDMA rx ring mode */ 781ee406810SNelson Chang enum mtk_rx_flags { 782ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0, 783ee406810SNelson Chang MTK_RX_FLAGS_HWLRO, 7846427dc1dSJohn Crispin MTK_RX_FLAGS_QDMA, 785ee406810SNelson Chang }; 786ee406810SNelson Chang 787656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 788656e7052SJohn Crispin * @dma: The descriptor ring 789656e7052SJohn Crispin * @data: The memory pointed at by the ring 790656e7052SJohn Crispin * @phys: The physical addr of rx_buf 791656e7052SJohn Crispin * @frag_size: How big can each fragment be 792656e7052SJohn Crispin * @buf_size: The size of each packet buffer 793656e7052SJohn Crispin * @calc_idx: The current head of ring 794656e7052SJohn Crispin */ 795656e7052SJohn Crispin struct mtk_rx_ring { 7967173eca8SLorenzo Bianconi void *dma; 797656e7052SJohn Crispin u8 **data; 798656e7052SJohn Crispin dma_addr_t phys; 799656e7052SJohn Crispin u16 frag_size; 800656e7052SJohn Crispin u16 buf_size; 801ee406810SNelson Chang u16 dma_size; 802ee406810SNelson Chang bool calc_idx_update; 803656e7052SJohn Crispin u16 calc_idx; 804ee406810SNelson Chang u32 crx_idx_reg; 80523233e57SLorenzo Bianconi /* page_pool */ 80623233e57SLorenzo Bianconi struct page_pool *page_pool; 80723233e57SLorenzo Bianconi struct xdp_rxq_info xdp_q; 808656e7052SJohn Crispin }; 809656e7052SJohn Crispin 810e2c74694SRené van Dorst enum mkt_eth_capabilities { 811e2c74694SRené van Dorst MTK_RGMII_BIT = 0, 812e2c74694SRené van Dorst MTK_TRGMII_BIT, 813e2c74694SRené van Dorst MTK_SGMII_BIT, 814e2c74694SRené van Dorst MTK_ESW_BIT, 815e2c74694SRené van Dorst MTK_GEPHY_BIT, 816e2c74694SRené van Dorst MTK_MUX_BIT, 817e2c74694SRené van Dorst MTK_INFRA_BIT, 818e2c74694SRené van Dorst MTK_SHARED_SGMII_BIT, 819e2c74694SRené van Dorst MTK_HWLRO_BIT, 820e2c74694SRené van Dorst MTK_SHARED_INT_BIT, 821e2c74694SRené van Dorst MTK_TRGMII_MT7621_CLK_BIT, 822296c9120SStefan Roese MTK_QDMA_BIT, 823296c9120SStefan Roese MTK_SOC_MT7628_BIT, 824160d3a9bSLorenzo Bianconi MTK_RSTCTRL_PPE1_BIT, 825f5d43dddSDaniel Golle MTK_U3_COPHY_V2_BIT, 8267093f9d8SSean Wang 827e2c74694SRené van Dorst /* MUX BITS*/ 828e2c74694SRené van Dorst MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 829e2c74694SRené van Dorst MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 830e2c74694SRené van Dorst MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 831e2c74694SRené van Dorst MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 832e2c74694SRené van Dorst MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 833e2c74694SRené van Dorst 834e2c74694SRené van Dorst /* PATH BITS */ 835e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_RGMII_BIT, 836e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_TRGMII_BIT, 837e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_SGMII_BIT, 838e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_RGMII_BIT, 839e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_SGMII_BIT, 840e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_GEPHY_BIT, 841e2c74694SRené van Dorst MTK_ETH_PATH_GDM1_ESW_BIT, 8427093f9d8SSean Wang }; 8437093f9d8SSean Wang 8447093f9d8SSean Wang /* Supported hardware group on SoCs */ 845e2c74694SRené van Dorst #define MTK_RGMII BIT(MTK_RGMII_BIT) 846e2c74694SRené van Dorst #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 847e2c74694SRené van Dorst #define MTK_SGMII BIT(MTK_SGMII_BIT) 848e2c74694SRené van Dorst #define MTK_ESW BIT(MTK_ESW_BIT) 849e2c74694SRené van Dorst #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 850e2c74694SRené van Dorst #define MTK_MUX BIT(MTK_MUX_BIT) 851e2c74694SRené van Dorst #define MTK_INFRA BIT(MTK_INFRA_BIT) 852e2c74694SRené van Dorst #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 853e2c74694SRené van Dorst #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 854e2c74694SRené van Dorst #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 855e2c74694SRené van Dorst #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 856296c9120SStefan Roese #define MTK_QDMA BIT(MTK_QDMA_BIT) 857296c9120SStefan Roese #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 858160d3a9bSLorenzo Bianconi #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) 859f5d43dddSDaniel Golle #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) 860e2c74694SRené van Dorst 861e2c74694SRené van Dorst #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 862e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 863e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 864e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 865e2c74694SRené van Dorst #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 866e2c74694SRené van Dorst BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 867e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 868e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 869e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 870e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 8717093f9d8SSean Wang 8727093f9d8SSean Wang /* Supported path present on SoCs */ 873e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 874e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 875e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 876e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 877e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 878e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 879e2c74694SRené van Dorst #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 8807093f9d8SSean Wang 881e2c74694SRené van Dorst #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 882e2c74694SRené van Dorst #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 883e2c74694SRené van Dorst #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 884e2c74694SRené van Dorst #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 885e2c74694SRené van Dorst #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 886e2c74694SRené van Dorst #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 887e2c74694SRené van Dorst #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 8887093f9d8SSean Wang 8897093f9d8SSean Wang /* MUXes present on SoCs */ 8907093f9d8SSean Wang /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 891e2c74694SRené van Dorst #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 8927093f9d8SSean Wang 8937093f9d8SSean Wang /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 8947093f9d8SSean Wang #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 895e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 8967093f9d8SSean Wang 8977093f9d8SSean Wang /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 8987093f9d8SSean Wang #define MTK_MUX_U3_GMAC2_TO_QPHY \ 899e2c74694SRené van Dorst (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 9007093f9d8SSean Wang 9017093f9d8SSean Wang /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 9027093f9d8SSean Wang #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 903e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 9047093f9d8SSean Wang MTK_SHARED_SGMII) 9057093f9d8SSean Wang 9067093f9d8SSean Wang /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 9077093f9d8SSean Wang #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 908e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 9097093f9d8SSean Wang 9102ec50f57SSean Wang #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 9112ec50f57SSean Wang 9128efaa653SRené van Dorst #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 913296c9120SStefan Roese MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 914296c9120SStefan Roese MTK_TRGMII_MT7621_CLK | MTK_QDMA) 9158efaa653SRené van Dorst 9167093f9d8SSean Wang #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 9177093f9d8SSean Wang MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 9187093f9d8SSean Wang MTK_MUX_GDM1_TO_GMAC1_ESW | \ 919296c9120SStefan Roese MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 9207093f9d8SSean Wang 921296c9120SStefan Roese #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 922296c9120SStefan Roese MTK_QDMA) 923296c9120SStefan Roese 924296c9120SStefan Roese #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 9257093f9d8SSean Wang 9267093f9d8SSean Wang #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 9277093f9d8SSean Wang MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 9287093f9d8SSean Wang MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 9297093f9d8SSean Wang MTK_MUX_U3_GMAC2_TO_QPHY | \ 930296c9120SStefan Roese MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 9317093f9d8SSean Wang 932f5d43dddSDaniel Golle #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 933f5d43dddSDaniel Golle MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 934f5d43dddSDaniel Golle MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ 935a008e2a8SLorenzo Bianconi MTK_RSTCTRL_PPE1) 936f5d43dddSDaniel Golle 937197c9e9bSLorenzo Bianconi #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 938197c9e9bSLorenzo Bianconi MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 939a008e2a8SLorenzo Bianconi MTK_RSTCTRL_PPE1) 940197c9e9bSLorenzo Bianconi 941731f3fd6SLorenzo Bianconi struct mtk_tx_dma_desc_info { 942731f3fd6SLorenzo Bianconi dma_addr_t addr; 943731f3fd6SLorenzo Bianconi u32 size; 944731f3fd6SLorenzo Bianconi u16 vlan_tci; 945160d3a9bSLorenzo Bianconi u16 qid; 946731f3fd6SLorenzo Bianconi u8 gso:1; 947731f3fd6SLorenzo Bianconi u8 csum:1; 948731f3fd6SLorenzo Bianconi u8 vlan:1; 949731f3fd6SLorenzo Bianconi u8 first:1; 950731f3fd6SLorenzo Bianconi u8 last:1; 951731f3fd6SLorenzo Bianconi }; 952731f3fd6SLorenzo Bianconi 9538cb42714SLorenzo Bianconi struct mtk_reg_map { 9548cb42714SLorenzo Bianconi u32 tx_irq_mask; 9558cb42714SLorenzo Bianconi u32 tx_irq_status; 9568cb42714SLorenzo Bianconi struct { 9578cb42714SLorenzo Bianconi u32 rx_ptr; /* rx base pointer */ 9588cb42714SLorenzo Bianconi u32 rx_cnt_cfg; /* rx max count configuration */ 9598cb42714SLorenzo Bianconi u32 pcrx_ptr; /* rx cpu pointer */ 9608cb42714SLorenzo Bianconi u32 glo_cfg; /* global configuration */ 9618cb42714SLorenzo Bianconi u32 rst_idx; /* reset index */ 9628cb42714SLorenzo Bianconi u32 delay_irq; /* delay interrupt */ 9638cb42714SLorenzo Bianconi u32 irq_status; /* interrupt status */ 9648cb42714SLorenzo Bianconi u32 irq_mask; /* interrupt mask */ 96593b2591aSLorenzo Bianconi u32 adma_rx_dbg0; 9668cb42714SLorenzo Bianconi u32 int_grp; 9678cb42714SLorenzo Bianconi } pdma; 9688cb42714SLorenzo Bianconi struct { 9698cb42714SLorenzo Bianconi u32 qtx_cfg; /* tx queue configuration */ 970f63959c7SFelix Fietkau u32 qtx_sch; /* tx queue scheduler configuration */ 9718cb42714SLorenzo Bianconi u32 rx_ptr; /* rx base pointer */ 9728cb42714SLorenzo Bianconi u32 rx_cnt_cfg; /* rx max count configuration */ 9738cb42714SLorenzo Bianconi u32 qcrx_ptr; /* rx cpu pointer */ 9748cb42714SLorenzo Bianconi u32 glo_cfg; /* global configuration */ 9758cb42714SLorenzo Bianconi u32 rst_idx; /* reset index */ 9768cb42714SLorenzo Bianconi u32 delay_irq; /* delay interrupt */ 9778cb42714SLorenzo Bianconi u32 fc_th; /* flow control */ 9788cb42714SLorenzo Bianconi u32 int_grp; 9798cb42714SLorenzo Bianconi u32 hred; /* interrupt mask */ 9808cb42714SLorenzo Bianconi u32 ctx_ptr; /* tx acquire cpu pointer */ 9818cb42714SLorenzo Bianconi u32 dtx_ptr; /* tx acquire dma pointer */ 9828cb42714SLorenzo Bianconi u32 crx_ptr; /* tx release cpu pointer */ 9838cb42714SLorenzo Bianconi u32 drx_ptr; /* tx release dma pointer */ 9848cb42714SLorenzo Bianconi u32 fq_head; /* fq head pointer */ 9858cb42714SLorenzo Bianconi u32 fq_tail; /* fq tail pointer */ 9868cb42714SLorenzo Bianconi u32 fq_count; /* fq free page count */ 9878cb42714SLorenzo Bianconi u32 fq_blen; /* fq free page buffer length */ 988f63959c7SFelix Fietkau u32 tx_sch_rate; /* tx scheduler rate control registers */ 9898cb42714SLorenzo Bianconi } qdma; 9908cb42714SLorenzo Bianconi u32 gdm1_cnt; 991329bce51SLorenzo Bianconi u32 gdma_to_ppe; 992329bce51SLorenzo Bianconi u32 ppe_base; 9930c1d3fb9SLorenzo Bianconi u32 wdma_base[2]; 99493b2591aSLorenzo Bianconi u32 pse_iq_sta; 99593b2591aSLorenzo Bianconi u32 pse_oq_sta; 9968cb42714SLorenzo Bianconi }; 9978cb42714SLorenzo Bianconi 99842c03844SSean Wang /* struct mtk_eth_data - This is the structure holding all differences 9992ec50f57SSean Wang * among various plaforms 10008cb42714SLorenzo Bianconi * @reg_map Soc register map. 10019ffee4a8SSean Wang * @ana_rgc3: The offset for register ANA_RGC3 related to 10029ffee4a8SSean Wang * sgmiisys syscon 10032ec50f57SSean Wang * @caps Flags shown the extra capability for the SoC 1004296c9120SStefan Roese * @hw_features Flags shown HW features 10052ec50f57SSean Wang * @required_clks Flags shown the bitmap for required clocks on 10062ec50f57SSean Wang * the target SoC 1007243dc5fbSSean Wang * @required_pctl A bool value to show whether the SoC requires 1008243dc5fbSSean Wang * the extra setup for those pins used by GMAC. 1009ba2fc48cSLorenzo Bianconi * @hash_offset Flow table hash offset. 1010a008e2a8SLorenzo Bianconi * @version SoC version. 10119d8cb4c0SLorenzo Bianconi * @foe_entry_size Foe table entry size. 10123fbe4d8cSDaniel Golle * @has_accounting Bool indicating support for accounting of 10133fbe4d8cSDaniel Golle * offloaded flows. 1014eb067347SLorenzo Bianconi * @txd_size Tx DMA descriptor size. 1015670ff7daSLorenzo Bianconi * @rxd_size Rx DMA descriptor size. 1016160d3a9bSLorenzo Bianconi * @rx_irq_done_mask Rx irq done register mask. 1017160d3a9bSLorenzo Bianconi * @rx_dma_l4_valid Rx DMA valid register mask. 1018160d3a9bSLorenzo Bianconi * @dma_max_len Max DMA tx/rx buffer length. 1019160d3a9bSLorenzo Bianconi * @dma_len_offset Tx/Rx DMA length field offset. 10202ec50f57SSean Wang */ 10212ec50f57SSean Wang struct mtk_soc_data { 10228cb42714SLorenzo Bianconi const struct mtk_reg_map *reg_map; 10239ffee4a8SSean Wang u32 ana_rgc3; 10242ec50f57SSean Wang u32 caps; 10252ec50f57SSean Wang u32 required_clks; 1026243dc5fbSSean Wang bool required_pctl; 1027ba37b7caSFelix Fietkau u8 offload_version; 1028ba2fc48cSLorenzo Bianconi u8 hash_offset; 1029a008e2a8SLorenzo Bianconi u8 version; 10309d8cb4c0SLorenzo Bianconi u16 foe_entry_size; 1031296c9120SStefan Roese netdev_features_t hw_features; 10323fbe4d8cSDaniel Golle bool has_accounting; 103376a4cb75SRussell King (Oracle) bool disable_pll_modes; 1034eb067347SLorenzo Bianconi struct { 1035eb067347SLorenzo Bianconi u32 txd_size; 1036670ff7daSLorenzo Bianconi u32 rxd_size; 1037160d3a9bSLorenzo Bianconi u32 rx_irq_done_mask; 1038160d3a9bSLorenzo Bianconi u32 rx_dma_l4_valid; 1039160d3a9bSLorenzo Bianconi u32 dma_max_len; 1040160d3a9bSLorenzo Bianconi u32 dma_len_offset; 1041eb067347SLorenzo Bianconi } txrx; 10422ec50f57SSean Wang }; 10432ec50f57SSean Wang 104493b2591aSLorenzo Bianconi #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) 104593b2591aSLorenzo Bianconi 1046*6ca26557SLorenzo Bianconi /* currently no SoC has more than 3 macs */ 1047*6ca26557SLorenzo Bianconi #define MTK_MAX_DEVS 3 1048656e7052SJohn Crispin 1049656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 1050656e7052SJohn Crispin * of the driver 1051656e7052SJohn Crispin * @dev: The device pointer 1052d776a57eSFelix Fietkau * @dev: The device pointer used for dma mapping/alloc 1053656e7052SJohn Crispin * @base: The mapped register i/o base 1054656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 10555cce0322SJohn Crispin * @tx_irq__lock: Make sure that IRQ register operations are atomic 10565cce0322SJohn Crispin * @rx_irq__lock: Make sure that IRQ register operations are atomic 1057e9229ffdSFelix Fietkau * @dim_lock: Make sure that Net DIM operations are atomic 1058656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 1059656e7052SJohn Crispin * dummy for NAPI to work 1060656e7052SJohn Crispin * @netdev: The netdev instances 1061656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 1062656e7052SJohn Crispin * @irq: The IRQ that we are using 1063656e7052SJohn Crispin * @msg_enable: Ethtool msg level 1064656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 1065656e7052SJohn Crispin * MII modes 10667093f9d8SSean Wang * @infra: The register map pointing at the range used to setup 10677093f9d8SSean Wang * SGMII and GePHY path 10682a3ec7aeSDaniel Golle * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances 1069656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 1070656e7052SJohn Crispin * GMAC port drive/slew values 1071656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 10720c07ce7fSJohn Crispin * @tx_ring: Pointer to the memory holding info about the TX ring 10730c07ce7fSJohn Crispin * @rx_ring: Pointer to the memory holding info about the RX ring 10746427dc1dSJohn Crispin * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 107580673029SJohn Crispin * @tx_napi: The TX NAPI struct 107680673029SJohn Crispin * @rx_napi: The RX NAPI struct 1077e9229ffdSFelix Fietkau * @rx_events: Net DIM RX event counter 1078e9229ffdSFelix Fietkau * @rx_packets: Net DIM RX packet counter 1079e9229ffdSFelix Fietkau * @rx_bytes: Net DIM RX byte counter 1080e9229ffdSFelix Fietkau * @rx_dim: Net DIM RX context 1081e9229ffdSFelix Fietkau * @tx_events: Net DIM TX event counter 1082e9229ffdSFelix Fietkau * @tx_packets: Net DIM TX packet counter 1083e9229ffdSFelix Fietkau * @tx_bytes: Net DIM TX byte counter 1084e9229ffdSFelix Fietkau * @tx_dim: Net DIM TX context 1085656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 1086605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 1087656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 1088549e5495SSean Wang * @clks: clock array for all clocks required 1089656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 10907c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 109142c03844SSean Wang * @state: Initialization and runtime state of the device 10922ec50f57SSean Wang * @soc: Holding specific data among vaious SoCs 1093656e7052SJohn Crispin */ 1094656e7052SJohn Crispin 1095656e7052SJohn Crispin struct mtk_eth { 1096656e7052SJohn Crispin struct device *dev; 1097d776a57eSFelix Fietkau struct device *dma_dev; 1098656e7052SJohn Crispin void __iomem *base; 1099656e7052SJohn Crispin spinlock_t page_lock; 11005cce0322SJohn Crispin spinlock_t tx_irq_lock; 11015cce0322SJohn Crispin spinlock_t rx_irq_lock; 1102656e7052SJohn Crispin struct net_device dummy_dev; 1103656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 1104656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 110580673029SJohn Crispin int irq[3]; 1106656e7052SJohn Crispin u32 msg_enable; 1107656e7052SJohn Crispin unsigned long sysclk; 1108656e7052SJohn Crispin struct regmap *ethsys; 11097093f9d8SSean Wang struct regmap *infra; 11102a3ec7aeSDaniel Golle struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS]; 1111656e7052SJohn Crispin struct regmap *pctl; 1112ee406810SNelson Chang bool hwlro; 1113c6d4e63eSElena Reshetova refcount_t dma_refcnt; 1114656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 1115ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 11166427dc1dSJohn Crispin struct mtk_rx_ring rx_ring_qdma; 111780673029SJohn Crispin struct napi_struct tx_napi; 1118656e7052SJohn Crispin struct napi_struct rx_napi; 11194d642690SLorenzo Bianconi void *scratch_ring; 1120605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 1121656e7052SJohn Crispin void *scratch_head; 1122549e5495SSean Wang struct clk *clks[MTK_CLK_MAX]; 1123549e5495SSean Wang 1124656e7052SJohn Crispin struct mii_bus *mii_bus; 11257c78b4adSJohn Crispin struct work_struct pending_work; 11269ea4d311SSean Wang unsigned long state; 11272ec50f57SSean Wang 11282ec50f57SSean Wang const struct mtk_soc_data *soc; 1129296c9120SStefan Roese 1130e9229ffdSFelix Fietkau spinlock_t dim_lock; 1131e9229ffdSFelix Fietkau 1132e9229ffdSFelix Fietkau u32 rx_events; 1133e9229ffdSFelix Fietkau u32 rx_packets; 1134e9229ffdSFelix Fietkau u32 rx_bytes; 1135e9229ffdSFelix Fietkau struct dim rx_dim; 1136e9229ffdSFelix Fietkau 1137e9229ffdSFelix Fietkau u32 tx_events; 1138e9229ffdSFelix Fietkau u32 tx_packets; 1139e9229ffdSFelix Fietkau u32 tx_bytes; 1140e9229ffdSFelix Fietkau struct dim tx_dim; 1141e9229ffdSFelix Fietkau 1142296c9120SStefan Roese int ip_align; 1143ba37b7caSFelix Fietkau 11442d7605a7SFelix Fietkau struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS]; 11452d7605a7SFelix Fietkau 11464ff1a3fcSLorenzo Bianconi struct mtk_ppe *ppe[2]; 1147502e84e2SFelix Fietkau struct rhashtable flow_table; 11487c26c20dSLorenzo Bianconi 11497c26c20dSLorenzo Bianconi struct bpf_prog __rcu *prog; 115093b2591aSLorenzo Bianconi 115193b2591aSLorenzo Bianconi struct { 115293b2591aSLorenzo Bianconi struct delayed_work monitor_work; 115393b2591aSLorenzo Bianconi u32 wdidx; 115493b2591aSLorenzo Bianconi u8 wdma_hang_count; 115593b2591aSLorenzo Bianconi u8 qdma_hang_count; 115693b2591aSLorenzo Bianconi u8 adma_hang_count; 115793b2591aSLorenzo Bianconi } reset; 1158656e7052SJohn Crispin }; 1159656e7052SJohn Crispin 1160656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 1161656e7052SJohn Crispin * SoC 1162656e7052SJohn Crispin * @id: The number of the MAC 1163b8fc9f30SRené van Dorst * @interface: Interface mode kept for detecting change in hw settings 1164656e7052SJohn Crispin * @of_node: Our devicetree node 1165656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 1166656e7052SJohn Crispin * @hw_stats: Packet statistics counter 1167656e7052SJohn Crispin */ 1168656e7052SJohn Crispin struct mtk_mac { 1169656e7052SJohn Crispin int id; 1170b8fc9f30SRené van Dorst phy_interface_t interface; 1171b8fc9f30SRené van Dorst int speed; 1172656e7052SJohn Crispin struct device_node *of_node; 1173b8fc9f30SRené van Dorst struct phylink *phylink; 1174b8fc9f30SRené van Dorst struct phylink_config phylink_config; 1175656e7052SJohn Crispin struct mtk_eth *hw; 1176656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 1177ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 1178ee406810SNelson Chang int hwlro_ip_cnt; 117921089867SRussell King (Oracle) unsigned int syscfg0; 1180f63959c7SFelix Fietkau struct notifier_block device_notifier; 1181656e7052SJohn Crispin }; 1182656e7052SJohn Crispin 1183656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1184656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 1185656e7052SJohn Crispin 1186a008e2a8SLorenzo Bianconi static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) 1187a008e2a8SLorenzo Bianconi { 1188a008e2a8SLorenzo Bianconi return eth->soc->version == 1; 1189a008e2a8SLorenzo Bianconi } 1190a008e2a8SLorenzo Bianconi 1191a008e2a8SLorenzo Bianconi static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth) 1192a008e2a8SLorenzo Bianconi { 1193a008e2a8SLorenzo Bianconi return eth->soc->version > 1; 1194a008e2a8SLorenzo Bianconi } 1195a008e2a8SLorenzo Bianconi 11969d8cb4c0SLorenzo Bianconi static inline struct mtk_foe_entry * 11979d8cb4c0SLorenzo Bianconi mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 11989d8cb4c0SLorenzo Bianconi { 11999d8cb4c0SLorenzo Bianconi const struct mtk_soc_data *soc = ppe->eth->soc; 12009d8cb4c0SLorenzo Bianconi 12019d8cb4c0SLorenzo Bianconi return ppe->foe_table + hash * soc->foe_entry_size; 12029d8cb4c0SLorenzo Bianconi } 12039d8cb4c0SLorenzo Bianconi 120403a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 120503a3180eSLorenzo Bianconi { 1206a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 120703a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_TIMESTAMP_V2; 120803a3180eSLorenzo Bianconi 120903a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_TIMESTAMP; 121003a3180eSLorenzo Bianconi } 121103a3180eSLorenzo Bianconi 121203a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 121303a3180eSLorenzo Bianconi { 1214a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 121503a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_PPPOE_V2; 121603a3180eSLorenzo Bianconi 121703a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_PPPOE; 121803a3180eSLorenzo Bianconi } 121903a3180eSLorenzo Bianconi 122003a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 122103a3180eSLorenzo Bianconi { 1222a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 122303a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_TAG_V2; 122403a3180eSLorenzo Bianconi 122503a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_TAG; 122603a3180eSLorenzo Bianconi } 122703a3180eSLorenzo Bianconi 122803a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 122903a3180eSLorenzo Bianconi { 1230a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 123103a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; 123203a3180eSLorenzo Bianconi 123303a3180eSLorenzo Bianconi return MTK_FOE_IB1_BIND_VLAN_LAYER; 123403a3180eSLorenzo Bianconi } 123503a3180eSLorenzo Bianconi 123603a3180eSLorenzo Bianconi static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 123703a3180eSLorenzo Bianconi { 1238a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 123903a3180eSLorenzo Bianconi return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 124003a3180eSLorenzo Bianconi 124103a3180eSLorenzo Bianconi return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 124203a3180eSLorenzo Bianconi } 124303a3180eSLorenzo Bianconi 124403a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 124503a3180eSLorenzo Bianconi { 1246a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 124703a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 124803a3180eSLorenzo Bianconi 124903a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); 125003a3180eSLorenzo Bianconi } 125103a3180eSLorenzo Bianconi 125203a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 125303a3180eSLorenzo Bianconi { 1254a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 125503a3180eSLorenzo Bianconi return MTK_FOE_IB1_PACKET_TYPE_V2; 125603a3180eSLorenzo Bianconi 125703a3180eSLorenzo Bianconi return MTK_FOE_IB1_PACKET_TYPE; 125803a3180eSLorenzo Bianconi } 125903a3180eSLorenzo Bianconi 126003a3180eSLorenzo Bianconi static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 126103a3180eSLorenzo Bianconi { 1262a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 126303a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); 126403a3180eSLorenzo Bianconi 126503a3180eSLorenzo Bianconi return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); 126603a3180eSLorenzo Bianconi } 126703a3180eSLorenzo Bianconi 126803a3180eSLorenzo Bianconi static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) 126903a3180eSLorenzo Bianconi { 1270a008e2a8SLorenzo Bianconi if (mtk_is_netsys_v2_or_greater(eth)) 127103a3180eSLorenzo Bianconi return MTK_FOE_IB2_MULTICAST_V2; 127203a3180eSLorenzo Bianconi 127303a3180eSLorenzo Bianconi return MTK_FOE_IB2_MULTICAST; 127403a3180eSLorenzo Bianconi } 127503a3180eSLorenzo Bianconi 1276656e7052SJohn Crispin /* read the hardware status register */ 1277656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 1278656e7052SJohn Crispin 1279656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1280656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1281656e7052SJohn Crispin 12827e538372SRené van Dorst int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 12837e538372SRené van Dorst int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 12847e538372SRené van Dorst int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 12859ffee4a8SSean Wang 1286502e84e2SFelix Fietkau int mtk_eth_offload_init(struct mtk_eth *eth); 1287502e84e2SFelix Fietkau int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 1288502e84e2SFelix Fietkau void *type_data); 128905f3ab77SFelix Fietkau int mtk_flow_offload_cmd(struct mtk_eth *eth, struct flow_cls_offload *cls, 129005f3ab77SFelix Fietkau int ppe_index); 129105f3ab77SFelix Fietkau void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list); 1292d776a57eSFelix Fietkau void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); 1293502e84e2SFelix Fietkau 1294502e84e2SFelix Fietkau 1295656e7052SJohn Crispin #endif /* MTK_ETH_H */ 1296