18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28e8e69d6SThomas Gleixner /* 3656e7052SJohn Crispin * 4656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7656e7052SJohn Crispin */ 8656e7052SJohn Crispin 9656e7052SJohn Crispin #ifndef MTK_ETH_H 10656e7052SJohn Crispin #define MTK_ETH_H 11656e7052SJohn Crispin 129ffee4a8SSean Wang #include <linux/dma-mapping.h> 139ffee4a8SSean Wang #include <linux/netdevice.h> 149ffee4a8SSean Wang #include <linux/of_net.h> 159ffee4a8SSean Wang #include <linux/u64_stats_sync.h> 16c6d4e63eSElena Reshetova #include <linux/refcount.h> 17b8fc9f30SRené van Dorst #include <linux/phylink.h> 18502e84e2SFelix Fietkau #include <linux/rhashtable.h> 19ba37b7caSFelix Fietkau #include "mtk_ppe.h" 20c6d4e63eSElena Reshetova 21656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 22656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 234fd59792SDENG Qingfang #define MTK_MAX_RX_LENGTH_2K 2048 24656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 25*6b4423b2SFelix Fietkau #define MTK_DMA_SIZE 512 26656e7052SJohn Crispin #define MTK_NAPI_WEIGHT 64 27656e7052SJohn Crispin #define MTK_MAC_COUNT 2 284fd59792SDENG Qingfang #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 29656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 30656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 31656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 32656e7052SJohn Crispin NETIF_MSG_PROBE | \ 33656e7052SJohn Crispin NETIF_MSG_LINK | \ 34656e7052SJohn Crispin NETIF_MSG_TIMER | \ 35656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 36656e7052SJohn Crispin NETIF_MSG_IFUP | \ 37656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 38656e7052SJohn Crispin NETIF_MSG_TX_ERR) 39656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 40656e7052SJohn Crispin NETIF_F_RXCSUM | \ 41656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 42656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_RX | \ 43656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 44656e7052SJohn Crispin NETIF_F_TSO6 | \ 45502e84e2SFelix Fietkau NETIF_F_IPV6_CSUM |\ 46502e84e2SFelix Fietkau NETIF_F_HW_TC) 47296c9120SStefan Roese #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 4808df5fa6SStefan Roese #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 49ee406810SNelson Chang 50ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4 51ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8 52ee406810SNelson Chang 53ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 54ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2 55ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 56ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 57ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 58ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 59ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64 60ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000 61ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000 62ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 63656e7052SJohn Crispin 64656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 65656e7052SJohn Crispin #define MTK_RST_GL 0x04 66656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 67656e7052SJohn Crispin 68656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 69656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 70656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 71656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 72656e7052SJohn Crispin 73ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */ 74ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 75ee406810SNelson Chang 76656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 77656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 78656e7052SJohn Crispin 7987e3df49SSean Wang /* CDMP Ingress Control Register */ 8087e3df49SSean Wang #define MTK_CDMQ_IG_CTRL 0x1400 8187e3df49SSean Wang #define MTK_CDMQ_STAG_EN BIT(0) 8287e3df49SSean Wang 83656e7052SJohn Crispin /* CDMP Exgress Control Register */ 84656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 85656e7052SJohn Crispin 86656e7052SJohn Crispin /* GDM Exgress Control Register */ 87656e7052SJohn Crispin #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 88d5c53da2SFelix Fietkau #define MTK_GDMA_SPECIAL_TAG BIT(24) 89656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 90656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 91656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 928d3f4a95SMarkLee #define MTK_GDMA_TO_PDMA 0x0 93ba37b7caSFelix Fietkau #define MTK_GDMA_TO_PPE 0x4444 948d66a818SMarkLee #define MTK_GDMA_DROP_ALL 0x7777 95656e7052SJohn Crispin 96656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 97656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 98656e7052SJohn Crispin 99656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 100656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 101656e7052SJohn Crispin 102bacfd110SNelson Chang /* PDMA RX Base Pointer Register */ 103bacfd110SNelson Chang #define MTK_PRX_BASE_PTR0 0x900 104ee406810SNelson Chang #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 105bacfd110SNelson Chang 106bacfd110SNelson Chang /* PDMA RX Maximum Count Register */ 107bacfd110SNelson Chang #define MTK_PRX_MAX_CNT0 0x904 108ee406810SNelson Chang #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 109bacfd110SNelson Chang 110bacfd110SNelson Chang /* PDMA RX CPU Pointer Register */ 111bacfd110SNelson Chang #define MTK_PRX_CRX_IDX0 0x908 112ee406810SNelson Chang #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 113ee406810SNelson Chang 114ee406810SNelson Chang /* PDMA HW LRO Control Registers */ 115ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980 116ee406810SNelson Chang #define MTK_LRO_EN BIT(0) 117ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7) 118ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 119ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 120ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 121ee406810SNelson Chang 122ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984 123ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988 124ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c 125ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15) 126ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 127bacfd110SNelson Chang 128bacfd110SNelson Chang /* PDMA Global Configuration Register */ 129bacfd110SNelson Chang #define MTK_PDMA_GLO_CFG 0xa04 130bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10) 131296c9120SStefan Roese #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 132bacfd110SNelson Chang 133bacfd110SNelson Chang /* PDMA Reset Index Register */ 134bacfd110SNelson Chang #define MTK_PDMA_RST_IDX 0xa08 135bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16) 136ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 137bacfd110SNelson Chang 138bacfd110SNelson Chang /* PDMA Delay Interrupt Register */ 139bacfd110SNelson Chang #define MTK_PDMA_DELAY_INT 0xa0c 140671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_EN BIT(15) 141671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT 4 142671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 143671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PTIME 4 144671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_DELAY \ 145671d41e6SJohn Crispin (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ 146671d41e6SJohn Crispin (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) 147bacfd110SNelson Chang 148bacfd110SNelson Chang /* PDMA Interrupt Status Register */ 149bacfd110SNelson Chang #define MTK_PDMA_INT_STATUS 0xa20 150bacfd110SNelson Chang 151bacfd110SNelson Chang /* PDMA Interrupt Mask Register */ 152bacfd110SNelson Chang #define MTK_PDMA_INT_MASK 0xa28 153bacfd110SNelson Chang 154ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */ 155ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 156ee406810SNelson Chang 15780673029SJohn Crispin /* PDMA Interrupt grouping registers */ 15880673029SJohn Crispin #define MTK_PDMA_INT_GRP1 0xa50 15980673029SJohn Crispin #define MTK_PDMA_INT_GRP2 0xa54 16080673029SJohn Crispin 161ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */ 162ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 163ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 164ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9) 165ee406810SNelson Chang 166ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */ 167ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 168ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 169ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 170ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 171ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 172ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 173ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 174ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 175ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 176ee406810SNelson Chang #define MTK_RING_VLD BIT(8) 177ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 178ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 179ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 180ee406810SNelson Chang 181656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 182656e7052SJohn Crispin #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 183656e7052SJohn Crispin #define QDMA_RES_THRES 4 184656e7052SJohn Crispin 185656e7052SJohn Crispin /* QDMA TX Queue Scheduler Registers */ 186656e7052SJohn Crispin #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 187656e7052SJohn Crispin 188656e7052SJohn Crispin /* QDMA RX Base Pointer Register */ 189656e7052SJohn Crispin #define MTK_QRX_BASE_PTR0 0x1900 190656e7052SJohn Crispin 191656e7052SJohn Crispin /* QDMA RX Maximum Count Register */ 192656e7052SJohn Crispin #define MTK_QRX_MAX_CNT0 0x1904 193656e7052SJohn Crispin 194656e7052SJohn Crispin /* QDMA RX CPU Pointer Register */ 195656e7052SJohn Crispin #define MTK_QRX_CRX_IDX0 0x1908 196656e7052SJohn Crispin 197656e7052SJohn Crispin /* QDMA RX DMA Pointer Register */ 198656e7052SJohn Crispin #define MTK_QRX_DRX_IDX0 0x190C 199656e7052SJohn Crispin 200656e7052SJohn Crispin /* QDMA Global Configuration Register */ 201656e7052SJohn Crispin #define MTK_QDMA_GLO_CFG 0x1A04 202656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 203656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 2046675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 205656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 20659555a8dSFelix Fietkau #define MTK_TX_BT_32DWORDS (3 << 4) 207656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 208656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 209656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 210656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 211656e7052SJohn Crispin #define MTK_DMA_BUSY_TIMEOUT HZ 212656e7052SJohn Crispin 213656e7052SJohn Crispin /* QDMA Reset Index Register */ 214656e7052SJohn Crispin #define MTK_QDMA_RST_IDX 0x1A08 215656e7052SJohn Crispin 216656e7052SJohn Crispin /* QDMA Delay Interrupt Register */ 217656e7052SJohn Crispin #define MTK_QDMA_DELAY_INT 0x1A0C 218656e7052SJohn Crispin 219656e7052SJohn Crispin /* QDMA Flow Control Register */ 220656e7052SJohn Crispin #define MTK_QDMA_FC_THRES 0x1A10 221656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 222656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 223656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 224656e7052SJohn Crispin 225656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 22645487403SStefan Roese #define MTK_QDMA_INT_STATUS 0x1A18 227671d41e6SJohn Crispin #define MTK_RX_DONE_DLY BIT(30) 228bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19) 229bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18) 230656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 231656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 232656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 233656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 234656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 235656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 236671d41e6SJohn Crispin #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 237656e7052SJohn Crispin #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 238656e7052SJohn Crispin MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 239656e7052SJohn Crispin 24080673029SJohn Crispin /* QDMA Interrupt grouping registers */ 24180673029SJohn Crispin #define MTK_QDMA_INT_GRP1 0x1a20 24280673029SJohn Crispin #define MTK_QDMA_INT_GRP2 0x1a24 24380673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0) 24480673029SJohn Crispin 245656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 246656e7052SJohn Crispin #define MTK_QDMA_INT_MASK 0x1A1C 247656e7052SJohn Crispin 248656e7052SJohn Crispin /* QDMA Interrupt Mask Register */ 249656e7052SJohn Crispin #define MTK_QDMA_HRED2 0x1A44 250656e7052SJohn Crispin 251656e7052SJohn Crispin /* QDMA TX Forward CPU Pointer Register */ 252656e7052SJohn Crispin #define MTK_QTX_CTX_PTR 0x1B00 253656e7052SJohn Crispin 254656e7052SJohn Crispin /* QDMA TX Forward DMA Pointer Register */ 255656e7052SJohn Crispin #define MTK_QTX_DTX_PTR 0x1B04 256656e7052SJohn Crispin 257656e7052SJohn Crispin /* QDMA TX Release CPU Pointer Register */ 258656e7052SJohn Crispin #define MTK_QTX_CRX_PTR 0x1B10 259656e7052SJohn Crispin 260656e7052SJohn Crispin /* QDMA TX Release DMA Pointer Register */ 261656e7052SJohn Crispin #define MTK_QTX_DRX_PTR 0x1B14 262656e7052SJohn Crispin 263656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 264656e7052SJohn Crispin #define MTK_QDMA_FQ_HEAD 0x1B20 265656e7052SJohn Crispin 266656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 267656e7052SJohn Crispin #define MTK_QDMA_FQ_TAIL 0x1B24 268656e7052SJohn Crispin 269656e7052SJohn Crispin /* QDMA FQ Free Page Counter Register */ 270656e7052SJohn Crispin #define MTK_QDMA_FQ_CNT 0x1B28 271656e7052SJohn Crispin 272656e7052SJohn Crispin /* QDMA FQ Free Page Buffer Length Register */ 273656e7052SJohn Crispin #define MTK_QDMA_FQ_BLEN 0x1B2C 274656e7052SJohn Crispin 275656e7052SJohn Crispin /* GMA1 Received Good Byte Count Register */ 276656e7052SJohn Crispin #define MTK_GDM1_TX_GBCNT 0x2400 277656e7052SJohn Crispin #define MTK_STAT_OFFSET 0x40 278656e7052SJohn Crispin 279656e7052SJohn Crispin /* QDMA descriptor txd4 */ 280656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 281656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 282656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 283656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 284656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 285656e7052SJohn Crispin 286656e7052SJohn Crispin /* QDMA descriptor txd3 */ 287656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 288656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 289656e7052SJohn Crispin #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 290296c9120SStefan Roese #define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN) 291656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 292656e7052SJohn Crispin #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 293656e7052SJohn Crispin 294296c9120SStefan Roese /* PDMA on MT7628 */ 295296c9120SStefan Roese #define TX_DMA_DONE BIT(31) 296296c9120SStefan Roese #define TX_DMA_LS1 BIT(14) 297296c9120SStefan Roese #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 298296c9120SStefan Roese 299656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 300656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 301296c9120SStefan Roese #define RX_DMA_LSO BIT(30) 302656e7052SJohn Crispin #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 303656e7052SJohn Crispin #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 3043f57d8c4SFelix Fietkau #define RX_DMA_VTAG BIT(15) 305656e7052SJohn Crispin 306656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 307656e7052SJohn Crispin #define RX_DMA_VID(_x) ((_x) & 0xfff) 308656e7052SJohn Crispin 309656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 310ba37b7caSFelix Fietkau #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 311ba37b7caSFelix Fietkau #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 312ba37b7caSFelix Fietkau #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 313ba37b7caSFelix Fietkau #define MTK_RXD4_ALG GENMASK(31, 22) 314ba37b7caSFelix Fietkau 315ba37b7caSFelix Fietkau /* QDMA descriptor rxd4 */ 316656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 317296c9120SStefan Roese #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 318656e7052SJohn Crispin #define RX_DMA_FPORT_SHIFT 19 319656e7052SJohn Crispin #define RX_DMA_FPORT_MASK 0x7 320d5c53da2SFelix Fietkau #define RX_DMA_SPECIAL_TAG BIT(22) 321656e7052SJohn Crispin 322656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 323656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 324656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 325656e7052SJohn Crispin #define PHY_IAC_READ BIT(19) 326656e7052SJohn Crispin #define PHY_IAC_WRITE BIT(18) 327656e7052SJohn Crispin #define PHY_IAC_START BIT(16) 328656e7052SJohn Crispin #define PHY_IAC_ADDR_SHIFT 20 329656e7052SJohn Crispin #define PHY_IAC_REG_SHIFT 25 330656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 331656e7052SJohn Crispin 33242c03844SSean Wang #define MTK_MAC_MISC 0x1000c 33342c03844SSean Wang #define MTK_MUX_TO_ESW BIT(0) 33442c03844SSean Wang 335656e7052SJohn Crispin /* Mac control registers */ 336656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 3374fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 3384fd59792SDENG Qingfang #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 3394fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1518 0x0 3404fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1536 0x1 3414fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1552 0x2 3424fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_2048 0x3 343656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 344656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 345656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 346656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 347656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 348656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 349656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 350656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 351656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 352656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 353656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 354656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 355b8fc9f30SRené van Dorst #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 356b8fc9f30SRené van Dorst 357b8fc9f30SRené van Dorst /* Mac status registers */ 358b8fc9f30SRené van Dorst #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 359b8fc9f30SRené van Dorst #define MAC_MSR_EEE1G BIT(7) 360b8fc9f30SRené van Dorst #define MAC_MSR_EEE100M BIT(6) 361b8fc9f30SRené van Dorst #define MAC_MSR_RX_FC BIT(5) 362b8fc9f30SRené van Dorst #define MAC_MSR_TX_FC BIT(4) 363b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_1000 BIT(3) 364b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_100 BIT(2) 365b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 366b8fc9f30SRené van Dorst #define MAC_MSR_DPX BIT(1) 367b8fc9f30SRené van Dorst #define MAC_MSR_LINK BIT(0) 368656e7052SJohn Crispin 369f430dea7SSean Wang /* TRGMII RXC control register */ 370f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300 371f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 372f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 373f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 374a5d75538SRené van Dorst #define RXC_RST BIT(31) 375f430dea7SSean Wang #define RXC_DQSISEL BIT(30) 376f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 377f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 378f430dea7SSean Wang 379a5d75538SRené van Dorst #define NUM_TRGMII_CTRL 5 380a5d75538SRené van Dorst 381f430dea7SSean Wang /* TRGMII RXC control register */ 382f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340 383f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 384f430dea7SSean Wang #define TXC_INV BIT(30) 385f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 386f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 387f430dea7SSean Wang 388a5d75538SRené van Dorst /* TRGMII TX Drive Strength */ 389a5d75538SRené van Dorst #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 390a5d75538SRené van Dorst #define TD_DM_DRVP(x) ((x) & 0xf) 391a5d75538SRené van Dorst #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 392a5d75538SRené van Dorst 393f430dea7SSean Wang /* TRGMII Interface mode register */ 394f430dea7SSean Wang #define INTF_MODE 0x10390 395f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0) 396f430dea7SSean Wang #define TRGMII_MODE BIT(1) 397f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2) 398f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 399f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0 400f430dea7SSean Wang 401656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 402656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 403656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 404656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 405656e7052SJohn Crispin 406b95b6d99SNelson Chang /* ethernet subsystem chip id register */ 407b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0 408b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4 409983e1a6cSNelson Chang #define MT7623_ETH 7623 41042c03844SSean Wang #define MT7622_ETH 7622 411889bcbdeSBjørn Mork #define MT7621_ETH 7621 412b95b6d99SNelson Chang 4138efaa653SRené van Dorst /* ethernet system control register */ 4148efaa653SRené van Dorst #define ETHSYS_SYSCFG 0x10 4158efaa653SRené van Dorst #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 4168efaa653SRené van Dorst 417656e7052SJohn Crispin /* ethernet subsystem config register */ 418656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 419656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 420656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 4217093f9d8SSean Wang #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 4227093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 4237093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 4247093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 4257093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 4267093f9d8SSean Wang 427656e7052SJohn Crispin 428f430dea7SSean Wang /* ethernet subsystem clock register */ 429f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c 430f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 4318efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 4328efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 4338efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 434f430dea7SSean Wang 4352a8307aaSSean Wang /* ethernet reset control register */ 4362a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34 4372a8307aaSSean Wang #define RSTCTRL_FE BIT(6) 4382a8307aaSSean Wang #define RSTCTRL_PPE BIT(31) 4392a8307aaSSean Wang 44042c03844SSean Wang /* SGMII subsystem config registers */ 44142c03844SSean Wang /* Register to auto-negotiation restart */ 44242c03844SSean Wang #define SGMSYS_PCS_CONTROL_1 0x0 44342c03844SSean Wang #define SGMII_AN_RESTART BIT(9) 4447e538372SRené van Dorst #define SGMII_ISOLATE BIT(10) 4457e538372SRené van Dorst #define SGMII_AN_ENABLE BIT(12) 4467e538372SRené van Dorst #define SGMII_LINK_STATYS BIT(18) 4477e538372SRené van Dorst #define SGMII_AN_ABILITY BIT(19) 4487e538372SRené van Dorst #define SGMII_AN_COMPLETE BIT(21) 4497e538372SRené van Dorst #define SGMII_PCS_FAULT BIT(23) 4507e538372SRené van Dorst #define SGMII_AN_EXPANSION_CLR BIT(30) 45142c03844SSean Wang 45242c03844SSean Wang /* Register to programmable link timer, the unit in 2 * 8ns */ 45342c03844SSean Wang #define SGMSYS_PCS_LINK_TIMER 0x18 45442c03844SSean Wang #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 45542c03844SSean Wang 45642c03844SSean Wang /* Register to control remote fault */ 45742c03844SSean Wang #define SGMSYS_SGMII_MODE 0x20 4587e538372SRené van Dorst #define SGMII_IF_MODE_BIT0 BIT(0) 4597e538372SRené van Dorst #define SGMII_SPEED_DUPLEX_AN BIT(1) 4607e538372SRené van Dorst #define SGMII_SPEED_10 0x0 4617e538372SRené van Dorst #define SGMII_SPEED_100 BIT(2) 4627e538372SRené van Dorst #define SGMII_SPEED_1000 BIT(3) 4637e538372SRené van Dorst #define SGMII_DUPLEX_FULL BIT(4) 4647e538372SRené van Dorst #define SGMII_IF_MODE_BIT5 BIT(5) 46542c03844SSean Wang #define SGMII_REMOTE_FAULT_DIS BIT(8) 4667e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_VAL BIT(9) 4677e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_EN BIT(10) 4687e538372SRené van Dorst #define SGMII_SEND_AN_ERROR_EN BIT(11) 4697e538372SRené van Dorst #define SGMII_IF_MODE_MASK GENMASK(5, 1) 4707e538372SRené van Dorst 4717e538372SRené van Dorst /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 4727e538372SRené van Dorst #define SGMSYS_ANA_RG_CS3 0x2028 4737e538372SRené van Dorst #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 4747e538372SRené van Dorst #define RG_PHY_SPEED_1_25G 0x0 4757e538372SRené van Dorst #define RG_PHY_SPEED_3_125G BIT(2) 47642c03844SSean Wang 47742c03844SSean Wang /* Register to power up QPHY */ 47842c03844SSean Wang #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 47942c03844SSean Wang #define SGMII_PHYA_PWD BIT(4) 48042c03844SSean Wang 4817093f9d8SSean Wang /* Infrasys subsystem config registers */ 4827093f9d8SSean Wang #define INFRA_MISC2 0x70c 4837093f9d8SSean Wang #define CO_QPHY_SEL BIT(0) 4847093f9d8SSean Wang #define GEPHY_MAC_SEL BIT(1) 4857093f9d8SSean Wang 486296c9120SStefan Roese /* MT7628/88 specific stuff */ 487296c9120SStefan Roese #define MT7628_PDMA_OFFSET 0x0800 488296c9120SStefan Roese #define MT7628_SDM_OFFSET 0x0c00 489296c9120SStefan Roese 490296c9120SStefan Roese #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 491296c9120SStefan Roese #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 492296c9120SStefan Roese #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 493296c9120SStefan Roese #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 494296c9120SStefan Roese #define MT7628_PST_DTX_IDX0 BIT(0) 495296c9120SStefan Roese 496296c9120SStefan Roese #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 497296c9120SStefan Roese #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 498296c9120SStefan Roese 499656e7052SJohn Crispin struct mtk_rx_dma { 500656e7052SJohn Crispin unsigned int rxd1; 501656e7052SJohn Crispin unsigned int rxd2; 502656e7052SJohn Crispin unsigned int rxd3; 503656e7052SJohn Crispin unsigned int rxd4; 504656e7052SJohn Crispin } __packed __aligned(4); 505656e7052SJohn Crispin 506656e7052SJohn Crispin struct mtk_tx_dma { 507656e7052SJohn Crispin unsigned int txd1; 508656e7052SJohn Crispin unsigned int txd2; 509656e7052SJohn Crispin unsigned int txd3; 510656e7052SJohn Crispin unsigned int txd4; 511656e7052SJohn Crispin } __packed __aligned(4); 512656e7052SJohn Crispin 513656e7052SJohn Crispin struct mtk_eth; 514656e7052SJohn Crispin struct mtk_mac; 515656e7052SJohn Crispin 516656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 517656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 518656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 519656e7052SJohn Crispin * @syncp: the refcount 520656e7052SJohn Crispin * 521656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 522656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 523656e7052SJohn Crispin * counters and store them in this struct. 524656e7052SJohn Crispin */ 525656e7052SJohn Crispin struct mtk_hw_stats { 526656e7052SJohn Crispin u64 tx_bytes; 527656e7052SJohn Crispin u64 tx_packets; 528656e7052SJohn Crispin u64 tx_skip; 529656e7052SJohn Crispin u64 tx_collisions; 530656e7052SJohn Crispin u64 rx_bytes; 531656e7052SJohn Crispin u64 rx_packets; 532656e7052SJohn Crispin u64 rx_overflow; 533656e7052SJohn Crispin u64 rx_fcs_errors; 534656e7052SJohn Crispin u64 rx_short_errors; 535656e7052SJohn Crispin u64 rx_long_errors; 536656e7052SJohn Crispin u64 rx_checksum_errors; 537656e7052SJohn Crispin u64 rx_flow_control_packets; 538656e7052SJohn Crispin 539656e7052SJohn Crispin spinlock_t stats_lock; 540656e7052SJohn Crispin u32 reg_offset; 541656e7052SJohn Crispin struct u64_stats_sync syncp; 542656e7052SJohn Crispin }; 543656e7052SJohn Crispin 544656e7052SJohn Crispin enum mtk_tx_flags { 545134d2152SSean Wang /* PDMA descriptor can point at 1-2 segments. This enum allows us to 546134d2152SSean Wang * track how memory was allocated so that it can be freed properly. 547134d2152SSean Wang */ 548656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 549656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 550134d2152SSean Wang 551134d2152SSean Wang /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 552134d2152SSean Wang * SKB out instead of looking up through hardware TX descriptor. 553134d2152SSean Wang */ 554134d2152SSean Wang MTK_TX_FLAGS_FPORT0 = 0x04, 555134d2152SSean Wang MTK_TX_FLAGS_FPORT1 = 0x08, 556656e7052SJohn Crispin }; 557656e7052SJohn Crispin 558549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the 559549e5495SSean Wang * clock in the order 560549e5495SSean Wang */ 561549e5495SSean Wang enum mtk_clks_map { 562549e5495SSean Wang MTK_CLK_ETHIF, 563d438e298SSean Wang MTK_CLK_SGMIITOP, 564549e5495SSean Wang MTK_CLK_ESW, 56542c03844SSean Wang MTK_CLK_GP0, 566549e5495SSean Wang MTK_CLK_GP1, 567549e5495SSean Wang MTK_CLK_GP2, 568d438e298SSean Wang MTK_CLK_FE, 569f430dea7SSean Wang MTK_CLK_TRGPLL, 57042c03844SSean Wang MTK_CLK_SGMII_TX_250M, 57142c03844SSean Wang MTK_CLK_SGMII_RX_250M, 57242c03844SSean Wang MTK_CLK_SGMII_CDR_REF, 57342c03844SSean Wang MTK_CLK_SGMII_CDR_FB, 574d438e298SSean Wang MTK_CLK_SGMII2_TX_250M, 575d438e298SSean Wang MTK_CLK_SGMII2_RX_250M, 576d438e298SSean Wang MTK_CLK_SGMII2_CDR_REF, 577d438e298SSean Wang MTK_CLK_SGMII2_CDR_FB, 57842c03844SSean Wang MTK_CLK_SGMII_CK, 57942c03844SSean Wang MTK_CLK_ETH2PLL, 580549e5495SSean Wang MTK_CLK_MAX 581549e5495SSean Wang }; 582549e5495SSean Wang 5832ec50f57SSean Wang #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 5842ec50f57SSean Wang BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 5852ec50f57SSean Wang BIT(MTK_CLK_TRGPLL)) 58642c03844SSean Wang #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 58742c03844SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 58842c03844SSean Wang BIT(MTK_CLK_GP2) | \ 58942c03844SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 59042c03844SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 59142c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 59242c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 59342c03844SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 59442c03844SSean Wang BIT(MTK_CLK_ETH2PLL)) 595889bcbdeSBjørn Mork #define MT7621_CLKS_BITMAP (0) 596296c9120SStefan Roese #define MT7628_CLKS_BITMAP (0) 597d438e298SSean Wang #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 598d438e298SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 599d438e298SSean Wang BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 600d438e298SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 601d438e298SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 602d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 603d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 604d438e298SSean Wang BIT(MTK_CLK_SGMII2_TX_250M) | \ 605d438e298SSean Wang BIT(MTK_CLK_SGMII2_RX_250M) | \ 606d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_REF) | \ 607d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_FB) | \ 608d438e298SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 609d438e298SSean Wang BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 610889bcbdeSBjørn Mork 6119ea4d311SSean Wang enum mtk_dev_state { 612dce6fa42SSean Wang MTK_HW_INIT, 613dce6fa42SSean Wang MTK_RESETTING 6149ea4d311SSean Wang }; 6159ea4d311SSean Wang 616656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 617656e7052SJohn Crispin * by the TX descriptor s 618656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 619656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 620656e7052SJohn Crispin * @dma_len0: The length of the first segment 621656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 622656e7052SJohn Crispin * @dma_len1: The length of the second segment 623656e7052SJohn Crispin */ 624656e7052SJohn Crispin struct mtk_tx_buf { 625656e7052SJohn Crispin struct sk_buff *skb; 626656e7052SJohn Crispin u32 flags; 627656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 628656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 629656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 630656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 631656e7052SJohn Crispin }; 632656e7052SJohn Crispin 633656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 634656e7052SJohn Crispin * @dma: The descriptor ring 635656e7052SJohn Crispin * @buf: The memory pointed at by the ring 636656e7052SJohn Crispin * @phys: The physical addr of tx_buf 637656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 638656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 639656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 640656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 641656e7052SJohn Crispin * are present 642656e7052SJohn Crispin */ 643656e7052SJohn Crispin struct mtk_tx_ring { 644656e7052SJohn Crispin struct mtk_tx_dma *dma; 645656e7052SJohn Crispin struct mtk_tx_buf *buf; 646656e7052SJohn Crispin dma_addr_t phys; 647656e7052SJohn Crispin struct mtk_tx_dma *next_free; 648656e7052SJohn Crispin struct mtk_tx_dma *last_free; 649656e7052SJohn Crispin u16 thresh; 650656e7052SJohn Crispin atomic_t free_count; 651296c9120SStefan Roese int dma_size; 652296c9120SStefan Roese struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 653296c9120SStefan Roese dma_addr_t phys_pdma; 654296c9120SStefan Roese int cpu_idx; 655656e7052SJohn Crispin }; 656656e7052SJohn Crispin 657ee406810SNelson Chang /* PDMA rx ring mode */ 658ee406810SNelson Chang enum mtk_rx_flags { 659ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0, 660ee406810SNelson Chang MTK_RX_FLAGS_HWLRO, 6616427dc1dSJohn Crispin MTK_RX_FLAGS_QDMA, 662ee406810SNelson Chang }; 663ee406810SNelson Chang 664656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 665656e7052SJohn Crispin * @dma: The descriptor ring 666656e7052SJohn Crispin * @data: The memory pointed at by the ring 667656e7052SJohn Crispin * @phys: The physical addr of rx_buf 668656e7052SJohn Crispin * @frag_size: How big can each fragment be 669656e7052SJohn Crispin * @buf_size: The size of each packet buffer 670656e7052SJohn Crispin * @calc_idx: The current head of ring 671656e7052SJohn Crispin */ 672656e7052SJohn Crispin struct mtk_rx_ring { 673656e7052SJohn Crispin struct mtk_rx_dma *dma; 674656e7052SJohn Crispin u8 **data; 675656e7052SJohn Crispin dma_addr_t phys; 676656e7052SJohn Crispin u16 frag_size; 677656e7052SJohn Crispin u16 buf_size; 678ee406810SNelson Chang u16 dma_size; 679ee406810SNelson Chang bool calc_idx_update; 680656e7052SJohn Crispin u16 calc_idx; 681ee406810SNelson Chang u32 crx_idx_reg; 682656e7052SJohn Crispin }; 683656e7052SJohn Crispin 684e2c74694SRené van Dorst enum mkt_eth_capabilities { 685e2c74694SRené van Dorst MTK_RGMII_BIT = 0, 686e2c74694SRené van Dorst MTK_TRGMII_BIT, 687e2c74694SRené van Dorst MTK_SGMII_BIT, 688e2c74694SRené van Dorst MTK_ESW_BIT, 689e2c74694SRené van Dorst MTK_GEPHY_BIT, 690e2c74694SRené van Dorst MTK_MUX_BIT, 691e2c74694SRené van Dorst MTK_INFRA_BIT, 692e2c74694SRené van Dorst MTK_SHARED_SGMII_BIT, 693e2c74694SRené van Dorst MTK_HWLRO_BIT, 694e2c74694SRené van Dorst MTK_SHARED_INT_BIT, 695e2c74694SRené van Dorst MTK_TRGMII_MT7621_CLK_BIT, 696296c9120SStefan Roese MTK_QDMA_BIT, 697296c9120SStefan Roese MTK_SOC_MT7628_BIT, 6987093f9d8SSean Wang 699e2c74694SRené van Dorst /* MUX BITS*/ 700e2c74694SRené van Dorst MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 701e2c74694SRené van Dorst MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 702e2c74694SRené van Dorst MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 703e2c74694SRené van Dorst MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 704e2c74694SRené van Dorst MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 705e2c74694SRené van Dorst 706e2c74694SRené van Dorst /* PATH BITS */ 707e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_RGMII_BIT, 708e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_TRGMII_BIT, 709e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_SGMII_BIT, 710e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_RGMII_BIT, 711e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_SGMII_BIT, 712e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_GEPHY_BIT, 713e2c74694SRené van Dorst MTK_ETH_PATH_GDM1_ESW_BIT, 7147093f9d8SSean Wang }; 7157093f9d8SSean Wang 7167093f9d8SSean Wang /* Supported hardware group on SoCs */ 717e2c74694SRené van Dorst #define MTK_RGMII BIT(MTK_RGMII_BIT) 718e2c74694SRené van Dorst #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 719e2c74694SRené van Dorst #define MTK_SGMII BIT(MTK_SGMII_BIT) 720e2c74694SRené van Dorst #define MTK_ESW BIT(MTK_ESW_BIT) 721e2c74694SRené van Dorst #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 722e2c74694SRené van Dorst #define MTK_MUX BIT(MTK_MUX_BIT) 723e2c74694SRené van Dorst #define MTK_INFRA BIT(MTK_INFRA_BIT) 724e2c74694SRené van Dorst #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 725e2c74694SRené van Dorst #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 726e2c74694SRené van Dorst #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 727e2c74694SRené van Dorst #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 728296c9120SStefan Roese #define MTK_QDMA BIT(MTK_QDMA_BIT) 729296c9120SStefan Roese #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 730e2c74694SRené van Dorst 731e2c74694SRené van Dorst #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 732e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 733e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 734e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 735e2c74694SRené van Dorst #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 736e2c74694SRené van Dorst BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 737e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 738e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 739e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 740e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 7417093f9d8SSean Wang 7427093f9d8SSean Wang /* Supported path present on SoCs */ 743e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 744e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 745e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 746e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 747e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 748e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 749e2c74694SRené van Dorst #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 7507093f9d8SSean Wang 751e2c74694SRené van Dorst #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 752e2c74694SRené van Dorst #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 753e2c74694SRené van Dorst #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 754e2c74694SRené van Dorst #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 755e2c74694SRené van Dorst #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 756e2c74694SRené van Dorst #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 757e2c74694SRené van Dorst #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 7587093f9d8SSean Wang 7597093f9d8SSean Wang /* MUXes present on SoCs */ 7607093f9d8SSean Wang /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 761e2c74694SRené van Dorst #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 7627093f9d8SSean Wang 7637093f9d8SSean Wang /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 7647093f9d8SSean Wang #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 765e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 7667093f9d8SSean Wang 7677093f9d8SSean Wang /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 7687093f9d8SSean Wang #define MTK_MUX_U3_GMAC2_TO_QPHY \ 769e2c74694SRené van Dorst (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 7707093f9d8SSean Wang 7717093f9d8SSean Wang /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 7727093f9d8SSean Wang #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 773e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 7747093f9d8SSean Wang MTK_SHARED_SGMII) 7757093f9d8SSean Wang 7767093f9d8SSean Wang /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 7777093f9d8SSean Wang #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 778e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 7797093f9d8SSean Wang 7802ec50f57SSean Wang #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 7812ec50f57SSean Wang 7828efaa653SRené van Dorst #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 783296c9120SStefan Roese MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 784296c9120SStefan Roese MTK_TRGMII_MT7621_CLK | MTK_QDMA) 7858efaa653SRené van Dorst 7867093f9d8SSean Wang #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 7877093f9d8SSean Wang MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 7887093f9d8SSean Wang MTK_MUX_GDM1_TO_GMAC1_ESW | \ 789296c9120SStefan Roese MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 7907093f9d8SSean Wang 791296c9120SStefan Roese #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 792296c9120SStefan Roese MTK_QDMA) 793296c9120SStefan Roese 794296c9120SStefan Roese #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 7957093f9d8SSean Wang 7967093f9d8SSean Wang #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 7977093f9d8SSean Wang MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 7987093f9d8SSean Wang MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 7997093f9d8SSean Wang MTK_MUX_U3_GMAC2_TO_QPHY | \ 800296c9120SStefan Roese MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 8017093f9d8SSean Wang 80242c03844SSean Wang /* struct mtk_eth_data - This is the structure holding all differences 8032ec50f57SSean Wang * among various plaforms 8049ffee4a8SSean Wang * @ana_rgc3: The offset for register ANA_RGC3 related to 8059ffee4a8SSean Wang * sgmiisys syscon 8062ec50f57SSean Wang * @caps Flags shown the extra capability for the SoC 807296c9120SStefan Roese * @hw_features Flags shown HW features 8082ec50f57SSean Wang * @required_clks Flags shown the bitmap for required clocks on 8092ec50f57SSean Wang * the target SoC 810243dc5fbSSean Wang * @required_pctl A bool value to show whether the SoC requires 811243dc5fbSSean Wang * the extra setup for those pins used by GMAC. 8122ec50f57SSean Wang */ 8132ec50f57SSean Wang struct mtk_soc_data { 8149ffee4a8SSean Wang u32 ana_rgc3; 8152ec50f57SSean Wang u32 caps; 8162ec50f57SSean Wang u32 required_clks; 817243dc5fbSSean Wang bool required_pctl; 818ba37b7caSFelix Fietkau u8 offload_version; 819296c9120SStefan Roese netdev_features_t hw_features; 8202ec50f57SSean Wang }; 8212ec50f57SSean Wang 822656e7052SJohn Crispin /* currently no SoC has more than 2 macs */ 823656e7052SJohn Crispin #define MTK_MAX_DEVS 2 824656e7052SJohn Crispin 8259ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_AN BIT(31) 826937a9440SJoe Perches #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) 8279ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_1000 BIT(0) 8289ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_2500 BIT(1) 8299ffee4a8SSean Wang #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) 8309ffee4a8SSean Wang 8319ffee4a8SSean Wang /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 8329ffee4a8SSean Wang * characteristics 8339ffee4a8SSean Wang * @regmap: The register map pointing at the range used to setup 8349ffee4a8SSean Wang * SGMII modes 8359ffee4a8SSean Wang * @flags: The enum refers to which mode the sgmii wants to run on 8369ffee4a8SSean Wang * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 8379ffee4a8SSean Wang */ 8389ffee4a8SSean Wang 8399ffee4a8SSean Wang struct mtk_sgmii { 8409ffee4a8SSean Wang struct regmap *regmap[MTK_MAX_DEVS]; 8419ffee4a8SSean Wang u32 flags[MTK_MAX_DEVS]; 8429ffee4a8SSean Wang u32 ana_rgc3; 8439ffee4a8SSean Wang }; 8449ffee4a8SSean Wang 845656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 846656e7052SJohn Crispin * of the driver 847656e7052SJohn Crispin * @dev: The device pointer 848656e7052SJohn Crispin * @base: The mapped register i/o base 849656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 8505cce0322SJohn Crispin * @tx_irq__lock: Make sure that IRQ register operations are atomic 8515cce0322SJohn Crispin * @rx_irq__lock: Make sure that IRQ register operations are atomic 852656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 853656e7052SJohn Crispin * dummy for NAPI to work 854656e7052SJohn Crispin * @netdev: The netdev instances 855656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 856656e7052SJohn Crispin * @irq: The IRQ that we are using 857656e7052SJohn Crispin * @msg_enable: Ethtool msg level 858656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 859656e7052SJohn Crispin * MII modes 8607093f9d8SSean Wang * @infra: The register map pointing at the range used to setup 8617093f9d8SSean Wang * SGMII and GePHY path 862656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 863656e7052SJohn Crispin * GMAC port drive/slew values 864656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 8650c07ce7fSJohn Crispin * @tx_ring: Pointer to the memory holding info about the TX ring 8660c07ce7fSJohn Crispin * @rx_ring: Pointer to the memory holding info about the RX ring 8676427dc1dSJohn Crispin * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 86880673029SJohn Crispin * @tx_napi: The TX NAPI struct 86980673029SJohn Crispin * @rx_napi: The RX NAPI struct 870656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 871605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 872656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 873549e5495SSean Wang * @clks: clock array for all clocks required 874656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 8757c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 87642c03844SSean Wang * @state: Initialization and runtime state of the device 8772ec50f57SSean Wang * @soc: Holding specific data among vaious SoCs 878656e7052SJohn Crispin */ 879656e7052SJohn Crispin 880656e7052SJohn Crispin struct mtk_eth { 881656e7052SJohn Crispin struct device *dev; 882656e7052SJohn Crispin void __iomem *base; 883656e7052SJohn Crispin spinlock_t page_lock; 8845cce0322SJohn Crispin spinlock_t tx_irq_lock; 8855cce0322SJohn Crispin spinlock_t rx_irq_lock; 886656e7052SJohn Crispin struct net_device dummy_dev; 887656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 888656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 88980673029SJohn Crispin int irq[3]; 890656e7052SJohn Crispin u32 msg_enable; 891656e7052SJohn Crispin unsigned long sysclk; 892656e7052SJohn Crispin struct regmap *ethsys; 8937093f9d8SSean Wang struct regmap *infra; 8949ffee4a8SSean Wang struct mtk_sgmii *sgmii; 895656e7052SJohn Crispin struct regmap *pctl; 896ee406810SNelson Chang bool hwlro; 897c6d4e63eSElena Reshetova refcount_t dma_refcnt; 898656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 899ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 9006427dc1dSJohn Crispin struct mtk_rx_ring rx_ring_qdma; 90180673029SJohn Crispin struct napi_struct tx_napi; 902656e7052SJohn Crispin struct napi_struct rx_napi; 903656e7052SJohn Crispin struct mtk_tx_dma *scratch_ring; 904605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 905656e7052SJohn Crispin void *scratch_head; 906549e5495SSean Wang struct clk *clks[MTK_CLK_MAX]; 907549e5495SSean Wang 908656e7052SJohn Crispin struct mii_bus *mii_bus; 9097c78b4adSJohn Crispin struct work_struct pending_work; 9109ea4d311SSean Wang unsigned long state; 9112ec50f57SSean Wang 9122ec50f57SSean Wang const struct mtk_soc_data *soc; 913296c9120SStefan Roese 914296c9120SStefan Roese u32 tx_int_mask_reg; 915296c9120SStefan Roese u32 tx_int_status_reg; 916296c9120SStefan Roese u32 rx_dma_l4_valid; 917296c9120SStefan Roese int ip_align; 918ba37b7caSFelix Fietkau 919ba37b7caSFelix Fietkau struct mtk_ppe ppe; 920502e84e2SFelix Fietkau struct rhashtable flow_table; 921656e7052SJohn Crispin }; 922656e7052SJohn Crispin 923656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 924656e7052SJohn Crispin * SoC 925656e7052SJohn Crispin * @id: The number of the MAC 926b8fc9f30SRené van Dorst * @interface: Interface mode kept for detecting change in hw settings 927656e7052SJohn Crispin * @of_node: Our devicetree node 928656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 929656e7052SJohn Crispin * @hw_stats: Packet statistics counter 930656e7052SJohn Crispin */ 931656e7052SJohn Crispin struct mtk_mac { 932656e7052SJohn Crispin int id; 933b8fc9f30SRené van Dorst phy_interface_t interface; 934b8fc9f30SRené van Dorst unsigned int mode; 935b8fc9f30SRené van Dorst int speed; 936656e7052SJohn Crispin struct device_node *of_node; 937b8fc9f30SRené van Dorst struct phylink *phylink; 938b8fc9f30SRené van Dorst struct phylink_config phylink_config; 939656e7052SJohn Crispin struct mtk_eth *hw; 940656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 941ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 942ee406810SNelson Chang int hwlro_ip_cnt; 943656e7052SJohn Crispin }; 944656e7052SJohn Crispin 945656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 946656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 947656e7052SJohn Crispin 948656e7052SJohn Crispin /* read the hardware status register */ 949656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 950656e7052SJohn Crispin 951656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 952656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 953656e7052SJohn Crispin 9549ffee4a8SSean Wang int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 9559ffee4a8SSean Wang u32 ana_rgc3); 9569ffee4a8SSean Wang int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); 9577e538372SRené van Dorst int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, 9587e538372SRené van Dorst const struct phylink_link_state *state); 9597e538372SRené van Dorst void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); 9607e538372SRené van Dorst 9617e538372SRené van Dorst int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 9627e538372SRené van Dorst int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 9637e538372SRené van Dorst int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 9649ffee4a8SSean Wang 965502e84e2SFelix Fietkau int mtk_eth_offload_init(struct mtk_eth *eth); 966502e84e2SFelix Fietkau int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 967502e84e2SFelix Fietkau void *type_data); 968502e84e2SFelix Fietkau 969502e84e2SFelix Fietkau 970656e7052SJohn Crispin #endif /* MTK_ETH_H */ 971