1656e7052SJohn Crispin /* This program is free software; you can redistribute it and/or modify 2656e7052SJohn Crispin * it under the terms of the GNU General Public License as published by 3656e7052SJohn Crispin * the Free Software Foundation; version 2 of the License 4656e7052SJohn Crispin * 5656e7052SJohn Crispin * This program is distributed in the hope that it will be useful, 6656e7052SJohn Crispin * but WITHOUT ANY WARRANTY; without even the implied warranty of 7656e7052SJohn Crispin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8656e7052SJohn Crispin * GNU General Public License for more details. 9656e7052SJohn Crispin * 10656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13656e7052SJohn Crispin */ 14656e7052SJohn Crispin 15656e7052SJohn Crispin #ifndef MTK_ETH_H 16656e7052SJohn Crispin #define MTK_ETH_H 17656e7052SJohn Crispin 18656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 19656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 20656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 21656e7052SJohn Crispin #define MTK_DMA_SIZE 256 22656e7052SJohn Crispin #define MTK_NAPI_WEIGHT 64 23656e7052SJohn Crispin #define MTK_MAC_COUNT 2 24656e7052SJohn Crispin #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 25656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 26656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 27656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 28656e7052SJohn Crispin NETIF_MSG_PROBE | \ 29656e7052SJohn Crispin NETIF_MSG_LINK | \ 30656e7052SJohn Crispin NETIF_MSG_TIMER | \ 31656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 32656e7052SJohn Crispin NETIF_MSG_IFUP | \ 33656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 34656e7052SJohn Crispin NETIF_MSG_TX_ERR) 35656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 36656e7052SJohn Crispin NETIF_F_RXCSUM | \ 37656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 38656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_RX | \ 39656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 40656e7052SJohn Crispin NETIF_F_TSO6 | \ 41656e7052SJohn Crispin NETIF_F_IPV6_CSUM) 42656e7052SJohn Crispin #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (MTK_DMA_SIZE - 1)) 43656e7052SJohn Crispin 44656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 45656e7052SJohn Crispin #define MTK_RST_GL 0x04 46656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 47656e7052SJohn Crispin 48656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 49656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 50656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 51656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 52656e7052SJohn Crispin 53656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 54656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 55656e7052SJohn Crispin 56656e7052SJohn Crispin /* CDMP Exgress Control Register */ 57656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 58656e7052SJohn Crispin 59656e7052SJohn Crispin /* GDM Exgress Control Register */ 60656e7052SJohn Crispin #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 61656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 62656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 63656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 64656e7052SJohn Crispin 65656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 66656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 67656e7052SJohn Crispin 68656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 69656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 70656e7052SJohn Crispin 71656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 72656e7052SJohn Crispin #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 73656e7052SJohn Crispin #define QDMA_RES_THRES 4 74656e7052SJohn Crispin 75656e7052SJohn Crispin /* QDMA TX Queue Scheduler Registers */ 76656e7052SJohn Crispin #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 77656e7052SJohn Crispin 78656e7052SJohn Crispin /* QDMA RX Base Pointer Register */ 79656e7052SJohn Crispin #define MTK_QRX_BASE_PTR0 0x1900 80656e7052SJohn Crispin 81656e7052SJohn Crispin /* QDMA RX Maximum Count Register */ 82656e7052SJohn Crispin #define MTK_QRX_MAX_CNT0 0x1904 83656e7052SJohn Crispin 84656e7052SJohn Crispin /* QDMA RX CPU Pointer Register */ 85656e7052SJohn Crispin #define MTK_QRX_CRX_IDX0 0x1908 86656e7052SJohn Crispin 87656e7052SJohn Crispin /* QDMA RX DMA Pointer Register */ 88656e7052SJohn Crispin #define MTK_QRX_DRX_IDX0 0x190C 89656e7052SJohn Crispin 90656e7052SJohn Crispin /* QDMA Global Configuration Register */ 91656e7052SJohn Crispin #define MTK_QDMA_GLO_CFG 0x1A04 92656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 93656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 946675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 95656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 96656e7052SJohn Crispin #define MTK_DMA_SIZE_16DWORDS (2 << 4) 97656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 98656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 99656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 100656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 101656e7052SJohn Crispin #define MTK_DMA_BUSY_TIMEOUT HZ 102656e7052SJohn Crispin 103656e7052SJohn Crispin /* QDMA Reset Index Register */ 104656e7052SJohn Crispin #define MTK_QDMA_RST_IDX 0x1A08 105656e7052SJohn Crispin #define MTK_PST_DRX_IDX0 BIT(16) 106656e7052SJohn Crispin 107656e7052SJohn Crispin /* QDMA Delay Interrupt Register */ 108656e7052SJohn Crispin #define MTK_QDMA_DELAY_INT 0x1A0C 109656e7052SJohn Crispin 110656e7052SJohn Crispin /* QDMA Flow Control Register */ 111656e7052SJohn Crispin #define MTK_QDMA_FC_THRES 0x1A10 112656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 113656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 114656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 115656e7052SJohn Crispin 116656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 117656e7052SJohn Crispin #define MTK_QMTK_INT_STATUS 0x1A18 118656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 119656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 120656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 121656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 122656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 123656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 124656e7052SJohn Crispin #define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1) 125656e7052SJohn Crispin #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ 126656e7052SJohn Crispin MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) 127656e7052SJohn Crispin 128656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 129656e7052SJohn Crispin #define MTK_QDMA_INT_MASK 0x1A1C 130656e7052SJohn Crispin 131656e7052SJohn Crispin /* QDMA Interrupt Mask Register */ 132656e7052SJohn Crispin #define MTK_QDMA_HRED2 0x1A44 133656e7052SJohn Crispin 134656e7052SJohn Crispin /* QDMA TX Forward CPU Pointer Register */ 135656e7052SJohn Crispin #define MTK_QTX_CTX_PTR 0x1B00 136656e7052SJohn Crispin 137656e7052SJohn Crispin /* QDMA TX Forward DMA Pointer Register */ 138656e7052SJohn Crispin #define MTK_QTX_DTX_PTR 0x1B04 139656e7052SJohn Crispin 140656e7052SJohn Crispin /* QDMA TX Release CPU Pointer Register */ 141656e7052SJohn Crispin #define MTK_QTX_CRX_PTR 0x1B10 142656e7052SJohn Crispin 143656e7052SJohn Crispin /* QDMA TX Release DMA Pointer Register */ 144656e7052SJohn Crispin #define MTK_QTX_DRX_PTR 0x1B14 145656e7052SJohn Crispin 146656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 147656e7052SJohn Crispin #define MTK_QDMA_FQ_HEAD 0x1B20 148656e7052SJohn Crispin 149656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 150656e7052SJohn Crispin #define MTK_QDMA_FQ_TAIL 0x1B24 151656e7052SJohn Crispin 152656e7052SJohn Crispin /* QDMA FQ Free Page Counter Register */ 153656e7052SJohn Crispin #define MTK_QDMA_FQ_CNT 0x1B28 154656e7052SJohn Crispin 155656e7052SJohn Crispin /* QDMA FQ Free Page Buffer Length Register */ 156656e7052SJohn Crispin #define MTK_QDMA_FQ_BLEN 0x1B2C 157656e7052SJohn Crispin 158656e7052SJohn Crispin /* GMA1 Received Good Byte Count Register */ 159656e7052SJohn Crispin #define MTK_GDM1_TX_GBCNT 0x2400 160656e7052SJohn Crispin #define MTK_STAT_OFFSET 0x40 161656e7052SJohn Crispin 162656e7052SJohn Crispin /* QDMA descriptor txd4 */ 163656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 164656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 165656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 166656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 167656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 168656e7052SJohn Crispin 169656e7052SJohn Crispin /* QDMA descriptor txd3 */ 170656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 171656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 172656e7052SJohn Crispin #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 173656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 174656e7052SJohn Crispin #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 175656e7052SJohn Crispin 176656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 177656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 178656e7052SJohn Crispin #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 179656e7052SJohn Crispin #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 180656e7052SJohn Crispin 181656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 182656e7052SJohn Crispin #define RX_DMA_VID(_x) ((_x) & 0xfff) 183656e7052SJohn Crispin 184656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 185656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 186656e7052SJohn Crispin #define RX_DMA_FPORT_SHIFT 19 187656e7052SJohn Crispin #define RX_DMA_FPORT_MASK 0x7 188656e7052SJohn Crispin 189656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 190656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 191656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 192656e7052SJohn Crispin #define PHY_IAC_READ BIT(19) 193656e7052SJohn Crispin #define PHY_IAC_WRITE BIT(18) 194656e7052SJohn Crispin #define PHY_IAC_START BIT(16) 195656e7052SJohn Crispin #define PHY_IAC_ADDR_SHIFT 20 196656e7052SJohn Crispin #define PHY_IAC_REG_SHIFT 25 197656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 198656e7052SJohn Crispin 199656e7052SJohn Crispin /* Mac control registers */ 200656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 201656e7052SJohn Crispin #define MAC_MCR_MAX_RX_1536 BIT(24) 202656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 203656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 204656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 205656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 206656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 207656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 208656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 209656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 210656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 211656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 212656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 213656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 214656e7052SJohn Crispin #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ 215656e7052SJohn Crispin MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ 216656e7052SJohn Crispin MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ 217656e7052SJohn Crispin MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ 218656e7052SJohn Crispin MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ 219656e7052SJohn Crispin MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) 220656e7052SJohn Crispin 221656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 222656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 223656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 224656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 225656e7052SJohn Crispin 226656e7052SJohn Crispin /* ethernet subsystem config register */ 227656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 228656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 229656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 230656e7052SJohn Crispin 231656e7052SJohn Crispin struct mtk_rx_dma { 232656e7052SJohn Crispin unsigned int rxd1; 233656e7052SJohn Crispin unsigned int rxd2; 234656e7052SJohn Crispin unsigned int rxd3; 235656e7052SJohn Crispin unsigned int rxd4; 236656e7052SJohn Crispin } __packed __aligned(4); 237656e7052SJohn Crispin 238656e7052SJohn Crispin struct mtk_tx_dma { 239656e7052SJohn Crispin unsigned int txd1; 240656e7052SJohn Crispin unsigned int txd2; 241656e7052SJohn Crispin unsigned int txd3; 242656e7052SJohn Crispin unsigned int txd4; 243656e7052SJohn Crispin } __packed __aligned(4); 244656e7052SJohn Crispin 245656e7052SJohn Crispin struct mtk_eth; 246656e7052SJohn Crispin struct mtk_mac; 247656e7052SJohn Crispin 248656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 249656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 250656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 251656e7052SJohn Crispin * @syncp: the refcount 252656e7052SJohn Crispin * 253656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 254656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 255656e7052SJohn Crispin * counters and store them in this struct. 256656e7052SJohn Crispin */ 257656e7052SJohn Crispin struct mtk_hw_stats { 258656e7052SJohn Crispin u64 tx_bytes; 259656e7052SJohn Crispin u64 tx_packets; 260656e7052SJohn Crispin u64 tx_skip; 261656e7052SJohn Crispin u64 tx_collisions; 262656e7052SJohn Crispin u64 rx_bytes; 263656e7052SJohn Crispin u64 rx_packets; 264656e7052SJohn Crispin u64 rx_overflow; 265656e7052SJohn Crispin u64 rx_fcs_errors; 266656e7052SJohn Crispin u64 rx_short_errors; 267656e7052SJohn Crispin u64 rx_long_errors; 268656e7052SJohn Crispin u64 rx_checksum_errors; 269656e7052SJohn Crispin u64 rx_flow_control_packets; 270656e7052SJohn Crispin 271656e7052SJohn Crispin spinlock_t stats_lock; 272656e7052SJohn Crispin u32 reg_offset; 273656e7052SJohn Crispin struct u64_stats_sync syncp; 274656e7052SJohn Crispin }; 275656e7052SJohn Crispin 276656e7052SJohn Crispin /* PDMA descriptor can point at 1-2 segments. This enum allows us to track how 277656e7052SJohn Crispin * memory was allocated so that it can be freed properly 278656e7052SJohn Crispin */ 279656e7052SJohn Crispin enum mtk_tx_flags { 280656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 281656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 282656e7052SJohn Crispin }; 283656e7052SJohn Crispin 284656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 285656e7052SJohn Crispin * by the TX descriptor s 286656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 287656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 288656e7052SJohn Crispin * @dma_len0: The length of the first segment 289656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 290656e7052SJohn Crispin * @dma_len1: The length of the second segment 291656e7052SJohn Crispin */ 292656e7052SJohn Crispin struct mtk_tx_buf { 293656e7052SJohn Crispin struct sk_buff *skb; 294656e7052SJohn Crispin u32 flags; 295656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 296656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 297656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 298656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 299656e7052SJohn Crispin }; 300656e7052SJohn Crispin 301656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 302656e7052SJohn Crispin * @dma: The descriptor ring 303656e7052SJohn Crispin * @buf: The memory pointed at by the ring 304656e7052SJohn Crispin * @phys: The physical addr of tx_buf 305656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 306656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 307656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 308656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 309656e7052SJohn Crispin * are present 310656e7052SJohn Crispin */ 311656e7052SJohn Crispin struct mtk_tx_ring { 312656e7052SJohn Crispin struct mtk_tx_dma *dma; 313656e7052SJohn Crispin struct mtk_tx_buf *buf; 314656e7052SJohn Crispin dma_addr_t phys; 315656e7052SJohn Crispin struct mtk_tx_dma *next_free; 316656e7052SJohn Crispin struct mtk_tx_dma *last_free; 317656e7052SJohn Crispin u16 thresh; 318656e7052SJohn Crispin atomic_t free_count; 319656e7052SJohn Crispin }; 320656e7052SJohn Crispin 321656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 322656e7052SJohn Crispin * @dma: The descriptor ring 323656e7052SJohn Crispin * @data: The memory pointed at by the ring 324656e7052SJohn Crispin * @phys: The physical addr of rx_buf 325656e7052SJohn Crispin * @frag_size: How big can each fragment be 326656e7052SJohn Crispin * @buf_size: The size of each packet buffer 327656e7052SJohn Crispin * @calc_idx: The current head of ring 328656e7052SJohn Crispin */ 329656e7052SJohn Crispin struct mtk_rx_ring { 330656e7052SJohn Crispin struct mtk_rx_dma *dma; 331656e7052SJohn Crispin u8 **data; 332656e7052SJohn Crispin dma_addr_t phys; 333656e7052SJohn Crispin u16 frag_size; 334656e7052SJohn Crispin u16 buf_size; 335656e7052SJohn Crispin u16 calc_idx; 336656e7052SJohn Crispin }; 337656e7052SJohn Crispin 338656e7052SJohn Crispin /* currently no SoC has more than 2 macs */ 339656e7052SJohn Crispin #define MTK_MAX_DEVS 2 340656e7052SJohn Crispin 341656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 342656e7052SJohn Crispin * of the driver 343656e7052SJohn Crispin * @dev: The device pointer 344656e7052SJohn Crispin * @base: The mapped register i/o base 345656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 346656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 347656e7052SJohn Crispin * dummy for NAPI to work 348656e7052SJohn Crispin * @netdev: The netdev instances 349656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 350656e7052SJohn Crispin * @irq: The IRQ that we are using 351656e7052SJohn Crispin * @msg_enable: Ethtool msg level 352656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 353656e7052SJohn Crispin * MII modes 354656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 355656e7052SJohn Crispin * GMAC port drive/slew values 356656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 357656e7052SJohn Crispin * @tx_ring: Pointer to the memore holding info about the TX ring 358656e7052SJohn Crispin * @rx_ring: Pointer to the memore holding info about the RX ring 359656e7052SJohn Crispin * @rx_napi: The NAPI struct 360656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 361605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 362656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 363656e7052SJohn Crispin * @clk_ethif: The ethif clock 364656e7052SJohn Crispin * @clk_esw: The switch clock 365656e7052SJohn Crispin * @clk_gp1: The gmac1 clock 366656e7052SJohn Crispin * @clk_gp2: The gmac2 clock 367656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 3687c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 369656e7052SJohn Crispin */ 370656e7052SJohn Crispin 371656e7052SJohn Crispin struct mtk_eth { 372656e7052SJohn Crispin struct device *dev; 373656e7052SJohn Crispin void __iomem *base; 374656e7052SJohn Crispin struct reset_control *rstc; 375656e7052SJohn Crispin spinlock_t page_lock; 376656e7052SJohn Crispin struct net_device dummy_dev; 377656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 378656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 379656e7052SJohn Crispin int irq; 380656e7052SJohn Crispin u32 msg_enable; 381656e7052SJohn Crispin unsigned long sysclk; 382656e7052SJohn Crispin struct regmap *ethsys; 383656e7052SJohn Crispin struct regmap *pctl; 384656e7052SJohn Crispin atomic_t dma_refcnt; 385656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 386656e7052SJohn Crispin struct mtk_rx_ring rx_ring; 387656e7052SJohn Crispin struct napi_struct rx_napi; 388656e7052SJohn Crispin struct mtk_tx_dma *scratch_ring; 389605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 390656e7052SJohn Crispin void *scratch_head; 391656e7052SJohn Crispin struct clk *clk_ethif; 392656e7052SJohn Crispin struct clk *clk_esw; 393656e7052SJohn Crispin struct clk *clk_gp1; 394656e7052SJohn Crispin struct clk *clk_gp2; 395656e7052SJohn Crispin struct mii_bus *mii_bus; 3967c78b4adSJohn Crispin struct work_struct pending_work; 397656e7052SJohn Crispin }; 398656e7052SJohn Crispin 399656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 400656e7052SJohn Crispin * SoC 401656e7052SJohn Crispin * @id: The number of the MAC 402656e7052SJohn Crispin * @of_node: Our devicetree node 403656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 404656e7052SJohn Crispin * @hw_stats: Packet statistics counter 405656e7052SJohn Crispin * @phy_dev: The attached PHY if available 406656e7052SJohn Crispin */ 407656e7052SJohn Crispin struct mtk_mac { 408656e7052SJohn Crispin int id; 409656e7052SJohn Crispin struct device_node *of_node; 410656e7052SJohn Crispin struct mtk_eth *hw; 411656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 412656e7052SJohn Crispin struct phy_device *phy_dev; 413656e7052SJohn Crispin }; 414656e7052SJohn Crispin 415656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 416656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 417656e7052SJohn Crispin 418656e7052SJohn Crispin /* read the hardware status register */ 419656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 420656e7052SJohn Crispin 421656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 422656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 423656e7052SJohn Crispin 424656e7052SJohn Crispin #endif /* MTK_ETH_H */ 425