18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28e8e69d6SThomas Gleixner /* 3656e7052SJohn Crispin * 4656e7052SJohn Crispin * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5656e7052SJohn Crispin * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6656e7052SJohn Crispin * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7656e7052SJohn Crispin */ 8656e7052SJohn Crispin 9656e7052SJohn Crispin #ifndef MTK_ETH_H 10656e7052SJohn Crispin #define MTK_ETH_H 11656e7052SJohn Crispin 129ffee4a8SSean Wang #include <linux/dma-mapping.h> 139ffee4a8SSean Wang #include <linux/netdevice.h> 149ffee4a8SSean Wang #include <linux/of_net.h> 159ffee4a8SSean Wang #include <linux/u64_stats_sync.h> 16c6d4e63eSElena Reshetova #include <linux/refcount.h> 17b8fc9f30SRené van Dorst #include <linux/phylink.h> 18502e84e2SFelix Fietkau #include <linux/rhashtable.h> 19e9229ffdSFelix Fietkau #include <linux/dim.h> 20ba37b7caSFelix Fietkau #include "mtk_ppe.h" 21c6d4e63eSElena Reshetova 22656e7052SJohn Crispin #define MTK_QDMA_PAGE_SIZE 2048 23656e7052SJohn Crispin #define MTK_MAX_RX_LENGTH 1536 244fd59792SDENG Qingfang #define MTK_MAX_RX_LENGTH_2K 2048 25656e7052SJohn Crispin #define MTK_TX_DMA_BUF_LEN 0x3fff 266b4423b2SFelix Fietkau #define MTK_DMA_SIZE 512 27656e7052SJohn Crispin #define MTK_NAPI_WEIGHT 64 28656e7052SJohn Crispin #define MTK_MAC_COUNT 2 294fd59792SDENG Qingfang #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 30656e7052SJohn Crispin #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 31656e7052SJohn Crispin #define MTK_DMA_DUMMY_DESC 0xffffffff 32656e7052SJohn Crispin #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ 33656e7052SJohn Crispin NETIF_MSG_PROBE | \ 34656e7052SJohn Crispin NETIF_MSG_LINK | \ 35656e7052SJohn Crispin NETIF_MSG_TIMER | \ 36656e7052SJohn Crispin NETIF_MSG_IFDOWN | \ 37656e7052SJohn Crispin NETIF_MSG_IFUP | \ 38656e7052SJohn Crispin NETIF_MSG_RX_ERR | \ 39656e7052SJohn Crispin NETIF_MSG_TX_ERR) 40656e7052SJohn Crispin #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ 41656e7052SJohn Crispin NETIF_F_RXCSUM | \ 42656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_TX | \ 43656e7052SJohn Crispin NETIF_F_HW_VLAN_CTAG_RX | \ 44656e7052SJohn Crispin NETIF_F_SG | NETIF_F_TSO | \ 45656e7052SJohn Crispin NETIF_F_TSO6 | \ 46502e84e2SFelix Fietkau NETIF_F_IPV6_CSUM |\ 47502e84e2SFelix Fietkau NETIF_F_HW_TC) 48296c9120SStefan Roese #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) 4908df5fa6SStefan Roese #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) 50ee406810SNelson Chang 51ee406810SNelson Chang #define MTK_MAX_RX_RING_NUM 4 52ee406810SNelson Chang #define MTK_HW_LRO_DMA_SIZE 8 53ee406810SNelson Chang 54ee406810SNelson Chang #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) 55ee406810SNelson Chang #define MTK_MAX_LRO_IP_CNT 2 56ee406810SNelson Chang #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ 57ee406810SNelson Chang #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ 58ee406810SNelson Chang #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ 59ee406810SNelson Chang #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ 60ee406810SNelson Chang #define MTK_HW_LRO_MAX_AGG_CNT 64 61ee406810SNelson Chang #define MTK_HW_LRO_BW_THRE 3000 62ee406810SNelson Chang #define MTK_HW_LRO_REPLACE_DELTA 1000 63ee406810SNelson Chang #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 64656e7052SJohn Crispin 65656e7052SJohn Crispin /* Frame Engine Global Reset Register */ 66656e7052SJohn Crispin #define MTK_RST_GL 0x04 67656e7052SJohn Crispin #define RST_GL_PSE BIT(0) 68656e7052SJohn Crispin 69656e7052SJohn Crispin /* Frame Engine Interrupt Status Register */ 70656e7052SJohn Crispin #define MTK_INT_STATUS2 0x08 71656e7052SJohn Crispin #define MTK_GDM1_AF BIT(28) 72656e7052SJohn Crispin #define MTK_GDM2_AF BIT(29) 73656e7052SJohn Crispin 74ee406810SNelson Chang /* PDMA HW LRO Alter Flow Timer Register */ 75ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c 76ee406810SNelson Chang 77656e7052SJohn Crispin /* Frame Engine Interrupt Grouping Register */ 78656e7052SJohn Crispin #define MTK_FE_INT_GRP 0x20 79656e7052SJohn Crispin 8087e3df49SSean Wang /* CDMP Ingress Control Register */ 8187e3df49SSean Wang #define MTK_CDMQ_IG_CTRL 0x1400 8287e3df49SSean Wang #define MTK_CDMQ_STAG_EN BIT(0) 8387e3df49SSean Wang 84656e7052SJohn Crispin /* CDMP Exgress Control Register */ 85656e7052SJohn Crispin #define MTK_CDMP_EG_CTRL 0x404 86656e7052SJohn Crispin 87656e7052SJohn Crispin /* GDM Exgress Control Register */ 88656e7052SJohn Crispin #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 89d5c53da2SFelix Fietkau #define MTK_GDMA_SPECIAL_TAG BIT(24) 90656e7052SJohn Crispin #define MTK_GDMA_ICS_EN BIT(22) 91656e7052SJohn Crispin #define MTK_GDMA_TCS_EN BIT(21) 92656e7052SJohn Crispin #define MTK_GDMA_UCS_EN BIT(20) 938d3f4a95SMarkLee #define MTK_GDMA_TO_PDMA 0x0 94ba37b7caSFelix Fietkau #define MTK_GDMA_TO_PPE 0x4444 958d66a818SMarkLee #define MTK_GDMA_DROP_ALL 0x7777 96656e7052SJohn Crispin 97656e7052SJohn Crispin /* Unicast Filter MAC Address Register - Low */ 98656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) 99656e7052SJohn Crispin 100656e7052SJohn Crispin /* Unicast Filter MAC Address Register - High */ 101656e7052SJohn Crispin #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) 102656e7052SJohn Crispin 103bacfd110SNelson Chang /* PDMA RX Base Pointer Register */ 104bacfd110SNelson Chang #define MTK_PRX_BASE_PTR0 0x900 105ee406810SNelson Chang #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) 106bacfd110SNelson Chang 107bacfd110SNelson Chang /* PDMA RX Maximum Count Register */ 108bacfd110SNelson Chang #define MTK_PRX_MAX_CNT0 0x904 109ee406810SNelson Chang #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) 110bacfd110SNelson Chang 111bacfd110SNelson Chang /* PDMA RX CPU Pointer Register */ 112bacfd110SNelson Chang #define MTK_PRX_CRX_IDX0 0x908 113ee406810SNelson Chang #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) 114ee406810SNelson Chang 115ee406810SNelson Chang /* PDMA HW LRO Control Registers */ 116ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW0 0x980 117ee406810SNelson Chang #define MTK_LRO_EN BIT(0) 118ee406810SNelson Chang #define MTK_L3_CKS_UPD_EN BIT(7) 119ee406810SNelson Chang #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) 120ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) 121ca3ba106SNelson Chang #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) 122ee406810SNelson Chang 123ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW1 0x984 124ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW2 0x988 125ee406810SNelson Chang #define MTK_PDMA_LRO_CTRL_DW3 0x98c 126ee406810SNelson Chang #define MTK_ADMA_MODE BIT(15) 127ee406810SNelson Chang #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) 128bacfd110SNelson Chang 129bacfd110SNelson Chang /* PDMA Global Configuration Register */ 130bacfd110SNelson Chang #define MTK_PDMA_GLO_CFG 0xa04 131bacfd110SNelson Chang #define MTK_MULTI_EN BIT(10) 132296c9120SStefan Roese #define MTK_PDMA_SIZE_8DWORDS (1 << 4) 133bacfd110SNelson Chang 134bacfd110SNelson Chang /* PDMA Reset Index Register */ 135bacfd110SNelson Chang #define MTK_PDMA_RST_IDX 0xa08 136bacfd110SNelson Chang #define MTK_PST_DRX_IDX0 BIT(16) 137ee406810SNelson Chang #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) 138bacfd110SNelson Chang 139bacfd110SNelson Chang /* PDMA Delay Interrupt Register */ 140bacfd110SNelson Chang #define MTK_PDMA_DELAY_INT 0xa0c 141e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) 142671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_EN BIT(15) 143671d41e6SJohn Crispin #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 144e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 145e9229ffdSFelix Fietkau 146e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) 147e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_EN BIT(31) 148e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 149e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 150e9229ffdSFelix Fietkau 151e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PINT_MASK 0x7f 152e9229ffdSFelix Fietkau #define MTK_PDMA_DELAY_PTIME_MASK 0xff 153bacfd110SNelson Chang 154bacfd110SNelson Chang /* PDMA Interrupt Status Register */ 155bacfd110SNelson Chang #define MTK_PDMA_INT_STATUS 0xa20 156bacfd110SNelson Chang 157bacfd110SNelson Chang /* PDMA Interrupt Mask Register */ 158bacfd110SNelson Chang #define MTK_PDMA_INT_MASK 0xa28 159bacfd110SNelson Chang 160ee406810SNelson Chang /* PDMA HW LRO Alter Flow Delta Register */ 161ee406810SNelson Chang #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c 162ee406810SNelson Chang 16380673029SJohn Crispin /* PDMA Interrupt grouping registers */ 16480673029SJohn Crispin #define MTK_PDMA_INT_GRP1 0xa50 16580673029SJohn Crispin #define MTK_PDMA_INT_GRP2 0xa54 16680673029SJohn Crispin 167ee406810SNelson Chang /* PDMA HW LRO IP Setting Registers */ 168ee406810SNelson Chang #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 169ee406810SNelson Chang #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) 170ee406810SNelson Chang #define MTK_RING_MYIP_VLD BIT(9) 171ee406810SNelson Chang 172ee406810SNelson Chang /* PDMA HW LRO Ring Control Registers */ 173ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 174ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c 175ee406810SNelson Chang #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 176ee406810SNelson Chang #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) 177ee406810SNelson Chang #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) 178ee406810SNelson Chang #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) 179ee406810SNelson Chang #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) 180ee406810SNelson Chang #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) 181ee406810SNelson Chang #define MTK_RING_AUTO_LERAN_MODE (3 << 6) 182ee406810SNelson Chang #define MTK_RING_VLD BIT(8) 183ee406810SNelson Chang #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) 184ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) 185ee406810SNelson Chang #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) 186ee406810SNelson Chang 187656e7052SJohn Crispin /* QDMA TX Queue Configuration Registers */ 188656e7052SJohn Crispin #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) 189656e7052SJohn Crispin #define QDMA_RES_THRES 4 190656e7052SJohn Crispin 191656e7052SJohn Crispin /* QDMA TX Queue Scheduler Registers */ 192656e7052SJohn Crispin #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) 193656e7052SJohn Crispin 194656e7052SJohn Crispin /* QDMA RX Base Pointer Register */ 195656e7052SJohn Crispin #define MTK_QRX_BASE_PTR0 0x1900 196656e7052SJohn Crispin 197656e7052SJohn Crispin /* QDMA RX Maximum Count Register */ 198656e7052SJohn Crispin #define MTK_QRX_MAX_CNT0 0x1904 199656e7052SJohn Crispin 200656e7052SJohn Crispin /* QDMA RX CPU Pointer Register */ 201656e7052SJohn Crispin #define MTK_QRX_CRX_IDX0 0x1908 202656e7052SJohn Crispin 203656e7052SJohn Crispin /* QDMA RX DMA Pointer Register */ 204656e7052SJohn Crispin #define MTK_QRX_DRX_IDX0 0x190C 205656e7052SJohn Crispin 206656e7052SJohn Crispin /* QDMA Global Configuration Register */ 207656e7052SJohn Crispin #define MTK_QDMA_GLO_CFG 0x1A04 208656e7052SJohn Crispin #define MTK_RX_2B_OFFSET BIT(31) 209656e7052SJohn Crispin #define MTK_RX_BT_32DWORDS (3 << 11) 2106675086dSJohn Crispin #define MTK_NDP_CO_PRO BIT(10) 211656e7052SJohn Crispin #define MTK_TX_WB_DDONE BIT(6) 21259555a8dSFelix Fietkau #define MTK_TX_BT_32DWORDS (3 << 4) 213656e7052SJohn Crispin #define MTK_RX_DMA_BUSY BIT(3) 214656e7052SJohn Crispin #define MTK_TX_DMA_BUSY BIT(1) 215656e7052SJohn Crispin #define MTK_RX_DMA_EN BIT(2) 216656e7052SJohn Crispin #define MTK_TX_DMA_EN BIT(0) 217*3bc8e0afSIlya Lipnitskiy #define MTK_DMA_BUSY_TIMEOUT_US 1000000 218656e7052SJohn Crispin 219656e7052SJohn Crispin /* QDMA Reset Index Register */ 220656e7052SJohn Crispin #define MTK_QDMA_RST_IDX 0x1A08 221656e7052SJohn Crispin 222656e7052SJohn Crispin /* QDMA Delay Interrupt Register */ 223656e7052SJohn Crispin #define MTK_QDMA_DELAY_INT 0x1A0C 224656e7052SJohn Crispin 225656e7052SJohn Crispin /* QDMA Flow Control Register */ 226656e7052SJohn Crispin #define MTK_QDMA_FC_THRES 0x1A10 227656e7052SJohn Crispin #define FC_THRES_DROP_MODE BIT(20) 228656e7052SJohn Crispin #define FC_THRES_DROP_EN (7 << 16) 229656e7052SJohn Crispin #define FC_THRES_MIN 0x4444 230656e7052SJohn Crispin 231656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 23245487403SStefan Roese #define MTK_QDMA_INT_STATUS 0x1A18 233671d41e6SJohn Crispin #define MTK_RX_DONE_DLY BIT(30) 234e9229ffdSFelix Fietkau #define MTK_TX_DONE_DLY BIT(28) 235bacfd110SNelson Chang #define MTK_RX_DONE_INT3 BIT(19) 236bacfd110SNelson Chang #define MTK_RX_DONE_INT2 BIT(18) 237656e7052SJohn Crispin #define MTK_RX_DONE_INT1 BIT(17) 238656e7052SJohn Crispin #define MTK_RX_DONE_INT0 BIT(16) 239656e7052SJohn Crispin #define MTK_TX_DONE_INT3 BIT(3) 240656e7052SJohn Crispin #define MTK_TX_DONE_INT2 BIT(2) 241656e7052SJohn Crispin #define MTK_TX_DONE_INT1 BIT(1) 242656e7052SJohn Crispin #define MTK_TX_DONE_INT0 BIT(0) 243671d41e6SJohn Crispin #define MTK_RX_DONE_INT MTK_RX_DONE_DLY 244e9229ffdSFelix Fietkau #define MTK_TX_DONE_INT MTK_TX_DONE_DLY 245656e7052SJohn Crispin 24680673029SJohn Crispin /* QDMA Interrupt grouping registers */ 24780673029SJohn Crispin #define MTK_QDMA_INT_GRP1 0x1a20 24880673029SJohn Crispin #define MTK_QDMA_INT_GRP2 0x1a24 24980673029SJohn Crispin #define MTK_RLS_DONE_INT BIT(0) 25080673029SJohn Crispin 251656e7052SJohn Crispin /* QDMA Interrupt Status Register */ 252656e7052SJohn Crispin #define MTK_QDMA_INT_MASK 0x1A1C 253656e7052SJohn Crispin 254656e7052SJohn Crispin /* QDMA Interrupt Mask Register */ 255656e7052SJohn Crispin #define MTK_QDMA_HRED2 0x1A44 256656e7052SJohn Crispin 257656e7052SJohn Crispin /* QDMA TX Forward CPU Pointer Register */ 258656e7052SJohn Crispin #define MTK_QTX_CTX_PTR 0x1B00 259656e7052SJohn Crispin 260656e7052SJohn Crispin /* QDMA TX Forward DMA Pointer Register */ 261656e7052SJohn Crispin #define MTK_QTX_DTX_PTR 0x1B04 262656e7052SJohn Crispin 263656e7052SJohn Crispin /* QDMA TX Release CPU Pointer Register */ 264656e7052SJohn Crispin #define MTK_QTX_CRX_PTR 0x1B10 265656e7052SJohn Crispin 266656e7052SJohn Crispin /* QDMA TX Release DMA Pointer Register */ 267656e7052SJohn Crispin #define MTK_QTX_DRX_PTR 0x1B14 268656e7052SJohn Crispin 269656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 270656e7052SJohn Crispin #define MTK_QDMA_FQ_HEAD 0x1B20 271656e7052SJohn Crispin 272656e7052SJohn Crispin /* QDMA FQ Head Pointer Register */ 273656e7052SJohn Crispin #define MTK_QDMA_FQ_TAIL 0x1B24 274656e7052SJohn Crispin 275656e7052SJohn Crispin /* QDMA FQ Free Page Counter Register */ 276656e7052SJohn Crispin #define MTK_QDMA_FQ_CNT 0x1B28 277656e7052SJohn Crispin 278656e7052SJohn Crispin /* QDMA FQ Free Page Buffer Length Register */ 279656e7052SJohn Crispin #define MTK_QDMA_FQ_BLEN 0x1B2C 280656e7052SJohn Crispin 281656e7052SJohn Crispin /* GMA1 Received Good Byte Count Register */ 282656e7052SJohn Crispin #define MTK_GDM1_TX_GBCNT 0x2400 283656e7052SJohn Crispin #define MTK_STAT_OFFSET 0x40 284656e7052SJohn Crispin 285656e7052SJohn Crispin /* QDMA descriptor txd4 */ 286656e7052SJohn Crispin #define TX_DMA_CHKSUM (0x7 << 29) 287656e7052SJohn Crispin #define TX_DMA_TSO BIT(28) 288656e7052SJohn Crispin #define TX_DMA_FPORT_SHIFT 25 289656e7052SJohn Crispin #define TX_DMA_FPORT_MASK 0x7 290656e7052SJohn Crispin #define TX_DMA_INS_VLAN BIT(16) 291656e7052SJohn Crispin 292656e7052SJohn Crispin /* QDMA descriptor txd3 */ 293656e7052SJohn Crispin #define TX_DMA_OWNER_CPU BIT(31) 294656e7052SJohn Crispin #define TX_DMA_LS0 BIT(30) 295656e7052SJohn Crispin #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) 296296c9120SStefan Roese #define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN) 297656e7052SJohn Crispin #define TX_DMA_SWC BIT(14) 298656e7052SJohn Crispin #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) 299656e7052SJohn Crispin 300296c9120SStefan Roese /* PDMA on MT7628 */ 301296c9120SStefan Roese #define TX_DMA_DONE BIT(31) 302296c9120SStefan Roese #define TX_DMA_LS1 BIT(14) 303296c9120SStefan Roese #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) 304296c9120SStefan Roese 305656e7052SJohn Crispin /* QDMA descriptor rxd2 */ 306656e7052SJohn Crispin #define RX_DMA_DONE BIT(31) 307296c9120SStefan Roese #define RX_DMA_LSO BIT(30) 308656e7052SJohn Crispin #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) 309656e7052SJohn Crispin #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) 3103f57d8c4SFelix Fietkau #define RX_DMA_VTAG BIT(15) 311656e7052SJohn Crispin 312656e7052SJohn Crispin /* QDMA descriptor rxd3 */ 313656e7052SJohn Crispin #define RX_DMA_VID(_x) ((_x) & 0xfff) 314656e7052SJohn Crispin 315656e7052SJohn Crispin /* QDMA descriptor rxd4 */ 316ba37b7caSFelix Fietkau #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) 317ba37b7caSFelix Fietkau #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) 318ba37b7caSFelix Fietkau #define MTK_RXD4_SRC_PORT GENMASK(21, 19) 319ba37b7caSFelix Fietkau #define MTK_RXD4_ALG GENMASK(31, 22) 320ba37b7caSFelix Fietkau 321ba37b7caSFelix Fietkau /* QDMA descriptor rxd4 */ 322656e7052SJohn Crispin #define RX_DMA_L4_VALID BIT(24) 323296c9120SStefan Roese #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ 324656e7052SJohn Crispin #define RX_DMA_FPORT_SHIFT 19 325656e7052SJohn Crispin #define RX_DMA_FPORT_MASK 0x7 326d5c53da2SFelix Fietkau #define RX_DMA_SPECIAL_TAG BIT(22) 327656e7052SJohn Crispin 328656e7052SJohn Crispin /* PHY Indirect Access Control registers */ 329656e7052SJohn Crispin #define MTK_PHY_IAC 0x10004 330656e7052SJohn Crispin #define PHY_IAC_ACCESS BIT(31) 331656e7052SJohn Crispin #define PHY_IAC_READ BIT(19) 332656e7052SJohn Crispin #define PHY_IAC_WRITE BIT(18) 333656e7052SJohn Crispin #define PHY_IAC_START BIT(16) 334656e7052SJohn Crispin #define PHY_IAC_ADDR_SHIFT 20 335656e7052SJohn Crispin #define PHY_IAC_REG_SHIFT 25 336656e7052SJohn Crispin #define PHY_IAC_TIMEOUT HZ 337656e7052SJohn Crispin 33842c03844SSean Wang #define MTK_MAC_MISC 0x1000c 33942c03844SSean Wang #define MTK_MUX_TO_ESW BIT(0) 34042c03844SSean Wang 341656e7052SJohn Crispin /* Mac control registers */ 342656e7052SJohn Crispin #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) 3434fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) 3444fd59792SDENG Qingfang #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) 3454fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1518 0x0 3464fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1536 0x1 3474fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_1552 0x2 3484fd59792SDENG Qingfang #define MAC_MCR_MAX_RX_2048 0x3 349656e7052SJohn Crispin #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) 350656e7052SJohn Crispin #define MAC_MCR_FORCE_MODE BIT(15) 351656e7052SJohn Crispin #define MAC_MCR_TX_EN BIT(14) 352656e7052SJohn Crispin #define MAC_MCR_RX_EN BIT(13) 353656e7052SJohn Crispin #define MAC_MCR_BACKOFF_EN BIT(9) 354656e7052SJohn Crispin #define MAC_MCR_BACKPR_EN BIT(8) 355656e7052SJohn Crispin #define MAC_MCR_FORCE_RX_FC BIT(5) 356656e7052SJohn Crispin #define MAC_MCR_FORCE_TX_FC BIT(4) 357656e7052SJohn Crispin #define MAC_MCR_SPEED_1000 BIT(3) 358656e7052SJohn Crispin #define MAC_MCR_SPEED_100 BIT(2) 359656e7052SJohn Crispin #define MAC_MCR_FORCE_DPX BIT(1) 360656e7052SJohn Crispin #define MAC_MCR_FORCE_LINK BIT(0) 361b8fc9f30SRené van Dorst #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) 362b8fc9f30SRené van Dorst 363b8fc9f30SRené van Dorst /* Mac status registers */ 364b8fc9f30SRené van Dorst #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) 365b8fc9f30SRené van Dorst #define MAC_MSR_EEE1G BIT(7) 366b8fc9f30SRené van Dorst #define MAC_MSR_EEE100M BIT(6) 367b8fc9f30SRené van Dorst #define MAC_MSR_RX_FC BIT(5) 368b8fc9f30SRené van Dorst #define MAC_MSR_TX_FC BIT(4) 369b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_1000 BIT(3) 370b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_100 BIT(2) 371b8fc9f30SRené van Dorst #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) 372b8fc9f30SRené van Dorst #define MAC_MSR_DPX BIT(1) 373b8fc9f30SRené van Dorst #define MAC_MSR_LINK BIT(0) 374656e7052SJohn Crispin 375f430dea7SSean Wang /* TRGMII RXC control register */ 376f430dea7SSean Wang #define TRGMII_RCK_CTRL 0x10300 377f430dea7SSean Wang #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) 378f430dea7SSean Wang #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) 379f430dea7SSean Wang #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 380a5d75538SRené van Dorst #define RXC_RST BIT(31) 381f430dea7SSean Wang #define RXC_DQSISEL BIT(30) 382f430dea7SSean Wang #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) 383f430dea7SSean Wang #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) 384f430dea7SSean Wang 385a5d75538SRené van Dorst #define NUM_TRGMII_CTRL 5 386a5d75538SRené van Dorst 387f430dea7SSean Wang /* TRGMII RXC control register */ 388f430dea7SSean Wang #define TRGMII_TCK_CTRL 0x10340 389f430dea7SSean Wang #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) 390f430dea7SSean Wang #define TXC_INV BIT(30) 391f430dea7SSean Wang #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) 392f430dea7SSean Wang #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) 393f430dea7SSean Wang 394a5d75538SRené van Dorst /* TRGMII TX Drive Strength */ 395a5d75538SRené van Dorst #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) 396a5d75538SRené van Dorst #define TD_DM_DRVP(x) ((x) & 0xf) 397a5d75538SRené van Dorst #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 398a5d75538SRené van Dorst 399f430dea7SSean Wang /* TRGMII Interface mode register */ 400f430dea7SSean Wang #define INTF_MODE 0x10390 401f430dea7SSean Wang #define TRGMII_INTF_DIS BIT(0) 402f430dea7SSean Wang #define TRGMII_MODE BIT(1) 403f430dea7SSean Wang #define TRGMII_CENTRAL_ALIGNED BIT(2) 404f430dea7SSean Wang #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) 405f430dea7SSean Wang #define INTF_MODE_RGMII_10_100 0 406f430dea7SSean Wang 407656e7052SJohn Crispin /* GPIO port control registers for GMAC 2*/ 408656e7052SJohn Crispin #define GPIO_OD33_CTRL8 0x4c0 409656e7052SJohn Crispin #define GPIO_BIAS_CTRL 0xed0 410656e7052SJohn Crispin #define GPIO_DRV_SEL10 0xf00 411656e7052SJohn Crispin 412b95b6d99SNelson Chang /* ethernet subsystem chip id register */ 413b95b6d99SNelson Chang #define ETHSYS_CHIPID0_3 0x0 414b95b6d99SNelson Chang #define ETHSYS_CHIPID4_7 0x4 415983e1a6cSNelson Chang #define MT7623_ETH 7623 41642c03844SSean Wang #define MT7622_ETH 7622 417889bcbdeSBjørn Mork #define MT7621_ETH 7621 418b95b6d99SNelson Chang 4198efaa653SRené van Dorst /* ethernet system control register */ 4208efaa653SRené van Dorst #define ETHSYS_SYSCFG 0x10 4218efaa653SRené van Dorst #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) 4228efaa653SRené van Dorst 423656e7052SJohn Crispin /* ethernet subsystem config register */ 424656e7052SJohn Crispin #define ETHSYS_SYSCFG0 0x14 425656e7052SJohn Crispin #define SYSCFG0_GE_MASK 0x3 426656e7052SJohn Crispin #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) 4277093f9d8SSean Wang #define SYSCFG0_SGMII_MASK GENMASK(9, 8) 4287093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) 4297093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) 4307093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) 4317093f9d8SSean Wang #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) 4327093f9d8SSean Wang 433656e7052SJohn Crispin 434f430dea7SSean Wang /* ethernet subsystem clock register */ 435f430dea7SSean Wang #define ETHSYS_CLKCFG0 0x2c 436f430dea7SSean Wang #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 4378efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) 4388efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_APLL BIT(6) 4398efaa653SRené van Dorst #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) 440f430dea7SSean Wang 4412a8307aaSSean Wang /* ethernet reset control register */ 4422a8307aaSSean Wang #define ETHSYS_RSTCTRL 0x34 4432a8307aaSSean Wang #define RSTCTRL_FE BIT(6) 4442a8307aaSSean Wang #define RSTCTRL_PPE BIT(31) 4452a8307aaSSean Wang 44642c03844SSean Wang /* SGMII subsystem config registers */ 44742c03844SSean Wang /* Register to auto-negotiation restart */ 44842c03844SSean Wang #define SGMSYS_PCS_CONTROL_1 0x0 44942c03844SSean Wang #define SGMII_AN_RESTART BIT(9) 4507e538372SRené van Dorst #define SGMII_ISOLATE BIT(10) 4517e538372SRené van Dorst #define SGMII_AN_ENABLE BIT(12) 4527e538372SRené van Dorst #define SGMII_LINK_STATYS BIT(18) 4537e538372SRené van Dorst #define SGMII_AN_ABILITY BIT(19) 4547e538372SRené van Dorst #define SGMII_AN_COMPLETE BIT(21) 4557e538372SRené van Dorst #define SGMII_PCS_FAULT BIT(23) 4567e538372SRené van Dorst #define SGMII_AN_EXPANSION_CLR BIT(30) 45742c03844SSean Wang 45842c03844SSean Wang /* Register to programmable link timer, the unit in 2 * 8ns */ 45942c03844SSean Wang #define SGMSYS_PCS_LINK_TIMER 0x18 46042c03844SSean Wang #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) 46142c03844SSean Wang 46242c03844SSean Wang /* Register to control remote fault */ 46342c03844SSean Wang #define SGMSYS_SGMII_MODE 0x20 4647e538372SRené van Dorst #define SGMII_IF_MODE_BIT0 BIT(0) 4657e538372SRené van Dorst #define SGMII_SPEED_DUPLEX_AN BIT(1) 4667e538372SRené van Dorst #define SGMII_SPEED_10 0x0 4677e538372SRené van Dorst #define SGMII_SPEED_100 BIT(2) 4687e538372SRené van Dorst #define SGMII_SPEED_1000 BIT(3) 4697e538372SRené van Dorst #define SGMII_DUPLEX_FULL BIT(4) 4707e538372SRené van Dorst #define SGMII_IF_MODE_BIT5 BIT(5) 47142c03844SSean Wang #define SGMII_REMOTE_FAULT_DIS BIT(8) 4727e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_VAL BIT(9) 4737e538372SRené van Dorst #define SGMII_CODE_SYNC_SET_EN BIT(10) 4747e538372SRené van Dorst #define SGMII_SEND_AN_ERROR_EN BIT(11) 4757e538372SRené van Dorst #define SGMII_IF_MODE_MASK GENMASK(5, 1) 4767e538372SRené van Dorst 4777e538372SRené van Dorst /* Register to set SGMII speed, ANA RG_ Control Signals III*/ 4787e538372SRené van Dorst #define SGMSYS_ANA_RG_CS3 0x2028 4797e538372SRené van Dorst #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) 4807e538372SRené van Dorst #define RG_PHY_SPEED_1_25G 0x0 4817e538372SRené van Dorst #define RG_PHY_SPEED_3_125G BIT(2) 48242c03844SSean Wang 48342c03844SSean Wang /* Register to power up QPHY */ 48442c03844SSean Wang #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 48542c03844SSean Wang #define SGMII_PHYA_PWD BIT(4) 48642c03844SSean Wang 4877093f9d8SSean Wang /* Infrasys subsystem config registers */ 4887093f9d8SSean Wang #define INFRA_MISC2 0x70c 4897093f9d8SSean Wang #define CO_QPHY_SEL BIT(0) 4907093f9d8SSean Wang #define GEPHY_MAC_SEL BIT(1) 4917093f9d8SSean Wang 492296c9120SStefan Roese /* MT7628/88 specific stuff */ 493296c9120SStefan Roese #define MT7628_PDMA_OFFSET 0x0800 494296c9120SStefan Roese #define MT7628_SDM_OFFSET 0x0c00 495296c9120SStefan Roese 496296c9120SStefan Roese #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) 497296c9120SStefan Roese #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) 498296c9120SStefan Roese #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) 499296c9120SStefan Roese #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) 500296c9120SStefan Roese #define MT7628_PST_DTX_IDX0 BIT(0) 501296c9120SStefan Roese 502296c9120SStefan Roese #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) 503296c9120SStefan Roese #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) 504296c9120SStefan Roese 505656e7052SJohn Crispin struct mtk_rx_dma { 506656e7052SJohn Crispin unsigned int rxd1; 507656e7052SJohn Crispin unsigned int rxd2; 508656e7052SJohn Crispin unsigned int rxd3; 509656e7052SJohn Crispin unsigned int rxd4; 510656e7052SJohn Crispin } __packed __aligned(4); 511656e7052SJohn Crispin 512656e7052SJohn Crispin struct mtk_tx_dma { 513656e7052SJohn Crispin unsigned int txd1; 514656e7052SJohn Crispin unsigned int txd2; 515656e7052SJohn Crispin unsigned int txd3; 516656e7052SJohn Crispin unsigned int txd4; 517656e7052SJohn Crispin } __packed __aligned(4); 518656e7052SJohn Crispin 519656e7052SJohn Crispin struct mtk_eth; 520656e7052SJohn Crispin struct mtk_mac; 521656e7052SJohn Crispin 522656e7052SJohn Crispin /* struct mtk_hw_stats - the structure that holds the traffic statistics. 523656e7052SJohn Crispin * @stats_lock: make sure that stats operations are atomic 524656e7052SJohn Crispin * @reg_offset: the status register offset of the SoC 525656e7052SJohn Crispin * @syncp: the refcount 526656e7052SJohn Crispin * 527656e7052SJohn Crispin * All of the supported SoCs have hardware counters for traffic statistics. 528656e7052SJohn Crispin * Whenever the status IRQ triggers we can read the latest stats from these 529656e7052SJohn Crispin * counters and store them in this struct. 530656e7052SJohn Crispin */ 531656e7052SJohn Crispin struct mtk_hw_stats { 532656e7052SJohn Crispin u64 tx_bytes; 533656e7052SJohn Crispin u64 tx_packets; 534656e7052SJohn Crispin u64 tx_skip; 535656e7052SJohn Crispin u64 tx_collisions; 536656e7052SJohn Crispin u64 rx_bytes; 537656e7052SJohn Crispin u64 rx_packets; 538656e7052SJohn Crispin u64 rx_overflow; 539656e7052SJohn Crispin u64 rx_fcs_errors; 540656e7052SJohn Crispin u64 rx_short_errors; 541656e7052SJohn Crispin u64 rx_long_errors; 542656e7052SJohn Crispin u64 rx_checksum_errors; 543656e7052SJohn Crispin u64 rx_flow_control_packets; 544656e7052SJohn Crispin 545656e7052SJohn Crispin spinlock_t stats_lock; 546656e7052SJohn Crispin u32 reg_offset; 547656e7052SJohn Crispin struct u64_stats_sync syncp; 548656e7052SJohn Crispin }; 549656e7052SJohn Crispin 550656e7052SJohn Crispin enum mtk_tx_flags { 551134d2152SSean Wang /* PDMA descriptor can point at 1-2 segments. This enum allows us to 552134d2152SSean Wang * track how memory was allocated so that it can be freed properly. 553134d2152SSean Wang */ 554656e7052SJohn Crispin MTK_TX_FLAGS_SINGLE0 = 0x01, 555656e7052SJohn Crispin MTK_TX_FLAGS_PAGE0 = 0x02, 556134d2152SSean Wang 557134d2152SSean Wang /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 558134d2152SSean Wang * SKB out instead of looking up through hardware TX descriptor. 559134d2152SSean Wang */ 560134d2152SSean Wang MTK_TX_FLAGS_FPORT0 = 0x04, 561134d2152SSean Wang MTK_TX_FLAGS_FPORT1 = 0x08, 562656e7052SJohn Crispin }; 563656e7052SJohn Crispin 564549e5495SSean Wang /* This enum allows us to identify how the clock is defined on the array of the 565549e5495SSean Wang * clock in the order 566549e5495SSean Wang */ 567549e5495SSean Wang enum mtk_clks_map { 568549e5495SSean Wang MTK_CLK_ETHIF, 569d438e298SSean Wang MTK_CLK_SGMIITOP, 570549e5495SSean Wang MTK_CLK_ESW, 57142c03844SSean Wang MTK_CLK_GP0, 572549e5495SSean Wang MTK_CLK_GP1, 573549e5495SSean Wang MTK_CLK_GP2, 574d438e298SSean Wang MTK_CLK_FE, 575f430dea7SSean Wang MTK_CLK_TRGPLL, 57642c03844SSean Wang MTK_CLK_SGMII_TX_250M, 57742c03844SSean Wang MTK_CLK_SGMII_RX_250M, 57842c03844SSean Wang MTK_CLK_SGMII_CDR_REF, 57942c03844SSean Wang MTK_CLK_SGMII_CDR_FB, 580d438e298SSean Wang MTK_CLK_SGMII2_TX_250M, 581d438e298SSean Wang MTK_CLK_SGMII2_RX_250M, 582d438e298SSean Wang MTK_CLK_SGMII2_CDR_REF, 583d438e298SSean Wang MTK_CLK_SGMII2_CDR_FB, 58442c03844SSean Wang MTK_CLK_SGMII_CK, 58542c03844SSean Wang MTK_CLK_ETH2PLL, 586549e5495SSean Wang MTK_CLK_MAX 587549e5495SSean Wang }; 588549e5495SSean Wang 5892ec50f57SSean Wang #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 5902ec50f57SSean Wang BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 5912ec50f57SSean Wang BIT(MTK_CLK_TRGPLL)) 59242c03844SSean Wang #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 59342c03844SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 59442c03844SSean Wang BIT(MTK_CLK_GP2) | \ 59542c03844SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 59642c03844SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 59742c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 59842c03844SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 59942c03844SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 60042c03844SSean Wang BIT(MTK_CLK_ETH2PLL)) 601889bcbdeSBjørn Mork #define MT7621_CLKS_BITMAP (0) 602296c9120SStefan Roese #define MT7628_CLKS_BITMAP (0) 603d438e298SSean Wang #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 604d438e298SSean Wang BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 605d438e298SSean Wang BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 606d438e298SSean Wang BIT(MTK_CLK_SGMII_TX_250M) | \ 607d438e298SSean Wang BIT(MTK_CLK_SGMII_RX_250M) | \ 608d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_REF) | \ 609d438e298SSean Wang BIT(MTK_CLK_SGMII_CDR_FB) | \ 610d438e298SSean Wang BIT(MTK_CLK_SGMII2_TX_250M) | \ 611d438e298SSean Wang BIT(MTK_CLK_SGMII2_RX_250M) | \ 612d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_REF) | \ 613d438e298SSean Wang BIT(MTK_CLK_SGMII2_CDR_FB) | \ 614d438e298SSean Wang BIT(MTK_CLK_SGMII_CK) | \ 615d438e298SSean Wang BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 616889bcbdeSBjørn Mork 6179ea4d311SSean Wang enum mtk_dev_state { 618dce6fa42SSean Wang MTK_HW_INIT, 619dce6fa42SSean Wang MTK_RESETTING 6209ea4d311SSean Wang }; 6219ea4d311SSean Wang 622656e7052SJohn Crispin /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at 623656e7052SJohn Crispin * by the TX descriptor s 624656e7052SJohn Crispin * @skb: The SKB pointer of the packet being sent 625656e7052SJohn Crispin * @dma_addr0: The base addr of the first segment 626656e7052SJohn Crispin * @dma_len0: The length of the first segment 627656e7052SJohn Crispin * @dma_addr1: The base addr of the second segment 628656e7052SJohn Crispin * @dma_len1: The length of the second segment 629656e7052SJohn Crispin */ 630656e7052SJohn Crispin struct mtk_tx_buf { 631656e7052SJohn Crispin struct sk_buff *skb; 632656e7052SJohn Crispin u32 flags; 633656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr0); 634656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len0); 635656e7052SJohn Crispin DEFINE_DMA_UNMAP_ADDR(dma_addr1); 636656e7052SJohn Crispin DEFINE_DMA_UNMAP_LEN(dma_len1); 637656e7052SJohn Crispin }; 638656e7052SJohn Crispin 639656e7052SJohn Crispin /* struct mtk_tx_ring - This struct holds info describing a TX ring 640656e7052SJohn Crispin * @dma: The descriptor ring 641656e7052SJohn Crispin * @buf: The memory pointed at by the ring 642656e7052SJohn Crispin * @phys: The physical addr of tx_buf 643656e7052SJohn Crispin * @next_free: Pointer to the next free descriptor 644656e7052SJohn Crispin * @last_free: Pointer to the last free descriptor 6454e6bf609SFelix Fietkau * @last_free_ptr: Hardware pointer value of the last free descriptor 646656e7052SJohn Crispin * @thresh: The threshold of minimum amount of free descriptors 647656e7052SJohn Crispin * @free_count: QDMA uses a linked list. Track how many free descriptors 648656e7052SJohn Crispin * are present 649656e7052SJohn Crispin */ 650656e7052SJohn Crispin struct mtk_tx_ring { 651656e7052SJohn Crispin struct mtk_tx_dma *dma; 652656e7052SJohn Crispin struct mtk_tx_buf *buf; 653656e7052SJohn Crispin dma_addr_t phys; 654656e7052SJohn Crispin struct mtk_tx_dma *next_free; 655656e7052SJohn Crispin struct mtk_tx_dma *last_free; 6564e6bf609SFelix Fietkau u32 last_free_ptr; 657656e7052SJohn Crispin u16 thresh; 658656e7052SJohn Crispin atomic_t free_count; 659296c9120SStefan Roese int dma_size; 660296c9120SStefan Roese struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ 661296c9120SStefan Roese dma_addr_t phys_pdma; 662296c9120SStefan Roese int cpu_idx; 663656e7052SJohn Crispin }; 664656e7052SJohn Crispin 665ee406810SNelson Chang /* PDMA rx ring mode */ 666ee406810SNelson Chang enum mtk_rx_flags { 667ee406810SNelson Chang MTK_RX_FLAGS_NORMAL = 0, 668ee406810SNelson Chang MTK_RX_FLAGS_HWLRO, 6696427dc1dSJohn Crispin MTK_RX_FLAGS_QDMA, 670ee406810SNelson Chang }; 671ee406810SNelson Chang 672656e7052SJohn Crispin /* struct mtk_rx_ring - This struct holds info describing a RX ring 673656e7052SJohn Crispin * @dma: The descriptor ring 674656e7052SJohn Crispin * @data: The memory pointed at by the ring 675656e7052SJohn Crispin * @phys: The physical addr of rx_buf 676656e7052SJohn Crispin * @frag_size: How big can each fragment be 677656e7052SJohn Crispin * @buf_size: The size of each packet buffer 678656e7052SJohn Crispin * @calc_idx: The current head of ring 679656e7052SJohn Crispin */ 680656e7052SJohn Crispin struct mtk_rx_ring { 681656e7052SJohn Crispin struct mtk_rx_dma *dma; 682656e7052SJohn Crispin u8 **data; 683656e7052SJohn Crispin dma_addr_t phys; 684656e7052SJohn Crispin u16 frag_size; 685656e7052SJohn Crispin u16 buf_size; 686ee406810SNelson Chang u16 dma_size; 687ee406810SNelson Chang bool calc_idx_update; 688656e7052SJohn Crispin u16 calc_idx; 689ee406810SNelson Chang u32 crx_idx_reg; 690656e7052SJohn Crispin }; 691656e7052SJohn Crispin 692e2c74694SRené van Dorst enum mkt_eth_capabilities { 693e2c74694SRené van Dorst MTK_RGMII_BIT = 0, 694e2c74694SRené van Dorst MTK_TRGMII_BIT, 695e2c74694SRené van Dorst MTK_SGMII_BIT, 696e2c74694SRené van Dorst MTK_ESW_BIT, 697e2c74694SRené van Dorst MTK_GEPHY_BIT, 698e2c74694SRené van Dorst MTK_MUX_BIT, 699e2c74694SRené van Dorst MTK_INFRA_BIT, 700e2c74694SRené van Dorst MTK_SHARED_SGMII_BIT, 701e2c74694SRené van Dorst MTK_HWLRO_BIT, 702e2c74694SRené van Dorst MTK_SHARED_INT_BIT, 703e2c74694SRené van Dorst MTK_TRGMII_MT7621_CLK_BIT, 704296c9120SStefan Roese MTK_QDMA_BIT, 705296c9120SStefan Roese MTK_SOC_MT7628_BIT, 7067093f9d8SSean Wang 707e2c74694SRené van Dorst /* MUX BITS*/ 708e2c74694SRené van Dorst MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, 709e2c74694SRené van Dorst MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, 710e2c74694SRené van Dorst MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, 711e2c74694SRené van Dorst MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, 712e2c74694SRené van Dorst MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, 713e2c74694SRené van Dorst 714e2c74694SRené van Dorst /* PATH BITS */ 715e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_RGMII_BIT, 716e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_TRGMII_BIT, 717e2c74694SRené van Dorst MTK_ETH_PATH_GMAC1_SGMII_BIT, 718e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_RGMII_BIT, 719e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_SGMII_BIT, 720e2c74694SRené van Dorst MTK_ETH_PATH_GMAC2_GEPHY_BIT, 721e2c74694SRené van Dorst MTK_ETH_PATH_GDM1_ESW_BIT, 7227093f9d8SSean Wang }; 7237093f9d8SSean Wang 7247093f9d8SSean Wang /* Supported hardware group on SoCs */ 725e2c74694SRené van Dorst #define MTK_RGMII BIT(MTK_RGMII_BIT) 726e2c74694SRené van Dorst #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 727e2c74694SRené van Dorst #define MTK_SGMII BIT(MTK_SGMII_BIT) 728e2c74694SRené van Dorst #define MTK_ESW BIT(MTK_ESW_BIT) 729e2c74694SRené van Dorst #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 730e2c74694SRené van Dorst #define MTK_MUX BIT(MTK_MUX_BIT) 731e2c74694SRené van Dorst #define MTK_INFRA BIT(MTK_INFRA_BIT) 732e2c74694SRené van Dorst #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 733e2c74694SRené van Dorst #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 734e2c74694SRené van Dorst #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 735e2c74694SRené van Dorst #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 736296c9120SStefan Roese #define MTK_QDMA BIT(MTK_QDMA_BIT) 737296c9120SStefan Roese #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 738e2c74694SRené van Dorst 739e2c74694SRené van Dorst #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 740e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 741e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 742e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 743e2c74694SRené van Dorst #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 744e2c74694SRené van Dorst BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 745e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 746e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 747e2c74694SRené van Dorst #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 748e2c74694SRené van Dorst BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 7497093f9d8SSean Wang 7507093f9d8SSean Wang /* Supported path present on SoCs */ 751e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 752e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 753e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 754e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 755e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 756e2c74694SRené van Dorst #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 757e2c74694SRené van Dorst #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 7587093f9d8SSean Wang 759e2c74694SRené van Dorst #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 760e2c74694SRené van Dorst #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) 761e2c74694SRené van Dorst #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) 762e2c74694SRené van Dorst #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) 763e2c74694SRené van Dorst #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) 764e2c74694SRené van Dorst #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) 765e2c74694SRené van Dorst #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) 7667093f9d8SSean Wang 7677093f9d8SSean Wang /* MUXes present on SoCs */ 7687093f9d8SSean Wang /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ 769e2c74694SRené van Dorst #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) 7707093f9d8SSean Wang 7717093f9d8SSean Wang /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ 7727093f9d8SSean Wang #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ 773e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) 7747093f9d8SSean Wang 7757093f9d8SSean Wang /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ 7767093f9d8SSean Wang #define MTK_MUX_U3_GMAC2_TO_QPHY \ 777e2c74694SRené van Dorst (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) 7787093f9d8SSean Wang 7797093f9d8SSean Wang /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ 7807093f9d8SSean Wang #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 781e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ 7827093f9d8SSean Wang MTK_SHARED_SGMII) 7837093f9d8SSean Wang 7847093f9d8SSean Wang /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ 7857093f9d8SSean Wang #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ 786e2c74694SRené van Dorst (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) 7877093f9d8SSean Wang 7882ec50f57SSean Wang #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) 7892ec50f57SSean Wang 7908efaa653SRené van Dorst #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ 791296c9120SStefan Roese MTK_GMAC2_RGMII | MTK_SHARED_INT | \ 792296c9120SStefan Roese MTK_TRGMII_MT7621_CLK | MTK_QDMA) 7938efaa653SRené van Dorst 7947093f9d8SSean Wang #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ 7957093f9d8SSean Wang MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ 7967093f9d8SSean Wang MTK_MUX_GDM1_TO_GMAC1_ESW | \ 797296c9120SStefan Roese MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) 7987093f9d8SSean Wang 799296c9120SStefan Roese #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ 800296c9120SStefan Roese MTK_QDMA) 801296c9120SStefan Roese 802296c9120SStefan Roese #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) 8037093f9d8SSean Wang 8047093f9d8SSean Wang #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 8057093f9d8SSean Wang MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ 8067093f9d8SSean Wang MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ 8077093f9d8SSean Wang MTK_MUX_U3_GMAC2_TO_QPHY | \ 808296c9120SStefan Roese MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) 8097093f9d8SSean Wang 81042c03844SSean Wang /* struct mtk_eth_data - This is the structure holding all differences 8112ec50f57SSean Wang * among various plaforms 8129ffee4a8SSean Wang * @ana_rgc3: The offset for register ANA_RGC3 related to 8139ffee4a8SSean Wang * sgmiisys syscon 8142ec50f57SSean Wang * @caps Flags shown the extra capability for the SoC 815296c9120SStefan Roese * @hw_features Flags shown HW features 8162ec50f57SSean Wang * @required_clks Flags shown the bitmap for required clocks on 8172ec50f57SSean Wang * the target SoC 818243dc5fbSSean Wang * @required_pctl A bool value to show whether the SoC requires 819243dc5fbSSean Wang * the extra setup for those pins used by GMAC. 8202ec50f57SSean Wang */ 8212ec50f57SSean Wang struct mtk_soc_data { 8229ffee4a8SSean Wang u32 ana_rgc3; 8232ec50f57SSean Wang u32 caps; 8242ec50f57SSean Wang u32 required_clks; 825243dc5fbSSean Wang bool required_pctl; 826ba37b7caSFelix Fietkau u8 offload_version; 827296c9120SStefan Roese netdev_features_t hw_features; 8282ec50f57SSean Wang }; 8292ec50f57SSean Wang 830656e7052SJohn Crispin /* currently no SoC has more than 2 macs */ 831656e7052SJohn Crispin #define MTK_MAX_DEVS 2 832656e7052SJohn Crispin 8339ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_AN BIT(31) 834937a9440SJoe Perches #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) 8359ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_1000 BIT(0) 8369ffee4a8SSean Wang #define MTK_SGMII_PHYSPEED_2500 BIT(1) 8379ffee4a8SSean Wang #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) 8389ffee4a8SSean Wang 8399ffee4a8SSean Wang /* struct mtk_sgmii - This is the structure holding sgmii regmap and its 8409ffee4a8SSean Wang * characteristics 8419ffee4a8SSean Wang * @regmap: The register map pointing at the range used to setup 8429ffee4a8SSean Wang * SGMII modes 8439ffee4a8SSean Wang * @flags: The enum refers to which mode the sgmii wants to run on 8449ffee4a8SSean Wang * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap 8459ffee4a8SSean Wang */ 8469ffee4a8SSean Wang 8479ffee4a8SSean Wang struct mtk_sgmii { 8489ffee4a8SSean Wang struct regmap *regmap[MTK_MAX_DEVS]; 8499ffee4a8SSean Wang u32 flags[MTK_MAX_DEVS]; 8509ffee4a8SSean Wang u32 ana_rgc3; 8519ffee4a8SSean Wang }; 8529ffee4a8SSean Wang 853656e7052SJohn Crispin /* struct mtk_eth - This is the main datasructure for holding the state 854656e7052SJohn Crispin * of the driver 855656e7052SJohn Crispin * @dev: The device pointer 856656e7052SJohn Crispin * @base: The mapped register i/o base 857656e7052SJohn Crispin * @page_lock: Make sure that register operations are atomic 8585cce0322SJohn Crispin * @tx_irq__lock: Make sure that IRQ register operations are atomic 8595cce0322SJohn Crispin * @rx_irq__lock: Make sure that IRQ register operations are atomic 860e9229ffdSFelix Fietkau * @dim_lock: Make sure that Net DIM operations are atomic 861656e7052SJohn Crispin * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a 862656e7052SJohn Crispin * dummy for NAPI to work 863656e7052SJohn Crispin * @netdev: The netdev instances 864656e7052SJohn Crispin * @mac: Each netdev is linked to a physical MAC 865656e7052SJohn Crispin * @irq: The IRQ that we are using 866656e7052SJohn Crispin * @msg_enable: Ethtool msg level 867656e7052SJohn Crispin * @ethsys: The register map pointing at the range used to setup 868656e7052SJohn Crispin * MII modes 8697093f9d8SSean Wang * @infra: The register map pointing at the range used to setup 8707093f9d8SSean Wang * SGMII and GePHY path 871656e7052SJohn Crispin * @pctl: The register map pointing at the range used to setup 872656e7052SJohn Crispin * GMAC port drive/slew values 873656e7052SJohn Crispin * @dma_refcnt: track how many netdevs are using the DMA engine 8740c07ce7fSJohn Crispin * @tx_ring: Pointer to the memory holding info about the TX ring 8750c07ce7fSJohn Crispin * @rx_ring: Pointer to the memory holding info about the RX ring 8766427dc1dSJohn Crispin * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring 87780673029SJohn Crispin * @tx_napi: The TX NAPI struct 87880673029SJohn Crispin * @rx_napi: The RX NAPI struct 879e9229ffdSFelix Fietkau * @rx_events: Net DIM RX event counter 880e9229ffdSFelix Fietkau * @rx_packets: Net DIM RX packet counter 881e9229ffdSFelix Fietkau * @rx_bytes: Net DIM RX byte counter 882e9229ffdSFelix Fietkau * @rx_dim: Net DIM RX context 883e9229ffdSFelix Fietkau * @tx_events: Net DIM TX event counter 884e9229ffdSFelix Fietkau * @tx_packets: Net DIM TX packet counter 885e9229ffdSFelix Fietkau * @tx_bytes: Net DIM TX byte counter 886e9229ffdSFelix Fietkau * @tx_dim: Net DIM TX context 887656e7052SJohn Crispin * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring 888605e4fe4SJohn Crispin * @phy_scratch_ring: physical address of scratch_ring 889656e7052SJohn Crispin * @scratch_head: The scratch memory that scratch_ring points to. 890549e5495SSean Wang * @clks: clock array for all clocks required 891656e7052SJohn Crispin * @mii_bus: If there is a bus we need to create an instance for it 8927c78b4adSJohn Crispin * @pending_work: The workqueue used to reset the dma ring 89342c03844SSean Wang * @state: Initialization and runtime state of the device 8942ec50f57SSean Wang * @soc: Holding specific data among vaious SoCs 895656e7052SJohn Crispin */ 896656e7052SJohn Crispin 897656e7052SJohn Crispin struct mtk_eth { 898656e7052SJohn Crispin struct device *dev; 899656e7052SJohn Crispin void __iomem *base; 900656e7052SJohn Crispin spinlock_t page_lock; 9015cce0322SJohn Crispin spinlock_t tx_irq_lock; 9025cce0322SJohn Crispin spinlock_t rx_irq_lock; 903656e7052SJohn Crispin struct net_device dummy_dev; 904656e7052SJohn Crispin struct net_device *netdev[MTK_MAX_DEVS]; 905656e7052SJohn Crispin struct mtk_mac *mac[MTK_MAX_DEVS]; 90680673029SJohn Crispin int irq[3]; 907656e7052SJohn Crispin u32 msg_enable; 908656e7052SJohn Crispin unsigned long sysclk; 909656e7052SJohn Crispin struct regmap *ethsys; 9107093f9d8SSean Wang struct regmap *infra; 9119ffee4a8SSean Wang struct mtk_sgmii *sgmii; 912656e7052SJohn Crispin struct regmap *pctl; 913ee406810SNelson Chang bool hwlro; 914c6d4e63eSElena Reshetova refcount_t dma_refcnt; 915656e7052SJohn Crispin struct mtk_tx_ring tx_ring; 916ee406810SNelson Chang struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; 9176427dc1dSJohn Crispin struct mtk_rx_ring rx_ring_qdma; 91880673029SJohn Crispin struct napi_struct tx_napi; 919656e7052SJohn Crispin struct napi_struct rx_napi; 920656e7052SJohn Crispin struct mtk_tx_dma *scratch_ring; 921605e4fe4SJohn Crispin dma_addr_t phy_scratch_ring; 922656e7052SJohn Crispin void *scratch_head; 923549e5495SSean Wang struct clk *clks[MTK_CLK_MAX]; 924549e5495SSean Wang 925656e7052SJohn Crispin struct mii_bus *mii_bus; 9267c78b4adSJohn Crispin struct work_struct pending_work; 9279ea4d311SSean Wang unsigned long state; 9282ec50f57SSean Wang 9292ec50f57SSean Wang const struct mtk_soc_data *soc; 930296c9120SStefan Roese 931e9229ffdSFelix Fietkau spinlock_t dim_lock; 932e9229ffdSFelix Fietkau 933e9229ffdSFelix Fietkau u32 rx_events; 934e9229ffdSFelix Fietkau u32 rx_packets; 935e9229ffdSFelix Fietkau u32 rx_bytes; 936e9229ffdSFelix Fietkau struct dim rx_dim; 937e9229ffdSFelix Fietkau 938e9229ffdSFelix Fietkau u32 tx_events; 939e9229ffdSFelix Fietkau u32 tx_packets; 940e9229ffdSFelix Fietkau u32 tx_bytes; 941e9229ffdSFelix Fietkau struct dim tx_dim; 942e9229ffdSFelix Fietkau 943296c9120SStefan Roese u32 tx_int_mask_reg; 944296c9120SStefan Roese u32 tx_int_status_reg; 945296c9120SStefan Roese u32 rx_dma_l4_valid; 946296c9120SStefan Roese int ip_align; 947ba37b7caSFelix Fietkau 948ba37b7caSFelix Fietkau struct mtk_ppe ppe; 949502e84e2SFelix Fietkau struct rhashtable flow_table; 950656e7052SJohn Crispin }; 951656e7052SJohn Crispin 952656e7052SJohn Crispin /* struct mtk_mac - the structure that holds the info about the MACs of the 953656e7052SJohn Crispin * SoC 954656e7052SJohn Crispin * @id: The number of the MAC 955b8fc9f30SRené van Dorst * @interface: Interface mode kept for detecting change in hw settings 956656e7052SJohn Crispin * @of_node: Our devicetree node 957656e7052SJohn Crispin * @hw: Backpointer to our main datastruture 958656e7052SJohn Crispin * @hw_stats: Packet statistics counter 959656e7052SJohn Crispin */ 960656e7052SJohn Crispin struct mtk_mac { 961656e7052SJohn Crispin int id; 962b8fc9f30SRené van Dorst phy_interface_t interface; 963b8fc9f30SRené van Dorst unsigned int mode; 964b8fc9f30SRené van Dorst int speed; 965656e7052SJohn Crispin struct device_node *of_node; 966b8fc9f30SRené van Dorst struct phylink *phylink; 967b8fc9f30SRené van Dorst struct phylink_config phylink_config; 968656e7052SJohn Crispin struct mtk_eth *hw; 969656e7052SJohn Crispin struct mtk_hw_stats *hw_stats; 970ee406810SNelson Chang __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; 971ee406810SNelson Chang int hwlro_ip_cnt; 972656e7052SJohn Crispin }; 973656e7052SJohn Crispin 974656e7052SJohn Crispin /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 975656e7052SJohn Crispin extern const struct of_device_id of_mtk_match[]; 976656e7052SJohn Crispin 977656e7052SJohn Crispin /* read the hardware status register */ 978656e7052SJohn Crispin void mtk_stats_update_mac(struct mtk_mac *mac); 979656e7052SJohn Crispin 980656e7052SJohn Crispin void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 981656e7052SJohn Crispin u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 982656e7052SJohn Crispin 9839ffee4a8SSean Wang int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, 9849ffee4a8SSean Wang u32 ana_rgc3); 9859ffee4a8SSean Wang int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); 9867e538372SRené van Dorst int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, 9877e538372SRené van Dorst const struct phylink_link_state *state); 9887e538372SRené van Dorst void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); 9897e538372SRené van Dorst 9907e538372SRené van Dorst int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 9917e538372SRené van Dorst int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); 9927e538372SRené van Dorst int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); 9939ffee4a8SSean Wang 994502e84e2SFelix Fietkau int mtk_eth_offload_init(struct mtk_eth *eth); 995502e84e2SFelix Fietkau int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, 996502e84e2SFelix Fietkau void *type_data); 997502e84e2SFelix Fietkau 998502e84e2SFelix Fietkau 999656e7052SJohn Crispin #endif /* MTK_ETH_H */ 1000