1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/regmap.h> 15 #include <linux/clk.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/if_vlan.h> 18 #include <linux/reset.h> 19 #include <linux/tcp.h> 20 #include <linux/interrupt.h> 21 #include <linux/pinctrl/devinfo.h> 22 #include <linux/phylink.h> 23 #include <linux/jhash.h> 24 #include <linux/bitfield.h> 25 #include <net/dsa.h> 26 27 #include "mtk_eth_soc.h" 28 #include "mtk_wed.h" 29 30 static int mtk_msg_level = -1; 31 module_param_named(msg_level, mtk_msg_level, int, 0); 32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 33 34 #define MTK_ETHTOOL_STAT(x) { #x, \ 35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 36 37 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 38 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 39 sizeof(u64) } 40 41 static const struct mtk_reg_map mtk_reg_map = { 42 .tx_irq_mask = 0x1a1c, 43 .tx_irq_status = 0x1a18, 44 .pdma = { 45 .rx_ptr = 0x0900, 46 .rx_cnt_cfg = 0x0904, 47 .pcrx_ptr = 0x0908, 48 .glo_cfg = 0x0a04, 49 .rst_idx = 0x0a08, 50 .delay_irq = 0x0a0c, 51 .irq_status = 0x0a20, 52 .irq_mask = 0x0a28, 53 .int_grp = 0x0a50, 54 }, 55 .qdma = { 56 .qtx_cfg = 0x1800, 57 .rx_ptr = 0x1900, 58 .rx_cnt_cfg = 0x1904, 59 .qcrx_ptr = 0x1908, 60 .glo_cfg = 0x1a04, 61 .rst_idx = 0x1a08, 62 .delay_irq = 0x1a0c, 63 .fc_th = 0x1a10, 64 .int_grp = 0x1a20, 65 .hred = 0x1a44, 66 .ctx_ptr = 0x1b00, 67 .dtx_ptr = 0x1b04, 68 .crx_ptr = 0x1b10, 69 .drx_ptr = 0x1b14, 70 .fq_head = 0x1b20, 71 .fq_tail = 0x1b24, 72 .fq_count = 0x1b28, 73 .fq_blen = 0x1b2c, 74 }, 75 .gdm1_cnt = 0x2400, 76 .gdma_to_ppe = 0x4444, 77 .ppe_base = 0x0c00, 78 .wdma_base = { 79 [0] = 0x2800, 80 [1] = 0x2c00, 81 }, 82 }; 83 84 static const struct mtk_reg_map mt7628_reg_map = { 85 .tx_irq_mask = 0x0a28, 86 .tx_irq_status = 0x0a20, 87 .pdma = { 88 .rx_ptr = 0x0900, 89 .rx_cnt_cfg = 0x0904, 90 .pcrx_ptr = 0x0908, 91 .glo_cfg = 0x0a04, 92 .rst_idx = 0x0a08, 93 .delay_irq = 0x0a0c, 94 .irq_status = 0x0a20, 95 .irq_mask = 0x0a28, 96 .int_grp = 0x0a50, 97 }, 98 }; 99 100 static const struct mtk_reg_map mt7986_reg_map = { 101 .tx_irq_mask = 0x461c, 102 .tx_irq_status = 0x4618, 103 .pdma = { 104 .rx_ptr = 0x6100, 105 .rx_cnt_cfg = 0x6104, 106 .pcrx_ptr = 0x6108, 107 .glo_cfg = 0x6204, 108 .rst_idx = 0x6208, 109 .delay_irq = 0x620c, 110 .irq_status = 0x6220, 111 .irq_mask = 0x6228, 112 .int_grp = 0x6250, 113 }, 114 .qdma = { 115 .qtx_cfg = 0x4400, 116 .rx_ptr = 0x4500, 117 .rx_cnt_cfg = 0x4504, 118 .qcrx_ptr = 0x4508, 119 .glo_cfg = 0x4604, 120 .rst_idx = 0x4608, 121 .delay_irq = 0x460c, 122 .fc_th = 0x4610, 123 .int_grp = 0x4620, 124 .hred = 0x4644, 125 .ctx_ptr = 0x4700, 126 .dtx_ptr = 0x4704, 127 .crx_ptr = 0x4710, 128 .drx_ptr = 0x4714, 129 .fq_head = 0x4720, 130 .fq_tail = 0x4724, 131 .fq_count = 0x4728, 132 .fq_blen = 0x472c, 133 }, 134 .gdm1_cnt = 0x1c00, 135 .gdma_to_ppe = 0x3333, 136 .ppe_base = 0x2000, 137 .wdma_base = { 138 [0] = 0x4800, 139 [1] = 0x4c00, 140 }, 141 }; 142 143 /* strings used by ethtool */ 144 static const struct mtk_ethtool_stats { 145 char str[ETH_GSTRING_LEN]; 146 u32 offset; 147 } mtk_ethtool_stats[] = { 148 MTK_ETHTOOL_STAT(tx_bytes), 149 MTK_ETHTOOL_STAT(tx_packets), 150 MTK_ETHTOOL_STAT(tx_skip), 151 MTK_ETHTOOL_STAT(tx_collisions), 152 MTK_ETHTOOL_STAT(rx_bytes), 153 MTK_ETHTOOL_STAT(rx_packets), 154 MTK_ETHTOOL_STAT(rx_overflow), 155 MTK_ETHTOOL_STAT(rx_fcs_errors), 156 MTK_ETHTOOL_STAT(rx_short_errors), 157 MTK_ETHTOOL_STAT(rx_long_errors), 158 MTK_ETHTOOL_STAT(rx_checksum_errors), 159 MTK_ETHTOOL_STAT(rx_flow_control_packets), 160 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 161 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 162 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 163 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 164 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 165 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 166 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 167 }; 168 169 static const char * const mtk_clks_source_name[] = { 170 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 171 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 172 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 173 "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" 174 }; 175 176 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 177 { 178 __raw_writel(val, eth->base + reg); 179 } 180 181 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 182 { 183 return __raw_readl(eth->base + reg); 184 } 185 186 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 187 { 188 u32 val; 189 190 val = mtk_r32(eth, reg); 191 val &= ~mask; 192 val |= set; 193 mtk_w32(eth, val, reg); 194 return reg; 195 } 196 197 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 198 { 199 unsigned long t_start = jiffies; 200 201 while (1) { 202 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 203 return 0; 204 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 205 break; 206 cond_resched(); 207 } 208 209 dev_err(eth->dev, "mdio: MDIO timeout\n"); 210 return -ETIMEDOUT; 211 } 212 213 static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 214 u32 write_data) 215 { 216 int ret; 217 218 ret = mtk_mdio_busy_wait(eth); 219 if (ret < 0) 220 return ret; 221 222 if (phy_reg & MII_ADDR_C45) { 223 mtk_w32(eth, PHY_IAC_ACCESS | 224 PHY_IAC_START_C45 | 225 PHY_IAC_CMD_C45_ADDR | 226 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 227 PHY_IAC_ADDR(phy_addr) | 228 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 229 MTK_PHY_IAC); 230 231 ret = mtk_mdio_busy_wait(eth); 232 if (ret < 0) 233 return ret; 234 235 mtk_w32(eth, PHY_IAC_ACCESS | 236 PHY_IAC_START_C45 | 237 PHY_IAC_CMD_WRITE | 238 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 239 PHY_IAC_ADDR(phy_addr) | 240 PHY_IAC_DATA(write_data), 241 MTK_PHY_IAC); 242 } else { 243 mtk_w32(eth, PHY_IAC_ACCESS | 244 PHY_IAC_START_C22 | 245 PHY_IAC_CMD_WRITE | 246 PHY_IAC_REG(phy_reg) | 247 PHY_IAC_ADDR(phy_addr) | 248 PHY_IAC_DATA(write_data), 249 MTK_PHY_IAC); 250 } 251 252 ret = mtk_mdio_busy_wait(eth); 253 if (ret < 0) 254 return ret; 255 256 return 0; 257 } 258 259 static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 260 { 261 int ret; 262 263 ret = mtk_mdio_busy_wait(eth); 264 if (ret < 0) 265 return ret; 266 267 if (phy_reg & MII_ADDR_C45) { 268 mtk_w32(eth, PHY_IAC_ACCESS | 269 PHY_IAC_START_C45 | 270 PHY_IAC_CMD_C45_ADDR | 271 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 272 PHY_IAC_ADDR(phy_addr) | 273 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 274 MTK_PHY_IAC); 275 276 ret = mtk_mdio_busy_wait(eth); 277 if (ret < 0) 278 return ret; 279 280 mtk_w32(eth, PHY_IAC_ACCESS | 281 PHY_IAC_START_C45 | 282 PHY_IAC_CMD_C45_READ | 283 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 284 PHY_IAC_ADDR(phy_addr), 285 MTK_PHY_IAC); 286 } else { 287 mtk_w32(eth, PHY_IAC_ACCESS | 288 PHY_IAC_START_C22 | 289 PHY_IAC_CMD_C22_READ | 290 PHY_IAC_REG(phy_reg) | 291 PHY_IAC_ADDR(phy_addr), 292 MTK_PHY_IAC); 293 } 294 295 ret = mtk_mdio_busy_wait(eth); 296 if (ret < 0) 297 return ret; 298 299 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 300 } 301 302 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 303 int phy_reg, u16 val) 304 { 305 struct mtk_eth *eth = bus->priv; 306 307 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 308 } 309 310 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 311 { 312 struct mtk_eth *eth = bus->priv; 313 314 return _mtk_mdio_read(eth, phy_addr, phy_reg); 315 } 316 317 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 318 phy_interface_t interface) 319 { 320 u32 val; 321 322 /* Check DDR memory type. 323 * Currently TRGMII mode with DDR2 memory is not supported. 324 */ 325 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 326 if (interface == PHY_INTERFACE_MODE_TRGMII && 327 val & SYSCFG_DRAM_TYPE_DDR2) { 328 dev_err(eth->dev, 329 "TRGMII mode with DDR2 memory is not supported!\n"); 330 return -EOPNOTSUPP; 331 } 332 333 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 334 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 335 336 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 337 ETHSYS_TRGMII_MT7621_MASK, val); 338 339 return 0; 340 } 341 342 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 343 phy_interface_t interface, int speed) 344 { 345 u32 val; 346 int ret; 347 348 if (interface == PHY_INTERFACE_MODE_TRGMII) { 349 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 350 val = 500000000; 351 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 352 if (ret) 353 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 354 return; 355 } 356 357 val = (speed == SPEED_1000) ? 358 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 359 mtk_w32(eth, val, INTF_MODE); 360 361 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 362 ETHSYS_TRGMII_CLK_SEL362_5, 363 ETHSYS_TRGMII_CLK_SEL362_5); 364 365 val = (speed == SPEED_1000) ? 250000000 : 500000000; 366 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 367 if (ret) 368 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 369 370 val = (speed == SPEED_1000) ? 371 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 372 mtk_w32(eth, val, TRGMII_RCK_CTRL); 373 374 val = (speed == SPEED_1000) ? 375 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 376 mtk_w32(eth, val, TRGMII_TCK_CTRL); 377 } 378 379 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 380 phy_interface_t interface) 381 { 382 struct mtk_mac *mac = container_of(config, struct mtk_mac, 383 phylink_config); 384 struct mtk_eth *eth = mac->hw; 385 unsigned int sid; 386 387 if (interface == PHY_INTERFACE_MODE_SGMII || 388 phy_interface_mode_is_8023z(interface)) { 389 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 390 0 : mac->id; 391 392 return mtk_sgmii_select_pcs(eth->sgmii, sid); 393 } 394 395 return NULL; 396 } 397 398 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 399 const struct phylink_link_state *state) 400 { 401 struct mtk_mac *mac = container_of(config, struct mtk_mac, 402 phylink_config); 403 struct mtk_eth *eth = mac->hw; 404 int val, ge_mode, err = 0; 405 u32 i; 406 407 /* MT76x8 has no hardware settings between for the MAC */ 408 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 409 mac->interface != state->interface) { 410 /* Setup soc pin functions */ 411 switch (state->interface) { 412 case PHY_INTERFACE_MODE_TRGMII: 413 if (mac->id) 414 goto err_phy; 415 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 416 MTK_GMAC1_TRGMII)) 417 goto err_phy; 418 fallthrough; 419 case PHY_INTERFACE_MODE_RGMII_TXID: 420 case PHY_INTERFACE_MODE_RGMII_RXID: 421 case PHY_INTERFACE_MODE_RGMII_ID: 422 case PHY_INTERFACE_MODE_RGMII: 423 case PHY_INTERFACE_MODE_MII: 424 case PHY_INTERFACE_MODE_REVMII: 425 case PHY_INTERFACE_MODE_RMII: 426 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 427 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 428 if (err) 429 goto init_err; 430 } 431 break; 432 case PHY_INTERFACE_MODE_1000BASEX: 433 case PHY_INTERFACE_MODE_2500BASEX: 434 case PHY_INTERFACE_MODE_SGMII: 435 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 436 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 437 if (err) 438 goto init_err; 439 } 440 break; 441 case PHY_INTERFACE_MODE_GMII: 442 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 443 err = mtk_gmac_gephy_path_setup(eth, mac->id); 444 if (err) 445 goto init_err; 446 } 447 break; 448 default: 449 goto err_phy; 450 } 451 452 /* Setup clock for 1st gmac */ 453 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 454 !phy_interface_mode_is_8023z(state->interface) && 455 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 456 if (MTK_HAS_CAPS(mac->hw->soc->caps, 457 MTK_TRGMII_MT7621_CLK)) { 458 if (mt7621_gmac0_rgmii_adjust(mac->hw, 459 state->interface)) 460 goto err_phy; 461 } else { 462 /* FIXME: this is incorrect. Not only does it 463 * use state->speed (which is not guaranteed 464 * to be correct) but it also makes use of it 465 * in a code path that will only be reachable 466 * when the PHY interface mode changes, not 467 * when the speed changes. Consequently, RGMII 468 * is probably broken. 469 */ 470 mtk_gmac0_rgmii_adjust(mac->hw, 471 state->interface, 472 state->speed); 473 474 /* mt7623_pad_clk_setup */ 475 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 476 mtk_w32(mac->hw, 477 TD_DM_DRVP(8) | TD_DM_DRVN(8), 478 TRGMII_TD_ODT(i)); 479 480 /* Assert/release MT7623 RXC reset */ 481 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 482 TRGMII_RCK_CTRL); 483 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 484 } 485 } 486 487 ge_mode = 0; 488 switch (state->interface) { 489 case PHY_INTERFACE_MODE_MII: 490 case PHY_INTERFACE_MODE_GMII: 491 ge_mode = 1; 492 break; 493 case PHY_INTERFACE_MODE_REVMII: 494 ge_mode = 2; 495 break; 496 case PHY_INTERFACE_MODE_RMII: 497 if (mac->id) 498 goto err_phy; 499 ge_mode = 3; 500 break; 501 default: 502 break; 503 } 504 505 /* put the gmac into the right mode */ 506 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 507 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 508 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 509 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 510 511 mac->interface = state->interface; 512 } 513 514 /* SGMII */ 515 if (state->interface == PHY_INTERFACE_MODE_SGMII || 516 phy_interface_mode_is_8023z(state->interface)) { 517 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 518 * being setup done. 519 */ 520 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 521 522 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 523 SYSCFG0_SGMII_MASK, 524 ~(u32)SYSCFG0_SGMII_MASK); 525 526 /* Save the syscfg0 value for mac_finish */ 527 mac->syscfg0 = val; 528 } else if (phylink_autoneg_inband(mode)) { 529 dev_err(eth->dev, 530 "In-band mode not supported in non SGMII mode!\n"); 531 return; 532 } 533 534 return; 535 536 err_phy: 537 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 538 mac->id, phy_modes(state->interface)); 539 return; 540 541 init_err: 542 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 543 mac->id, phy_modes(state->interface), err); 544 } 545 546 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 547 phy_interface_t interface) 548 { 549 struct mtk_mac *mac = container_of(config, struct mtk_mac, 550 phylink_config); 551 struct mtk_eth *eth = mac->hw; 552 u32 mcr_cur, mcr_new; 553 554 /* Enable SGMII */ 555 if (interface == PHY_INTERFACE_MODE_SGMII || 556 phy_interface_mode_is_8023z(interface)) 557 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 558 SYSCFG0_SGMII_MASK, mac->syscfg0); 559 560 /* Setup gmac */ 561 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 562 mcr_new = mcr_cur; 563 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 564 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; 565 566 /* Only update control register when needed! */ 567 if (mcr_new != mcr_cur) 568 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 569 570 return 0; 571 } 572 573 static void mtk_mac_pcs_get_state(struct phylink_config *config, 574 struct phylink_link_state *state) 575 { 576 struct mtk_mac *mac = container_of(config, struct mtk_mac, 577 phylink_config); 578 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 579 580 state->link = (pmsr & MAC_MSR_LINK); 581 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 582 583 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 584 case 0: 585 state->speed = SPEED_10; 586 break; 587 case MAC_MSR_SPEED_100: 588 state->speed = SPEED_100; 589 break; 590 case MAC_MSR_SPEED_1000: 591 state->speed = SPEED_1000; 592 break; 593 default: 594 state->speed = SPEED_UNKNOWN; 595 break; 596 } 597 598 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 599 if (pmsr & MAC_MSR_RX_FC) 600 state->pause |= MLO_PAUSE_RX; 601 if (pmsr & MAC_MSR_TX_FC) 602 state->pause |= MLO_PAUSE_TX; 603 } 604 605 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 606 phy_interface_t interface) 607 { 608 struct mtk_mac *mac = container_of(config, struct mtk_mac, 609 phylink_config); 610 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 611 612 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 613 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 614 } 615 616 static void mtk_mac_link_up(struct phylink_config *config, 617 struct phy_device *phy, 618 unsigned int mode, phy_interface_t interface, 619 int speed, int duplex, bool tx_pause, bool rx_pause) 620 { 621 struct mtk_mac *mac = container_of(config, struct mtk_mac, 622 phylink_config); 623 u32 mcr; 624 625 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 626 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 627 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 628 MAC_MCR_FORCE_RX_FC); 629 630 /* Configure speed */ 631 switch (speed) { 632 case SPEED_2500: 633 case SPEED_1000: 634 mcr |= MAC_MCR_SPEED_1000; 635 break; 636 case SPEED_100: 637 mcr |= MAC_MCR_SPEED_100; 638 break; 639 } 640 641 /* Configure duplex */ 642 if (duplex == DUPLEX_FULL) 643 mcr |= MAC_MCR_FORCE_DPX; 644 645 /* Configure pause modes - phylink will avoid these for half duplex */ 646 if (tx_pause) 647 mcr |= MAC_MCR_FORCE_TX_FC; 648 if (rx_pause) 649 mcr |= MAC_MCR_FORCE_RX_FC; 650 651 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 652 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 653 } 654 655 static const struct phylink_mac_ops mtk_phylink_ops = { 656 .mac_select_pcs = mtk_mac_select_pcs, 657 .mac_pcs_get_state = mtk_mac_pcs_get_state, 658 .mac_config = mtk_mac_config, 659 .mac_finish = mtk_mac_finish, 660 .mac_link_down = mtk_mac_link_down, 661 .mac_link_up = mtk_mac_link_up, 662 }; 663 664 static int mtk_mdio_init(struct mtk_eth *eth) 665 { 666 struct device_node *mii_np; 667 int ret; 668 669 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 670 if (!mii_np) { 671 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 672 return -ENODEV; 673 } 674 675 if (!of_device_is_available(mii_np)) { 676 ret = -ENODEV; 677 goto err_put_node; 678 } 679 680 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 681 if (!eth->mii_bus) { 682 ret = -ENOMEM; 683 goto err_put_node; 684 } 685 686 eth->mii_bus->name = "mdio"; 687 eth->mii_bus->read = mtk_mdio_read; 688 eth->mii_bus->write = mtk_mdio_write; 689 eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; 690 eth->mii_bus->priv = eth; 691 eth->mii_bus->parent = eth->dev; 692 693 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 694 ret = of_mdiobus_register(eth->mii_bus, mii_np); 695 696 err_put_node: 697 of_node_put(mii_np); 698 return ret; 699 } 700 701 static void mtk_mdio_cleanup(struct mtk_eth *eth) 702 { 703 if (!eth->mii_bus) 704 return; 705 706 mdiobus_unregister(eth->mii_bus); 707 } 708 709 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 710 { 711 unsigned long flags; 712 u32 val; 713 714 spin_lock_irqsave(ð->tx_irq_lock, flags); 715 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 716 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 717 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 718 } 719 720 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 721 { 722 unsigned long flags; 723 u32 val; 724 725 spin_lock_irqsave(ð->tx_irq_lock, flags); 726 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 727 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 728 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 729 } 730 731 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 732 { 733 unsigned long flags; 734 u32 val; 735 736 spin_lock_irqsave(ð->rx_irq_lock, flags); 737 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 738 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 739 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 740 } 741 742 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 743 { 744 unsigned long flags; 745 u32 val; 746 747 spin_lock_irqsave(ð->rx_irq_lock, flags); 748 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 749 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 750 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 751 } 752 753 static int mtk_set_mac_address(struct net_device *dev, void *p) 754 { 755 int ret = eth_mac_addr(dev, p); 756 struct mtk_mac *mac = netdev_priv(dev); 757 struct mtk_eth *eth = mac->hw; 758 const char *macaddr = dev->dev_addr; 759 760 if (ret) 761 return ret; 762 763 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 764 return -EBUSY; 765 766 spin_lock_bh(&mac->hw->page_lock); 767 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 768 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 769 MT7628_SDM_MAC_ADRH); 770 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 771 (macaddr[4] << 8) | macaddr[5], 772 MT7628_SDM_MAC_ADRL); 773 } else { 774 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 775 MTK_GDMA_MAC_ADRH(mac->id)); 776 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 777 (macaddr[4] << 8) | macaddr[5], 778 MTK_GDMA_MAC_ADRL(mac->id)); 779 } 780 spin_unlock_bh(&mac->hw->page_lock); 781 782 return 0; 783 } 784 785 void mtk_stats_update_mac(struct mtk_mac *mac) 786 { 787 struct mtk_hw_stats *hw_stats = mac->hw_stats; 788 struct mtk_eth *eth = mac->hw; 789 790 u64_stats_update_begin(&hw_stats->syncp); 791 792 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 793 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 794 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 795 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 796 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 797 hw_stats->rx_checksum_errors += 798 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 799 } else { 800 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 801 unsigned int offs = hw_stats->reg_offset; 802 u64 stats; 803 804 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 805 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 806 if (stats) 807 hw_stats->rx_bytes += (stats << 32); 808 hw_stats->rx_packets += 809 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 810 hw_stats->rx_overflow += 811 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 812 hw_stats->rx_fcs_errors += 813 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 814 hw_stats->rx_short_errors += 815 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 816 hw_stats->rx_long_errors += 817 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 818 hw_stats->rx_checksum_errors += 819 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 820 hw_stats->rx_flow_control_packets += 821 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 822 hw_stats->tx_skip += 823 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 824 hw_stats->tx_collisions += 825 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 826 hw_stats->tx_bytes += 827 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 828 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 829 if (stats) 830 hw_stats->tx_bytes += (stats << 32); 831 hw_stats->tx_packets += 832 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 833 } 834 835 u64_stats_update_end(&hw_stats->syncp); 836 } 837 838 static void mtk_stats_update(struct mtk_eth *eth) 839 { 840 int i; 841 842 for (i = 0; i < MTK_MAC_COUNT; i++) { 843 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 844 continue; 845 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 846 mtk_stats_update_mac(eth->mac[i]); 847 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 848 } 849 } 850 } 851 852 static void mtk_get_stats64(struct net_device *dev, 853 struct rtnl_link_stats64 *storage) 854 { 855 struct mtk_mac *mac = netdev_priv(dev); 856 struct mtk_hw_stats *hw_stats = mac->hw_stats; 857 unsigned int start; 858 859 if (netif_running(dev) && netif_device_present(dev)) { 860 if (spin_trylock_bh(&hw_stats->stats_lock)) { 861 mtk_stats_update_mac(mac); 862 spin_unlock_bh(&hw_stats->stats_lock); 863 } 864 } 865 866 do { 867 start = u64_stats_fetch_begin(&hw_stats->syncp); 868 storage->rx_packets = hw_stats->rx_packets; 869 storage->tx_packets = hw_stats->tx_packets; 870 storage->rx_bytes = hw_stats->rx_bytes; 871 storage->tx_bytes = hw_stats->tx_bytes; 872 storage->collisions = hw_stats->tx_collisions; 873 storage->rx_length_errors = hw_stats->rx_short_errors + 874 hw_stats->rx_long_errors; 875 storage->rx_over_errors = hw_stats->rx_overflow; 876 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 877 storage->rx_errors = hw_stats->rx_checksum_errors; 878 storage->tx_aborted_errors = hw_stats->tx_skip; 879 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 880 881 storage->tx_errors = dev->stats.tx_errors; 882 storage->rx_dropped = dev->stats.rx_dropped; 883 storage->tx_dropped = dev->stats.tx_dropped; 884 } 885 886 static inline int mtk_max_frag_size(int mtu) 887 { 888 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 889 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 890 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 891 892 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 893 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 894 } 895 896 static inline int mtk_max_buf_size(int frag_size) 897 { 898 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 899 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 900 901 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 902 903 return buf_size; 904 } 905 906 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 907 struct mtk_rx_dma_v2 *dma_rxd) 908 { 909 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 910 if (!(rxd->rxd2 & RX_DMA_DONE)) 911 return false; 912 913 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 914 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 915 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 916 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 917 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 918 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 919 } 920 921 return true; 922 } 923 924 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 925 { 926 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 927 unsigned long data; 928 929 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 930 get_order(size)); 931 932 return (void *)data; 933 } 934 935 /* the qdma core needs scratch memory to be setup */ 936 static int mtk_init_fq_dma(struct mtk_eth *eth) 937 { 938 const struct mtk_soc_data *soc = eth->soc; 939 dma_addr_t phy_ring_tail; 940 int cnt = MTK_DMA_SIZE; 941 dma_addr_t dma_addr; 942 int i; 943 944 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 945 cnt * soc->txrx.txd_size, 946 ð->phy_scratch_ring, 947 GFP_KERNEL); 948 if (unlikely(!eth->scratch_ring)) 949 return -ENOMEM; 950 951 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 952 if (unlikely(!eth->scratch_head)) 953 return -ENOMEM; 954 955 dma_addr = dma_map_single(eth->dma_dev, 956 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 957 DMA_FROM_DEVICE); 958 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 959 return -ENOMEM; 960 961 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); 962 963 for (i = 0; i < cnt; i++) { 964 struct mtk_tx_dma_v2 *txd; 965 966 txd = eth->scratch_ring + i * soc->txrx.txd_size; 967 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 968 if (i < cnt - 1) 969 txd->txd2 = eth->phy_scratch_ring + 970 (i + 1) * soc->txrx.txd_size; 971 972 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 973 txd->txd4 = 0; 974 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 975 txd->txd5 = 0; 976 txd->txd6 = 0; 977 txd->txd7 = 0; 978 txd->txd8 = 0; 979 } 980 } 981 982 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 983 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 984 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 985 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 986 987 return 0; 988 } 989 990 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 991 { 992 return ring->dma + (desc - ring->phys); 993 } 994 995 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 996 void *txd, u32 txd_size) 997 { 998 int idx = (txd - ring->dma) / txd_size; 999 1000 return &ring->buf[idx]; 1001 } 1002 1003 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1004 struct mtk_tx_dma *dma) 1005 { 1006 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1007 } 1008 1009 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1010 { 1011 return (dma - ring->dma) / txd_size; 1012 } 1013 1014 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1015 struct xdp_frame_bulk *bq, bool napi) 1016 { 1017 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1018 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1019 dma_unmap_single(eth->dma_dev, 1020 dma_unmap_addr(tx_buf, dma_addr0), 1021 dma_unmap_len(tx_buf, dma_len0), 1022 DMA_TO_DEVICE); 1023 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1024 dma_unmap_page(eth->dma_dev, 1025 dma_unmap_addr(tx_buf, dma_addr0), 1026 dma_unmap_len(tx_buf, dma_len0), 1027 DMA_TO_DEVICE); 1028 } 1029 } else { 1030 if (dma_unmap_len(tx_buf, dma_len0)) { 1031 dma_unmap_page(eth->dma_dev, 1032 dma_unmap_addr(tx_buf, dma_addr0), 1033 dma_unmap_len(tx_buf, dma_len0), 1034 DMA_TO_DEVICE); 1035 } 1036 1037 if (dma_unmap_len(tx_buf, dma_len1)) { 1038 dma_unmap_page(eth->dma_dev, 1039 dma_unmap_addr(tx_buf, dma_addr1), 1040 dma_unmap_len(tx_buf, dma_len1), 1041 DMA_TO_DEVICE); 1042 } 1043 } 1044 1045 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1046 if (tx_buf->type == MTK_TYPE_SKB) { 1047 struct sk_buff *skb = tx_buf->data; 1048 1049 if (napi) 1050 napi_consume_skb(skb, napi); 1051 else 1052 dev_kfree_skb_any(skb); 1053 } else { 1054 struct xdp_frame *xdpf = tx_buf->data; 1055 1056 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1057 xdp_return_frame_rx_napi(xdpf); 1058 else if (bq) 1059 xdp_return_frame_bulk(xdpf, bq); 1060 else 1061 xdp_return_frame(xdpf); 1062 } 1063 } 1064 tx_buf->flags = 0; 1065 tx_buf->data = NULL; 1066 } 1067 1068 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1069 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1070 size_t size, int idx) 1071 { 1072 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1073 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1074 dma_unmap_len_set(tx_buf, dma_len0, size); 1075 } else { 1076 if (idx & 1) { 1077 txd->txd3 = mapped_addr; 1078 txd->txd2 |= TX_DMA_PLEN1(size); 1079 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1080 dma_unmap_len_set(tx_buf, dma_len1, size); 1081 } else { 1082 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1083 txd->txd1 = mapped_addr; 1084 txd->txd2 = TX_DMA_PLEN0(size); 1085 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1086 dma_unmap_len_set(tx_buf, dma_len0, size); 1087 } 1088 } 1089 } 1090 1091 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1092 struct mtk_tx_dma_desc_info *info) 1093 { 1094 struct mtk_mac *mac = netdev_priv(dev); 1095 struct mtk_eth *eth = mac->hw; 1096 struct mtk_tx_dma *desc = txd; 1097 u32 data; 1098 1099 WRITE_ONCE(desc->txd1, info->addr); 1100 1101 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size); 1102 if (info->last) 1103 data |= TX_DMA_LS0; 1104 WRITE_ONCE(desc->txd3, data); 1105 1106 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1107 if (info->first) { 1108 if (info->gso) 1109 data |= TX_DMA_TSO; 1110 /* tx checksum offload */ 1111 if (info->csum) 1112 data |= TX_DMA_CHKSUM; 1113 /* vlan header offload */ 1114 if (info->vlan) 1115 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1116 } 1117 WRITE_ONCE(desc->txd4, data); 1118 } 1119 1120 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1121 struct mtk_tx_dma_desc_info *info) 1122 { 1123 struct mtk_mac *mac = netdev_priv(dev); 1124 struct mtk_tx_dma_v2 *desc = txd; 1125 struct mtk_eth *eth = mac->hw; 1126 u32 data; 1127 1128 WRITE_ONCE(desc->txd1, info->addr); 1129 1130 data = TX_DMA_PLEN0(info->size); 1131 if (info->last) 1132 data |= TX_DMA_LS0; 1133 WRITE_ONCE(desc->txd3, data); 1134 1135 if (!info->qid && mac->id) 1136 info->qid = MTK_QDMA_GMAC2_QID; 1137 1138 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ 1139 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1140 WRITE_ONCE(desc->txd4, data); 1141 1142 data = 0; 1143 if (info->first) { 1144 if (info->gso) 1145 data |= TX_DMA_TSO_V2; 1146 /* tx checksum offload */ 1147 if (info->csum) 1148 data |= TX_DMA_CHKSUM_V2; 1149 } 1150 WRITE_ONCE(desc->txd5, data); 1151 1152 data = 0; 1153 if (info->first && info->vlan) 1154 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1155 WRITE_ONCE(desc->txd6, data); 1156 1157 WRITE_ONCE(desc->txd7, 0); 1158 WRITE_ONCE(desc->txd8, 0); 1159 } 1160 1161 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1162 struct mtk_tx_dma_desc_info *info) 1163 { 1164 struct mtk_mac *mac = netdev_priv(dev); 1165 struct mtk_eth *eth = mac->hw; 1166 1167 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1168 mtk_tx_set_dma_desc_v2(dev, txd, info); 1169 else 1170 mtk_tx_set_dma_desc_v1(dev, txd, info); 1171 } 1172 1173 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1174 int tx_num, struct mtk_tx_ring *ring, bool gso) 1175 { 1176 struct mtk_tx_dma_desc_info txd_info = { 1177 .size = skb_headlen(skb), 1178 .gso = gso, 1179 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1180 .vlan = skb_vlan_tag_present(skb), 1181 .qid = skb->mark & MTK_QDMA_TX_MASK, 1182 .vlan_tci = skb_vlan_tag_get(skb), 1183 .first = true, 1184 .last = !skb_is_nonlinear(skb), 1185 }; 1186 struct mtk_mac *mac = netdev_priv(dev); 1187 struct mtk_eth *eth = mac->hw; 1188 const struct mtk_soc_data *soc = eth->soc; 1189 struct mtk_tx_dma *itxd, *txd; 1190 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1191 struct mtk_tx_buf *itx_buf, *tx_buf; 1192 int i, n_desc = 1; 1193 int k = 0; 1194 1195 itxd = ring->next_free; 1196 itxd_pdma = qdma_to_pdma(ring, itxd); 1197 if (itxd == ring->last_free) 1198 return -ENOMEM; 1199 1200 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1201 memset(itx_buf, 0, sizeof(*itx_buf)); 1202 1203 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1204 DMA_TO_DEVICE); 1205 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1206 return -ENOMEM; 1207 1208 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1209 1210 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1211 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1212 MTK_TX_FLAGS_FPORT1; 1213 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1214 k++); 1215 1216 /* TX SG offload */ 1217 txd = itxd; 1218 txd_pdma = qdma_to_pdma(ring, txd); 1219 1220 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1221 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1222 unsigned int offset = 0; 1223 int frag_size = skb_frag_size(frag); 1224 1225 while (frag_size) { 1226 bool new_desc = true; 1227 1228 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1229 (i & 0x1)) { 1230 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1231 txd_pdma = qdma_to_pdma(ring, txd); 1232 if (txd == ring->last_free) 1233 goto err_dma; 1234 1235 n_desc++; 1236 } else { 1237 new_desc = false; 1238 } 1239 1240 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1241 txd_info.size = min_t(unsigned int, frag_size, 1242 soc->txrx.dma_max_len); 1243 txd_info.qid = skb->mark & MTK_QDMA_TX_MASK; 1244 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1245 !(frag_size - txd_info.size); 1246 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1247 offset, txd_info.size, 1248 DMA_TO_DEVICE); 1249 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1250 goto err_dma; 1251 1252 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1253 1254 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1255 soc->txrx.txd_size); 1256 if (new_desc) 1257 memset(tx_buf, 0, sizeof(*tx_buf)); 1258 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1259 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1260 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1261 MTK_TX_FLAGS_FPORT1; 1262 1263 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1264 txd_info.size, k++); 1265 1266 frag_size -= txd_info.size; 1267 offset += txd_info.size; 1268 } 1269 } 1270 1271 /* store skb to cleanup */ 1272 itx_buf->type = MTK_TYPE_SKB; 1273 itx_buf->data = skb; 1274 1275 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1276 if (k & 0x1) 1277 txd_pdma->txd2 |= TX_DMA_LS0; 1278 else 1279 txd_pdma->txd2 |= TX_DMA_LS1; 1280 } 1281 1282 netdev_sent_queue(dev, skb->len); 1283 skb_tx_timestamp(skb); 1284 1285 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1286 atomic_sub(n_desc, &ring->free_count); 1287 1288 /* make sure that all changes to the dma ring are flushed before we 1289 * continue 1290 */ 1291 wmb(); 1292 1293 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1294 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 1295 !netdev_xmit_more()) 1296 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1297 } else { 1298 int next_idx; 1299 1300 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), 1301 ring->dma_size); 1302 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1303 } 1304 1305 return 0; 1306 1307 err_dma: 1308 do { 1309 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1310 1311 /* unmap dma */ 1312 mtk_tx_unmap(eth, tx_buf, NULL, false); 1313 1314 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1315 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1316 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1317 1318 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1319 itxd_pdma = qdma_to_pdma(ring, itxd); 1320 } while (itxd != txd); 1321 1322 return -ENOMEM; 1323 } 1324 1325 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1326 { 1327 int i, nfrags = 1; 1328 skb_frag_t *frag; 1329 1330 if (skb_is_gso(skb)) { 1331 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1332 frag = &skb_shinfo(skb)->frags[i]; 1333 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1334 eth->soc->txrx.dma_max_len); 1335 } 1336 } else { 1337 nfrags += skb_shinfo(skb)->nr_frags; 1338 } 1339 1340 return nfrags; 1341 } 1342 1343 static int mtk_queue_stopped(struct mtk_eth *eth) 1344 { 1345 int i; 1346 1347 for (i = 0; i < MTK_MAC_COUNT; i++) { 1348 if (!eth->netdev[i]) 1349 continue; 1350 if (netif_queue_stopped(eth->netdev[i])) 1351 return 1; 1352 } 1353 1354 return 0; 1355 } 1356 1357 static void mtk_wake_queue(struct mtk_eth *eth) 1358 { 1359 int i; 1360 1361 for (i = 0; i < MTK_MAC_COUNT; i++) { 1362 if (!eth->netdev[i]) 1363 continue; 1364 netif_wake_queue(eth->netdev[i]); 1365 } 1366 } 1367 1368 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1369 { 1370 struct mtk_mac *mac = netdev_priv(dev); 1371 struct mtk_eth *eth = mac->hw; 1372 struct mtk_tx_ring *ring = ð->tx_ring; 1373 struct net_device_stats *stats = &dev->stats; 1374 bool gso = false; 1375 int tx_num; 1376 1377 /* normally we can rely on the stack not calling this more than once, 1378 * however we have 2 queues running on the same ring so we need to lock 1379 * the ring access 1380 */ 1381 spin_lock(ð->page_lock); 1382 1383 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1384 goto drop; 1385 1386 tx_num = mtk_cal_txd_req(eth, skb); 1387 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1388 netif_stop_queue(dev); 1389 netif_err(eth, tx_queued, dev, 1390 "Tx Ring full when queue awake!\n"); 1391 spin_unlock(ð->page_lock); 1392 return NETDEV_TX_BUSY; 1393 } 1394 1395 /* TSO: fill MSS info in tcp checksum field */ 1396 if (skb_is_gso(skb)) { 1397 if (skb_cow_head(skb, 0)) { 1398 netif_warn(eth, tx_err, dev, 1399 "GSO expand head fail.\n"); 1400 goto drop; 1401 } 1402 1403 if (skb_shinfo(skb)->gso_type & 1404 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1405 gso = true; 1406 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1407 } 1408 } 1409 1410 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1411 goto drop; 1412 1413 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1414 netif_stop_queue(dev); 1415 1416 spin_unlock(ð->page_lock); 1417 1418 return NETDEV_TX_OK; 1419 1420 drop: 1421 spin_unlock(ð->page_lock); 1422 stats->tx_dropped++; 1423 dev_kfree_skb_any(skb); 1424 return NETDEV_TX_OK; 1425 } 1426 1427 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1428 { 1429 int i; 1430 struct mtk_rx_ring *ring; 1431 int idx; 1432 1433 if (!eth->hwlro) 1434 return ð->rx_ring[0]; 1435 1436 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1437 struct mtk_rx_dma *rxd; 1438 1439 ring = ð->rx_ring[i]; 1440 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1441 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1442 if (rxd->rxd2 & RX_DMA_DONE) { 1443 ring->calc_idx_update = true; 1444 return ring; 1445 } 1446 } 1447 1448 return NULL; 1449 } 1450 1451 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1452 { 1453 struct mtk_rx_ring *ring; 1454 int i; 1455 1456 if (!eth->hwlro) { 1457 ring = ð->rx_ring[0]; 1458 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1459 } else { 1460 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1461 ring = ð->rx_ring[i]; 1462 if (ring->calc_idx_update) { 1463 ring->calc_idx_update = false; 1464 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1465 } 1466 } 1467 } 1468 } 1469 1470 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1471 { 1472 return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2); 1473 } 1474 1475 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1476 struct xdp_rxq_info *xdp_q, 1477 int id, int size) 1478 { 1479 struct page_pool_params pp_params = { 1480 .order = 0, 1481 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1482 .pool_size = size, 1483 .nid = NUMA_NO_NODE, 1484 .dev = eth->dma_dev, 1485 .offset = MTK_PP_HEADROOM, 1486 .max_len = MTK_PP_MAX_BUF_SIZE, 1487 }; 1488 struct page_pool *pp; 1489 int err; 1490 1491 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1492 : DMA_FROM_DEVICE; 1493 pp = page_pool_create(&pp_params); 1494 if (IS_ERR(pp)) 1495 return pp; 1496 1497 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, eth->rx_napi.napi_id, 1498 id, PAGE_SIZE); 1499 if (err < 0) 1500 goto err_free_pp; 1501 1502 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1503 if (err) 1504 goto err_unregister_rxq; 1505 1506 return pp; 1507 1508 err_unregister_rxq: 1509 xdp_rxq_info_unreg(xdp_q); 1510 err_free_pp: 1511 page_pool_destroy(pp); 1512 1513 return ERR_PTR(err); 1514 } 1515 1516 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1517 gfp_t gfp_mask) 1518 { 1519 struct page *page; 1520 1521 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1522 if (!page) 1523 return NULL; 1524 1525 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1526 return page_address(page); 1527 } 1528 1529 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1530 { 1531 if (ring->page_pool) 1532 page_pool_put_full_page(ring->page_pool, 1533 virt_to_head_page(data), napi); 1534 else 1535 skb_free_frag(data); 1536 } 1537 1538 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1539 struct mtk_tx_dma_desc_info *txd_info, 1540 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1541 void *data, u16 headroom, int index, bool dma_map) 1542 { 1543 struct mtk_tx_ring *ring = ð->tx_ring; 1544 struct mtk_mac *mac = netdev_priv(dev); 1545 struct mtk_tx_dma *txd_pdma; 1546 1547 if (dma_map) { /* ndo_xdp_xmit */ 1548 txd_info->addr = dma_map_single(eth->dma_dev, data, 1549 txd_info->size, DMA_TO_DEVICE); 1550 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1551 return -ENOMEM; 1552 1553 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1554 } else { 1555 struct page *page = virt_to_head_page(data); 1556 1557 txd_info->addr = page_pool_get_dma_addr(page) + 1558 sizeof(struct xdp_frame) + headroom; 1559 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1560 txd_info->size, DMA_BIDIRECTIONAL); 1561 } 1562 mtk_tx_set_dma_desc(dev, txd, txd_info); 1563 1564 tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; 1565 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1566 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1567 1568 txd_pdma = qdma_to_pdma(ring, txd); 1569 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1570 index); 1571 1572 return 0; 1573 } 1574 1575 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1576 struct net_device *dev, bool dma_map) 1577 { 1578 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1579 const struct mtk_soc_data *soc = eth->soc; 1580 struct mtk_tx_ring *ring = ð->tx_ring; 1581 struct mtk_tx_dma_desc_info txd_info = { 1582 .size = xdpf->len, 1583 .first = true, 1584 .last = !xdp_frame_has_frags(xdpf), 1585 }; 1586 int err, index = 0, n_desc = 1, nr_frags; 1587 struct mtk_tx_buf *htx_buf, *tx_buf; 1588 struct mtk_tx_dma *htxd, *txd; 1589 void *data = xdpf->data; 1590 1591 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1592 return -EBUSY; 1593 1594 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1595 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1596 return -EBUSY; 1597 1598 spin_lock(ð->page_lock); 1599 1600 txd = ring->next_free; 1601 if (txd == ring->last_free) { 1602 spin_unlock(ð->page_lock); 1603 return -ENOMEM; 1604 } 1605 htxd = txd; 1606 1607 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); 1608 memset(tx_buf, 0, sizeof(*tx_buf)); 1609 htx_buf = tx_buf; 1610 1611 for (;;) { 1612 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1613 data, xdpf->headroom, index, dma_map); 1614 if (err < 0) 1615 goto unmap; 1616 1617 if (txd_info.last) 1618 break; 1619 1620 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1621 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1622 if (txd == ring->last_free) 1623 goto unmap; 1624 1625 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1626 soc->txrx.txd_size); 1627 memset(tx_buf, 0, sizeof(*tx_buf)); 1628 n_desc++; 1629 } 1630 1631 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1632 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1633 txd_info.last = index + 1 == nr_frags; 1634 data = skb_frag_address(&sinfo->frags[index]); 1635 1636 index++; 1637 } 1638 /* store xdpf for cleanup */ 1639 htx_buf->data = xdpf; 1640 1641 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1642 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1643 1644 if (index & 1) 1645 txd_pdma->txd2 |= TX_DMA_LS0; 1646 else 1647 txd_pdma->txd2 |= TX_DMA_LS1; 1648 } 1649 1650 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1651 atomic_sub(n_desc, &ring->free_count); 1652 1653 /* make sure that all changes to the dma ring are flushed before we 1654 * continue 1655 */ 1656 wmb(); 1657 1658 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1659 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1660 } else { 1661 int idx; 1662 1663 idx = txd_to_idx(ring, txd, soc->txrx.txd_size); 1664 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1665 MT7628_TX_CTX_IDX0); 1666 } 1667 1668 spin_unlock(ð->page_lock); 1669 1670 return 0; 1671 1672 unmap: 1673 while (htxd != txd) { 1674 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); 1675 mtk_tx_unmap(eth, tx_buf, NULL, false); 1676 1677 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1678 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1679 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1680 1681 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1682 } 1683 1684 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1685 } 1686 1687 spin_unlock(ð->page_lock); 1688 1689 return err; 1690 } 1691 1692 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1693 struct xdp_frame **frames, u32 flags) 1694 { 1695 struct mtk_mac *mac = netdev_priv(dev); 1696 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1697 struct mtk_eth *eth = mac->hw; 1698 int i, nxmit = 0; 1699 1700 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1701 return -EINVAL; 1702 1703 for (i = 0; i < num_frame; i++) { 1704 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1705 break; 1706 nxmit++; 1707 } 1708 1709 u64_stats_update_begin(&hw_stats->syncp); 1710 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1711 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1712 u64_stats_update_end(&hw_stats->syncp); 1713 1714 return nxmit; 1715 } 1716 1717 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1718 struct xdp_buff *xdp, struct net_device *dev) 1719 { 1720 struct mtk_mac *mac = netdev_priv(dev); 1721 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1722 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 1723 struct bpf_prog *prog; 1724 u32 act = XDP_PASS; 1725 1726 rcu_read_lock(); 1727 1728 prog = rcu_dereference(eth->prog); 1729 if (!prog) 1730 goto out; 1731 1732 act = bpf_prog_run_xdp(prog, xdp); 1733 switch (act) { 1734 case XDP_PASS: 1735 count = &hw_stats->xdp_stats.rx_xdp_pass; 1736 goto update_stats; 1737 case XDP_REDIRECT: 1738 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 1739 act = XDP_DROP; 1740 break; 1741 } 1742 1743 count = &hw_stats->xdp_stats.rx_xdp_redirect; 1744 goto update_stats; 1745 case XDP_TX: { 1746 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 1747 1748 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 1749 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 1750 act = XDP_DROP; 1751 break; 1752 } 1753 1754 count = &hw_stats->xdp_stats.rx_xdp_tx; 1755 goto update_stats; 1756 } 1757 default: 1758 bpf_warn_invalid_xdp_action(dev, prog, act); 1759 fallthrough; 1760 case XDP_ABORTED: 1761 trace_xdp_exception(dev, prog, act); 1762 fallthrough; 1763 case XDP_DROP: 1764 break; 1765 } 1766 1767 page_pool_put_full_page(ring->page_pool, 1768 virt_to_head_page(xdp->data), true); 1769 1770 update_stats: 1771 u64_stats_update_begin(&hw_stats->syncp); 1772 *count = *count + 1; 1773 u64_stats_update_end(&hw_stats->syncp); 1774 out: 1775 rcu_read_unlock(); 1776 1777 return act; 1778 } 1779 1780 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1781 struct mtk_eth *eth) 1782 { 1783 struct dim_sample dim_sample = {}; 1784 struct mtk_rx_ring *ring; 1785 bool xdp_flush = false; 1786 int idx; 1787 struct sk_buff *skb; 1788 u8 *data, *new_data; 1789 struct mtk_rx_dma_v2 *rxd, trxd; 1790 int done = 0, bytes = 0; 1791 1792 while (done < budget) { 1793 unsigned int pktlen, *rxdcsum; 1794 struct net_device *netdev; 1795 dma_addr_t dma_addr; 1796 u32 hash, reason; 1797 int mac = 0; 1798 1799 ring = mtk_get_rx_ring(eth); 1800 if (unlikely(!ring)) 1801 goto rx_done; 1802 1803 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1804 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1805 data = ring->data[idx]; 1806 1807 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 1808 break; 1809 1810 /* find out which mac the packet come from. values start at 1 */ 1811 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1812 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; 1813 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 1814 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 1815 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 1816 1817 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1818 !eth->netdev[mac])) 1819 goto release_desc; 1820 1821 netdev = eth->netdev[mac]; 1822 1823 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1824 goto release_desc; 1825 1826 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1827 1828 /* alloc new buffer */ 1829 if (ring->page_pool) { 1830 struct page *page = virt_to_head_page(data); 1831 struct xdp_buff xdp; 1832 u32 ret; 1833 1834 new_data = mtk_page_pool_get_buff(ring->page_pool, 1835 &dma_addr, 1836 GFP_ATOMIC); 1837 if (unlikely(!new_data)) { 1838 netdev->stats.rx_dropped++; 1839 goto release_desc; 1840 } 1841 1842 dma_sync_single_for_cpu(eth->dma_dev, 1843 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 1844 pktlen, page_pool_get_dma_dir(ring->page_pool)); 1845 1846 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 1847 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 1848 false); 1849 xdp_buff_clear_frags_flag(&xdp); 1850 1851 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 1852 if (ret == XDP_REDIRECT) 1853 xdp_flush = true; 1854 1855 if (ret != XDP_PASS) 1856 goto skip_rx; 1857 1858 skb = build_skb(data, PAGE_SIZE); 1859 if (unlikely(!skb)) { 1860 page_pool_put_full_page(ring->page_pool, 1861 page, true); 1862 netdev->stats.rx_dropped++; 1863 goto skip_rx; 1864 } 1865 1866 skb_reserve(skb, xdp.data - xdp.data_hard_start); 1867 skb_put(skb, xdp.data_end - xdp.data); 1868 skb_mark_for_recycle(skb); 1869 } else { 1870 if (ring->frag_size <= PAGE_SIZE) 1871 new_data = napi_alloc_frag(ring->frag_size); 1872 else 1873 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 1874 1875 if (unlikely(!new_data)) { 1876 netdev->stats.rx_dropped++; 1877 goto release_desc; 1878 } 1879 1880 dma_addr = dma_map_single(eth->dma_dev, 1881 new_data + NET_SKB_PAD + eth->ip_align, 1882 ring->buf_size, DMA_FROM_DEVICE); 1883 if (unlikely(dma_mapping_error(eth->dma_dev, 1884 dma_addr))) { 1885 skb_free_frag(new_data); 1886 netdev->stats.rx_dropped++; 1887 goto release_desc; 1888 } 1889 1890 dma_unmap_single(eth->dma_dev, trxd.rxd1, 1891 ring->buf_size, DMA_FROM_DEVICE); 1892 1893 skb = build_skb(data, ring->frag_size); 1894 if (unlikely(!skb)) { 1895 netdev->stats.rx_dropped++; 1896 skb_free_frag(data); 1897 goto skip_rx; 1898 } 1899 1900 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1901 skb_put(skb, pktlen); 1902 } 1903 1904 skb->dev = netdev; 1905 bytes += skb->len; 1906 1907 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 1908 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 1909 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 1910 if (hash != MTK_RXD5_FOE_ENTRY) 1911 skb_set_hash(skb, jhash_1word(hash, 0), 1912 PKT_HASH_TYPE_L4); 1913 rxdcsum = &trxd.rxd3; 1914 } else { 1915 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 1916 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 1917 if (hash != MTK_RXD4_FOE_ENTRY) 1918 skb_set_hash(skb, jhash_1word(hash, 0), 1919 PKT_HASH_TYPE_L4); 1920 rxdcsum = &trxd.rxd4; 1921 } 1922 1923 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) 1924 skb->ip_summed = CHECKSUM_UNNECESSARY; 1925 else 1926 skb_checksum_none_assert(skb); 1927 skb->protocol = eth_type_trans(skb, netdev); 1928 1929 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 1930 mtk_ppe_check_skb(eth->ppe[0], skb, hash); 1931 1932 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 1933 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 1934 if (trxd.rxd3 & RX_DMA_VTAG_V2) 1935 __vlan_hwaccel_put_tag(skb, 1936 htons(RX_DMA_VPID(trxd.rxd4)), 1937 RX_DMA_VID(trxd.rxd4)); 1938 } else if (trxd.rxd2 & RX_DMA_VTAG) { 1939 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1940 RX_DMA_VID(trxd.rxd3)); 1941 } 1942 1943 /* If the device is attached to a dsa switch, the special 1944 * tag inserted in VLAN field by hw switch can * be offloaded 1945 * by RX HW VLAN offload. Clear vlan info. 1946 */ 1947 if (netdev_uses_dsa(netdev)) 1948 __vlan_hwaccel_clear_tag(skb); 1949 } 1950 1951 skb_record_rx_queue(skb, 0); 1952 napi_gro_receive(napi, skb); 1953 1954 skip_rx: 1955 ring->data[idx] = new_data; 1956 rxd->rxd1 = (unsigned int)dma_addr; 1957 release_desc: 1958 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1959 rxd->rxd2 = RX_DMA_LSO; 1960 else 1961 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 1962 1963 ring->calc_idx = idx; 1964 done++; 1965 } 1966 1967 rx_done: 1968 if (done) { 1969 /* make sure that all changes to the dma ring are flushed before 1970 * we continue 1971 */ 1972 wmb(); 1973 mtk_update_rx_cpu_idx(eth); 1974 } 1975 1976 eth->rx_packets += done; 1977 eth->rx_bytes += bytes; 1978 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 1979 &dim_sample); 1980 net_dim(ð->rx_dim, dim_sample); 1981 1982 if (xdp_flush) 1983 xdp_do_flush_map(); 1984 1985 return done; 1986 } 1987 1988 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 1989 unsigned int *done, unsigned int *bytes) 1990 { 1991 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 1992 struct mtk_tx_ring *ring = ð->tx_ring; 1993 struct mtk_tx_buf *tx_buf; 1994 struct xdp_frame_bulk bq; 1995 struct mtk_tx_dma *desc; 1996 u32 cpu, dma; 1997 1998 cpu = ring->last_free_ptr; 1999 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2000 2001 desc = mtk_qdma_phys_to_virt(ring, cpu); 2002 xdp_frame_bulk_init(&bq); 2003 2004 while ((cpu != dma) && budget) { 2005 u32 next_cpu = desc->txd2; 2006 int mac = 0; 2007 2008 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2009 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2010 break; 2011 2012 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2013 eth->soc->txrx.txd_size); 2014 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 2015 mac = 1; 2016 2017 if (!tx_buf->data) 2018 break; 2019 2020 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2021 if (tx_buf->type == MTK_TYPE_SKB) { 2022 struct sk_buff *skb = tx_buf->data; 2023 2024 bytes[mac] += skb->len; 2025 done[mac]++; 2026 } 2027 budget--; 2028 } 2029 mtk_tx_unmap(eth, tx_buf, &bq, true); 2030 2031 ring->last_free = desc; 2032 atomic_inc(&ring->free_count); 2033 2034 cpu = next_cpu; 2035 } 2036 xdp_flush_frame_bulk(&bq); 2037 2038 ring->last_free_ptr = cpu; 2039 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2040 2041 return budget; 2042 } 2043 2044 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2045 unsigned int *done, unsigned int *bytes) 2046 { 2047 struct mtk_tx_ring *ring = ð->tx_ring; 2048 struct mtk_tx_buf *tx_buf; 2049 struct xdp_frame_bulk bq; 2050 struct mtk_tx_dma *desc; 2051 u32 cpu, dma; 2052 2053 cpu = ring->cpu_idx; 2054 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2055 xdp_frame_bulk_init(&bq); 2056 2057 while ((cpu != dma) && budget) { 2058 tx_buf = &ring->buf[cpu]; 2059 if (!tx_buf->data) 2060 break; 2061 2062 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2063 if (tx_buf->type == MTK_TYPE_SKB) { 2064 struct sk_buff *skb = tx_buf->data; 2065 2066 bytes[0] += skb->len; 2067 done[0]++; 2068 } 2069 budget--; 2070 } 2071 mtk_tx_unmap(eth, tx_buf, &bq, true); 2072 2073 desc = ring->dma + cpu * eth->soc->txrx.txd_size; 2074 ring->last_free = desc; 2075 atomic_inc(&ring->free_count); 2076 2077 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2078 } 2079 xdp_flush_frame_bulk(&bq); 2080 2081 ring->cpu_idx = cpu; 2082 2083 return budget; 2084 } 2085 2086 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2087 { 2088 struct mtk_tx_ring *ring = ð->tx_ring; 2089 struct dim_sample dim_sample = {}; 2090 unsigned int done[MTK_MAX_DEVS]; 2091 unsigned int bytes[MTK_MAX_DEVS]; 2092 int total = 0, i; 2093 2094 memset(done, 0, sizeof(done)); 2095 memset(bytes, 0, sizeof(bytes)); 2096 2097 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2098 budget = mtk_poll_tx_qdma(eth, budget, done, bytes); 2099 else 2100 budget = mtk_poll_tx_pdma(eth, budget, done, bytes); 2101 2102 for (i = 0; i < MTK_MAC_COUNT; i++) { 2103 if (!eth->netdev[i] || !done[i]) 2104 continue; 2105 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 2106 total += done[i]; 2107 eth->tx_packets += done[i]; 2108 eth->tx_bytes += bytes[i]; 2109 } 2110 2111 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2112 &dim_sample); 2113 net_dim(ð->tx_dim, dim_sample); 2114 2115 if (mtk_queue_stopped(eth) && 2116 (atomic_read(&ring->free_count) > ring->thresh)) 2117 mtk_wake_queue(eth); 2118 2119 return total; 2120 } 2121 2122 static void mtk_handle_status_irq(struct mtk_eth *eth) 2123 { 2124 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2125 2126 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2127 mtk_stats_update(eth); 2128 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2129 MTK_INT_STATUS2); 2130 } 2131 } 2132 2133 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2134 { 2135 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2136 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2137 int tx_done = 0; 2138 2139 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2140 mtk_handle_status_irq(eth); 2141 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2142 tx_done = mtk_poll_tx(eth, budget); 2143 2144 if (unlikely(netif_msg_intr(eth))) { 2145 dev_info(eth->dev, 2146 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2147 mtk_r32(eth, reg_map->tx_irq_status), 2148 mtk_r32(eth, reg_map->tx_irq_mask)); 2149 } 2150 2151 if (tx_done == budget) 2152 return budget; 2153 2154 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2155 return budget; 2156 2157 if (napi_complete_done(napi, tx_done)) 2158 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2159 2160 return tx_done; 2161 } 2162 2163 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2164 { 2165 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2166 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2167 int rx_done_total = 0; 2168 2169 mtk_handle_status_irq(eth); 2170 2171 do { 2172 int rx_done; 2173 2174 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, 2175 reg_map->pdma.irq_status); 2176 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2177 rx_done_total += rx_done; 2178 2179 if (unlikely(netif_msg_intr(eth))) { 2180 dev_info(eth->dev, 2181 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2182 mtk_r32(eth, reg_map->pdma.irq_status), 2183 mtk_r32(eth, reg_map->pdma.irq_mask)); 2184 } 2185 2186 if (rx_done_total == budget) 2187 return budget; 2188 2189 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2190 eth->soc->txrx.rx_irq_done_mask); 2191 2192 if (napi_complete_done(napi, rx_done_total)) 2193 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2194 2195 return rx_done_total; 2196 } 2197 2198 static int mtk_tx_alloc(struct mtk_eth *eth) 2199 { 2200 const struct mtk_soc_data *soc = eth->soc; 2201 struct mtk_tx_ring *ring = ð->tx_ring; 2202 int i, sz = soc->txrx.txd_size; 2203 struct mtk_tx_dma_v2 *txd; 2204 2205 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 2206 GFP_KERNEL); 2207 if (!ring->buf) 2208 goto no_tx_mem; 2209 2210 ring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, 2211 &ring->phys, GFP_KERNEL); 2212 if (!ring->dma) 2213 goto no_tx_mem; 2214 2215 for (i = 0; i < MTK_DMA_SIZE; i++) { 2216 int next = (i + 1) % MTK_DMA_SIZE; 2217 u32 next_ptr = ring->phys + next * sz; 2218 2219 txd = ring->dma + i * sz; 2220 txd->txd2 = next_ptr; 2221 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2222 txd->txd4 = 0; 2223 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 2224 txd->txd5 = 0; 2225 txd->txd6 = 0; 2226 txd->txd7 = 0; 2227 txd->txd8 = 0; 2228 } 2229 } 2230 2231 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2232 * only as the framework. The real HW descriptors are the PDMA 2233 * descriptors in ring->dma_pdma. 2234 */ 2235 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2236 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, 2237 &ring->phys_pdma, GFP_KERNEL); 2238 if (!ring->dma_pdma) 2239 goto no_tx_mem; 2240 2241 for (i = 0; i < MTK_DMA_SIZE; i++) { 2242 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2243 ring->dma_pdma[i].txd4 = 0; 2244 } 2245 } 2246 2247 ring->dma_size = MTK_DMA_SIZE; 2248 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 2249 ring->next_free = ring->dma; 2250 ring->last_free = (void *)txd; 2251 ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz)); 2252 ring->thresh = MAX_SKB_FRAGS; 2253 2254 /* make sure that all changes to the dma ring are flushed before we 2255 * continue 2256 */ 2257 wmb(); 2258 2259 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2260 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2261 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2262 mtk_w32(eth, 2263 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 2264 soc->reg_map->qdma.crx_ptr); 2265 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2266 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, 2267 soc->reg_map->qdma.qtx_cfg); 2268 } else { 2269 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2270 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); 2271 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2272 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2273 } 2274 2275 return 0; 2276 2277 no_tx_mem: 2278 return -ENOMEM; 2279 } 2280 2281 static void mtk_tx_clean(struct mtk_eth *eth) 2282 { 2283 const struct mtk_soc_data *soc = eth->soc; 2284 struct mtk_tx_ring *ring = ð->tx_ring; 2285 int i; 2286 2287 if (ring->buf) { 2288 for (i = 0; i < MTK_DMA_SIZE; i++) 2289 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2290 kfree(ring->buf); 2291 ring->buf = NULL; 2292 } 2293 2294 if (ring->dma) { 2295 dma_free_coherent(eth->dma_dev, 2296 MTK_DMA_SIZE * soc->txrx.txd_size, 2297 ring->dma, ring->phys); 2298 ring->dma = NULL; 2299 } 2300 2301 if (ring->dma_pdma) { 2302 dma_free_coherent(eth->dma_dev, 2303 MTK_DMA_SIZE * soc->txrx.txd_size, 2304 ring->dma_pdma, ring->phys_pdma); 2305 ring->dma_pdma = NULL; 2306 } 2307 } 2308 2309 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2310 { 2311 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2312 struct mtk_rx_ring *ring; 2313 int rx_data_len, rx_dma_size; 2314 int i; 2315 2316 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2317 if (ring_no) 2318 return -EINVAL; 2319 ring = ð->rx_ring_qdma; 2320 } else { 2321 ring = ð->rx_ring[ring_no]; 2322 } 2323 2324 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2325 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2326 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2327 } else { 2328 rx_data_len = ETH_DATA_LEN; 2329 rx_dma_size = MTK_DMA_SIZE; 2330 } 2331 2332 ring->frag_size = mtk_max_frag_size(rx_data_len); 2333 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2334 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2335 GFP_KERNEL); 2336 if (!ring->data) 2337 return -ENOMEM; 2338 2339 if (mtk_page_pool_enabled(eth)) { 2340 struct page_pool *pp; 2341 2342 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2343 rx_dma_size); 2344 if (IS_ERR(pp)) 2345 return PTR_ERR(pp); 2346 2347 ring->page_pool = pp; 2348 } 2349 2350 ring->dma = dma_alloc_coherent(eth->dma_dev, 2351 rx_dma_size * eth->soc->txrx.rxd_size, 2352 &ring->phys, GFP_KERNEL); 2353 if (!ring->dma) 2354 return -ENOMEM; 2355 2356 for (i = 0; i < rx_dma_size; i++) { 2357 struct mtk_rx_dma_v2 *rxd; 2358 dma_addr_t dma_addr; 2359 void *data; 2360 2361 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2362 if (ring->page_pool) { 2363 data = mtk_page_pool_get_buff(ring->page_pool, 2364 &dma_addr, GFP_KERNEL); 2365 if (!data) 2366 return -ENOMEM; 2367 } else { 2368 if (ring->frag_size <= PAGE_SIZE) 2369 data = netdev_alloc_frag(ring->frag_size); 2370 else 2371 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2372 2373 if (!data) 2374 return -ENOMEM; 2375 2376 dma_addr = dma_map_single(eth->dma_dev, 2377 data + NET_SKB_PAD + eth->ip_align, 2378 ring->buf_size, DMA_FROM_DEVICE); 2379 if (unlikely(dma_mapping_error(eth->dma_dev, 2380 dma_addr))) 2381 return -ENOMEM; 2382 } 2383 rxd->rxd1 = (unsigned int)dma_addr; 2384 ring->data[i] = data; 2385 2386 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2387 rxd->rxd2 = RX_DMA_LSO; 2388 else 2389 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2390 2391 rxd->rxd3 = 0; 2392 rxd->rxd4 = 0; 2393 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2394 rxd->rxd5 = 0; 2395 rxd->rxd6 = 0; 2396 rxd->rxd7 = 0; 2397 rxd->rxd8 = 0; 2398 } 2399 } 2400 2401 ring->dma_size = rx_dma_size; 2402 ring->calc_idx_update = false; 2403 ring->calc_idx = rx_dma_size - 1; 2404 if (rx_flag == MTK_RX_FLAGS_QDMA) 2405 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2406 ring_no * MTK_QRX_OFFSET; 2407 else 2408 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2409 ring_no * MTK_QRX_OFFSET; 2410 /* make sure that all changes to the dma ring are flushed before we 2411 * continue 2412 */ 2413 wmb(); 2414 2415 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2416 mtk_w32(eth, ring->phys, 2417 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2418 mtk_w32(eth, rx_dma_size, 2419 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2420 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2421 reg_map->qdma.rst_idx); 2422 } else { 2423 mtk_w32(eth, ring->phys, 2424 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2425 mtk_w32(eth, rx_dma_size, 2426 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2427 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2428 reg_map->pdma.rst_idx); 2429 } 2430 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2431 2432 return 0; 2433 } 2434 2435 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 2436 { 2437 int i; 2438 2439 if (ring->data && ring->dma) { 2440 for (i = 0; i < ring->dma_size; i++) { 2441 struct mtk_rx_dma *rxd; 2442 2443 if (!ring->data[i]) 2444 continue; 2445 2446 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2447 if (!rxd->rxd1) 2448 continue; 2449 2450 dma_unmap_single(eth->dma_dev, rxd->rxd1, 2451 ring->buf_size, DMA_FROM_DEVICE); 2452 mtk_rx_put_buff(ring, ring->data[i], false); 2453 } 2454 kfree(ring->data); 2455 ring->data = NULL; 2456 } 2457 2458 if (ring->dma) { 2459 dma_free_coherent(eth->dma_dev, 2460 ring->dma_size * eth->soc->txrx.rxd_size, 2461 ring->dma, ring->phys); 2462 ring->dma = NULL; 2463 } 2464 2465 if (ring->page_pool) { 2466 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2467 xdp_rxq_info_unreg(&ring->xdp_q); 2468 page_pool_destroy(ring->page_pool); 2469 ring->page_pool = NULL; 2470 } 2471 } 2472 2473 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2474 { 2475 int i; 2476 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2477 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2478 2479 /* set LRO rings to auto-learn modes */ 2480 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2481 2482 /* validate LRO ring */ 2483 ring_ctrl_dw2 |= MTK_RING_VLD; 2484 2485 /* set AGE timer (unit: 20us) */ 2486 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2487 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2488 2489 /* set max AGG timer (unit: 20us) */ 2490 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2491 2492 /* set max LRO AGG count */ 2493 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2494 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2495 2496 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2497 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2498 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2499 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2500 } 2501 2502 /* IPv4 checksum update enable */ 2503 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2504 2505 /* switch priority comparison to packet count mode */ 2506 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2507 2508 /* bandwidth threshold setting */ 2509 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2510 2511 /* auto-learn score delta setting */ 2512 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2513 2514 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2515 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2516 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2517 2518 /* set HW LRO mode & the max aggregation count for rx packets */ 2519 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2520 2521 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2522 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2523 2524 /* enable HW LRO */ 2525 lro_ctrl_dw0 |= MTK_LRO_EN; 2526 2527 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2528 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2529 2530 return 0; 2531 } 2532 2533 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2534 { 2535 int i; 2536 u32 val; 2537 2538 /* relinquish lro rings, flush aggregated packets */ 2539 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2540 2541 /* wait for relinquishments done */ 2542 for (i = 0; i < 10; i++) { 2543 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2544 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2545 msleep(20); 2546 continue; 2547 } 2548 break; 2549 } 2550 2551 /* invalidate lro rings */ 2552 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2553 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2554 2555 /* disable HW LRO */ 2556 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2557 } 2558 2559 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2560 { 2561 u32 reg_val; 2562 2563 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2564 2565 /* invalidate the IP setting */ 2566 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2567 2568 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2569 2570 /* validate the IP setting */ 2571 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2572 } 2573 2574 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2575 { 2576 u32 reg_val; 2577 2578 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2579 2580 /* invalidate the IP setting */ 2581 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2582 2583 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2584 } 2585 2586 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2587 { 2588 int cnt = 0; 2589 int i; 2590 2591 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2592 if (mac->hwlro_ip[i]) 2593 cnt++; 2594 } 2595 2596 return cnt; 2597 } 2598 2599 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2600 struct ethtool_rxnfc *cmd) 2601 { 2602 struct ethtool_rx_flow_spec *fsp = 2603 (struct ethtool_rx_flow_spec *)&cmd->fs; 2604 struct mtk_mac *mac = netdev_priv(dev); 2605 struct mtk_eth *eth = mac->hw; 2606 int hwlro_idx; 2607 2608 if ((fsp->flow_type != TCP_V4_FLOW) || 2609 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2610 (fsp->location > 1)) 2611 return -EINVAL; 2612 2613 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2614 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2615 2616 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2617 2618 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2619 2620 return 0; 2621 } 2622 2623 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2624 struct ethtool_rxnfc *cmd) 2625 { 2626 struct ethtool_rx_flow_spec *fsp = 2627 (struct ethtool_rx_flow_spec *)&cmd->fs; 2628 struct mtk_mac *mac = netdev_priv(dev); 2629 struct mtk_eth *eth = mac->hw; 2630 int hwlro_idx; 2631 2632 if (fsp->location > 1) 2633 return -EINVAL; 2634 2635 mac->hwlro_ip[fsp->location] = 0; 2636 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2637 2638 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2639 2640 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2641 2642 return 0; 2643 } 2644 2645 static void mtk_hwlro_netdev_disable(struct net_device *dev) 2646 { 2647 struct mtk_mac *mac = netdev_priv(dev); 2648 struct mtk_eth *eth = mac->hw; 2649 int i, hwlro_idx; 2650 2651 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2652 mac->hwlro_ip[i] = 0; 2653 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 2654 2655 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2656 } 2657 2658 mac->hwlro_ip_cnt = 0; 2659 } 2660 2661 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 2662 struct ethtool_rxnfc *cmd) 2663 { 2664 struct mtk_mac *mac = netdev_priv(dev); 2665 struct ethtool_rx_flow_spec *fsp = 2666 (struct ethtool_rx_flow_spec *)&cmd->fs; 2667 2668 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 2669 return -EINVAL; 2670 2671 /* only tcp dst ipv4 is meaningful, others are meaningless */ 2672 fsp->flow_type = TCP_V4_FLOW; 2673 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 2674 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 2675 2676 fsp->h_u.tcp_ip4_spec.ip4src = 0; 2677 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 2678 fsp->h_u.tcp_ip4_spec.psrc = 0; 2679 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 2680 fsp->h_u.tcp_ip4_spec.pdst = 0; 2681 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 2682 fsp->h_u.tcp_ip4_spec.tos = 0; 2683 fsp->m_u.tcp_ip4_spec.tos = 0xff; 2684 2685 return 0; 2686 } 2687 2688 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 2689 struct ethtool_rxnfc *cmd, 2690 u32 *rule_locs) 2691 { 2692 struct mtk_mac *mac = netdev_priv(dev); 2693 int cnt = 0; 2694 int i; 2695 2696 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2697 if (mac->hwlro_ip[i]) { 2698 rule_locs[cnt] = i; 2699 cnt++; 2700 } 2701 } 2702 2703 cmd->rule_cnt = cnt; 2704 2705 return 0; 2706 } 2707 2708 static netdev_features_t mtk_fix_features(struct net_device *dev, 2709 netdev_features_t features) 2710 { 2711 if (!(features & NETIF_F_LRO)) { 2712 struct mtk_mac *mac = netdev_priv(dev); 2713 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2714 2715 if (ip_cnt) { 2716 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 2717 2718 features |= NETIF_F_LRO; 2719 } 2720 } 2721 2722 return features; 2723 } 2724 2725 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2726 { 2727 int err = 0; 2728 2729 if (!((dev->features ^ features) & NETIF_F_LRO)) 2730 return 0; 2731 2732 if (!(features & NETIF_F_LRO)) 2733 mtk_hwlro_netdev_disable(dev); 2734 2735 return err; 2736 } 2737 2738 /* wait for DMA to finish whatever it is doing before we start using it again */ 2739 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2740 { 2741 unsigned int reg; 2742 int ret; 2743 u32 val; 2744 2745 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2746 reg = eth->soc->reg_map->qdma.glo_cfg; 2747 else 2748 reg = eth->soc->reg_map->pdma.glo_cfg; 2749 2750 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 2751 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 2752 5, MTK_DMA_BUSY_TIMEOUT_US); 2753 if (ret) 2754 dev_err(eth->dev, "DMA init timeout\n"); 2755 2756 return ret; 2757 } 2758 2759 static int mtk_dma_init(struct mtk_eth *eth) 2760 { 2761 int err; 2762 u32 i; 2763 2764 if (mtk_dma_busy_wait(eth)) 2765 return -EBUSY; 2766 2767 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2768 /* QDMA needs scratch memory for internal reordering of the 2769 * descriptors 2770 */ 2771 err = mtk_init_fq_dma(eth); 2772 if (err) 2773 return err; 2774 } 2775 2776 err = mtk_tx_alloc(eth); 2777 if (err) 2778 return err; 2779 2780 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2781 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2782 if (err) 2783 return err; 2784 } 2785 2786 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2787 if (err) 2788 return err; 2789 2790 if (eth->hwlro) { 2791 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2792 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2793 if (err) 2794 return err; 2795 } 2796 err = mtk_hwlro_rx_init(eth); 2797 if (err) 2798 return err; 2799 } 2800 2801 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2802 /* Enable random early drop and set drop threshold 2803 * automatically 2804 */ 2805 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2806 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 2807 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 2808 } 2809 2810 return 0; 2811 } 2812 2813 static void mtk_dma_free(struct mtk_eth *eth) 2814 { 2815 const struct mtk_soc_data *soc = eth->soc; 2816 int i; 2817 2818 for (i = 0; i < MTK_MAC_COUNT; i++) 2819 if (eth->netdev[i]) 2820 netdev_reset_queue(eth->netdev[i]); 2821 if (eth->scratch_ring) { 2822 dma_free_coherent(eth->dma_dev, 2823 MTK_DMA_SIZE * soc->txrx.txd_size, 2824 eth->scratch_ring, eth->phy_scratch_ring); 2825 eth->scratch_ring = NULL; 2826 eth->phy_scratch_ring = 0; 2827 } 2828 mtk_tx_clean(eth); 2829 mtk_rx_clean(eth, ð->rx_ring[0]); 2830 mtk_rx_clean(eth, ð->rx_ring_qdma); 2831 2832 if (eth->hwlro) { 2833 mtk_hwlro_rx_uninit(eth); 2834 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2835 mtk_rx_clean(eth, ð->rx_ring[i]); 2836 } 2837 2838 kfree(eth->scratch_head); 2839 } 2840 2841 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 2842 { 2843 struct mtk_mac *mac = netdev_priv(dev); 2844 struct mtk_eth *eth = mac->hw; 2845 2846 eth->netdev[mac->id]->stats.tx_errors++; 2847 netif_err(eth, tx_err, dev, 2848 "transmit timed out\n"); 2849 schedule_work(ð->pending_work); 2850 } 2851 2852 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 2853 { 2854 struct mtk_eth *eth = _eth; 2855 2856 eth->rx_events++; 2857 if (likely(napi_schedule_prep(ð->rx_napi))) { 2858 __napi_schedule(ð->rx_napi); 2859 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 2860 } 2861 2862 return IRQ_HANDLED; 2863 } 2864 2865 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 2866 { 2867 struct mtk_eth *eth = _eth; 2868 2869 eth->tx_events++; 2870 if (likely(napi_schedule_prep(ð->tx_napi))) { 2871 __napi_schedule(ð->tx_napi); 2872 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2873 } 2874 2875 return IRQ_HANDLED; 2876 } 2877 2878 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 2879 { 2880 struct mtk_eth *eth = _eth; 2881 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2882 2883 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 2884 eth->soc->txrx.rx_irq_done_mask) { 2885 if (mtk_r32(eth, reg_map->pdma.irq_status) & 2886 eth->soc->txrx.rx_irq_done_mask) 2887 mtk_handle_irq_rx(irq, _eth); 2888 } 2889 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 2890 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2891 mtk_handle_irq_tx(irq, _eth); 2892 } 2893 2894 return IRQ_HANDLED; 2895 } 2896 2897 #ifdef CONFIG_NET_POLL_CONTROLLER 2898 static void mtk_poll_controller(struct net_device *dev) 2899 { 2900 struct mtk_mac *mac = netdev_priv(dev); 2901 struct mtk_eth *eth = mac->hw; 2902 2903 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2904 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 2905 mtk_handle_irq_rx(eth->irq[2], dev); 2906 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2907 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2908 } 2909 #endif 2910 2911 static int mtk_start_dma(struct mtk_eth *eth) 2912 { 2913 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 2914 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2915 int err; 2916 2917 err = mtk_dma_init(eth); 2918 if (err) { 2919 mtk_dma_free(eth); 2920 return err; 2921 } 2922 2923 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2924 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 2925 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2926 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 2927 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 2928 2929 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2930 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 2931 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 2932 MTK_CHK_DDONE_EN; 2933 else 2934 val |= MTK_RX_BT_32DWORDS; 2935 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 2936 2937 mtk_w32(eth, 2938 MTK_RX_DMA_EN | rx_2b_offset | 2939 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 2940 reg_map->pdma.glo_cfg); 2941 } else { 2942 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2943 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 2944 reg_map->pdma.glo_cfg); 2945 } 2946 2947 return 0; 2948 } 2949 2950 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 2951 { 2952 int i; 2953 2954 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2955 return; 2956 2957 for (i = 0; i < MTK_MAC_COUNT; i++) { 2958 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 2959 2960 /* default setup the forward port to send frame to PDMA */ 2961 val &= ~0xffff; 2962 2963 /* Enable RX checksum */ 2964 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2965 2966 val |= config; 2967 2968 if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0])) 2969 val |= MTK_GDMA_SPECIAL_TAG; 2970 2971 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2972 } 2973 /* Reset and enable PSE */ 2974 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 2975 mtk_w32(eth, 0, MTK_RST_GL); 2976 } 2977 2978 static int mtk_open(struct net_device *dev) 2979 { 2980 struct mtk_mac *mac = netdev_priv(dev); 2981 struct mtk_eth *eth = mac->hw; 2982 int err; 2983 2984 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 2985 if (err) { 2986 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 2987 err); 2988 return err; 2989 } 2990 2991 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 2992 if (!refcount_read(ð->dma_refcnt)) { 2993 const struct mtk_soc_data *soc = eth->soc; 2994 u32 gdm_config; 2995 int i; 2996 2997 err = mtk_start_dma(eth); 2998 if (err) 2999 return err; 3000 3001 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3002 mtk_ppe_start(eth->ppe[i]); 3003 3004 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe 3005 : MTK_GDMA_TO_PDMA; 3006 mtk_gdm_config(eth, gdm_config); 3007 3008 napi_enable(ð->tx_napi); 3009 napi_enable(ð->rx_napi); 3010 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3011 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); 3012 refcount_set(ð->dma_refcnt, 1); 3013 } 3014 else 3015 refcount_inc(ð->dma_refcnt); 3016 3017 phylink_start(mac->phylink); 3018 netif_start_queue(dev); 3019 return 0; 3020 } 3021 3022 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3023 { 3024 u32 val; 3025 int i; 3026 3027 /* stop the dma engine */ 3028 spin_lock_bh(ð->page_lock); 3029 val = mtk_r32(eth, glo_cfg); 3030 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3031 glo_cfg); 3032 spin_unlock_bh(ð->page_lock); 3033 3034 /* wait for dma stop */ 3035 for (i = 0; i < 10; i++) { 3036 val = mtk_r32(eth, glo_cfg); 3037 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3038 msleep(20); 3039 continue; 3040 } 3041 break; 3042 } 3043 } 3044 3045 static int mtk_stop(struct net_device *dev) 3046 { 3047 struct mtk_mac *mac = netdev_priv(dev); 3048 struct mtk_eth *eth = mac->hw; 3049 int i; 3050 3051 phylink_stop(mac->phylink); 3052 3053 netif_tx_disable(dev); 3054 3055 phylink_disconnect_phy(mac->phylink); 3056 3057 /* only shutdown DMA if this is the last user */ 3058 if (!refcount_dec_and_test(ð->dma_refcnt)) 3059 return 0; 3060 3061 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 3062 3063 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3064 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3065 napi_disable(ð->tx_napi); 3066 napi_disable(ð->rx_napi); 3067 3068 cancel_work_sync(ð->rx_dim.work); 3069 cancel_work_sync(ð->tx_dim.work); 3070 3071 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3072 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3073 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3074 3075 mtk_dma_free(eth); 3076 3077 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3078 mtk_ppe_stop(eth->ppe[i]); 3079 3080 return 0; 3081 } 3082 3083 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3084 struct netlink_ext_ack *extack) 3085 { 3086 struct mtk_mac *mac = netdev_priv(dev); 3087 struct mtk_eth *eth = mac->hw; 3088 struct bpf_prog *old_prog; 3089 bool need_update; 3090 3091 if (eth->hwlro) { 3092 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3093 return -EOPNOTSUPP; 3094 } 3095 3096 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3097 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3098 return -EOPNOTSUPP; 3099 } 3100 3101 need_update = !!eth->prog != !!prog; 3102 if (netif_running(dev) && need_update) 3103 mtk_stop(dev); 3104 3105 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3106 if (old_prog) 3107 bpf_prog_put(old_prog); 3108 3109 if (netif_running(dev) && need_update) 3110 return mtk_open(dev); 3111 3112 return 0; 3113 } 3114 3115 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3116 { 3117 switch (xdp->command) { 3118 case XDP_SETUP_PROG: 3119 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3120 default: 3121 return -EINVAL; 3122 } 3123 } 3124 3125 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3126 { 3127 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3128 reset_bits, 3129 reset_bits); 3130 3131 usleep_range(1000, 1100); 3132 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3133 reset_bits, 3134 ~reset_bits); 3135 mdelay(10); 3136 } 3137 3138 static void mtk_clk_disable(struct mtk_eth *eth) 3139 { 3140 int clk; 3141 3142 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3143 clk_disable_unprepare(eth->clks[clk]); 3144 } 3145 3146 static int mtk_clk_enable(struct mtk_eth *eth) 3147 { 3148 int clk, ret; 3149 3150 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3151 ret = clk_prepare_enable(eth->clks[clk]); 3152 if (ret) 3153 goto err_disable_clks; 3154 } 3155 3156 return 0; 3157 3158 err_disable_clks: 3159 while (--clk >= 0) 3160 clk_disable_unprepare(eth->clks[clk]); 3161 3162 return ret; 3163 } 3164 3165 static void mtk_dim_rx(struct work_struct *work) 3166 { 3167 struct dim *dim = container_of(work, struct dim, work); 3168 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3169 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3170 struct dim_cq_moder cur_profile; 3171 u32 val, cur; 3172 3173 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3174 dim->profile_ix); 3175 spin_lock_bh(ð->dim_lock); 3176 3177 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3178 val &= MTK_PDMA_DELAY_TX_MASK; 3179 val |= MTK_PDMA_DELAY_RX_EN; 3180 3181 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3182 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3183 3184 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3185 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3186 3187 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3188 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3189 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3190 3191 spin_unlock_bh(ð->dim_lock); 3192 3193 dim->state = DIM_START_MEASURE; 3194 } 3195 3196 static void mtk_dim_tx(struct work_struct *work) 3197 { 3198 struct dim *dim = container_of(work, struct dim, work); 3199 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3200 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3201 struct dim_cq_moder cur_profile; 3202 u32 val, cur; 3203 3204 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3205 dim->profile_ix); 3206 spin_lock_bh(ð->dim_lock); 3207 3208 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3209 val &= MTK_PDMA_DELAY_RX_MASK; 3210 val |= MTK_PDMA_DELAY_TX_EN; 3211 3212 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3213 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3214 3215 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3216 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3217 3218 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3219 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3220 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3221 3222 spin_unlock_bh(ð->dim_lock); 3223 3224 dim->state = DIM_START_MEASURE; 3225 } 3226 3227 static int mtk_hw_init(struct mtk_eth *eth) 3228 { 3229 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3230 ETHSYS_DMA_AG_MAP_PPE; 3231 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3232 int i, val, ret; 3233 3234 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 3235 return 0; 3236 3237 pm_runtime_enable(eth->dev); 3238 pm_runtime_get_sync(eth->dev); 3239 3240 ret = mtk_clk_enable(eth); 3241 if (ret) 3242 goto err_disable_pm; 3243 3244 if (eth->ethsys) 3245 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3246 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3247 3248 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3249 ret = device_reset(eth->dev); 3250 if (ret) { 3251 dev_err(eth->dev, "MAC reset failed!\n"); 3252 goto err_disable_pm; 3253 } 3254 3255 /* set interrupt delays based on current Net DIM sample */ 3256 mtk_dim_rx(ð->rx_dim.work); 3257 mtk_dim_tx(ð->tx_dim.work); 3258 3259 /* disable delay and normal interrupt */ 3260 mtk_tx_irq_disable(eth, ~0); 3261 mtk_rx_irq_disable(eth, ~0); 3262 3263 return 0; 3264 } 3265 3266 val = RSTCTRL_FE | RSTCTRL_PPE; 3267 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3268 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3269 3270 val |= RSTCTRL_ETH; 3271 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3272 val |= RSTCTRL_PPE1; 3273 } 3274 3275 ethsys_reset(eth, val); 3276 3277 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3278 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3279 0x3ffffff); 3280 3281 /* Set FE to PDMAv2 if necessary */ 3282 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3283 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3284 } 3285 3286 if (eth->pctl) { 3287 /* Set GE2 driving and slew rate */ 3288 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3289 3290 /* set GE2 TDSEL */ 3291 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3292 3293 /* set GE2 TUNE */ 3294 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3295 } 3296 3297 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3298 * up with the more appropriate value when mtk_mac_config call is being 3299 * invoked. 3300 */ 3301 for (i = 0; i < MTK_MAC_COUNT; i++) 3302 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3303 3304 /* Indicates CDM to parse the MTK special tag from CPU 3305 * which also is working out for untag packets. 3306 */ 3307 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3308 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 3309 3310 /* Enable RX VLan Offloading */ 3311 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 3312 3313 /* set interrupt delays based on current Net DIM sample */ 3314 mtk_dim_rx(ð->rx_dim.work); 3315 mtk_dim_tx(ð->tx_dim.work); 3316 3317 /* disable delay and normal interrupt */ 3318 mtk_tx_irq_disable(eth, ~0); 3319 mtk_rx_irq_disable(eth, ~0); 3320 3321 /* FE int grouping */ 3322 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 3323 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); 3324 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 3325 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 3326 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 3327 3328 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3329 /* PSE should not drop port8 and port9 packets */ 3330 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 3331 3332 /* PSE Free Queue Flow Control */ 3333 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 3334 3335 /* PSE config input queue threshold */ 3336 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 3337 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 3338 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 3339 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 3340 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 3341 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 3342 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 3343 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 3344 3345 /* PSE config output queue threshold */ 3346 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 3347 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 3348 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 3349 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 3350 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 3351 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 3352 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 3353 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 3354 3355 /* GDM and CDM Threshold */ 3356 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 3357 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 3358 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 3359 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 3360 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 3361 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 3362 } 3363 3364 return 0; 3365 3366 err_disable_pm: 3367 pm_runtime_put_sync(eth->dev); 3368 pm_runtime_disable(eth->dev); 3369 3370 return ret; 3371 } 3372 3373 static int mtk_hw_deinit(struct mtk_eth *eth) 3374 { 3375 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 3376 return 0; 3377 3378 mtk_clk_disable(eth); 3379 3380 pm_runtime_put_sync(eth->dev); 3381 pm_runtime_disable(eth->dev); 3382 3383 return 0; 3384 } 3385 3386 static int __init mtk_init(struct net_device *dev) 3387 { 3388 struct mtk_mac *mac = netdev_priv(dev); 3389 struct mtk_eth *eth = mac->hw; 3390 int ret; 3391 3392 ret = of_get_ethdev_address(mac->of_node, dev); 3393 if (ret) { 3394 /* If the mac address is invalid, use random mac address */ 3395 eth_hw_addr_random(dev); 3396 dev_err(eth->dev, "generated random MAC address %pM\n", 3397 dev->dev_addr); 3398 } 3399 3400 return 0; 3401 } 3402 3403 static void mtk_uninit(struct net_device *dev) 3404 { 3405 struct mtk_mac *mac = netdev_priv(dev); 3406 struct mtk_eth *eth = mac->hw; 3407 3408 phylink_disconnect_phy(mac->phylink); 3409 mtk_tx_irq_disable(eth, ~0); 3410 mtk_rx_irq_disable(eth, ~0); 3411 } 3412 3413 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 3414 { 3415 int length = new_mtu + MTK_RX_ETH_HLEN; 3416 struct mtk_mac *mac = netdev_priv(dev); 3417 struct mtk_eth *eth = mac->hw; 3418 u32 mcr_cur, mcr_new; 3419 3420 if (rcu_access_pointer(eth->prog) && 3421 length > MTK_PP_MAX_BUF_SIZE) { 3422 netdev_err(dev, "Invalid MTU for XDP mode\n"); 3423 return -EINVAL; 3424 } 3425 3426 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3427 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3428 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3429 3430 if (length <= 1518) 3431 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3432 else if (length <= 1536) 3433 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3434 else if (length <= 1552) 3435 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3436 else 3437 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3438 3439 if (mcr_new != mcr_cur) 3440 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3441 } 3442 3443 dev->mtu = new_mtu; 3444 3445 return 0; 3446 } 3447 3448 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3449 { 3450 struct mtk_mac *mac = netdev_priv(dev); 3451 3452 switch (cmd) { 3453 case SIOCGMIIPHY: 3454 case SIOCGMIIREG: 3455 case SIOCSMIIREG: 3456 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 3457 default: 3458 break; 3459 } 3460 3461 return -EOPNOTSUPP; 3462 } 3463 3464 static void mtk_pending_work(struct work_struct *work) 3465 { 3466 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 3467 int err, i; 3468 unsigned long restart = 0; 3469 3470 rtnl_lock(); 3471 3472 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 3473 3474 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 3475 cpu_relax(); 3476 3477 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 3478 /* stop all devices to make sure that dma is properly shut down */ 3479 for (i = 0; i < MTK_MAC_COUNT; i++) { 3480 if (!eth->netdev[i]) 3481 continue; 3482 mtk_stop(eth->netdev[i]); 3483 __set_bit(i, &restart); 3484 } 3485 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 3486 3487 /* restart underlying hardware such as power, clock, pin mux 3488 * and the connected phy 3489 */ 3490 mtk_hw_deinit(eth); 3491 3492 if (eth->dev->pins) 3493 pinctrl_select_state(eth->dev->pins->p, 3494 eth->dev->pins->default_state); 3495 mtk_hw_init(eth); 3496 3497 /* restart DMA and enable IRQs */ 3498 for (i = 0; i < MTK_MAC_COUNT; i++) { 3499 if (!test_bit(i, &restart)) 3500 continue; 3501 err = mtk_open(eth->netdev[i]); 3502 if (err) { 3503 netif_alert(eth, ifup, eth->netdev[i], 3504 "Driver up/down cycle failed, closing device.\n"); 3505 dev_close(eth->netdev[i]); 3506 } 3507 } 3508 3509 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 3510 3511 clear_bit_unlock(MTK_RESETTING, ð->state); 3512 3513 rtnl_unlock(); 3514 } 3515 3516 static int mtk_free_dev(struct mtk_eth *eth) 3517 { 3518 int i; 3519 3520 for (i = 0; i < MTK_MAC_COUNT; i++) { 3521 if (!eth->netdev[i]) 3522 continue; 3523 free_netdev(eth->netdev[i]); 3524 } 3525 3526 return 0; 3527 } 3528 3529 static int mtk_unreg_dev(struct mtk_eth *eth) 3530 { 3531 int i; 3532 3533 for (i = 0; i < MTK_MAC_COUNT; i++) { 3534 if (!eth->netdev[i]) 3535 continue; 3536 unregister_netdev(eth->netdev[i]); 3537 } 3538 3539 return 0; 3540 } 3541 3542 static int mtk_cleanup(struct mtk_eth *eth) 3543 { 3544 mtk_unreg_dev(eth); 3545 mtk_free_dev(eth); 3546 cancel_work_sync(ð->pending_work); 3547 3548 return 0; 3549 } 3550 3551 static int mtk_get_link_ksettings(struct net_device *ndev, 3552 struct ethtool_link_ksettings *cmd) 3553 { 3554 struct mtk_mac *mac = netdev_priv(ndev); 3555 3556 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3557 return -EBUSY; 3558 3559 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 3560 } 3561 3562 static int mtk_set_link_ksettings(struct net_device *ndev, 3563 const struct ethtool_link_ksettings *cmd) 3564 { 3565 struct mtk_mac *mac = netdev_priv(ndev); 3566 3567 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3568 return -EBUSY; 3569 3570 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 3571 } 3572 3573 static void mtk_get_drvinfo(struct net_device *dev, 3574 struct ethtool_drvinfo *info) 3575 { 3576 struct mtk_mac *mac = netdev_priv(dev); 3577 3578 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 3579 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 3580 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 3581 } 3582 3583 static u32 mtk_get_msglevel(struct net_device *dev) 3584 { 3585 struct mtk_mac *mac = netdev_priv(dev); 3586 3587 return mac->hw->msg_enable; 3588 } 3589 3590 static void mtk_set_msglevel(struct net_device *dev, u32 value) 3591 { 3592 struct mtk_mac *mac = netdev_priv(dev); 3593 3594 mac->hw->msg_enable = value; 3595 } 3596 3597 static int mtk_nway_reset(struct net_device *dev) 3598 { 3599 struct mtk_mac *mac = netdev_priv(dev); 3600 3601 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3602 return -EBUSY; 3603 3604 if (!mac->phylink) 3605 return -ENOTSUPP; 3606 3607 return phylink_ethtool_nway_reset(mac->phylink); 3608 } 3609 3610 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3611 { 3612 int i; 3613 3614 switch (stringset) { 3615 case ETH_SS_STATS: { 3616 struct mtk_mac *mac = netdev_priv(dev); 3617 3618 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 3619 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 3620 data += ETH_GSTRING_LEN; 3621 } 3622 if (mtk_page_pool_enabled(mac->hw)) 3623 page_pool_ethtool_stats_get_strings(data); 3624 break; 3625 } 3626 default: 3627 break; 3628 } 3629 } 3630 3631 static int mtk_get_sset_count(struct net_device *dev, int sset) 3632 { 3633 switch (sset) { 3634 case ETH_SS_STATS: { 3635 int count = ARRAY_SIZE(mtk_ethtool_stats); 3636 struct mtk_mac *mac = netdev_priv(dev); 3637 3638 if (mtk_page_pool_enabled(mac->hw)) 3639 count += page_pool_ethtool_stats_get_count(); 3640 return count; 3641 } 3642 default: 3643 return -EOPNOTSUPP; 3644 } 3645 } 3646 3647 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 3648 { 3649 struct page_pool_stats stats = {}; 3650 int i; 3651 3652 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 3653 struct mtk_rx_ring *ring = ð->rx_ring[i]; 3654 3655 if (!ring->page_pool) 3656 continue; 3657 3658 page_pool_get_stats(ring->page_pool, &stats); 3659 } 3660 page_pool_ethtool_stats_get(data, &stats); 3661 } 3662 3663 static void mtk_get_ethtool_stats(struct net_device *dev, 3664 struct ethtool_stats *stats, u64 *data) 3665 { 3666 struct mtk_mac *mac = netdev_priv(dev); 3667 struct mtk_hw_stats *hwstats = mac->hw_stats; 3668 u64 *data_src, *data_dst; 3669 unsigned int start; 3670 int i; 3671 3672 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3673 return; 3674 3675 if (netif_running(dev) && netif_device_present(dev)) { 3676 if (spin_trylock_bh(&hwstats->stats_lock)) { 3677 mtk_stats_update_mac(mac); 3678 spin_unlock_bh(&hwstats->stats_lock); 3679 } 3680 } 3681 3682 data_src = (u64 *)hwstats; 3683 3684 do { 3685 data_dst = data; 3686 start = u64_stats_fetch_begin(&hwstats->syncp); 3687 3688 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 3689 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 3690 if (mtk_page_pool_enabled(mac->hw)) 3691 mtk_ethtool_pp_stats(mac->hw, data_dst); 3692 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 3693 } 3694 3695 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 3696 u32 *rule_locs) 3697 { 3698 int ret = -EOPNOTSUPP; 3699 3700 switch (cmd->cmd) { 3701 case ETHTOOL_GRXRINGS: 3702 if (dev->hw_features & NETIF_F_LRO) { 3703 cmd->data = MTK_MAX_RX_RING_NUM; 3704 ret = 0; 3705 } 3706 break; 3707 case ETHTOOL_GRXCLSRLCNT: 3708 if (dev->hw_features & NETIF_F_LRO) { 3709 struct mtk_mac *mac = netdev_priv(dev); 3710 3711 cmd->rule_cnt = mac->hwlro_ip_cnt; 3712 ret = 0; 3713 } 3714 break; 3715 case ETHTOOL_GRXCLSRULE: 3716 if (dev->hw_features & NETIF_F_LRO) 3717 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 3718 break; 3719 case ETHTOOL_GRXCLSRLALL: 3720 if (dev->hw_features & NETIF_F_LRO) 3721 ret = mtk_hwlro_get_fdir_all(dev, cmd, 3722 rule_locs); 3723 break; 3724 default: 3725 break; 3726 } 3727 3728 return ret; 3729 } 3730 3731 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 3732 { 3733 int ret = -EOPNOTSUPP; 3734 3735 switch (cmd->cmd) { 3736 case ETHTOOL_SRXCLSRLINS: 3737 if (dev->hw_features & NETIF_F_LRO) 3738 ret = mtk_hwlro_add_ipaddr(dev, cmd); 3739 break; 3740 case ETHTOOL_SRXCLSRLDEL: 3741 if (dev->hw_features & NETIF_F_LRO) 3742 ret = mtk_hwlro_del_ipaddr(dev, cmd); 3743 break; 3744 default: 3745 break; 3746 } 3747 3748 return ret; 3749 } 3750 3751 static const struct ethtool_ops mtk_ethtool_ops = { 3752 .get_link_ksettings = mtk_get_link_ksettings, 3753 .set_link_ksettings = mtk_set_link_ksettings, 3754 .get_drvinfo = mtk_get_drvinfo, 3755 .get_msglevel = mtk_get_msglevel, 3756 .set_msglevel = mtk_set_msglevel, 3757 .nway_reset = mtk_nway_reset, 3758 .get_link = ethtool_op_get_link, 3759 .get_strings = mtk_get_strings, 3760 .get_sset_count = mtk_get_sset_count, 3761 .get_ethtool_stats = mtk_get_ethtool_stats, 3762 .get_rxnfc = mtk_get_rxnfc, 3763 .set_rxnfc = mtk_set_rxnfc, 3764 }; 3765 3766 static const struct net_device_ops mtk_netdev_ops = { 3767 .ndo_init = mtk_init, 3768 .ndo_uninit = mtk_uninit, 3769 .ndo_open = mtk_open, 3770 .ndo_stop = mtk_stop, 3771 .ndo_start_xmit = mtk_start_xmit, 3772 .ndo_set_mac_address = mtk_set_mac_address, 3773 .ndo_validate_addr = eth_validate_addr, 3774 .ndo_eth_ioctl = mtk_do_ioctl, 3775 .ndo_change_mtu = mtk_change_mtu, 3776 .ndo_tx_timeout = mtk_tx_timeout, 3777 .ndo_get_stats64 = mtk_get_stats64, 3778 .ndo_fix_features = mtk_fix_features, 3779 .ndo_set_features = mtk_set_features, 3780 #ifdef CONFIG_NET_POLL_CONTROLLER 3781 .ndo_poll_controller = mtk_poll_controller, 3782 #endif 3783 .ndo_setup_tc = mtk_eth_setup_tc, 3784 .ndo_bpf = mtk_xdp, 3785 .ndo_xdp_xmit = mtk_xdp_xmit, 3786 }; 3787 3788 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 3789 { 3790 const __be32 *_id = of_get_property(np, "reg", NULL); 3791 phy_interface_t phy_mode; 3792 struct phylink *phylink; 3793 struct mtk_mac *mac; 3794 int id, err; 3795 3796 if (!_id) { 3797 dev_err(eth->dev, "missing mac id\n"); 3798 return -EINVAL; 3799 } 3800 3801 id = be32_to_cpup(_id); 3802 if (id >= MTK_MAC_COUNT) { 3803 dev_err(eth->dev, "%d is not a valid mac id\n", id); 3804 return -EINVAL; 3805 } 3806 3807 if (eth->netdev[id]) { 3808 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 3809 return -EINVAL; 3810 } 3811 3812 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 3813 if (!eth->netdev[id]) { 3814 dev_err(eth->dev, "alloc_etherdev failed\n"); 3815 return -ENOMEM; 3816 } 3817 mac = netdev_priv(eth->netdev[id]); 3818 eth->mac[id] = mac; 3819 mac->id = id; 3820 mac->hw = eth; 3821 mac->of_node = np; 3822 3823 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 3824 mac->hwlro_ip_cnt = 0; 3825 3826 mac->hw_stats = devm_kzalloc(eth->dev, 3827 sizeof(*mac->hw_stats), 3828 GFP_KERNEL); 3829 if (!mac->hw_stats) { 3830 dev_err(eth->dev, "failed to allocate counter memory\n"); 3831 err = -ENOMEM; 3832 goto free_netdev; 3833 } 3834 spin_lock_init(&mac->hw_stats->stats_lock); 3835 u64_stats_init(&mac->hw_stats->syncp); 3836 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 3837 3838 /* phylink create */ 3839 err = of_get_phy_mode(np, &phy_mode); 3840 if (err) { 3841 dev_err(eth->dev, "incorrect phy-mode\n"); 3842 goto free_netdev; 3843 } 3844 3845 /* mac config is not set */ 3846 mac->interface = PHY_INTERFACE_MODE_NA; 3847 mac->speed = SPEED_UNKNOWN; 3848 3849 mac->phylink_config.dev = ð->netdev[id]->dev; 3850 mac->phylink_config.type = PHYLINK_NETDEV; 3851 /* This driver makes use of state->speed in mac_config */ 3852 mac->phylink_config.legacy_pre_march2020 = true; 3853 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 3854 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 3855 3856 __set_bit(PHY_INTERFACE_MODE_MII, 3857 mac->phylink_config.supported_interfaces); 3858 __set_bit(PHY_INTERFACE_MODE_GMII, 3859 mac->phylink_config.supported_interfaces); 3860 3861 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 3862 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 3863 3864 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 3865 __set_bit(PHY_INTERFACE_MODE_TRGMII, 3866 mac->phylink_config.supported_interfaces); 3867 3868 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 3869 __set_bit(PHY_INTERFACE_MODE_SGMII, 3870 mac->phylink_config.supported_interfaces); 3871 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 3872 mac->phylink_config.supported_interfaces); 3873 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 3874 mac->phylink_config.supported_interfaces); 3875 } 3876 3877 phylink = phylink_create(&mac->phylink_config, 3878 of_fwnode_handle(mac->of_node), 3879 phy_mode, &mtk_phylink_ops); 3880 if (IS_ERR(phylink)) { 3881 err = PTR_ERR(phylink); 3882 goto free_netdev; 3883 } 3884 3885 mac->phylink = phylink; 3886 3887 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 3888 eth->netdev[id]->watchdog_timeo = 5 * HZ; 3889 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 3890 eth->netdev[id]->base_addr = (unsigned long)eth->base; 3891 3892 eth->netdev[id]->hw_features = eth->soc->hw_features; 3893 if (eth->hwlro) 3894 eth->netdev[id]->hw_features |= NETIF_F_LRO; 3895 3896 eth->netdev[id]->vlan_features = eth->soc->hw_features & 3897 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 3898 eth->netdev[id]->features |= eth->soc->hw_features; 3899 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 3900 3901 eth->netdev[id]->irq = eth->irq[0]; 3902 eth->netdev[id]->dev.of_node = np; 3903 3904 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3905 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 3906 else 3907 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 3908 3909 return 0; 3910 3911 free_netdev: 3912 free_netdev(eth->netdev[id]); 3913 return err; 3914 } 3915 3916 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 3917 { 3918 struct net_device *dev, *tmp; 3919 LIST_HEAD(dev_list); 3920 int i; 3921 3922 rtnl_lock(); 3923 3924 for (i = 0; i < MTK_MAC_COUNT; i++) { 3925 dev = eth->netdev[i]; 3926 3927 if (!dev || !(dev->flags & IFF_UP)) 3928 continue; 3929 3930 list_add_tail(&dev->close_list, &dev_list); 3931 } 3932 3933 dev_close_many(&dev_list, false); 3934 3935 eth->dma_dev = dma_dev; 3936 3937 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 3938 list_del_init(&dev->close_list); 3939 dev_open(dev, NULL); 3940 } 3941 3942 rtnl_unlock(); 3943 } 3944 3945 static int mtk_probe(struct platform_device *pdev) 3946 { 3947 struct resource *res = NULL; 3948 struct device_node *mac_np; 3949 struct mtk_eth *eth; 3950 int err, i; 3951 3952 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 3953 if (!eth) 3954 return -ENOMEM; 3955 3956 eth->soc = of_device_get_match_data(&pdev->dev); 3957 3958 eth->dev = &pdev->dev; 3959 eth->dma_dev = &pdev->dev; 3960 eth->base = devm_platform_ioremap_resource(pdev, 0); 3961 if (IS_ERR(eth->base)) 3962 return PTR_ERR(eth->base); 3963 3964 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3965 eth->ip_align = NET_IP_ALIGN; 3966 3967 spin_lock_init(ð->page_lock); 3968 spin_lock_init(ð->tx_irq_lock); 3969 spin_lock_init(ð->rx_irq_lock); 3970 spin_lock_init(ð->dim_lock); 3971 3972 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3973 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 3974 3975 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3976 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 3977 3978 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3979 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3980 "mediatek,ethsys"); 3981 if (IS_ERR(eth->ethsys)) { 3982 dev_err(&pdev->dev, "no ethsys regmap found\n"); 3983 return PTR_ERR(eth->ethsys); 3984 } 3985 } 3986 3987 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 3988 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3989 "mediatek,infracfg"); 3990 if (IS_ERR(eth->infra)) { 3991 dev_err(&pdev->dev, "no infracfg regmap found\n"); 3992 return PTR_ERR(eth->infra); 3993 } 3994 } 3995 3996 if (of_dma_is_coherent(pdev->dev.of_node)) { 3997 struct regmap *cci; 3998 3999 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4000 "cci-control-port"); 4001 /* enable CPU/bus coherency */ 4002 if (!IS_ERR(cci)) 4003 regmap_write(cci, 0, 3); 4004 } 4005 4006 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4007 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 4008 GFP_KERNEL); 4009 if (!eth->sgmii) 4010 return -ENOMEM; 4011 4012 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 4013 eth->soc->ana_rgc3); 4014 4015 if (err) 4016 return err; 4017 } 4018 4019 if (eth->soc->required_pctl) { 4020 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4021 "mediatek,pctl"); 4022 if (IS_ERR(eth->pctl)) { 4023 dev_err(&pdev->dev, "no pctl regmap found\n"); 4024 return PTR_ERR(eth->pctl); 4025 } 4026 } 4027 4028 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 4029 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4030 if (!res) 4031 return -EINVAL; 4032 } 4033 4034 if (eth->soc->offload_version) { 4035 for (i = 0;; i++) { 4036 struct device_node *np; 4037 phys_addr_t wdma_phy; 4038 u32 wdma_base; 4039 4040 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4041 break; 4042 4043 np = of_parse_phandle(pdev->dev.of_node, 4044 "mediatek,wed", i); 4045 if (!np) 4046 break; 4047 4048 wdma_base = eth->soc->reg_map->wdma_base[i]; 4049 wdma_phy = res ? res->start + wdma_base : 0; 4050 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4051 wdma_phy, i); 4052 } 4053 } 4054 4055 for (i = 0; i < 3; i++) { 4056 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4057 eth->irq[i] = eth->irq[0]; 4058 else 4059 eth->irq[i] = platform_get_irq(pdev, i); 4060 if (eth->irq[i] < 0) { 4061 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4062 err = -ENXIO; 4063 goto err_wed_exit; 4064 } 4065 } 4066 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4067 eth->clks[i] = devm_clk_get(eth->dev, 4068 mtk_clks_source_name[i]); 4069 if (IS_ERR(eth->clks[i])) { 4070 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 4071 err = -EPROBE_DEFER; 4072 goto err_wed_exit; 4073 } 4074 if (eth->soc->required_clks & BIT(i)) { 4075 dev_err(&pdev->dev, "clock %s not found\n", 4076 mtk_clks_source_name[i]); 4077 err = -EINVAL; 4078 goto err_wed_exit; 4079 } 4080 eth->clks[i] = NULL; 4081 } 4082 } 4083 4084 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 4085 INIT_WORK(ð->pending_work, mtk_pending_work); 4086 4087 err = mtk_hw_init(eth); 4088 if (err) 4089 goto err_wed_exit; 4090 4091 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 4092 4093 for_each_child_of_node(pdev->dev.of_node, mac_np) { 4094 if (!of_device_is_compatible(mac_np, 4095 "mediatek,eth-mac")) 4096 continue; 4097 4098 if (!of_device_is_available(mac_np)) 4099 continue; 4100 4101 err = mtk_add_mac(eth, mac_np); 4102 if (err) { 4103 of_node_put(mac_np); 4104 goto err_deinit_hw; 4105 } 4106 } 4107 4108 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 4109 err = devm_request_irq(eth->dev, eth->irq[0], 4110 mtk_handle_irq, 0, 4111 dev_name(eth->dev), eth); 4112 } else { 4113 err = devm_request_irq(eth->dev, eth->irq[1], 4114 mtk_handle_irq_tx, 0, 4115 dev_name(eth->dev), eth); 4116 if (err) 4117 goto err_free_dev; 4118 4119 err = devm_request_irq(eth->dev, eth->irq[2], 4120 mtk_handle_irq_rx, 0, 4121 dev_name(eth->dev), eth); 4122 } 4123 if (err) 4124 goto err_free_dev; 4125 4126 /* No MT7628/88 support yet */ 4127 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4128 err = mtk_mdio_init(eth); 4129 if (err) 4130 goto err_free_dev; 4131 } 4132 4133 if (eth->soc->offload_version) { 4134 u32 num_ppe; 4135 4136 num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; 4137 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); 4138 for (i = 0; i < num_ppe; i++) { 4139 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; 4140 4141 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, 4142 eth->soc->offload_version, i); 4143 if (!eth->ppe[i]) { 4144 err = -ENOMEM; 4145 goto err_free_dev; 4146 } 4147 } 4148 4149 err = mtk_eth_offload_init(eth); 4150 if (err) 4151 goto err_free_dev; 4152 } 4153 4154 for (i = 0; i < MTK_MAX_DEVS; i++) { 4155 if (!eth->netdev[i]) 4156 continue; 4157 4158 err = register_netdev(eth->netdev[i]); 4159 if (err) { 4160 dev_err(eth->dev, "error bringing up device\n"); 4161 goto err_deinit_mdio; 4162 } else 4163 netif_info(eth, probe, eth->netdev[i], 4164 "mediatek frame engine at 0x%08lx, irq %d\n", 4165 eth->netdev[i]->base_addr, eth->irq[0]); 4166 } 4167 4168 /* we run 2 devices on the same DMA ring so we need a dummy device 4169 * for NAPI to work 4170 */ 4171 init_dummy_netdev(ð->dummy_dev); 4172 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx); 4173 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx); 4174 4175 platform_set_drvdata(pdev, eth); 4176 4177 return 0; 4178 4179 err_deinit_mdio: 4180 mtk_mdio_cleanup(eth); 4181 err_free_dev: 4182 mtk_free_dev(eth); 4183 err_deinit_hw: 4184 mtk_hw_deinit(eth); 4185 err_wed_exit: 4186 mtk_wed_exit(); 4187 4188 return err; 4189 } 4190 4191 static int mtk_remove(struct platform_device *pdev) 4192 { 4193 struct mtk_eth *eth = platform_get_drvdata(pdev); 4194 struct mtk_mac *mac; 4195 int i; 4196 4197 /* stop all devices to make sure that dma is properly shut down */ 4198 for (i = 0; i < MTK_MAC_COUNT; i++) { 4199 if (!eth->netdev[i]) 4200 continue; 4201 mtk_stop(eth->netdev[i]); 4202 mac = netdev_priv(eth->netdev[i]); 4203 phylink_disconnect_phy(mac->phylink); 4204 } 4205 4206 mtk_wed_exit(); 4207 mtk_hw_deinit(eth); 4208 4209 netif_napi_del(ð->tx_napi); 4210 netif_napi_del(ð->rx_napi); 4211 mtk_cleanup(eth); 4212 mtk_mdio_cleanup(eth); 4213 4214 return 0; 4215 } 4216 4217 static const struct mtk_soc_data mt2701_data = { 4218 .reg_map = &mtk_reg_map, 4219 .caps = MT7623_CAPS | MTK_HWLRO, 4220 .hw_features = MTK_HW_FEATURES, 4221 .required_clks = MT7623_CLKS_BITMAP, 4222 .required_pctl = true, 4223 .txrx = { 4224 .txd_size = sizeof(struct mtk_tx_dma), 4225 .rxd_size = sizeof(struct mtk_rx_dma), 4226 .rx_irq_done_mask = MTK_RX_DONE_INT, 4227 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4228 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4229 .dma_len_offset = 16, 4230 }, 4231 }; 4232 4233 static const struct mtk_soc_data mt7621_data = { 4234 .reg_map = &mtk_reg_map, 4235 .caps = MT7621_CAPS, 4236 .hw_features = MTK_HW_FEATURES, 4237 .required_clks = MT7621_CLKS_BITMAP, 4238 .required_pctl = false, 4239 .offload_version = 2, 4240 .hash_offset = 2, 4241 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4242 .txrx = { 4243 .txd_size = sizeof(struct mtk_tx_dma), 4244 .rxd_size = sizeof(struct mtk_rx_dma), 4245 .rx_irq_done_mask = MTK_RX_DONE_INT, 4246 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4247 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4248 .dma_len_offset = 16, 4249 }, 4250 }; 4251 4252 static const struct mtk_soc_data mt7622_data = { 4253 .reg_map = &mtk_reg_map, 4254 .ana_rgc3 = 0x2028, 4255 .caps = MT7622_CAPS | MTK_HWLRO, 4256 .hw_features = MTK_HW_FEATURES, 4257 .required_clks = MT7622_CLKS_BITMAP, 4258 .required_pctl = false, 4259 .offload_version = 2, 4260 .hash_offset = 2, 4261 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4262 .txrx = { 4263 .txd_size = sizeof(struct mtk_tx_dma), 4264 .rxd_size = sizeof(struct mtk_rx_dma), 4265 .rx_irq_done_mask = MTK_RX_DONE_INT, 4266 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4267 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4268 .dma_len_offset = 16, 4269 }, 4270 }; 4271 4272 static const struct mtk_soc_data mt7623_data = { 4273 .reg_map = &mtk_reg_map, 4274 .caps = MT7623_CAPS | MTK_HWLRO, 4275 .hw_features = MTK_HW_FEATURES, 4276 .required_clks = MT7623_CLKS_BITMAP, 4277 .required_pctl = true, 4278 .offload_version = 2, 4279 .hash_offset = 2, 4280 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4281 .txrx = { 4282 .txd_size = sizeof(struct mtk_tx_dma), 4283 .rxd_size = sizeof(struct mtk_rx_dma), 4284 .rx_irq_done_mask = MTK_RX_DONE_INT, 4285 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4286 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4287 .dma_len_offset = 16, 4288 }, 4289 }; 4290 4291 static const struct mtk_soc_data mt7629_data = { 4292 .reg_map = &mtk_reg_map, 4293 .ana_rgc3 = 0x128, 4294 .caps = MT7629_CAPS | MTK_HWLRO, 4295 .hw_features = MTK_HW_FEATURES, 4296 .required_clks = MT7629_CLKS_BITMAP, 4297 .required_pctl = false, 4298 .txrx = { 4299 .txd_size = sizeof(struct mtk_tx_dma), 4300 .rxd_size = sizeof(struct mtk_rx_dma), 4301 .rx_irq_done_mask = MTK_RX_DONE_INT, 4302 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4303 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4304 .dma_len_offset = 16, 4305 }, 4306 }; 4307 4308 static const struct mtk_soc_data mt7986_data = { 4309 .reg_map = &mt7986_reg_map, 4310 .ana_rgc3 = 0x128, 4311 .caps = MT7986_CAPS, 4312 .hw_features = MTK_HW_FEATURES, 4313 .required_clks = MT7986_CLKS_BITMAP, 4314 .required_pctl = false, 4315 .hash_offset = 4, 4316 .foe_entry_size = sizeof(struct mtk_foe_entry), 4317 .txrx = { 4318 .txd_size = sizeof(struct mtk_tx_dma_v2), 4319 .rxd_size = sizeof(struct mtk_rx_dma_v2), 4320 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 4321 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 4322 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 4323 .dma_len_offset = 8, 4324 }, 4325 }; 4326 4327 static const struct mtk_soc_data rt5350_data = { 4328 .reg_map = &mt7628_reg_map, 4329 .caps = MT7628_CAPS, 4330 .hw_features = MTK_HW_FEATURES_MT7628, 4331 .required_clks = MT7628_CLKS_BITMAP, 4332 .required_pctl = false, 4333 .txrx = { 4334 .txd_size = sizeof(struct mtk_tx_dma), 4335 .rxd_size = sizeof(struct mtk_rx_dma), 4336 .rx_irq_done_mask = MTK_RX_DONE_INT, 4337 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, 4338 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4339 .dma_len_offset = 16, 4340 }, 4341 }; 4342 4343 const struct of_device_id of_mtk_match[] = { 4344 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 4345 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 4346 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 4347 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 4348 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 4349 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, 4350 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 4351 {}, 4352 }; 4353 MODULE_DEVICE_TABLE(of, of_mtk_match); 4354 4355 static struct platform_driver mtk_driver = { 4356 .probe = mtk_probe, 4357 .remove = mtk_remove, 4358 .driver = { 4359 .name = "mtk_soc_eth", 4360 .of_match_table = of_mtk_match, 4361 }, 4362 }; 4363 4364 module_platform_driver(mtk_driver); 4365 4366 MODULE_LICENSE("GPL"); 4367 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 4368 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 4369