1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #include <linux/of_device.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/regmap.h> 20 #include <linux/clk.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/if_vlan.h> 23 #include <linux/reset.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/pinctrl/devinfo.h> 27 28 #include "mtk_eth_soc.h" 29 30 static int mtk_msg_level = -1; 31 module_param_named(msg_level, mtk_msg_level, int, 0); 32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 33 34 #define MTK_ETHTOOL_STAT(x) { #x, \ 35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 36 37 /* strings used by ethtool */ 38 static const struct mtk_ethtool_stats { 39 char str[ETH_GSTRING_LEN]; 40 u32 offset; 41 } mtk_ethtool_stats[] = { 42 MTK_ETHTOOL_STAT(tx_bytes), 43 MTK_ETHTOOL_STAT(tx_packets), 44 MTK_ETHTOOL_STAT(tx_skip), 45 MTK_ETHTOOL_STAT(tx_collisions), 46 MTK_ETHTOOL_STAT(rx_bytes), 47 MTK_ETHTOOL_STAT(rx_packets), 48 MTK_ETHTOOL_STAT(rx_overflow), 49 MTK_ETHTOOL_STAT(rx_fcs_errors), 50 MTK_ETHTOOL_STAT(rx_short_errors), 51 MTK_ETHTOOL_STAT(rx_long_errors), 52 MTK_ETHTOOL_STAT(rx_checksum_errors), 53 MTK_ETHTOOL_STAT(rx_flow_control_packets), 54 }; 55 56 static const char * const mtk_clks_source_name[] = { 57 "ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m", 58 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" 59 }; 60 61 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 62 { 63 __raw_writel(val, eth->base + reg); 64 } 65 66 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 67 { 68 return __raw_readl(eth->base + reg); 69 } 70 71 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 72 { 73 unsigned long t_start = jiffies; 74 75 while (1) { 76 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 77 return 0; 78 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 79 break; 80 usleep_range(10, 20); 81 } 82 83 dev_err(eth->dev, "mdio: MDIO timeout\n"); 84 return -1; 85 } 86 87 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 88 u32 phy_register, u32 write_data) 89 { 90 if (mtk_mdio_busy_wait(eth)) 91 return -1; 92 93 write_data &= 0xffff; 94 95 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 96 (phy_register << PHY_IAC_REG_SHIFT) | 97 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 98 MTK_PHY_IAC); 99 100 if (mtk_mdio_busy_wait(eth)) 101 return -1; 102 103 return 0; 104 } 105 106 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 107 { 108 u32 d; 109 110 if (mtk_mdio_busy_wait(eth)) 111 return 0xffff; 112 113 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 114 (phy_reg << PHY_IAC_REG_SHIFT) | 115 (phy_addr << PHY_IAC_ADDR_SHIFT), 116 MTK_PHY_IAC); 117 118 if (mtk_mdio_busy_wait(eth)) 119 return 0xffff; 120 121 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 122 123 return d; 124 } 125 126 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 127 int phy_reg, u16 val) 128 { 129 struct mtk_eth *eth = bus->priv; 130 131 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 132 } 133 134 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 135 { 136 struct mtk_eth *eth = bus->priv; 137 138 return _mtk_mdio_read(eth, phy_addr, phy_reg); 139 } 140 141 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 142 { 143 u32 val; 144 int ret; 145 146 val = (speed == SPEED_1000) ? 147 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 148 mtk_w32(eth, val, INTF_MODE); 149 150 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 151 ETHSYS_TRGMII_CLK_SEL362_5, 152 ETHSYS_TRGMII_CLK_SEL362_5); 153 154 val = (speed == SPEED_1000) ? 250000000 : 500000000; 155 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 156 if (ret) 157 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 158 159 val = (speed == SPEED_1000) ? 160 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 161 mtk_w32(eth, val, TRGMII_RCK_CTRL); 162 163 val = (speed == SPEED_1000) ? 164 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 165 mtk_w32(eth, val, TRGMII_TCK_CTRL); 166 } 167 168 static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id) 169 { 170 u32 val; 171 172 /* Setup the link timer and QPHY power up inside SGMIISYS */ 173 regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER, 174 SGMII_LINK_TIMER_DEFAULT); 175 176 regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val); 177 val |= SGMII_REMOTE_FAULT_DIS; 178 regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val); 179 180 regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val); 181 val |= SGMII_AN_RESTART; 182 regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val); 183 184 regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val); 185 val &= ~SGMII_PHYA_PWD; 186 regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val); 187 188 /* Determine MUX for which GMAC uses the SGMII interface */ 189 if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) { 190 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 191 val &= ~SYSCFG0_SGMII_MASK; 192 val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2; 193 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 194 195 dev_info(eth->dev, "setup shared sgmii for gmac=%d\n", 196 mac_id); 197 } 198 199 /* Setup the GMAC1 going through SGMII path when SoC also support 200 * ESW on GMAC1 201 */ 202 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) && 203 !mac_id) { 204 mtk_w32(eth, 0, MTK_MAC_MISC); 205 dev_info(eth->dev, "setup gmac1 going through sgmii"); 206 } 207 } 208 209 static void mtk_phy_link_adjust(struct net_device *dev) 210 { 211 struct mtk_mac *mac = netdev_priv(dev); 212 u16 lcl_adv = 0, rmt_adv = 0; 213 u8 flowctrl; 214 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 215 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 216 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 217 MAC_MCR_BACKPR_EN; 218 219 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 220 return; 221 222 switch (dev->phydev->speed) { 223 case SPEED_1000: 224 mcr |= MAC_MCR_SPEED_1000; 225 break; 226 case SPEED_100: 227 mcr |= MAC_MCR_SPEED_100; 228 break; 229 }; 230 231 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 232 !mac->id && !mac->trgmii) 233 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed); 234 235 if (dev->phydev->link) 236 mcr |= MAC_MCR_FORCE_LINK; 237 238 if (dev->phydev->duplex) { 239 mcr |= MAC_MCR_FORCE_DPX; 240 241 if (dev->phydev->pause) 242 rmt_adv = LPA_PAUSE_CAP; 243 if (dev->phydev->asym_pause) 244 rmt_adv |= LPA_PAUSE_ASYM; 245 246 if (dev->phydev->advertising & ADVERTISED_Pause) 247 lcl_adv |= ADVERTISE_PAUSE_CAP; 248 if (dev->phydev->advertising & ADVERTISED_Asym_Pause) 249 lcl_adv |= ADVERTISE_PAUSE_ASYM; 250 251 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 252 253 if (flowctrl & FLOW_CTRL_TX) 254 mcr |= MAC_MCR_FORCE_TX_FC; 255 if (flowctrl & FLOW_CTRL_RX) 256 mcr |= MAC_MCR_FORCE_RX_FC; 257 258 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 259 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 260 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 261 } 262 263 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 264 265 if (dev->phydev->link) 266 netif_carrier_on(dev); 267 else 268 netif_carrier_off(dev); 269 270 if (!of_phy_is_fixed_link(mac->of_node)) 271 phy_print_status(dev->phydev); 272 } 273 274 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 275 struct device_node *phy_node) 276 { 277 struct phy_device *phydev; 278 int phy_mode; 279 280 phy_mode = of_get_phy_mode(phy_node); 281 if (phy_mode < 0) { 282 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 283 return -EINVAL; 284 } 285 286 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 287 mtk_phy_link_adjust, 0, phy_mode); 288 if (!phydev) { 289 dev_err(eth->dev, "could not connect to PHY\n"); 290 return -ENODEV; 291 } 292 293 dev_info(eth->dev, 294 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 295 mac->id, phydev_name(phydev), phydev->phy_id, 296 phydev->drv->name); 297 298 return 0; 299 } 300 301 static int mtk_phy_connect(struct net_device *dev) 302 { 303 struct mtk_mac *mac = netdev_priv(dev); 304 struct mtk_eth *eth; 305 struct device_node *np; 306 u32 val; 307 308 eth = mac->hw; 309 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 310 if (!np && of_phy_is_fixed_link(mac->of_node)) 311 if (!of_phy_register_fixed_link(mac->of_node)) 312 np = of_node_get(mac->of_node); 313 if (!np) 314 return -ENODEV; 315 316 mac->ge_mode = 0; 317 switch (of_get_phy_mode(np)) { 318 case PHY_INTERFACE_MODE_TRGMII: 319 mac->trgmii = true; 320 case PHY_INTERFACE_MODE_RGMII_TXID: 321 case PHY_INTERFACE_MODE_RGMII_RXID: 322 case PHY_INTERFACE_MODE_RGMII_ID: 323 case PHY_INTERFACE_MODE_RGMII: 324 break; 325 case PHY_INTERFACE_MODE_SGMII: 326 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) 327 mtk_gmac_sgmii_hw_setup(eth, mac->id); 328 break; 329 case PHY_INTERFACE_MODE_MII: 330 mac->ge_mode = 1; 331 break; 332 case PHY_INTERFACE_MODE_REVMII: 333 mac->ge_mode = 2; 334 break; 335 case PHY_INTERFACE_MODE_RMII: 336 if (!mac->id) 337 goto err_phy; 338 mac->ge_mode = 3; 339 break; 340 default: 341 goto err_phy; 342 } 343 344 /* put the gmac into the right mode */ 345 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 346 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 347 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id); 348 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 349 350 /* couple phydev to net_device */ 351 if (mtk_phy_connect_node(eth, mac, np)) 352 goto err_phy; 353 354 dev->phydev->autoneg = AUTONEG_ENABLE; 355 dev->phydev->speed = 0; 356 dev->phydev->duplex = 0; 357 358 phy_set_max_speed(dev->phydev, SPEED_1000); 359 phy_support_asym_pause(dev->phydev); 360 dev->phydev->advertising = dev->phydev->supported | 361 ADVERTISED_Autoneg; 362 phy_start_aneg(dev->phydev); 363 364 of_node_put(np); 365 366 return 0; 367 368 err_phy: 369 if (of_phy_is_fixed_link(mac->of_node)) 370 of_phy_deregister_fixed_link(mac->of_node); 371 of_node_put(np); 372 dev_err(eth->dev, "%s: invalid phy\n", __func__); 373 return -EINVAL; 374 } 375 376 static int mtk_mdio_init(struct mtk_eth *eth) 377 { 378 struct device_node *mii_np; 379 int ret; 380 381 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 382 if (!mii_np) { 383 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 384 return -ENODEV; 385 } 386 387 if (!of_device_is_available(mii_np)) { 388 ret = -ENODEV; 389 goto err_put_node; 390 } 391 392 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 393 if (!eth->mii_bus) { 394 ret = -ENOMEM; 395 goto err_put_node; 396 } 397 398 eth->mii_bus->name = "mdio"; 399 eth->mii_bus->read = mtk_mdio_read; 400 eth->mii_bus->write = mtk_mdio_write; 401 eth->mii_bus->priv = eth; 402 eth->mii_bus->parent = eth->dev; 403 404 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 405 ret = of_mdiobus_register(eth->mii_bus, mii_np); 406 407 err_put_node: 408 of_node_put(mii_np); 409 return ret; 410 } 411 412 static void mtk_mdio_cleanup(struct mtk_eth *eth) 413 { 414 if (!eth->mii_bus) 415 return; 416 417 mdiobus_unregister(eth->mii_bus); 418 } 419 420 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 421 { 422 unsigned long flags; 423 u32 val; 424 425 spin_lock_irqsave(ð->tx_irq_lock, flags); 426 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 427 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); 428 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 429 } 430 431 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 432 { 433 unsigned long flags; 434 u32 val; 435 436 spin_lock_irqsave(ð->tx_irq_lock, flags); 437 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 438 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); 439 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 440 } 441 442 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 443 { 444 unsigned long flags; 445 u32 val; 446 447 spin_lock_irqsave(ð->rx_irq_lock, flags); 448 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 449 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 450 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 451 } 452 453 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 454 { 455 unsigned long flags; 456 u32 val; 457 458 spin_lock_irqsave(ð->rx_irq_lock, flags); 459 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 460 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 461 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 462 } 463 464 static int mtk_set_mac_address(struct net_device *dev, void *p) 465 { 466 int ret = eth_mac_addr(dev, p); 467 struct mtk_mac *mac = netdev_priv(dev); 468 const char *macaddr = dev->dev_addr; 469 470 if (ret) 471 return ret; 472 473 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 474 return -EBUSY; 475 476 spin_lock_bh(&mac->hw->page_lock); 477 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 478 MTK_GDMA_MAC_ADRH(mac->id)); 479 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 480 (macaddr[4] << 8) | macaddr[5], 481 MTK_GDMA_MAC_ADRL(mac->id)); 482 spin_unlock_bh(&mac->hw->page_lock); 483 484 return 0; 485 } 486 487 void mtk_stats_update_mac(struct mtk_mac *mac) 488 { 489 struct mtk_hw_stats *hw_stats = mac->hw_stats; 490 unsigned int base = MTK_GDM1_TX_GBCNT; 491 u64 stats; 492 493 base += hw_stats->reg_offset; 494 495 u64_stats_update_begin(&hw_stats->syncp); 496 497 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 498 stats = mtk_r32(mac->hw, base + 0x04); 499 if (stats) 500 hw_stats->rx_bytes += (stats << 32); 501 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 502 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 503 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 504 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 505 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 506 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 507 hw_stats->rx_flow_control_packets += 508 mtk_r32(mac->hw, base + 0x24); 509 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 510 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 511 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 512 stats = mtk_r32(mac->hw, base + 0x34); 513 if (stats) 514 hw_stats->tx_bytes += (stats << 32); 515 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 516 u64_stats_update_end(&hw_stats->syncp); 517 } 518 519 static void mtk_stats_update(struct mtk_eth *eth) 520 { 521 int i; 522 523 for (i = 0; i < MTK_MAC_COUNT; i++) { 524 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 525 continue; 526 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 527 mtk_stats_update_mac(eth->mac[i]); 528 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 529 } 530 } 531 } 532 533 static void mtk_get_stats64(struct net_device *dev, 534 struct rtnl_link_stats64 *storage) 535 { 536 struct mtk_mac *mac = netdev_priv(dev); 537 struct mtk_hw_stats *hw_stats = mac->hw_stats; 538 unsigned int start; 539 540 if (netif_running(dev) && netif_device_present(dev)) { 541 if (spin_trylock_bh(&hw_stats->stats_lock)) { 542 mtk_stats_update_mac(mac); 543 spin_unlock_bh(&hw_stats->stats_lock); 544 } 545 } 546 547 do { 548 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 549 storage->rx_packets = hw_stats->rx_packets; 550 storage->tx_packets = hw_stats->tx_packets; 551 storage->rx_bytes = hw_stats->rx_bytes; 552 storage->tx_bytes = hw_stats->tx_bytes; 553 storage->collisions = hw_stats->tx_collisions; 554 storage->rx_length_errors = hw_stats->rx_short_errors + 555 hw_stats->rx_long_errors; 556 storage->rx_over_errors = hw_stats->rx_overflow; 557 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 558 storage->rx_errors = hw_stats->rx_checksum_errors; 559 storage->tx_aborted_errors = hw_stats->tx_skip; 560 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 561 562 storage->tx_errors = dev->stats.tx_errors; 563 storage->rx_dropped = dev->stats.rx_dropped; 564 storage->tx_dropped = dev->stats.tx_dropped; 565 } 566 567 static inline int mtk_max_frag_size(int mtu) 568 { 569 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 570 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 571 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 572 573 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 574 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 575 } 576 577 static inline int mtk_max_buf_size(int frag_size) 578 { 579 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 580 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 581 582 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 583 584 return buf_size; 585 } 586 587 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 588 struct mtk_rx_dma *dma_rxd) 589 { 590 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 591 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 592 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 593 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 594 } 595 596 /* the qdma core needs scratch memory to be setup */ 597 static int mtk_init_fq_dma(struct mtk_eth *eth) 598 { 599 dma_addr_t phy_ring_tail; 600 int cnt = MTK_DMA_SIZE; 601 dma_addr_t dma_addr; 602 int i; 603 604 eth->scratch_ring = dma_zalloc_coherent(eth->dev, 605 cnt * sizeof(struct mtk_tx_dma), 606 ð->phy_scratch_ring, 607 GFP_ATOMIC); 608 if (unlikely(!eth->scratch_ring)) 609 return -ENOMEM; 610 611 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 612 GFP_KERNEL); 613 if (unlikely(!eth->scratch_head)) 614 return -ENOMEM; 615 616 dma_addr = dma_map_single(eth->dev, 617 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 618 DMA_FROM_DEVICE); 619 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 620 return -ENOMEM; 621 622 phy_ring_tail = eth->phy_scratch_ring + 623 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 624 625 for (i = 0; i < cnt; i++) { 626 eth->scratch_ring[i].txd1 = 627 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 628 if (i < cnt - 1) 629 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 630 ((i + 1) * sizeof(struct mtk_tx_dma))); 631 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 632 } 633 634 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 635 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 636 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 637 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 638 639 return 0; 640 } 641 642 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 643 { 644 void *ret = ring->dma; 645 646 return ret + (desc - ring->phys); 647 } 648 649 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 650 struct mtk_tx_dma *txd) 651 { 652 int idx = txd - ring->dma; 653 654 return &ring->buf[idx]; 655 } 656 657 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 658 { 659 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 660 dma_unmap_single(eth->dev, 661 dma_unmap_addr(tx_buf, dma_addr0), 662 dma_unmap_len(tx_buf, dma_len0), 663 DMA_TO_DEVICE); 664 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 665 dma_unmap_page(eth->dev, 666 dma_unmap_addr(tx_buf, dma_addr0), 667 dma_unmap_len(tx_buf, dma_len0), 668 DMA_TO_DEVICE); 669 } 670 tx_buf->flags = 0; 671 if (tx_buf->skb && 672 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 673 dev_kfree_skb_any(tx_buf->skb); 674 tx_buf->skb = NULL; 675 } 676 677 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 678 int tx_num, struct mtk_tx_ring *ring, bool gso) 679 { 680 struct mtk_mac *mac = netdev_priv(dev); 681 struct mtk_eth *eth = mac->hw; 682 struct mtk_tx_dma *itxd, *txd; 683 struct mtk_tx_buf *itx_buf, *tx_buf; 684 dma_addr_t mapped_addr; 685 unsigned int nr_frags; 686 int i, n_desc = 1; 687 u32 txd4 = 0, fport; 688 689 itxd = ring->next_free; 690 if (itxd == ring->last_free) 691 return -ENOMEM; 692 693 /* set the forward port */ 694 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 695 txd4 |= fport; 696 697 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 698 memset(itx_buf, 0, sizeof(*itx_buf)); 699 700 if (gso) 701 txd4 |= TX_DMA_TSO; 702 703 /* TX Checksum offload */ 704 if (skb->ip_summed == CHECKSUM_PARTIAL) 705 txd4 |= TX_DMA_CHKSUM; 706 707 /* VLAN header offload */ 708 if (skb_vlan_tag_present(skb)) 709 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 710 711 mapped_addr = dma_map_single(eth->dev, skb->data, 712 skb_headlen(skb), DMA_TO_DEVICE); 713 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 714 return -ENOMEM; 715 716 WRITE_ONCE(itxd->txd1, mapped_addr); 717 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 718 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 719 MTK_TX_FLAGS_FPORT1; 720 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr); 721 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb)); 722 723 /* TX SG offload */ 724 txd = itxd; 725 nr_frags = skb_shinfo(skb)->nr_frags; 726 for (i = 0; i < nr_frags; i++) { 727 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 728 unsigned int offset = 0; 729 int frag_size = skb_frag_size(frag); 730 731 while (frag_size) { 732 bool last_frag = false; 733 unsigned int frag_map_size; 734 735 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 736 if (txd == ring->last_free) 737 goto err_dma; 738 739 n_desc++; 740 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 741 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 742 frag_map_size, 743 DMA_TO_DEVICE); 744 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 745 goto err_dma; 746 747 if (i == nr_frags - 1 && 748 (frag_size - frag_map_size) == 0) 749 last_frag = true; 750 751 WRITE_ONCE(txd->txd1, mapped_addr); 752 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 753 TX_DMA_PLEN0(frag_map_size) | 754 last_frag * TX_DMA_LS0)); 755 WRITE_ONCE(txd->txd4, fport); 756 757 tx_buf = mtk_desc_to_tx_buf(ring, txd); 758 memset(tx_buf, 0, sizeof(*tx_buf)); 759 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 760 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 761 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 762 MTK_TX_FLAGS_FPORT1; 763 764 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 765 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 766 frag_size -= frag_map_size; 767 offset += frag_map_size; 768 } 769 } 770 771 /* store skb to cleanup */ 772 itx_buf->skb = skb; 773 774 WRITE_ONCE(itxd->txd4, txd4); 775 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 776 (!nr_frags * TX_DMA_LS0))); 777 778 netdev_sent_queue(dev, skb->len); 779 skb_tx_timestamp(skb); 780 781 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 782 atomic_sub(n_desc, &ring->free_count); 783 784 /* make sure that all changes to the dma ring are flushed before we 785 * continue 786 */ 787 wmb(); 788 789 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more) 790 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 791 792 return 0; 793 794 err_dma: 795 do { 796 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 797 798 /* unmap dma */ 799 mtk_tx_unmap(eth, tx_buf); 800 801 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 802 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 803 } while (itxd != txd); 804 805 return -ENOMEM; 806 } 807 808 static inline int mtk_cal_txd_req(struct sk_buff *skb) 809 { 810 int i, nfrags; 811 struct skb_frag_struct *frag; 812 813 nfrags = 1; 814 if (skb_is_gso(skb)) { 815 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 816 frag = &skb_shinfo(skb)->frags[i]; 817 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); 818 } 819 } else { 820 nfrags += skb_shinfo(skb)->nr_frags; 821 } 822 823 return nfrags; 824 } 825 826 static int mtk_queue_stopped(struct mtk_eth *eth) 827 { 828 int i; 829 830 for (i = 0; i < MTK_MAC_COUNT; i++) { 831 if (!eth->netdev[i]) 832 continue; 833 if (netif_queue_stopped(eth->netdev[i])) 834 return 1; 835 } 836 837 return 0; 838 } 839 840 static void mtk_wake_queue(struct mtk_eth *eth) 841 { 842 int i; 843 844 for (i = 0; i < MTK_MAC_COUNT; i++) { 845 if (!eth->netdev[i]) 846 continue; 847 netif_wake_queue(eth->netdev[i]); 848 } 849 } 850 851 static void mtk_stop_queue(struct mtk_eth *eth) 852 { 853 int i; 854 855 for (i = 0; i < MTK_MAC_COUNT; i++) { 856 if (!eth->netdev[i]) 857 continue; 858 netif_stop_queue(eth->netdev[i]); 859 } 860 } 861 862 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 863 { 864 struct mtk_mac *mac = netdev_priv(dev); 865 struct mtk_eth *eth = mac->hw; 866 struct mtk_tx_ring *ring = ð->tx_ring; 867 struct net_device_stats *stats = &dev->stats; 868 bool gso = false; 869 int tx_num; 870 871 /* normally we can rely on the stack not calling this more than once, 872 * however we have 2 queues running on the same ring so we need to lock 873 * the ring access 874 */ 875 spin_lock(ð->page_lock); 876 877 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 878 goto drop; 879 880 tx_num = mtk_cal_txd_req(skb); 881 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 882 mtk_stop_queue(eth); 883 netif_err(eth, tx_queued, dev, 884 "Tx Ring full when queue awake!\n"); 885 spin_unlock(ð->page_lock); 886 return NETDEV_TX_BUSY; 887 } 888 889 /* TSO: fill MSS info in tcp checksum field */ 890 if (skb_is_gso(skb)) { 891 if (skb_cow_head(skb, 0)) { 892 netif_warn(eth, tx_err, dev, 893 "GSO expand head fail.\n"); 894 goto drop; 895 } 896 897 if (skb_shinfo(skb)->gso_type & 898 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 899 gso = true; 900 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 901 } 902 } 903 904 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 905 goto drop; 906 907 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 908 mtk_stop_queue(eth); 909 910 spin_unlock(ð->page_lock); 911 912 return NETDEV_TX_OK; 913 914 drop: 915 spin_unlock(ð->page_lock); 916 stats->tx_dropped++; 917 dev_kfree_skb_any(skb); 918 return NETDEV_TX_OK; 919 } 920 921 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 922 { 923 int i; 924 struct mtk_rx_ring *ring; 925 int idx; 926 927 if (!eth->hwlro) 928 return ð->rx_ring[0]; 929 930 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 931 ring = ð->rx_ring[i]; 932 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 933 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 934 ring->calc_idx_update = true; 935 return ring; 936 } 937 } 938 939 return NULL; 940 } 941 942 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 943 { 944 struct mtk_rx_ring *ring; 945 int i; 946 947 if (!eth->hwlro) { 948 ring = ð->rx_ring[0]; 949 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 950 } else { 951 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 952 ring = ð->rx_ring[i]; 953 if (ring->calc_idx_update) { 954 ring->calc_idx_update = false; 955 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 956 } 957 } 958 } 959 } 960 961 static int mtk_poll_rx(struct napi_struct *napi, int budget, 962 struct mtk_eth *eth) 963 { 964 struct mtk_rx_ring *ring; 965 int idx; 966 struct sk_buff *skb; 967 u8 *data, *new_data; 968 struct mtk_rx_dma *rxd, trxd; 969 int done = 0; 970 971 while (done < budget) { 972 struct net_device *netdev; 973 unsigned int pktlen; 974 dma_addr_t dma_addr; 975 int mac = 0; 976 977 ring = mtk_get_rx_ring(eth); 978 if (unlikely(!ring)) 979 goto rx_done; 980 981 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 982 rxd = &ring->dma[idx]; 983 data = ring->data[idx]; 984 985 mtk_rx_get_desc(&trxd, rxd); 986 if (!(trxd.rxd2 & RX_DMA_DONE)) 987 break; 988 989 /* find out which mac the packet come from. values start at 1 */ 990 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 991 RX_DMA_FPORT_MASK; 992 mac--; 993 994 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 995 !eth->netdev[mac])) 996 goto release_desc; 997 998 netdev = eth->netdev[mac]; 999 1000 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1001 goto release_desc; 1002 1003 /* alloc new buffer */ 1004 new_data = napi_alloc_frag(ring->frag_size); 1005 if (unlikely(!new_data)) { 1006 netdev->stats.rx_dropped++; 1007 goto release_desc; 1008 } 1009 dma_addr = dma_map_single(eth->dev, 1010 new_data + NET_SKB_PAD, 1011 ring->buf_size, 1012 DMA_FROM_DEVICE); 1013 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 1014 skb_free_frag(new_data); 1015 netdev->stats.rx_dropped++; 1016 goto release_desc; 1017 } 1018 1019 /* receive data */ 1020 skb = build_skb(data, ring->frag_size); 1021 if (unlikely(!skb)) { 1022 skb_free_frag(new_data); 1023 netdev->stats.rx_dropped++; 1024 goto release_desc; 1025 } 1026 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1027 1028 dma_unmap_single(eth->dev, trxd.rxd1, 1029 ring->buf_size, DMA_FROM_DEVICE); 1030 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1031 skb->dev = netdev; 1032 skb_put(skb, pktlen); 1033 if (trxd.rxd4 & RX_DMA_L4_VALID) 1034 skb->ip_summed = CHECKSUM_UNNECESSARY; 1035 else 1036 skb_checksum_none_assert(skb); 1037 skb->protocol = eth_type_trans(skb, netdev); 1038 1039 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1040 RX_DMA_VID(trxd.rxd3)) 1041 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1042 RX_DMA_VID(trxd.rxd3)); 1043 skb_record_rx_queue(skb, 0); 1044 napi_gro_receive(napi, skb); 1045 1046 ring->data[idx] = new_data; 1047 rxd->rxd1 = (unsigned int)dma_addr; 1048 1049 release_desc: 1050 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1051 1052 ring->calc_idx = idx; 1053 1054 done++; 1055 } 1056 1057 rx_done: 1058 if (done) { 1059 /* make sure that all changes to the dma ring are flushed before 1060 * we continue 1061 */ 1062 wmb(); 1063 mtk_update_rx_cpu_idx(eth); 1064 } 1065 1066 return done; 1067 } 1068 1069 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1070 { 1071 struct mtk_tx_ring *ring = ð->tx_ring; 1072 struct mtk_tx_dma *desc; 1073 struct sk_buff *skb; 1074 struct mtk_tx_buf *tx_buf; 1075 unsigned int done[MTK_MAX_DEVS]; 1076 unsigned int bytes[MTK_MAX_DEVS]; 1077 u32 cpu, dma; 1078 int total = 0, i; 1079 1080 memset(done, 0, sizeof(done)); 1081 memset(bytes, 0, sizeof(bytes)); 1082 1083 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1084 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1085 1086 desc = mtk_qdma_phys_to_virt(ring, cpu); 1087 1088 while ((cpu != dma) && budget) { 1089 u32 next_cpu = desc->txd2; 1090 int mac = 0; 1091 1092 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1093 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1094 break; 1095 1096 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1097 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1098 mac = 1; 1099 1100 skb = tx_buf->skb; 1101 if (!skb) 1102 break; 1103 1104 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1105 bytes[mac] += skb->len; 1106 done[mac]++; 1107 budget--; 1108 } 1109 mtk_tx_unmap(eth, tx_buf); 1110 1111 ring->last_free = desc; 1112 atomic_inc(&ring->free_count); 1113 1114 cpu = next_cpu; 1115 } 1116 1117 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1118 1119 for (i = 0; i < MTK_MAC_COUNT; i++) { 1120 if (!eth->netdev[i] || !done[i]) 1121 continue; 1122 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1123 total += done[i]; 1124 } 1125 1126 if (mtk_queue_stopped(eth) && 1127 (atomic_read(&ring->free_count) > ring->thresh)) 1128 mtk_wake_queue(eth); 1129 1130 return total; 1131 } 1132 1133 static void mtk_handle_status_irq(struct mtk_eth *eth) 1134 { 1135 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1136 1137 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1138 mtk_stats_update(eth); 1139 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1140 MTK_INT_STATUS2); 1141 } 1142 } 1143 1144 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1145 { 1146 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1147 u32 status, mask; 1148 int tx_done = 0; 1149 1150 mtk_handle_status_irq(eth); 1151 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 1152 tx_done = mtk_poll_tx(eth, budget); 1153 1154 if (unlikely(netif_msg_intr(eth))) { 1155 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1156 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 1157 dev_info(eth->dev, 1158 "done tx %d, intr 0x%08x/0x%x\n", 1159 tx_done, status, mask); 1160 } 1161 1162 if (tx_done == budget) 1163 return budget; 1164 1165 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1166 if (status & MTK_TX_DONE_INT) 1167 return budget; 1168 1169 napi_complete(napi); 1170 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1171 1172 return tx_done; 1173 } 1174 1175 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1176 { 1177 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1178 u32 status, mask; 1179 int rx_done = 0; 1180 int remain_budget = budget; 1181 1182 mtk_handle_status_irq(eth); 1183 1184 poll_again: 1185 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1186 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1187 1188 if (unlikely(netif_msg_intr(eth))) { 1189 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1190 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1191 dev_info(eth->dev, 1192 "done rx %d, intr 0x%08x/0x%x\n", 1193 rx_done, status, mask); 1194 } 1195 if (rx_done == remain_budget) 1196 return budget; 1197 1198 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1199 if (status & MTK_RX_DONE_INT) { 1200 remain_budget -= rx_done; 1201 goto poll_again; 1202 } 1203 napi_complete(napi); 1204 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1205 1206 return rx_done + budget - remain_budget; 1207 } 1208 1209 static int mtk_tx_alloc(struct mtk_eth *eth) 1210 { 1211 struct mtk_tx_ring *ring = ð->tx_ring; 1212 int i, sz = sizeof(*ring->dma); 1213 1214 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1215 GFP_KERNEL); 1216 if (!ring->buf) 1217 goto no_tx_mem; 1218 1219 ring->dma = dma_zalloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1220 &ring->phys, GFP_ATOMIC); 1221 if (!ring->dma) 1222 goto no_tx_mem; 1223 1224 for (i = 0; i < MTK_DMA_SIZE; i++) { 1225 int next = (i + 1) % MTK_DMA_SIZE; 1226 u32 next_ptr = ring->phys + next * sz; 1227 1228 ring->dma[i].txd2 = next_ptr; 1229 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1230 } 1231 1232 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1233 ring->next_free = &ring->dma[0]; 1234 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1235 ring->thresh = MAX_SKB_FRAGS; 1236 1237 /* make sure that all changes to the dma ring are flushed before we 1238 * continue 1239 */ 1240 wmb(); 1241 1242 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1243 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1244 mtk_w32(eth, 1245 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1246 MTK_QTX_CRX_PTR); 1247 mtk_w32(eth, 1248 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1249 MTK_QTX_DRX_PTR); 1250 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1251 1252 return 0; 1253 1254 no_tx_mem: 1255 return -ENOMEM; 1256 } 1257 1258 static void mtk_tx_clean(struct mtk_eth *eth) 1259 { 1260 struct mtk_tx_ring *ring = ð->tx_ring; 1261 int i; 1262 1263 if (ring->buf) { 1264 for (i = 0; i < MTK_DMA_SIZE; i++) 1265 mtk_tx_unmap(eth, &ring->buf[i]); 1266 kfree(ring->buf); 1267 ring->buf = NULL; 1268 } 1269 1270 if (ring->dma) { 1271 dma_free_coherent(eth->dev, 1272 MTK_DMA_SIZE * sizeof(*ring->dma), 1273 ring->dma, 1274 ring->phys); 1275 ring->dma = NULL; 1276 } 1277 } 1278 1279 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1280 { 1281 struct mtk_rx_ring *ring; 1282 int rx_data_len, rx_dma_size; 1283 int i; 1284 u32 offset = 0; 1285 1286 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1287 if (ring_no) 1288 return -EINVAL; 1289 ring = ð->rx_ring_qdma; 1290 offset = 0x1000; 1291 } else { 1292 ring = ð->rx_ring[ring_no]; 1293 } 1294 1295 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1296 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1297 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1298 } else { 1299 rx_data_len = ETH_DATA_LEN; 1300 rx_dma_size = MTK_DMA_SIZE; 1301 } 1302 1303 ring->frag_size = mtk_max_frag_size(rx_data_len); 1304 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1305 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1306 GFP_KERNEL); 1307 if (!ring->data) 1308 return -ENOMEM; 1309 1310 for (i = 0; i < rx_dma_size; i++) { 1311 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1312 if (!ring->data[i]) 1313 return -ENOMEM; 1314 } 1315 1316 ring->dma = dma_zalloc_coherent(eth->dev, 1317 rx_dma_size * sizeof(*ring->dma), 1318 &ring->phys, GFP_ATOMIC); 1319 if (!ring->dma) 1320 return -ENOMEM; 1321 1322 for (i = 0; i < rx_dma_size; i++) { 1323 dma_addr_t dma_addr = dma_map_single(eth->dev, 1324 ring->data[i] + NET_SKB_PAD, 1325 ring->buf_size, 1326 DMA_FROM_DEVICE); 1327 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1328 return -ENOMEM; 1329 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1330 1331 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1332 } 1333 ring->dma_size = rx_dma_size; 1334 ring->calc_idx_update = false; 1335 ring->calc_idx = rx_dma_size - 1; 1336 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1337 /* make sure that all changes to the dma ring are flushed before we 1338 * continue 1339 */ 1340 wmb(); 1341 1342 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1343 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1344 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1345 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1346 1347 return 0; 1348 } 1349 1350 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1351 { 1352 int i; 1353 1354 if (ring->data && ring->dma) { 1355 for (i = 0; i < ring->dma_size; i++) { 1356 if (!ring->data[i]) 1357 continue; 1358 if (!ring->dma[i].rxd1) 1359 continue; 1360 dma_unmap_single(eth->dev, 1361 ring->dma[i].rxd1, 1362 ring->buf_size, 1363 DMA_FROM_DEVICE); 1364 skb_free_frag(ring->data[i]); 1365 } 1366 kfree(ring->data); 1367 ring->data = NULL; 1368 } 1369 1370 if (ring->dma) { 1371 dma_free_coherent(eth->dev, 1372 ring->dma_size * sizeof(*ring->dma), 1373 ring->dma, 1374 ring->phys); 1375 ring->dma = NULL; 1376 } 1377 } 1378 1379 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1380 { 1381 int i; 1382 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1383 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1384 1385 /* set LRO rings to auto-learn modes */ 1386 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1387 1388 /* validate LRO ring */ 1389 ring_ctrl_dw2 |= MTK_RING_VLD; 1390 1391 /* set AGE timer (unit: 20us) */ 1392 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1393 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1394 1395 /* set max AGG timer (unit: 20us) */ 1396 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1397 1398 /* set max LRO AGG count */ 1399 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1400 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1401 1402 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1403 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1404 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1405 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1406 } 1407 1408 /* IPv4 checksum update enable */ 1409 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1410 1411 /* switch priority comparison to packet count mode */ 1412 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1413 1414 /* bandwidth threshold setting */ 1415 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1416 1417 /* auto-learn score delta setting */ 1418 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1419 1420 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1421 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1422 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1423 1424 /* set HW LRO mode & the max aggregation count for rx packets */ 1425 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1426 1427 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1428 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1429 1430 /* enable HW LRO */ 1431 lro_ctrl_dw0 |= MTK_LRO_EN; 1432 1433 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1434 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1435 1436 return 0; 1437 } 1438 1439 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1440 { 1441 int i; 1442 u32 val; 1443 1444 /* relinquish lro rings, flush aggregated packets */ 1445 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1446 1447 /* wait for relinquishments done */ 1448 for (i = 0; i < 10; i++) { 1449 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1450 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1451 msleep(20); 1452 continue; 1453 } 1454 break; 1455 } 1456 1457 /* invalidate lro rings */ 1458 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1459 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1460 1461 /* disable HW LRO */ 1462 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1463 } 1464 1465 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1466 { 1467 u32 reg_val; 1468 1469 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1470 1471 /* invalidate the IP setting */ 1472 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1473 1474 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1475 1476 /* validate the IP setting */ 1477 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1478 } 1479 1480 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1481 { 1482 u32 reg_val; 1483 1484 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1485 1486 /* invalidate the IP setting */ 1487 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1488 1489 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1490 } 1491 1492 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1493 { 1494 int cnt = 0; 1495 int i; 1496 1497 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1498 if (mac->hwlro_ip[i]) 1499 cnt++; 1500 } 1501 1502 return cnt; 1503 } 1504 1505 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1506 struct ethtool_rxnfc *cmd) 1507 { 1508 struct ethtool_rx_flow_spec *fsp = 1509 (struct ethtool_rx_flow_spec *)&cmd->fs; 1510 struct mtk_mac *mac = netdev_priv(dev); 1511 struct mtk_eth *eth = mac->hw; 1512 int hwlro_idx; 1513 1514 if ((fsp->flow_type != TCP_V4_FLOW) || 1515 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1516 (fsp->location > 1)) 1517 return -EINVAL; 1518 1519 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1520 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1521 1522 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1523 1524 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1525 1526 return 0; 1527 } 1528 1529 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1530 struct ethtool_rxnfc *cmd) 1531 { 1532 struct ethtool_rx_flow_spec *fsp = 1533 (struct ethtool_rx_flow_spec *)&cmd->fs; 1534 struct mtk_mac *mac = netdev_priv(dev); 1535 struct mtk_eth *eth = mac->hw; 1536 int hwlro_idx; 1537 1538 if (fsp->location > 1) 1539 return -EINVAL; 1540 1541 mac->hwlro_ip[fsp->location] = 0; 1542 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1543 1544 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1545 1546 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1547 1548 return 0; 1549 } 1550 1551 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1552 { 1553 struct mtk_mac *mac = netdev_priv(dev); 1554 struct mtk_eth *eth = mac->hw; 1555 int i, hwlro_idx; 1556 1557 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1558 mac->hwlro_ip[i] = 0; 1559 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1560 1561 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1562 } 1563 1564 mac->hwlro_ip_cnt = 0; 1565 } 1566 1567 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1568 struct ethtool_rxnfc *cmd) 1569 { 1570 struct mtk_mac *mac = netdev_priv(dev); 1571 struct ethtool_rx_flow_spec *fsp = 1572 (struct ethtool_rx_flow_spec *)&cmd->fs; 1573 1574 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1575 fsp->flow_type = TCP_V4_FLOW; 1576 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1577 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1578 1579 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1580 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1581 fsp->h_u.tcp_ip4_spec.psrc = 0; 1582 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1583 fsp->h_u.tcp_ip4_spec.pdst = 0; 1584 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1585 fsp->h_u.tcp_ip4_spec.tos = 0; 1586 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1587 1588 return 0; 1589 } 1590 1591 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1592 struct ethtool_rxnfc *cmd, 1593 u32 *rule_locs) 1594 { 1595 struct mtk_mac *mac = netdev_priv(dev); 1596 int cnt = 0; 1597 int i; 1598 1599 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1600 if (mac->hwlro_ip[i]) { 1601 rule_locs[cnt] = i; 1602 cnt++; 1603 } 1604 } 1605 1606 cmd->rule_cnt = cnt; 1607 1608 return 0; 1609 } 1610 1611 static netdev_features_t mtk_fix_features(struct net_device *dev, 1612 netdev_features_t features) 1613 { 1614 if (!(features & NETIF_F_LRO)) { 1615 struct mtk_mac *mac = netdev_priv(dev); 1616 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1617 1618 if (ip_cnt) { 1619 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1620 1621 features |= NETIF_F_LRO; 1622 } 1623 } 1624 1625 return features; 1626 } 1627 1628 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1629 { 1630 int err = 0; 1631 1632 if (!((dev->features ^ features) & NETIF_F_LRO)) 1633 return 0; 1634 1635 if (!(features & NETIF_F_LRO)) 1636 mtk_hwlro_netdev_disable(dev); 1637 1638 return err; 1639 } 1640 1641 /* wait for DMA to finish whatever it is doing before we start using it again */ 1642 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1643 { 1644 unsigned long t_start = jiffies; 1645 1646 while (1) { 1647 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1648 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1649 return 0; 1650 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1651 break; 1652 } 1653 1654 dev_err(eth->dev, "DMA init timeout\n"); 1655 return -1; 1656 } 1657 1658 static int mtk_dma_init(struct mtk_eth *eth) 1659 { 1660 int err; 1661 u32 i; 1662 1663 if (mtk_dma_busy_wait(eth)) 1664 return -EBUSY; 1665 1666 /* QDMA needs scratch memory for internal reordering of the 1667 * descriptors 1668 */ 1669 err = mtk_init_fq_dma(eth); 1670 if (err) 1671 return err; 1672 1673 err = mtk_tx_alloc(eth); 1674 if (err) 1675 return err; 1676 1677 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 1678 if (err) 1679 return err; 1680 1681 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 1682 if (err) 1683 return err; 1684 1685 if (eth->hwlro) { 1686 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1687 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 1688 if (err) 1689 return err; 1690 } 1691 err = mtk_hwlro_rx_init(eth); 1692 if (err) 1693 return err; 1694 } 1695 1696 /* Enable random early drop and set drop threshold automatically */ 1697 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1698 MTK_QDMA_FC_THRES); 1699 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1700 1701 return 0; 1702 } 1703 1704 static void mtk_dma_free(struct mtk_eth *eth) 1705 { 1706 int i; 1707 1708 for (i = 0; i < MTK_MAC_COUNT; i++) 1709 if (eth->netdev[i]) 1710 netdev_reset_queue(eth->netdev[i]); 1711 if (eth->scratch_ring) { 1712 dma_free_coherent(eth->dev, 1713 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 1714 eth->scratch_ring, 1715 eth->phy_scratch_ring); 1716 eth->scratch_ring = NULL; 1717 eth->phy_scratch_ring = 0; 1718 } 1719 mtk_tx_clean(eth); 1720 mtk_rx_clean(eth, ð->rx_ring[0]); 1721 mtk_rx_clean(eth, ð->rx_ring_qdma); 1722 1723 if (eth->hwlro) { 1724 mtk_hwlro_rx_uninit(eth); 1725 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1726 mtk_rx_clean(eth, ð->rx_ring[i]); 1727 } 1728 1729 kfree(eth->scratch_head); 1730 } 1731 1732 static void mtk_tx_timeout(struct net_device *dev) 1733 { 1734 struct mtk_mac *mac = netdev_priv(dev); 1735 struct mtk_eth *eth = mac->hw; 1736 1737 eth->netdev[mac->id]->stats.tx_errors++; 1738 netif_err(eth, tx_err, dev, 1739 "transmit timed out\n"); 1740 schedule_work(ð->pending_work); 1741 } 1742 1743 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 1744 { 1745 struct mtk_eth *eth = _eth; 1746 1747 if (likely(napi_schedule_prep(ð->rx_napi))) { 1748 __napi_schedule(ð->rx_napi); 1749 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1750 } 1751 1752 return IRQ_HANDLED; 1753 } 1754 1755 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 1756 { 1757 struct mtk_eth *eth = _eth; 1758 1759 if (likely(napi_schedule_prep(ð->tx_napi))) { 1760 __napi_schedule(ð->tx_napi); 1761 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1762 } 1763 1764 return IRQ_HANDLED; 1765 } 1766 1767 #ifdef CONFIG_NET_POLL_CONTROLLER 1768 static void mtk_poll_controller(struct net_device *dev) 1769 { 1770 struct mtk_mac *mac = netdev_priv(dev); 1771 struct mtk_eth *eth = mac->hw; 1772 1773 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1774 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1775 mtk_handle_irq_rx(eth->irq[2], dev); 1776 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1777 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1778 } 1779 #endif 1780 1781 static int mtk_start_dma(struct mtk_eth *eth) 1782 { 1783 int err; 1784 1785 err = mtk_dma_init(eth); 1786 if (err) { 1787 mtk_dma_free(eth); 1788 return err; 1789 } 1790 1791 mtk_w32(eth, 1792 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 1793 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | 1794 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1795 MTK_RX_BT_32DWORDS, 1796 MTK_QDMA_GLO_CFG); 1797 1798 mtk_w32(eth, 1799 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1800 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 1801 MTK_PDMA_GLO_CFG); 1802 1803 return 0; 1804 } 1805 1806 static int mtk_open(struct net_device *dev) 1807 { 1808 struct mtk_mac *mac = netdev_priv(dev); 1809 struct mtk_eth *eth = mac->hw; 1810 1811 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1812 if (!refcount_read(ð->dma_refcnt)) { 1813 int err = mtk_start_dma(eth); 1814 1815 if (err) 1816 return err; 1817 1818 napi_enable(ð->tx_napi); 1819 napi_enable(ð->rx_napi); 1820 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1821 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1822 refcount_set(ð->dma_refcnt, 1); 1823 } 1824 else 1825 refcount_inc(ð->dma_refcnt); 1826 1827 phy_start(dev->phydev); 1828 netif_start_queue(dev); 1829 1830 return 0; 1831 } 1832 1833 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1834 { 1835 u32 val; 1836 int i; 1837 1838 /* stop the dma engine */ 1839 spin_lock_bh(ð->page_lock); 1840 val = mtk_r32(eth, glo_cfg); 1841 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1842 glo_cfg); 1843 spin_unlock_bh(ð->page_lock); 1844 1845 /* wait for dma stop */ 1846 for (i = 0; i < 10; i++) { 1847 val = mtk_r32(eth, glo_cfg); 1848 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1849 msleep(20); 1850 continue; 1851 } 1852 break; 1853 } 1854 } 1855 1856 static int mtk_stop(struct net_device *dev) 1857 { 1858 struct mtk_mac *mac = netdev_priv(dev); 1859 struct mtk_eth *eth = mac->hw; 1860 1861 netif_tx_disable(dev); 1862 phy_stop(dev->phydev); 1863 1864 /* only shutdown DMA if this is the last user */ 1865 if (!refcount_dec_and_test(ð->dma_refcnt)) 1866 return 0; 1867 1868 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1869 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1870 napi_disable(ð->tx_napi); 1871 napi_disable(ð->rx_napi); 1872 1873 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1874 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 1875 1876 mtk_dma_free(eth); 1877 1878 return 0; 1879 } 1880 1881 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 1882 { 1883 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1884 reset_bits, 1885 reset_bits); 1886 1887 usleep_range(1000, 1100); 1888 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1889 reset_bits, 1890 ~reset_bits); 1891 mdelay(10); 1892 } 1893 1894 static void mtk_clk_disable(struct mtk_eth *eth) 1895 { 1896 int clk; 1897 1898 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 1899 clk_disable_unprepare(eth->clks[clk]); 1900 } 1901 1902 static int mtk_clk_enable(struct mtk_eth *eth) 1903 { 1904 int clk, ret; 1905 1906 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 1907 ret = clk_prepare_enable(eth->clks[clk]); 1908 if (ret) 1909 goto err_disable_clks; 1910 } 1911 1912 return 0; 1913 1914 err_disable_clks: 1915 while (--clk >= 0) 1916 clk_disable_unprepare(eth->clks[clk]); 1917 1918 return ret; 1919 } 1920 1921 static int mtk_hw_init(struct mtk_eth *eth) 1922 { 1923 int i, val, ret; 1924 1925 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 1926 return 0; 1927 1928 pm_runtime_enable(eth->dev); 1929 pm_runtime_get_sync(eth->dev); 1930 1931 ret = mtk_clk_enable(eth); 1932 if (ret) 1933 goto err_disable_pm; 1934 1935 ethsys_reset(eth, RSTCTRL_FE); 1936 ethsys_reset(eth, RSTCTRL_PPE); 1937 1938 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 1939 for (i = 0; i < MTK_MAC_COUNT; i++) { 1940 if (!eth->mac[i]) 1941 continue; 1942 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id); 1943 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id); 1944 } 1945 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 1946 1947 if (eth->pctl) { 1948 /* Set GE2 driving and slew rate */ 1949 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1950 1951 /* set GE2 TDSEL */ 1952 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1953 1954 /* set GE2 TUNE */ 1955 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1956 } 1957 1958 /* Set linkdown as the default for each GMAC. Its own MCR would be set 1959 * up with the more appropriate value when mtk_phy_link_adjust call is 1960 * being invoked. 1961 */ 1962 for (i = 0; i < MTK_MAC_COUNT; i++) 1963 mtk_w32(eth, 0, MTK_MAC_MCR(i)); 1964 1965 /* Indicates CDM to parse the MTK special tag from CPU 1966 * which also is working out for untag packets. 1967 */ 1968 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 1969 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 1970 1971 /* Enable RX VLan Offloading */ 1972 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1973 1974 /* enable interrupt delay for RX */ 1975 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 1976 1977 /* disable delay and normal interrupt */ 1978 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1979 mtk_tx_irq_disable(eth, ~0); 1980 mtk_rx_irq_disable(eth, ~0); 1981 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1982 mtk_w32(eth, 0, MTK_RST_GL); 1983 1984 /* FE int grouping */ 1985 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 1986 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 1987 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 1988 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 1989 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 1990 1991 for (i = 0; i < 2; i++) { 1992 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1993 1994 /* setup the forward port to send frame to PDMA */ 1995 val &= ~0xffff; 1996 1997 /* Enable RX checksum */ 1998 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 1999 2000 /* setup the mac dma */ 2001 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2002 } 2003 2004 return 0; 2005 2006 err_disable_pm: 2007 pm_runtime_put_sync(eth->dev); 2008 pm_runtime_disable(eth->dev); 2009 2010 return ret; 2011 } 2012 2013 static int mtk_hw_deinit(struct mtk_eth *eth) 2014 { 2015 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2016 return 0; 2017 2018 mtk_clk_disable(eth); 2019 2020 pm_runtime_put_sync(eth->dev); 2021 pm_runtime_disable(eth->dev); 2022 2023 return 0; 2024 } 2025 2026 static int __init mtk_init(struct net_device *dev) 2027 { 2028 struct mtk_mac *mac = netdev_priv(dev); 2029 struct mtk_eth *eth = mac->hw; 2030 const char *mac_addr; 2031 2032 mac_addr = of_get_mac_address(mac->of_node); 2033 if (mac_addr) 2034 ether_addr_copy(dev->dev_addr, mac_addr); 2035 2036 /* If the mac address is invalid, use random mac address */ 2037 if (!is_valid_ether_addr(dev->dev_addr)) { 2038 eth_hw_addr_random(dev); 2039 dev_err(eth->dev, "generated random MAC address %pM\n", 2040 dev->dev_addr); 2041 } 2042 2043 return mtk_phy_connect(dev); 2044 } 2045 2046 static void mtk_uninit(struct net_device *dev) 2047 { 2048 struct mtk_mac *mac = netdev_priv(dev); 2049 struct mtk_eth *eth = mac->hw; 2050 2051 phy_disconnect(dev->phydev); 2052 if (of_phy_is_fixed_link(mac->of_node)) 2053 of_phy_deregister_fixed_link(mac->of_node); 2054 mtk_tx_irq_disable(eth, ~0); 2055 mtk_rx_irq_disable(eth, ~0); 2056 } 2057 2058 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2059 { 2060 switch (cmd) { 2061 case SIOCGMIIPHY: 2062 case SIOCGMIIREG: 2063 case SIOCSMIIREG: 2064 return phy_mii_ioctl(dev->phydev, ifr, cmd); 2065 default: 2066 break; 2067 } 2068 2069 return -EOPNOTSUPP; 2070 } 2071 2072 static void mtk_pending_work(struct work_struct *work) 2073 { 2074 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2075 int err, i; 2076 unsigned long restart = 0; 2077 2078 rtnl_lock(); 2079 2080 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2081 2082 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2083 cpu_relax(); 2084 2085 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2086 /* stop all devices to make sure that dma is properly shut down */ 2087 for (i = 0; i < MTK_MAC_COUNT; i++) { 2088 if (!eth->netdev[i]) 2089 continue; 2090 mtk_stop(eth->netdev[i]); 2091 __set_bit(i, &restart); 2092 } 2093 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2094 2095 /* restart underlying hardware such as power, clock, pin mux 2096 * and the connected phy 2097 */ 2098 mtk_hw_deinit(eth); 2099 2100 if (eth->dev->pins) 2101 pinctrl_select_state(eth->dev->pins->p, 2102 eth->dev->pins->default_state); 2103 mtk_hw_init(eth); 2104 2105 for (i = 0; i < MTK_MAC_COUNT; i++) { 2106 if (!eth->mac[i] || 2107 of_phy_is_fixed_link(eth->mac[i]->of_node)) 2108 continue; 2109 err = phy_init_hw(eth->netdev[i]->phydev); 2110 if (err) 2111 dev_err(eth->dev, "%s: PHY init failed.\n", 2112 eth->netdev[i]->name); 2113 } 2114 2115 /* restart DMA and enable IRQs */ 2116 for (i = 0; i < MTK_MAC_COUNT; i++) { 2117 if (!test_bit(i, &restart)) 2118 continue; 2119 err = mtk_open(eth->netdev[i]); 2120 if (err) { 2121 netif_alert(eth, ifup, eth->netdev[i], 2122 "Driver up/down cycle failed, closing device.\n"); 2123 dev_close(eth->netdev[i]); 2124 } 2125 } 2126 2127 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2128 2129 clear_bit_unlock(MTK_RESETTING, ð->state); 2130 2131 rtnl_unlock(); 2132 } 2133 2134 static int mtk_free_dev(struct mtk_eth *eth) 2135 { 2136 int i; 2137 2138 for (i = 0; i < MTK_MAC_COUNT; i++) { 2139 if (!eth->netdev[i]) 2140 continue; 2141 free_netdev(eth->netdev[i]); 2142 } 2143 2144 return 0; 2145 } 2146 2147 static int mtk_unreg_dev(struct mtk_eth *eth) 2148 { 2149 int i; 2150 2151 for (i = 0; i < MTK_MAC_COUNT; i++) { 2152 if (!eth->netdev[i]) 2153 continue; 2154 unregister_netdev(eth->netdev[i]); 2155 } 2156 2157 return 0; 2158 } 2159 2160 static int mtk_cleanup(struct mtk_eth *eth) 2161 { 2162 mtk_unreg_dev(eth); 2163 mtk_free_dev(eth); 2164 cancel_work_sync(ð->pending_work); 2165 2166 return 0; 2167 } 2168 2169 static int mtk_get_link_ksettings(struct net_device *ndev, 2170 struct ethtool_link_ksettings *cmd) 2171 { 2172 struct mtk_mac *mac = netdev_priv(ndev); 2173 2174 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2175 return -EBUSY; 2176 2177 phy_ethtool_ksettings_get(ndev->phydev, cmd); 2178 2179 return 0; 2180 } 2181 2182 static int mtk_set_link_ksettings(struct net_device *ndev, 2183 const struct ethtool_link_ksettings *cmd) 2184 { 2185 struct mtk_mac *mac = netdev_priv(ndev); 2186 2187 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2188 return -EBUSY; 2189 2190 return phy_ethtool_ksettings_set(ndev->phydev, cmd); 2191 } 2192 2193 static void mtk_get_drvinfo(struct net_device *dev, 2194 struct ethtool_drvinfo *info) 2195 { 2196 struct mtk_mac *mac = netdev_priv(dev); 2197 2198 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2199 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2200 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2201 } 2202 2203 static u32 mtk_get_msglevel(struct net_device *dev) 2204 { 2205 struct mtk_mac *mac = netdev_priv(dev); 2206 2207 return mac->hw->msg_enable; 2208 } 2209 2210 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2211 { 2212 struct mtk_mac *mac = netdev_priv(dev); 2213 2214 mac->hw->msg_enable = value; 2215 } 2216 2217 static int mtk_nway_reset(struct net_device *dev) 2218 { 2219 struct mtk_mac *mac = netdev_priv(dev); 2220 2221 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2222 return -EBUSY; 2223 2224 return genphy_restart_aneg(dev->phydev); 2225 } 2226 2227 static u32 mtk_get_link(struct net_device *dev) 2228 { 2229 struct mtk_mac *mac = netdev_priv(dev); 2230 int err; 2231 2232 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2233 return -EBUSY; 2234 2235 err = genphy_update_link(dev->phydev); 2236 if (err) 2237 return ethtool_op_get_link(dev); 2238 2239 return dev->phydev->link; 2240 } 2241 2242 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2243 { 2244 int i; 2245 2246 switch (stringset) { 2247 case ETH_SS_STATS: 2248 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2249 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2250 data += ETH_GSTRING_LEN; 2251 } 2252 break; 2253 } 2254 } 2255 2256 static int mtk_get_sset_count(struct net_device *dev, int sset) 2257 { 2258 switch (sset) { 2259 case ETH_SS_STATS: 2260 return ARRAY_SIZE(mtk_ethtool_stats); 2261 default: 2262 return -EOPNOTSUPP; 2263 } 2264 } 2265 2266 static void mtk_get_ethtool_stats(struct net_device *dev, 2267 struct ethtool_stats *stats, u64 *data) 2268 { 2269 struct mtk_mac *mac = netdev_priv(dev); 2270 struct mtk_hw_stats *hwstats = mac->hw_stats; 2271 u64 *data_src, *data_dst; 2272 unsigned int start; 2273 int i; 2274 2275 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2276 return; 2277 2278 if (netif_running(dev) && netif_device_present(dev)) { 2279 if (spin_trylock_bh(&hwstats->stats_lock)) { 2280 mtk_stats_update_mac(mac); 2281 spin_unlock_bh(&hwstats->stats_lock); 2282 } 2283 } 2284 2285 data_src = (u64 *)hwstats; 2286 2287 do { 2288 data_dst = data; 2289 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2290 2291 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2292 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2293 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2294 } 2295 2296 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2297 u32 *rule_locs) 2298 { 2299 int ret = -EOPNOTSUPP; 2300 2301 switch (cmd->cmd) { 2302 case ETHTOOL_GRXRINGS: 2303 if (dev->features & NETIF_F_LRO) { 2304 cmd->data = MTK_MAX_RX_RING_NUM; 2305 ret = 0; 2306 } 2307 break; 2308 case ETHTOOL_GRXCLSRLCNT: 2309 if (dev->features & NETIF_F_LRO) { 2310 struct mtk_mac *mac = netdev_priv(dev); 2311 2312 cmd->rule_cnt = mac->hwlro_ip_cnt; 2313 ret = 0; 2314 } 2315 break; 2316 case ETHTOOL_GRXCLSRULE: 2317 if (dev->features & NETIF_F_LRO) 2318 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2319 break; 2320 case ETHTOOL_GRXCLSRLALL: 2321 if (dev->features & NETIF_F_LRO) 2322 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2323 rule_locs); 2324 break; 2325 default: 2326 break; 2327 } 2328 2329 return ret; 2330 } 2331 2332 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2333 { 2334 int ret = -EOPNOTSUPP; 2335 2336 switch (cmd->cmd) { 2337 case ETHTOOL_SRXCLSRLINS: 2338 if (dev->features & NETIF_F_LRO) 2339 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2340 break; 2341 case ETHTOOL_SRXCLSRLDEL: 2342 if (dev->features & NETIF_F_LRO) 2343 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2344 break; 2345 default: 2346 break; 2347 } 2348 2349 return ret; 2350 } 2351 2352 static const struct ethtool_ops mtk_ethtool_ops = { 2353 .get_link_ksettings = mtk_get_link_ksettings, 2354 .set_link_ksettings = mtk_set_link_ksettings, 2355 .get_drvinfo = mtk_get_drvinfo, 2356 .get_msglevel = mtk_get_msglevel, 2357 .set_msglevel = mtk_set_msglevel, 2358 .nway_reset = mtk_nway_reset, 2359 .get_link = mtk_get_link, 2360 .get_strings = mtk_get_strings, 2361 .get_sset_count = mtk_get_sset_count, 2362 .get_ethtool_stats = mtk_get_ethtool_stats, 2363 .get_rxnfc = mtk_get_rxnfc, 2364 .set_rxnfc = mtk_set_rxnfc, 2365 }; 2366 2367 static const struct net_device_ops mtk_netdev_ops = { 2368 .ndo_init = mtk_init, 2369 .ndo_uninit = mtk_uninit, 2370 .ndo_open = mtk_open, 2371 .ndo_stop = mtk_stop, 2372 .ndo_start_xmit = mtk_start_xmit, 2373 .ndo_set_mac_address = mtk_set_mac_address, 2374 .ndo_validate_addr = eth_validate_addr, 2375 .ndo_do_ioctl = mtk_do_ioctl, 2376 .ndo_tx_timeout = mtk_tx_timeout, 2377 .ndo_get_stats64 = mtk_get_stats64, 2378 .ndo_fix_features = mtk_fix_features, 2379 .ndo_set_features = mtk_set_features, 2380 #ifdef CONFIG_NET_POLL_CONTROLLER 2381 .ndo_poll_controller = mtk_poll_controller, 2382 #endif 2383 }; 2384 2385 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2386 { 2387 struct mtk_mac *mac; 2388 const __be32 *_id = of_get_property(np, "reg", NULL); 2389 int id, err; 2390 2391 if (!_id) { 2392 dev_err(eth->dev, "missing mac id\n"); 2393 return -EINVAL; 2394 } 2395 2396 id = be32_to_cpup(_id); 2397 if (id >= MTK_MAC_COUNT) { 2398 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2399 return -EINVAL; 2400 } 2401 2402 if (eth->netdev[id]) { 2403 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2404 return -EINVAL; 2405 } 2406 2407 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2408 if (!eth->netdev[id]) { 2409 dev_err(eth->dev, "alloc_etherdev failed\n"); 2410 return -ENOMEM; 2411 } 2412 mac = netdev_priv(eth->netdev[id]); 2413 eth->mac[id] = mac; 2414 mac->id = id; 2415 mac->hw = eth; 2416 mac->of_node = np; 2417 2418 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2419 mac->hwlro_ip_cnt = 0; 2420 2421 mac->hw_stats = devm_kzalloc(eth->dev, 2422 sizeof(*mac->hw_stats), 2423 GFP_KERNEL); 2424 if (!mac->hw_stats) { 2425 dev_err(eth->dev, "failed to allocate counter memory\n"); 2426 err = -ENOMEM; 2427 goto free_netdev; 2428 } 2429 spin_lock_init(&mac->hw_stats->stats_lock); 2430 u64_stats_init(&mac->hw_stats->syncp); 2431 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2432 2433 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2434 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2435 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2436 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2437 2438 eth->netdev[id]->hw_features = MTK_HW_FEATURES; 2439 if (eth->hwlro) 2440 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2441 2442 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 2443 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2444 eth->netdev[id]->features |= MTK_HW_FEATURES; 2445 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2446 2447 eth->netdev[id]->irq = eth->irq[0]; 2448 eth->netdev[id]->dev.of_node = np; 2449 2450 return 0; 2451 2452 free_netdev: 2453 free_netdev(eth->netdev[id]); 2454 return err; 2455 } 2456 2457 static int mtk_probe(struct platform_device *pdev) 2458 { 2459 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2460 struct device_node *mac_np; 2461 struct mtk_eth *eth; 2462 int err; 2463 int i; 2464 2465 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2466 if (!eth) 2467 return -ENOMEM; 2468 2469 eth->soc = of_device_get_match_data(&pdev->dev); 2470 2471 eth->dev = &pdev->dev; 2472 eth->base = devm_ioremap_resource(&pdev->dev, res); 2473 if (IS_ERR(eth->base)) 2474 return PTR_ERR(eth->base); 2475 2476 spin_lock_init(ð->page_lock); 2477 spin_lock_init(ð->tx_irq_lock); 2478 spin_lock_init(ð->rx_irq_lock); 2479 2480 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2481 "mediatek,ethsys"); 2482 if (IS_ERR(eth->ethsys)) { 2483 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2484 return PTR_ERR(eth->ethsys); 2485 } 2486 2487 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 2488 eth->sgmiisys = 2489 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2490 "mediatek,sgmiisys"); 2491 if (IS_ERR(eth->sgmiisys)) { 2492 dev_err(&pdev->dev, "no sgmiisys regmap found\n"); 2493 return PTR_ERR(eth->sgmiisys); 2494 } 2495 } 2496 2497 if (eth->soc->required_pctl) { 2498 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2499 "mediatek,pctl"); 2500 if (IS_ERR(eth->pctl)) { 2501 dev_err(&pdev->dev, "no pctl regmap found\n"); 2502 return PTR_ERR(eth->pctl); 2503 } 2504 } 2505 2506 for (i = 0; i < 3; i++) { 2507 eth->irq[i] = platform_get_irq(pdev, i); 2508 if (eth->irq[i] < 0) { 2509 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2510 return -ENXIO; 2511 } 2512 } 2513 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2514 eth->clks[i] = devm_clk_get(eth->dev, 2515 mtk_clks_source_name[i]); 2516 if (IS_ERR(eth->clks[i])) { 2517 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2518 return -EPROBE_DEFER; 2519 if (eth->soc->required_clks & BIT(i)) { 2520 dev_err(&pdev->dev, "clock %s not found\n", 2521 mtk_clks_source_name[i]); 2522 return -EINVAL; 2523 } 2524 eth->clks[i] = NULL; 2525 } 2526 } 2527 2528 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 2529 INIT_WORK(ð->pending_work, mtk_pending_work); 2530 2531 err = mtk_hw_init(eth); 2532 if (err) 2533 return err; 2534 2535 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 2536 2537 for_each_child_of_node(pdev->dev.of_node, mac_np) { 2538 if (!of_device_is_compatible(mac_np, 2539 "mediatek,eth-mac")) 2540 continue; 2541 2542 if (!of_device_is_available(mac_np)) 2543 continue; 2544 2545 err = mtk_add_mac(eth, mac_np); 2546 if (err) 2547 goto err_deinit_hw; 2548 } 2549 2550 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0, 2551 dev_name(eth->dev), eth); 2552 if (err) 2553 goto err_free_dev; 2554 2555 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0, 2556 dev_name(eth->dev), eth); 2557 if (err) 2558 goto err_free_dev; 2559 2560 err = mtk_mdio_init(eth); 2561 if (err) 2562 goto err_free_dev; 2563 2564 for (i = 0; i < MTK_MAX_DEVS; i++) { 2565 if (!eth->netdev[i]) 2566 continue; 2567 2568 err = register_netdev(eth->netdev[i]); 2569 if (err) { 2570 dev_err(eth->dev, "error bringing up device\n"); 2571 goto err_deinit_mdio; 2572 } else 2573 netif_info(eth, probe, eth->netdev[i], 2574 "mediatek frame engine at 0x%08lx, irq %d\n", 2575 eth->netdev[i]->base_addr, eth->irq[0]); 2576 } 2577 2578 /* we run 2 devices on the same DMA ring so we need a dummy device 2579 * for NAPI to work 2580 */ 2581 init_dummy_netdev(ð->dummy_dev); 2582 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 2583 MTK_NAPI_WEIGHT); 2584 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 2585 MTK_NAPI_WEIGHT); 2586 2587 platform_set_drvdata(pdev, eth); 2588 2589 return 0; 2590 2591 err_deinit_mdio: 2592 mtk_mdio_cleanup(eth); 2593 err_free_dev: 2594 mtk_free_dev(eth); 2595 err_deinit_hw: 2596 mtk_hw_deinit(eth); 2597 2598 return err; 2599 } 2600 2601 static int mtk_remove(struct platform_device *pdev) 2602 { 2603 struct mtk_eth *eth = platform_get_drvdata(pdev); 2604 int i; 2605 2606 /* stop all devices to make sure that dma is properly shut down */ 2607 for (i = 0; i < MTK_MAC_COUNT; i++) { 2608 if (!eth->netdev[i]) 2609 continue; 2610 mtk_stop(eth->netdev[i]); 2611 } 2612 2613 mtk_hw_deinit(eth); 2614 2615 netif_napi_del(ð->tx_napi); 2616 netif_napi_del(ð->rx_napi); 2617 mtk_cleanup(eth); 2618 mtk_mdio_cleanup(eth); 2619 2620 return 0; 2621 } 2622 2623 static const struct mtk_soc_data mt2701_data = { 2624 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO, 2625 .required_clks = MT7623_CLKS_BITMAP, 2626 .required_pctl = true, 2627 }; 2628 2629 static const struct mtk_soc_data mt7622_data = { 2630 .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW | MTK_HWLRO, 2631 .required_clks = MT7622_CLKS_BITMAP, 2632 .required_pctl = false, 2633 }; 2634 2635 static const struct mtk_soc_data mt7623_data = { 2636 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO, 2637 .required_clks = MT7623_CLKS_BITMAP, 2638 .required_pctl = true, 2639 }; 2640 2641 const struct of_device_id of_mtk_match[] = { 2642 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 2643 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 2644 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 2645 {}, 2646 }; 2647 MODULE_DEVICE_TABLE(of, of_mtk_match); 2648 2649 static struct platform_driver mtk_driver = { 2650 .probe = mtk_probe, 2651 .remove = mtk_remove, 2652 .driver = { 2653 .name = "mtk_soc_eth", 2654 .of_match_table = of_mtk_match, 2655 }, 2656 }; 2657 2658 module_platform_driver(mtk_driver); 2659 2660 MODULE_LICENSE("GPL"); 2661 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 2662 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 2663