1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/regmap.h> 14 #include <linux/clk.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/if_vlan.h> 17 #include <linux/reset.h> 18 #include <linux/tcp.h> 19 #include <linux/interrupt.h> 20 #include <linux/pinctrl/devinfo.h> 21 #include <linux/phylink.h> 22 #include <linux/jhash.h> 23 #include <net/dsa.h> 24 25 #include "mtk_eth_soc.h" 26 27 static int mtk_msg_level = -1; 28 module_param_named(msg_level, mtk_msg_level, int, 0); 29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 30 31 #define MTK_ETHTOOL_STAT(x) { #x, \ 32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 33 34 /* strings used by ethtool */ 35 static const struct mtk_ethtool_stats { 36 char str[ETH_GSTRING_LEN]; 37 u32 offset; 38 } mtk_ethtool_stats[] = { 39 MTK_ETHTOOL_STAT(tx_bytes), 40 MTK_ETHTOOL_STAT(tx_packets), 41 MTK_ETHTOOL_STAT(tx_skip), 42 MTK_ETHTOOL_STAT(tx_collisions), 43 MTK_ETHTOOL_STAT(rx_bytes), 44 MTK_ETHTOOL_STAT(rx_packets), 45 MTK_ETHTOOL_STAT(rx_overflow), 46 MTK_ETHTOOL_STAT(rx_fcs_errors), 47 MTK_ETHTOOL_STAT(rx_short_errors), 48 MTK_ETHTOOL_STAT(rx_long_errors), 49 MTK_ETHTOOL_STAT(rx_checksum_errors), 50 MTK_ETHTOOL_STAT(rx_flow_control_packets), 51 }; 52 53 static const char * const mtk_clks_source_name[] = { 54 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 55 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 56 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 57 "sgmii_ck", "eth2pll", 58 }; 59 60 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 61 { 62 __raw_writel(val, eth->base + reg); 63 } 64 65 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 66 { 67 return __raw_readl(eth->base + reg); 68 } 69 70 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 71 { 72 u32 val; 73 74 val = mtk_r32(eth, reg); 75 val &= ~mask; 76 val |= set; 77 mtk_w32(eth, val, reg); 78 return reg; 79 } 80 81 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 82 { 83 unsigned long t_start = jiffies; 84 85 while (1) { 86 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 87 return 0; 88 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 89 break; 90 cond_resched(); 91 } 92 93 dev_err(eth->dev, "mdio: MDIO timeout\n"); 94 return -1; 95 } 96 97 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 98 u32 phy_register, u32 write_data) 99 { 100 if (mtk_mdio_busy_wait(eth)) 101 return -1; 102 103 write_data &= 0xffff; 104 105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 106 (phy_register << PHY_IAC_REG_SHIFT) | 107 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 108 MTK_PHY_IAC); 109 110 if (mtk_mdio_busy_wait(eth)) 111 return -1; 112 113 return 0; 114 } 115 116 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 117 { 118 u32 d; 119 120 if (mtk_mdio_busy_wait(eth)) 121 return 0xffff; 122 123 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 124 (phy_reg << PHY_IAC_REG_SHIFT) | 125 (phy_addr << PHY_IAC_ADDR_SHIFT), 126 MTK_PHY_IAC); 127 128 if (mtk_mdio_busy_wait(eth)) 129 return 0xffff; 130 131 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 132 133 return d; 134 } 135 136 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 137 int phy_reg, u16 val) 138 { 139 struct mtk_eth *eth = bus->priv; 140 141 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 142 } 143 144 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 145 { 146 struct mtk_eth *eth = bus->priv; 147 148 return _mtk_mdio_read(eth, phy_addr, phy_reg); 149 } 150 151 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 152 phy_interface_t interface) 153 { 154 u32 val; 155 156 /* Check DDR memory type. 157 * Currently TRGMII mode with DDR2 memory is not supported. 158 */ 159 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 160 if (interface == PHY_INTERFACE_MODE_TRGMII && 161 val & SYSCFG_DRAM_TYPE_DDR2) { 162 dev_err(eth->dev, 163 "TRGMII mode with DDR2 memory is not supported!\n"); 164 return -EOPNOTSUPP; 165 } 166 167 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 168 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 169 170 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 171 ETHSYS_TRGMII_MT7621_MASK, val); 172 173 return 0; 174 } 175 176 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 177 phy_interface_t interface, int speed) 178 { 179 u32 val; 180 int ret; 181 182 if (interface == PHY_INTERFACE_MODE_TRGMII) { 183 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 184 val = 500000000; 185 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 186 if (ret) 187 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 188 return; 189 } 190 191 val = (speed == SPEED_1000) ? 192 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 193 mtk_w32(eth, val, INTF_MODE); 194 195 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 196 ETHSYS_TRGMII_CLK_SEL362_5, 197 ETHSYS_TRGMII_CLK_SEL362_5); 198 199 val = (speed == SPEED_1000) ? 250000000 : 500000000; 200 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 201 if (ret) 202 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 203 204 val = (speed == SPEED_1000) ? 205 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 206 mtk_w32(eth, val, TRGMII_RCK_CTRL); 207 208 val = (speed == SPEED_1000) ? 209 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 210 mtk_w32(eth, val, TRGMII_TCK_CTRL); 211 } 212 213 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 214 const struct phylink_link_state *state) 215 { 216 struct mtk_mac *mac = container_of(config, struct mtk_mac, 217 phylink_config); 218 struct mtk_eth *eth = mac->hw; 219 u32 mcr_cur, mcr_new, sid, i; 220 int val, ge_mode, err; 221 222 /* MT76x8 has no hardware settings between for the MAC */ 223 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 224 mac->interface != state->interface) { 225 /* Setup soc pin functions */ 226 switch (state->interface) { 227 case PHY_INTERFACE_MODE_TRGMII: 228 if (mac->id) 229 goto err_phy; 230 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 231 MTK_GMAC1_TRGMII)) 232 goto err_phy; 233 fallthrough; 234 case PHY_INTERFACE_MODE_RGMII_TXID: 235 case PHY_INTERFACE_MODE_RGMII_RXID: 236 case PHY_INTERFACE_MODE_RGMII_ID: 237 case PHY_INTERFACE_MODE_RGMII: 238 case PHY_INTERFACE_MODE_MII: 239 case PHY_INTERFACE_MODE_REVMII: 240 case PHY_INTERFACE_MODE_RMII: 241 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 242 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 243 if (err) 244 goto init_err; 245 } 246 break; 247 case PHY_INTERFACE_MODE_1000BASEX: 248 case PHY_INTERFACE_MODE_2500BASEX: 249 case PHY_INTERFACE_MODE_SGMII: 250 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 251 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 252 if (err) 253 goto init_err; 254 } 255 break; 256 case PHY_INTERFACE_MODE_GMII: 257 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 258 err = mtk_gmac_gephy_path_setup(eth, mac->id); 259 if (err) 260 goto init_err; 261 } 262 break; 263 default: 264 goto err_phy; 265 } 266 267 /* Setup clock for 1st gmac */ 268 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 269 !phy_interface_mode_is_8023z(state->interface) && 270 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 271 if (MTK_HAS_CAPS(mac->hw->soc->caps, 272 MTK_TRGMII_MT7621_CLK)) { 273 if (mt7621_gmac0_rgmii_adjust(mac->hw, 274 state->interface)) 275 goto err_phy; 276 } else { 277 mtk_gmac0_rgmii_adjust(mac->hw, 278 state->interface, 279 state->speed); 280 281 /* mt7623_pad_clk_setup */ 282 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 283 mtk_w32(mac->hw, 284 TD_DM_DRVP(8) | TD_DM_DRVN(8), 285 TRGMII_TD_ODT(i)); 286 287 /* Assert/release MT7623 RXC reset */ 288 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 289 TRGMII_RCK_CTRL); 290 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 291 } 292 } 293 294 ge_mode = 0; 295 switch (state->interface) { 296 case PHY_INTERFACE_MODE_MII: 297 case PHY_INTERFACE_MODE_GMII: 298 ge_mode = 1; 299 break; 300 case PHY_INTERFACE_MODE_REVMII: 301 ge_mode = 2; 302 break; 303 case PHY_INTERFACE_MODE_RMII: 304 if (mac->id) 305 goto err_phy; 306 ge_mode = 3; 307 break; 308 default: 309 break; 310 } 311 312 /* put the gmac into the right mode */ 313 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 314 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 315 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 316 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 317 318 mac->interface = state->interface; 319 } 320 321 /* SGMII */ 322 if (state->interface == PHY_INTERFACE_MODE_SGMII || 323 phy_interface_mode_is_8023z(state->interface)) { 324 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 325 * being setup done. 326 */ 327 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 328 329 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 330 SYSCFG0_SGMII_MASK, 331 ~(u32)SYSCFG0_SGMII_MASK); 332 333 /* Decide how GMAC and SGMIISYS be mapped */ 334 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 335 0 : mac->id; 336 337 /* Setup SGMIISYS with the determined property */ 338 if (state->interface != PHY_INTERFACE_MODE_SGMII) 339 err = mtk_sgmii_setup_mode_force(eth->sgmii, sid, 340 state); 341 else if (phylink_autoneg_inband(mode)) 342 err = mtk_sgmii_setup_mode_an(eth->sgmii, sid); 343 344 if (err) 345 goto init_err; 346 347 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 348 SYSCFG0_SGMII_MASK, val); 349 } else if (phylink_autoneg_inband(mode)) { 350 dev_err(eth->dev, 351 "In-band mode not supported in non SGMII mode!\n"); 352 return; 353 } 354 355 /* Setup gmac */ 356 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 357 mcr_new = mcr_cur; 358 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 359 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; 360 361 /* Only update control register when needed! */ 362 if (mcr_new != mcr_cur) 363 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 364 365 return; 366 367 err_phy: 368 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 369 mac->id, phy_modes(state->interface)); 370 return; 371 372 init_err: 373 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 374 mac->id, phy_modes(state->interface), err); 375 } 376 377 static void mtk_mac_pcs_get_state(struct phylink_config *config, 378 struct phylink_link_state *state) 379 { 380 struct mtk_mac *mac = container_of(config, struct mtk_mac, 381 phylink_config); 382 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 383 384 state->link = (pmsr & MAC_MSR_LINK); 385 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 386 387 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 388 case 0: 389 state->speed = SPEED_10; 390 break; 391 case MAC_MSR_SPEED_100: 392 state->speed = SPEED_100; 393 break; 394 case MAC_MSR_SPEED_1000: 395 state->speed = SPEED_1000; 396 break; 397 default: 398 state->speed = SPEED_UNKNOWN; 399 break; 400 } 401 402 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 403 if (pmsr & MAC_MSR_RX_FC) 404 state->pause |= MLO_PAUSE_RX; 405 if (pmsr & MAC_MSR_TX_FC) 406 state->pause |= MLO_PAUSE_TX; 407 } 408 409 static void mtk_mac_an_restart(struct phylink_config *config) 410 { 411 struct mtk_mac *mac = container_of(config, struct mtk_mac, 412 phylink_config); 413 414 mtk_sgmii_restart_an(mac->hw, mac->id); 415 } 416 417 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 418 phy_interface_t interface) 419 { 420 struct mtk_mac *mac = container_of(config, struct mtk_mac, 421 phylink_config); 422 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 423 424 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 425 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 426 } 427 428 static void mtk_mac_link_up(struct phylink_config *config, 429 struct phy_device *phy, 430 unsigned int mode, phy_interface_t interface, 431 int speed, int duplex, bool tx_pause, bool rx_pause) 432 { 433 struct mtk_mac *mac = container_of(config, struct mtk_mac, 434 phylink_config); 435 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 436 437 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 438 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 439 MAC_MCR_FORCE_RX_FC); 440 441 /* Configure speed */ 442 switch (speed) { 443 case SPEED_2500: 444 case SPEED_1000: 445 mcr |= MAC_MCR_SPEED_1000; 446 break; 447 case SPEED_100: 448 mcr |= MAC_MCR_SPEED_100; 449 break; 450 } 451 452 /* Configure duplex */ 453 if (duplex == DUPLEX_FULL) 454 mcr |= MAC_MCR_FORCE_DPX; 455 456 /* Configure pause modes - phylink will avoid these for half duplex */ 457 if (tx_pause) 458 mcr |= MAC_MCR_FORCE_TX_FC; 459 if (rx_pause) 460 mcr |= MAC_MCR_FORCE_RX_FC; 461 462 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 463 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 464 } 465 466 static void mtk_validate(struct phylink_config *config, 467 unsigned long *supported, 468 struct phylink_link_state *state) 469 { 470 struct mtk_mac *mac = container_of(config, struct mtk_mac, 471 phylink_config); 472 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 473 474 if (state->interface != PHY_INTERFACE_MODE_NA && 475 state->interface != PHY_INTERFACE_MODE_MII && 476 state->interface != PHY_INTERFACE_MODE_GMII && 477 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) && 478 phy_interface_mode_is_rgmii(state->interface)) && 479 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && 480 !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) && 481 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) && 482 (state->interface == PHY_INTERFACE_MODE_SGMII || 483 phy_interface_mode_is_8023z(state->interface)))) { 484 linkmode_zero(supported); 485 return; 486 } 487 488 phylink_set_port_modes(mask); 489 phylink_set(mask, Autoneg); 490 491 switch (state->interface) { 492 case PHY_INTERFACE_MODE_TRGMII: 493 phylink_set(mask, 1000baseT_Full); 494 break; 495 case PHY_INTERFACE_MODE_1000BASEX: 496 case PHY_INTERFACE_MODE_2500BASEX: 497 phylink_set(mask, 1000baseX_Full); 498 phylink_set(mask, 2500baseX_Full); 499 break; 500 case PHY_INTERFACE_MODE_GMII: 501 case PHY_INTERFACE_MODE_RGMII: 502 case PHY_INTERFACE_MODE_RGMII_ID: 503 case PHY_INTERFACE_MODE_RGMII_RXID: 504 case PHY_INTERFACE_MODE_RGMII_TXID: 505 phylink_set(mask, 1000baseT_Half); 506 fallthrough; 507 case PHY_INTERFACE_MODE_SGMII: 508 phylink_set(mask, 1000baseT_Full); 509 phylink_set(mask, 1000baseX_Full); 510 fallthrough; 511 case PHY_INTERFACE_MODE_MII: 512 case PHY_INTERFACE_MODE_RMII: 513 case PHY_INTERFACE_MODE_REVMII: 514 case PHY_INTERFACE_MODE_NA: 515 default: 516 phylink_set(mask, 10baseT_Half); 517 phylink_set(mask, 10baseT_Full); 518 phylink_set(mask, 100baseT_Half); 519 phylink_set(mask, 100baseT_Full); 520 break; 521 } 522 523 if (state->interface == PHY_INTERFACE_MODE_NA) { 524 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 525 phylink_set(mask, 1000baseT_Full); 526 phylink_set(mask, 1000baseX_Full); 527 phylink_set(mask, 2500baseX_Full); 528 } 529 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) { 530 phylink_set(mask, 1000baseT_Full); 531 phylink_set(mask, 1000baseT_Half); 532 phylink_set(mask, 1000baseX_Full); 533 } 534 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) { 535 phylink_set(mask, 1000baseT_Full); 536 phylink_set(mask, 1000baseT_Half); 537 } 538 } 539 540 phylink_set(mask, Pause); 541 phylink_set(mask, Asym_Pause); 542 543 linkmode_and(supported, supported, mask); 544 linkmode_and(state->advertising, state->advertising, mask); 545 546 /* We can only operate at 2500BaseX or 1000BaseX. If requested 547 * to advertise both, only report advertising at 2500BaseX. 548 */ 549 phylink_helper_basex_speed(state); 550 } 551 552 static const struct phylink_mac_ops mtk_phylink_ops = { 553 .validate = mtk_validate, 554 .mac_pcs_get_state = mtk_mac_pcs_get_state, 555 .mac_an_restart = mtk_mac_an_restart, 556 .mac_config = mtk_mac_config, 557 .mac_link_down = mtk_mac_link_down, 558 .mac_link_up = mtk_mac_link_up, 559 }; 560 561 static int mtk_mdio_init(struct mtk_eth *eth) 562 { 563 struct device_node *mii_np; 564 int ret; 565 566 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 567 if (!mii_np) { 568 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 569 return -ENODEV; 570 } 571 572 if (!of_device_is_available(mii_np)) { 573 ret = -ENODEV; 574 goto err_put_node; 575 } 576 577 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 578 if (!eth->mii_bus) { 579 ret = -ENOMEM; 580 goto err_put_node; 581 } 582 583 eth->mii_bus->name = "mdio"; 584 eth->mii_bus->read = mtk_mdio_read; 585 eth->mii_bus->write = mtk_mdio_write; 586 eth->mii_bus->priv = eth; 587 eth->mii_bus->parent = eth->dev; 588 589 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 590 ret = of_mdiobus_register(eth->mii_bus, mii_np); 591 592 err_put_node: 593 of_node_put(mii_np); 594 return ret; 595 } 596 597 static void mtk_mdio_cleanup(struct mtk_eth *eth) 598 { 599 if (!eth->mii_bus) 600 return; 601 602 mdiobus_unregister(eth->mii_bus); 603 } 604 605 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 606 { 607 unsigned long flags; 608 u32 val; 609 610 spin_lock_irqsave(ð->tx_irq_lock, flags); 611 val = mtk_r32(eth, eth->tx_int_mask_reg); 612 mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg); 613 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 614 } 615 616 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 617 { 618 unsigned long flags; 619 u32 val; 620 621 spin_lock_irqsave(ð->tx_irq_lock, flags); 622 val = mtk_r32(eth, eth->tx_int_mask_reg); 623 mtk_w32(eth, val | mask, eth->tx_int_mask_reg); 624 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 625 } 626 627 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 628 { 629 unsigned long flags; 630 u32 val; 631 632 spin_lock_irqsave(ð->rx_irq_lock, flags); 633 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 634 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 635 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 636 } 637 638 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 639 { 640 unsigned long flags; 641 u32 val; 642 643 spin_lock_irqsave(ð->rx_irq_lock, flags); 644 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 645 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 646 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 647 } 648 649 static int mtk_set_mac_address(struct net_device *dev, void *p) 650 { 651 int ret = eth_mac_addr(dev, p); 652 struct mtk_mac *mac = netdev_priv(dev); 653 struct mtk_eth *eth = mac->hw; 654 const char *macaddr = dev->dev_addr; 655 656 if (ret) 657 return ret; 658 659 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 660 return -EBUSY; 661 662 spin_lock_bh(&mac->hw->page_lock); 663 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 664 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 665 MT7628_SDM_MAC_ADRH); 666 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 667 (macaddr[4] << 8) | macaddr[5], 668 MT7628_SDM_MAC_ADRL); 669 } else { 670 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 671 MTK_GDMA_MAC_ADRH(mac->id)); 672 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 673 (macaddr[4] << 8) | macaddr[5], 674 MTK_GDMA_MAC_ADRL(mac->id)); 675 } 676 spin_unlock_bh(&mac->hw->page_lock); 677 678 return 0; 679 } 680 681 void mtk_stats_update_mac(struct mtk_mac *mac) 682 { 683 struct mtk_hw_stats *hw_stats = mac->hw_stats; 684 unsigned int base = MTK_GDM1_TX_GBCNT; 685 u64 stats; 686 687 base += hw_stats->reg_offset; 688 689 u64_stats_update_begin(&hw_stats->syncp); 690 691 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 692 stats = mtk_r32(mac->hw, base + 0x04); 693 if (stats) 694 hw_stats->rx_bytes += (stats << 32); 695 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 696 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 697 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 698 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 699 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 700 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 701 hw_stats->rx_flow_control_packets += 702 mtk_r32(mac->hw, base + 0x24); 703 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 704 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 705 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 706 stats = mtk_r32(mac->hw, base + 0x34); 707 if (stats) 708 hw_stats->tx_bytes += (stats << 32); 709 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 710 u64_stats_update_end(&hw_stats->syncp); 711 } 712 713 static void mtk_stats_update(struct mtk_eth *eth) 714 { 715 int i; 716 717 for (i = 0; i < MTK_MAC_COUNT; i++) { 718 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 719 continue; 720 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 721 mtk_stats_update_mac(eth->mac[i]); 722 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 723 } 724 } 725 } 726 727 static void mtk_get_stats64(struct net_device *dev, 728 struct rtnl_link_stats64 *storage) 729 { 730 struct mtk_mac *mac = netdev_priv(dev); 731 struct mtk_hw_stats *hw_stats = mac->hw_stats; 732 unsigned int start; 733 734 if (netif_running(dev) && netif_device_present(dev)) { 735 if (spin_trylock_bh(&hw_stats->stats_lock)) { 736 mtk_stats_update_mac(mac); 737 spin_unlock_bh(&hw_stats->stats_lock); 738 } 739 } 740 741 do { 742 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 743 storage->rx_packets = hw_stats->rx_packets; 744 storage->tx_packets = hw_stats->tx_packets; 745 storage->rx_bytes = hw_stats->rx_bytes; 746 storage->tx_bytes = hw_stats->tx_bytes; 747 storage->collisions = hw_stats->tx_collisions; 748 storage->rx_length_errors = hw_stats->rx_short_errors + 749 hw_stats->rx_long_errors; 750 storage->rx_over_errors = hw_stats->rx_overflow; 751 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 752 storage->rx_errors = hw_stats->rx_checksum_errors; 753 storage->tx_aborted_errors = hw_stats->tx_skip; 754 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 755 756 storage->tx_errors = dev->stats.tx_errors; 757 storage->rx_dropped = dev->stats.rx_dropped; 758 storage->tx_dropped = dev->stats.tx_dropped; 759 } 760 761 static inline int mtk_max_frag_size(int mtu) 762 { 763 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 764 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 765 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 766 767 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 768 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 769 } 770 771 static inline int mtk_max_buf_size(int frag_size) 772 { 773 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 774 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 775 776 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 777 778 return buf_size; 779 } 780 781 static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd, 782 struct mtk_rx_dma *dma_rxd) 783 { 784 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 785 if (!(rxd->rxd2 & RX_DMA_DONE)) 786 return false; 787 788 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 789 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 790 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 791 792 return true; 793 } 794 795 /* the qdma core needs scratch memory to be setup */ 796 static int mtk_init_fq_dma(struct mtk_eth *eth) 797 { 798 dma_addr_t phy_ring_tail; 799 int cnt = MTK_DMA_SIZE; 800 dma_addr_t dma_addr; 801 int i; 802 803 eth->scratch_ring = dma_alloc_coherent(eth->dev, 804 cnt * sizeof(struct mtk_tx_dma), 805 ð->phy_scratch_ring, 806 GFP_ATOMIC); 807 if (unlikely(!eth->scratch_ring)) 808 return -ENOMEM; 809 810 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 811 GFP_KERNEL); 812 if (unlikely(!eth->scratch_head)) 813 return -ENOMEM; 814 815 dma_addr = dma_map_single(eth->dev, 816 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 817 DMA_FROM_DEVICE); 818 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 819 return -ENOMEM; 820 821 phy_ring_tail = eth->phy_scratch_ring + 822 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 823 824 for (i = 0; i < cnt; i++) { 825 eth->scratch_ring[i].txd1 = 826 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 827 if (i < cnt - 1) 828 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 829 ((i + 1) * sizeof(struct mtk_tx_dma))); 830 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 831 } 832 833 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 834 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 835 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 836 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 837 838 return 0; 839 } 840 841 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 842 { 843 void *ret = ring->dma; 844 845 return ret + (desc - ring->phys); 846 } 847 848 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 849 struct mtk_tx_dma *txd) 850 { 851 int idx = txd - ring->dma; 852 853 return &ring->buf[idx]; 854 } 855 856 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 857 struct mtk_tx_dma *dma) 858 { 859 return ring->dma_pdma - ring->dma + dma; 860 } 861 862 static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma) 863 { 864 return ((void *)dma - (void *)ring->dma) / sizeof(*dma); 865 } 866 867 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 868 bool napi) 869 { 870 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 871 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 872 dma_unmap_single(eth->dev, 873 dma_unmap_addr(tx_buf, dma_addr0), 874 dma_unmap_len(tx_buf, dma_len0), 875 DMA_TO_DEVICE); 876 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 877 dma_unmap_page(eth->dev, 878 dma_unmap_addr(tx_buf, dma_addr0), 879 dma_unmap_len(tx_buf, dma_len0), 880 DMA_TO_DEVICE); 881 } 882 } else { 883 if (dma_unmap_len(tx_buf, dma_len0)) { 884 dma_unmap_page(eth->dev, 885 dma_unmap_addr(tx_buf, dma_addr0), 886 dma_unmap_len(tx_buf, dma_len0), 887 DMA_TO_DEVICE); 888 } 889 890 if (dma_unmap_len(tx_buf, dma_len1)) { 891 dma_unmap_page(eth->dev, 892 dma_unmap_addr(tx_buf, dma_addr1), 893 dma_unmap_len(tx_buf, dma_len1), 894 DMA_TO_DEVICE); 895 } 896 } 897 898 tx_buf->flags = 0; 899 if (tx_buf->skb && 900 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) { 901 if (napi) 902 napi_consume_skb(tx_buf->skb, napi); 903 else 904 dev_kfree_skb_any(tx_buf->skb); 905 } 906 tx_buf->skb = NULL; 907 } 908 909 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 910 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 911 size_t size, int idx) 912 { 913 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 914 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 915 dma_unmap_len_set(tx_buf, dma_len0, size); 916 } else { 917 if (idx & 1) { 918 txd->txd3 = mapped_addr; 919 txd->txd2 |= TX_DMA_PLEN1(size); 920 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 921 dma_unmap_len_set(tx_buf, dma_len1, size); 922 } else { 923 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 924 txd->txd1 = mapped_addr; 925 txd->txd2 = TX_DMA_PLEN0(size); 926 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 927 dma_unmap_len_set(tx_buf, dma_len0, size); 928 } 929 } 930 } 931 932 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 933 int tx_num, struct mtk_tx_ring *ring, bool gso) 934 { 935 struct mtk_mac *mac = netdev_priv(dev); 936 struct mtk_eth *eth = mac->hw; 937 struct mtk_tx_dma *itxd, *txd; 938 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 939 struct mtk_tx_buf *itx_buf, *tx_buf; 940 dma_addr_t mapped_addr; 941 unsigned int nr_frags; 942 int i, n_desc = 1; 943 u32 txd4 = 0, fport; 944 int k = 0; 945 946 itxd = ring->next_free; 947 itxd_pdma = qdma_to_pdma(ring, itxd); 948 if (itxd == ring->last_free) 949 return -ENOMEM; 950 951 /* set the forward port */ 952 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 953 txd4 |= fport; 954 955 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 956 memset(itx_buf, 0, sizeof(*itx_buf)); 957 958 if (gso) 959 txd4 |= TX_DMA_TSO; 960 961 /* TX Checksum offload */ 962 if (skb->ip_summed == CHECKSUM_PARTIAL) 963 txd4 |= TX_DMA_CHKSUM; 964 965 /* VLAN header offload */ 966 if (skb_vlan_tag_present(skb)) 967 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 968 969 mapped_addr = dma_map_single(eth->dev, skb->data, 970 skb_headlen(skb), DMA_TO_DEVICE); 971 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 972 return -ENOMEM; 973 974 WRITE_ONCE(itxd->txd1, mapped_addr); 975 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 976 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 977 MTK_TX_FLAGS_FPORT1; 978 setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb), 979 k++); 980 981 /* TX SG offload */ 982 txd = itxd; 983 txd_pdma = qdma_to_pdma(ring, txd); 984 nr_frags = skb_shinfo(skb)->nr_frags; 985 986 for (i = 0; i < nr_frags; i++) { 987 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 988 unsigned int offset = 0; 989 int frag_size = skb_frag_size(frag); 990 991 while (frag_size) { 992 bool last_frag = false; 993 unsigned int frag_map_size; 994 bool new_desc = true; 995 996 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) || 997 (i & 0x1)) { 998 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 999 txd_pdma = qdma_to_pdma(ring, txd); 1000 if (txd == ring->last_free) 1001 goto err_dma; 1002 1003 n_desc++; 1004 } else { 1005 new_desc = false; 1006 } 1007 1008 1009 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 1010 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 1011 frag_map_size, 1012 DMA_TO_DEVICE); 1013 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 1014 goto err_dma; 1015 1016 if (i == nr_frags - 1 && 1017 (frag_size - frag_map_size) == 0) 1018 last_frag = true; 1019 1020 WRITE_ONCE(txd->txd1, mapped_addr); 1021 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 1022 TX_DMA_PLEN0(frag_map_size) | 1023 last_frag * TX_DMA_LS0)); 1024 WRITE_ONCE(txd->txd4, fport); 1025 1026 tx_buf = mtk_desc_to_tx_buf(ring, txd); 1027 if (new_desc) 1028 memset(tx_buf, 0, sizeof(*tx_buf)); 1029 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 1030 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1031 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1032 MTK_TX_FLAGS_FPORT1; 1033 1034 setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr, 1035 frag_map_size, k++); 1036 1037 frag_size -= frag_map_size; 1038 offset += frag_map_size; 1039 } 1040 } 1041 1042 /* store skb to cleanup */ 1043 itx_buf->skb = skb; 1044 1045 WRITE_ONCE(itxd->txd4, txd4); 1046 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 1047 (!nr_frags * TX_DMA_LS0))); 1048 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1049 if (k & 0x1) 1050 txd_pdma->txd2 |= TX_DMA_LS0; 1051 else 1052 txd_pdma->txd2 |= TX_DMA_LS1; 1053 } 1054 1055 netdev_sent_queue(dev, skb->len); 1056 skb_tx_timestamp(skb); 1057 1058 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1059 atomic_sub(n_desc, &ring->free_count); 1060 1061 /* make sure that all changes to the dma ring are flushed before we 1062 * continue 1063 */ 1064 wmb(); 1065 1066 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1067 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 1068 !netdev_xmit_more()) 1069 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 1070 } else { 1071 int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd), 1072 ring->dma_size); 1073 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1074 } 1075 1076 return 0; 1077 1078 err_dma: 1079 do { 1080 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 1081 1082 /* unmap dma */ 1083 mtk_tx_unmap(eth, tx_buf, false); 1084 1085 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1086 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1087 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1088 1089 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1090 itxd_pdma = qdma_to_pdma(ring, itxd); 1091 } while (itxd != txd); 1092 1093 return -ENOMEM; 1094 } 1095 1096 static inline int mtk_cal_txd_req(struct sk_buff *skb) 1097 { 1098 int i, nfrags; 1099 skb_frag_t *frag; 1100 1101 nfrags = 1; 1102 if (skb_is_gso(skb)) { 1103 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1104 frag = &skb_shinfo(skb)->frags[i]; 1105 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1106 MTK_TX_DMA_BUF_LEN); 1107 } 1108 } else { 1109 nfrags += skb_shinfo(skb)->nr_frags; 1110 } 1111 1112 return nfrags; 1113 } 1114 1115 static int mtk_queue_stopped(struct mtk_eth *eth) 1116 { 1117 int i; 1118 1119 for (i = 0; i < MTK_MAC_COUNT; i++) { 1120 if (!eth->netdev[i]) 1121 continue; 1122 if (netif_queue_stopped(eth->netdev[i])) 1123 return 1; 1124 } 1125 1126 return 0; 1127 } 1128 1129 static void mtk_wake_queue(struct mtk_eth *eth) 1130 { 1131 int i; 1132 1133 for (i = 0; i < MTK_MAC_COUNT; i++) { 1134 if (!eth->netdev[i]) 1135 continue; 1136 netif_wake_queue(eth->netdev[i]); 1137 } 1138 } 1139 1140 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1141 { 1142 struct mtk_mac *mac = netdev_priv(dev); 1143 struct mtk_eth *eth = mac->hw; 1144 struct mtk_tx_ring *ring = ð->tx_ring; 1145 struct net_device_stats *stats = &dev->stats; 1146 bool gso = false; 1147 int tx_num; 1148 1149 /* normally we can rely on the stack not calling this more than once, 1150 * however we have 2 queues running on the same ring so we need to lock 1151 * the ring access 1152 */ 1153 spin_lock(ð->page_lock); 1154 1155 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1156 goto drop; 1157 1158 tx_num = mtk_cal_txd_req(skb); 1159 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1160 netif_stop_queue(dev); 1161 netif_err(eth, tx_queued, dev, 1162 "Tx Ring full when queue awake!\n"); 1163 spin_unlock(ð->page_lock); 1164 return NETDEV_TX_BUSY; 1165 } 1166 1167 /* TSO: fill MSS info in tcp checksum field */ 1168 if (skb_is_gso(skb)) { 1169 if (skb_cow_head(skb, 0)) { 1170 netif_warn(eth, tx_err, dev, 1171 "GSO expand head fail.\n"); 1172 goto drop; 1173 } 1174 1175 if (skb_shinfo(skb)->gso_type & 1176 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1177 gso = true; 1178 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1179 } 1180 } 1181 1182 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1183 goto drop; 1184 1185 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1186 netif_stop_queue(dev); 1187 1188 spin_unlock(ð->page_lock); 1189 1190 return NETDEV_TX_OK; 1191 1192 drop: 1193 spin_unlock(ð->page_lock); 1194 stats->tx_dropped++; 1195 dev_kfree_skb_any(skb); 1196 return NETDEV_TX_OK; 1197 } 1198 1199 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1200 { 1201 int i; 1202 struct mtk_rx_ring *ring; 1203 int idx; 1204 1205 if (!eth->hwlro) 1206 return ð->rx_ring[0]; 1207 1208 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1209 ring = ð->rx_ring[i]; 1210 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1211 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 1212 ring->calc_idx_update = true; 1213 return ring; 1214 } 1215 } 1216 1217 return NULL; 1218 } 1219 1220 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1221 { 1222 struct mtk_rx_ring *ring; 1223 int i; 1224 1225 if (!eth->hwlro) { 1226 ring = ð->rx_ring[0]; 1227 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1228 } else { 1229 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1230 ring = ð->rx_ring[i]; 1231 if (ring->calc_idx_update) { 1232 ring->calc_idx_update = false; 1233 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1234 } 1235 } 1236 } 1237 } 1238 1239 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1240 struct mtk_eth *eth) 1241 { 1242 struct dim_sample dim_sample = {}; 1243 struct mtk_rx_ring *ring; 1244 int idx; 1245 struct sk_buff *skb; 1246 u8 *data, *new_data; 1247 struct mtk_rx_dma *rxd, trxd; 1248 int done = 0, bytes = 0; 1249 1250 while (done < budget) { 1251 struct net_device *netdev; 1252 unsigned int pktlen; 1253 dma_addr_t dma_addr; 1254 u32 hash; 1255 int mac; 1256 1257 ring = mtk_get_rx_ring(eth); 1258 if (unlikely(!ring)) 1259 goto rx_done; 1260 1261 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1262 rxd = &ring->dma[idx]; 1263 data = ring->data[idx]; 1264 1265 if (!mtk_rx_get_desc(&trxd, rxd)) 1266 break; 1267 1268 /* find out which mac the packet come from. values start at 1 */ 1269 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) || 1270 (trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 1271 mac = 0; 1272 else 1273 mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 1274 RX_DMA_FPORT_MASK) - 1; 1275 1276 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1277 !eth->netdev[mac])) 1278 goto release_desc; 1279 1280 netdev = eth->netdev[mac]; 1281 1282 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1283 goto release_desc; 1284 1285 /* alloc new buffer */ 1286 new_data = napi_alloc_frag(ring->frag_size); 1287 if (unlikely(!new_data)) { 1288 netdev->stats.rx_dropped++; 1289 goto release_desc; 1290 } 1291 dma_addr = dma_map_single(eth->dev, 1292 new_data + NET_SKB_PAD + 1293 eth->ip_align, 1294 ring->buf_size, 1295 DMA_FROM_DEVICE); 1296 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 1297 skb_free_frag(new_data); 1298 netdev->stats.rx_dropped++; 1299 goto release_desc; 1300 } 1301 1302 dma_unmap_single(eth->dev, trxd.rxd1, 1303 ring->buf_size, DMA_FROM_DEVICE); 1304 1305 /* receive data */ 1306 skb = build_skb(data, ring->frag_size); 1307 if (unlikely(!skb)) { 1308 skb_free_frag(data); 1309 netdev->stats.rx_dropped++; 1310 goto skip_rx; 1311 } 1312 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1313 1314 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1315 skb->dev = netdev; 1316 skb_put(skb, pktlen); 1317 if (trxd.rxd4 & eth->rx_dma_l4_valid) 1318 skb->ip_summed = CHECKSUM_UNNECESSARY; 1319 else 1320 skb_checksum_none_assert(skb); 1321 skb->protocol = eth_type_trans(skb, netdev); 1322 bytes += pktlen; 1323 1324 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 1325 if (hash != MTK_RXD4_FOE_ENTRY) { 1326 hash = jhash_1word(hash, 0); 1327 skb_set_hash(skb, hash, PKT_HASH_TYPE_L4); 1328 } 1329 1330 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1331 (trxd.rxd2 & RX_DMA_VTAG)) 1332 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1333 RX_DMA_VID(trxd.rxd3)); 1334 skb_record_rx_queue(skb, 0); 1335 napi_gro_receive(napi, skb); 1336 1337 skip_rx: 1338 ring->data[idx] = new_data; 1339 rxd->rxd1 = (unsigned int)dma_addr; 1340 1341 release_desc: 1342 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1343 rxd->rxd2 = RX_DMA_LSO; 1344 else 1345 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1346 1347 ring->calc_idx = idx; 1348 1349 done++; 1350 } 1351 1352 rx_done: 1353 if (done) { 1354 /* make sure that all changes to the dma ring are flushed before 1355 * we continue 1356 */ 1357 wmb(); 1358 mtk_update_rx_cpu_idx(eth); 1359 } 1360 1361 eth->rx_packets += done; 1362 eth->rx_bytes += bytes; 1363 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 1364 &dim_sample); 1365 net_dim(ð->rx_dim, dim_sample); 1366 1367 return done; 1368 } 1369 1370 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 1371 unsigned int *done, unsigned int *bytes) 1372 { 1373 struct mtk_tx_ring *ring = ð->tx_ring; 1374 struct mtk_tx_dma *desc; 1375 struct sk_buff *skb; 1376 struct mtk_tx_buf *tx_buf; 1377 u32 cpu, dma; 1378 1379 cpu = ring->last_free_ptr; 1380 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1381 1382 desc = mtk_qdma_phys_to_virt(ring, cpu); 1383 1384 while ((cpu != dma) && budget) { 1385 u32 next_cpu = desc->txd2; 1386 int mac = 0; 1387 1388 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1389 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1390 break; 1391 1392 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1393 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1394 mac = 1; 1395 1396 skb = tx_buf->skb; 1397 if (!skb) 1398 break; 1399 1400 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1401 bytes[mac] += skb->len; 1402 done[mac]++; 1403 budget--; 1404 } 1405 mtk_tx_unmap(eth, tx_buf, true); 1406 1407 ring->last_free = desc; 1408 atomic_inc(&ring->free_count); 1409 1410 cpu = next_cpu; 1411 } 1412 1413 ring->last_free_ptr = cpu; 1414 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1415 1416 return budget; 1417 } 1418 1419 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 1420 unsigned int *done, unsigned int *bytes) 1421 { 1422 struct mtk_tx_ring *ring = ð->tx_ring; 1423 struct mtk_tx_dma *desc; 1424 struct sk_buff *skb; 1425 struct mtk_tx_buf *tx_buf; 1426 u32 cpu, dma; 1427 1428 cpu = ring->cpu_idx; 1429 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 1430 1431 while ((cpu != dma) && budget) { 1432 tx_buf = &ring->buf[cpu]; 1433 skb = tx_buf->skb; 1434 if (!skb) 1435 break; 1436 1437 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1438 bytes[0] += skb->len; 1439 done[0]++; 1440 budget--; 1441 } 1442 1443 mtk_tx_unmap(eth, tx_buf, true); 1444 1445 desc = &ring->dma[cpu]; 1446 ring->last_free = desc; 1447 atomic_inc(&ring->free_count); 1448 1449 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 1450 } 1451 1452 ring->cpu_idx = cpu; 1453 1454 return budget; 1455 } 1456 1457 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1458 { 1459 struct mtk_tx_ring *ring = ð->tx_ring; 1460 struct dim_sample dim_sample = {}; 1461 unsigned int done[MTK_MAX_DEVS]; 1462 unsigned int bytes[MTK_MAX_DEVS]; 1463 int total = 0, i; 1464 1465 memset(done, 0, sizeof(done)); 1466 memset(bytes, 0, sizeof(bytes)); 1467 1468 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1469 budget = mtk_poll_tx_qdma(eth, budget, done, bytes); 1470 else 1471 budget = mtk_poll_tx_pdma(eth, budget, done, bytes); 1472 1473 for (i = 0; i < MTK_MAC_COUNT; i++) { 1474 if (!eth->netdev[i] || !done[i]) 1475 continue; 1476 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1477 total += done[i]; 1478 eth->tx_packets += done[i]; 1479 eth->tx_bytes += bytes[i]; 1480 } 1481 1482 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 1483 &dim_sample); 1484 net_dim(ð->tx_dim, dim_sample); 1485 1486 if (mtk_queue_stopped(eth) && 1487 (atomic_read(&ring->free_count) > ring->thresh)) 1488 mtk_wake_queue(eth); 1489 1490 return total; 1491 } 1492 1493 static void mtk_handle_status_irq(struct mtk_eth *eth) 1494 { 1495 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1496 1497 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1498 mtk_stats_update(eth); 1499 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1500 MTK_INT_STATUS2); 1501 } 1502 } 1503 1504 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1505 { 1506 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1507 int tx_done = 0; 1508 1509 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1510 mtk_handle_status_irq(eth); 1511 mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg); 1512 tx_done = mtk_poll_tx(eth, budget); 1513 1514 if (unlikely(netif_msg_intr(eth))) { 1515 dev_info(eth->dev, 1516 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 1517 mtk_r32(eth, eth->tx_int_status_reg), 1518 mtk_r32(eth, eth->tx_int_mask_reg)); 1519 } 1520 1521 if (tx_done == budget) 1522 return budget; 1523 1524 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) 1525 return budget; 1526 1527 if (napi_complete_done(napi, tx_done)) 1528 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1529 1530 return tx_done; 1531 } 1532 1533 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1534 { 1535 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1536 int rx_done_total = 0; 1537 1538 mtk_handle_status_irq(eth); 1539 1540 do { 1541 int rx_done; 1542 1543 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1544 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 1545 rx_done_total += rx_done; 1546 1547 if (unlikely(netif_msg_intr(eth))) { 1548 dev_info(eth->dev, 1549 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 1550 mtk_r32(eth, MTK_PDMA_INT_STATUS), 1551 mtk_r32(eth, MTK_PDMA_INT_MASK)); 1552 } 1553 1554 if (rx_done_total == budget) 1555 return budget; 1556 1557 } while (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT); 1558 1559 if (napi_complete_done(napi, rx_done_total)) 1560 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1561 1562 return rx_done_total; 1563 } 1564 1565 static int mtk_tx_alloc(struct mtk_eth *eth) 1566 { 1567 struct mtk_tx_ring *ring = ð->tx_ring; 1568 int i, sz = sizeof(*ring->dma); 1569 1570 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1571 GFP_KERNEL); 1572 if (!ring->buf) 1573 goto no_tx_mem; 1574 1575 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1576 &ring->phys, GFP_ATOMIC); 1577 if (!ring->dma) 1578 goto no_tx_mem; 1579 1580 for (i = 0; i < MTK_DMA_SIZE; i++) { 1581 int next = (i + 1) % MTK_DMA_SIZE; 1582 u32 next_ptr = ring->phys + next * sz; 1583 1584 ring->dma[i].txd2 = next_ptr; 1585 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1586 } 1587 1588 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 1589 * only as the framework. The real HW descriptors are the PDMA 1590 * descriptors in ring->dma_pdma. 1591 */ 1592 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1593 ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1594 &ring->phys_pdma, 1595 GFP_ATOMIC); 1596 if (!ring->dma_pdma) 1597 goto no_tx_mem; 1598 1599 for (i = 0; i < MTK_DMA_SIZE; i++) { 1600 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 1601 ring->dma_pdma[i].txd4 = 0; 1602 } 1603 } 1604 1605 ring->dma_size = MTK_DMA_SIZE; 1606 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1607 ring->next_free = &ring->dma[0]; 1608 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1609 ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz)); 1610 ring->thresh = MAX_SKB_FRAGS; 1611 1612 /* make sure that all changes to the dma ring are flushed before we 1613 * continue 1614 */ 1615 wmb(); 1616 1617 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1618 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1619 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1620 mtk_w32(eth, 1621 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1622 MTK_QTX_CRX_PTR); 1623 mtk_w32(eth, ring->last_free_ptr, MTK_QTX_DRX_PTR); 1624 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, 1625 MTK_QTX_CFG(0)); 1626 } else { 1627 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 1628 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); 1629 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 1630 mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX); 1631 } 1632 1633 return 0; 1634 1635 no_tx_mem: 1636 return -ENOMEM; 1637 } 1638 1639 static void mtk_tx_clean(struct mtk_eth *eth) 1640 { 1641 struct mtk_tx_ring *ring = ð->tx_ring; 1642 int i; 1643 1644 if (ring->buf) { 1645 for (i = 0; i < MTK_DMA_SIZE; i++) 1646 mtk_tx_unmap(eth, &ring->buf[i], false); 1647 kfree(ring->buf); 1648 ring->buf = NULL; 1649 } 1650 1651 if (ring->dma) { 1652 dma_free_coherent(eth->dev, 1653 MTK_DMA_SIZE * sizeof(*ring->dma), 1654 ring->dma, 1655 ring->phys); 1656 ring->dma = NULL; 1657 } 1658 1659 if (ring->dma_pdma) { 1660 dma_free_coherent(eth->dev, 1661 MTK_DMA_SIZE * sizeof(*ring->dma_pdma), 1662 ring->dma_pdma, 1663 ring->phys_pdma); 1664 ring->dma_pdma = NULL; 1665 } 1666 } 1667 1668 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1669 { 1670 struct mtk_rx_ring *ring; 1671 int rx_data_len, rx_dma_size; 1672 int i; 1673 u32 offset = 0; 1674 1675 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1676 if (ring_no) 1677 return -EINVAL; 1678 ring = ð->rx_ring_qdma; 1679 offset = 0x1000; 1680 } else { 1681 ring = ð->rx_ring[ring_no]; 1682 } 1683 1684 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1685 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1686 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1687 } else { 1688 rx_data_len = ETH_DATA_LEN; 1689 rx_dma_size = MTK_DMA_SIZE; 1690 } 1691 1692 ring->frag_size = mtk_max_frag_size(rx_data_len); 1693 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1694 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1695 GFP_KERNEL); 1696 if (!ring->data) 1697 return -ENOMEM; 1698 1699 for (i = 0; i < rx_dma_size; i++) { 1700 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1701 if (!ring->data[i]) 1702 return -ENOMEM; 1703 } 1704 1705 ring->dma = dma_alloc_coherent(eth->dev, 1706 rx_dma_size * sizeof(*ring->dma), 1707 &ring->phys, GFP_ATOMIC); 1708 if (!ring->dma) 1709 return -ENOMEM; 1710 1711 for (i = 0; i < rx_dma_size; i++) { 1712 dma_addr_t dma_addr = dma_map_single(eth->dev, 1713 ring->data[i] + NET_SKB_PAD + eth->ip_align, 1714 ring->buf_size, 1715 DMA_FROM_DEVICE); 1716 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1717 return -ENOMEM; 1718 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1719 1720 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1721 ring->dma[i].rxd2 = RX_DMA_LSO; 1722 else 1723 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1724 } 1725 ring->dma_size = rx_dma_size; 1726 ring->calc_idx_update = false; 1727 ring->calc_idx = rx_dma_size - 1; 1728 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1729 /* make sure that all changes to the dma ring are flushed before we 1730 * continue 1731 */ 1732 wmb(); 1733 1734 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1735 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1736 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1737 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1738 1739 return 0; 1740 } 1741 1742 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1743 { 1744 int i; 1745 1746 if (ring->data && ring->dma) { 1747 for (i = 0; i < ring->dma_size; i++) { 1748 if (!ring->data[i]) 1749 continue; 1750 if (!ring->dma[i].rxd1) 1751 continue; 1752 dma_unmap_single(eth->dev, 1753 ring->dma[i].rxd1, 1754 ring->buf_size, 1755 DMA_FROM_DEVICE); 1756 skb_free_frag(ring->data[i]); 1757 } 1758 kfree(ring->data); 1759 ring->data = NULL; 1760 } 1761 1762 if (ring->dma) { 1763 dma_free_coherent(eth->dev, 1764 ring->dma_size * sizeof(*ring->dma), 1765 ring->dma, 1766 ring->phys); 1767 ring->dma = NULL; 1768 } 1769 } 1770 1771 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1772 { 1773 int i; 1774 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1775 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1776 1777 /* set LRO rings to auto-learn modes */ 1778 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1779 1780 /* validate LRO ring */ 1781 ring_ctrl_dw2 |= MTK_RING_VLD; 1782 1783 /* set AGE timer (unit: 20us) */ 1784 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1785 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1786 1787 /* set max AGG timer (unit: 20us) */ 1788 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1789 1790 /* set max LRO AGG count */ 1791 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1792 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1793 1794 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1795 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1796 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1797 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1798 } 1799 1800 /* IPv4 checksum update enable */ 1801 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1802 1803 /* switch priority comparison to packet count mode */ 1804 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1805 1806 /* bandwidth threshold setting */ 1807 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1808 1809 /* auto-learn score delta setting */ 1810 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1811 1812 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1813 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1814 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1815 1816 /* set HW LRO mode & the max aggregation count for rx packets */ 1817 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1818 1819 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1820 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1821 1822 /* enable HW LRO */ 1823 lro_ctrl_dw0 |= MTK_LRO_EN; 1824 1825 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1826 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1827 1828 return 0; 1829 } 1830 1831 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1832 { 1833 int i; 1834 u32 val; 1835 1836 /* relinquish lro rings, flush aggregated packets */ 1837 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1838 1839 /* wait for relinquishments done */ 1840 for (i = 0; i < 10; i++) { 1841 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1842 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1843 msleep(20); 1844 continue; 1845 } 1846 break; 1847 } 1848 1849 /* invalidate lro rings */ 1850 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1851 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1852 1853 /* disable HW LRO */ 1854 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1855 } 1856 1857 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1858 { 1859 u32 reg_val; 1860 1861 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1862 1863 /* invalidate the IP setting */ 1864 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1865 1866 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1867 1868 /* validate the IP setting */ 1869 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1870 } 1871 1872 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1873 { 1874 u32 reg_val; 1875 1876 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1877 1878 /* invalidate the IP setting */ 1879 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1880 1881 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1882 } 1883 1884 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1885 { 1886 int cnt = 0; 1887 int i; 1888 1889 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1890 if (mac->hwlro_ip[i]) 1891 cnt++; 1892 } 1893 1894 return cnt; 1895 } 1896 1897 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1898 struct ethtool_rxnfc *cmd) 1899 { 1900 struct ethtool_rx_flow_spec *fsp = 1901 (struct ethtool_rx_flow_spec *)&cmd->fs; 1902 struct mtk_mac *mac = netdev_priv(dev); 1903 struct mtk_eth *eth = mac->hw; 1904 int hwlro_idx; 1905 1906 if ((fsp->flow_type != TCP_V4_FLOW) || 1907 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1908 (fsp->location > 1)) 1909 return -EINVAL; 1910 1911 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1912 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1913 1914 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1915 1916 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1917 1918 return 0; 1919 } 1920 1921 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1922 struct ethtool_rxnfc *cmd) 1923 { 1924 struct ethtool_rx_flow_spec *fsp = 1925 (struct ethtool_rx_flow_spec *)&cmd->fs; 1926 struct mtk_mac *mac = netdev_priv(dev); 1927 struct mtk_eth *eth = mac->hw; 1928 int hwlro_idx; 1929 1930 if (fsp->location > 1) 1931 return -EINVAL; 1932 1933 mac->hwlro_ip[fsp->location] = 0; 1934 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1935 1936 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1937 1938 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1939 1940 return 0; 1941 } 1942 1943 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1944 { 1945 struct mtk_mac *mac = netdev_priv(dev); 1946 struct mtk_eth *eth = mac->hw; 1947 int i, hwlro_idx; 1948 1949 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1950 mac->hwlro_ip[i] = 0; 1951 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1952 1953 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1954 } 1955 1956 mac->hwlro_ip_cnt = 0; 1957 } 1958 1959 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1960 struct ethtool_rxnfc *cmd) 1961 { 1962 struct mtk_mac *mac = netdev_priv(dev); 1963 struct ethtool_rx_flow_spec *fsp = 1964 (struct ethtool_rx_flow_spec *)&cmd->fs; 1965 1966 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1967 fsp->flow_type = TCP_V4_FLOW; 1968 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1969 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1970 1971 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1972 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1973 fsp->h_u.tcp_ip4_spec.psrc = 0; 1974 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1975 fsp->h_u.tcp_ip4_spec.pdst = 0; 1976 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1977 fsp->h_u.tcp_ip4_spec.tos = 0; 1978 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1979 1980 return 0; 1981 } 1982 1983 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1984 struct ethtool_rxnfc *cmd, 1985 u32 *rule_locs) 1986 { 1987 struct mtk_mac *mac = netdev_priv(dev); 1988 int cnt = 0; 1989 int i; 1990 1991 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1992 if (mac->hwlro_ip[i]) { 1993 rule_locs[cnt] = i; 1994 cnt++; 1995 } 1996 } 1997 1998 cmd->rule_cnt = cnt; 1999 2000 return 0; 2001 } 2002 2003 static netdev_features_t mtk_fix_features(struct net_device *dev, 2004 netdev_features_t features) 2005 { 2006 if (!(features & NETIF_F_LRO)) { 2007 struct mtk_mac *mac = netdev_priv(dev); 2008 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2009 2010 if (ip_cnt) { 2011 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 2012 2013 features |= NETIF_F_LRO; 2014 } 2015 } 2016 2017 return features; 2018 } 2019 2020 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2021 { 2022 int err = 0; 2023 2024 if (!((dev->features ^ features) & NETIF_F_LRO)) 2025 return 0; 2026 2027 if (!(features & NETIF_F_LRO)) 2028 mtk_hwlro_netdev_disable(dev); 2029 2030 return err; 2031 } 2032 2033 /* wait for DMA to finish whatever it is doing before we start using it again */ 2034 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2035 { 2036 unsigned int reg; 2037 int ret; 2038 u32 val; 2039 2040 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2041 reg = MTK_QDMA_GLO_CFG; 2042 else 2043 reg = MTK_PDMA_GLO_CFG; 2044 2045 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 2046 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 2047 5, MTK_DMA_BUSY_TIMEOUT_US); 2048 if (ret) 2049 dev_err(eth->dev, "DMA init timeout\n"); 2050 2051 return ret; 2052 } 2053 2054 static int mtk_dma_init(struct mtk_eth *eth) 2055 { 2056 int err; 2057 u32 i; 2058 2059 if (mtk_dma_busy_wait(eth)) 2060 return -EBUSY; 2061 2062 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2063 /* QDMA needs scratch memory for internal reordering of the 2064 * descriptors 2065 */ 2066 err = mtk_init_fq_dma(eth); 2067 if (err) 2068 return err; 2069 } 2070 2071 err = mtk_tx_alloc(eth); 2072 if (err) 2073 return err; 2074 2075 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2076 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2077 if (err) 2078 return err; 2079 } 2080 2081 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2082 if (err) 2083 return err; 2084 2085 if (eth->hwlro) { 2086 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2087 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2088 if (err) 2089 return err; 2090 } 2091 err = mtk_hwlro_rx_init(eth); 2092 if (err) 2093 return err; 2094 } 2095 2096 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2097 /* Enable random early drop and set drop threshold 2098 * automatically 2099 */ 2100 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2101 FC_THRES_MIN, MTK_QDMA_FC_THRES); 2102 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 2103 } 2104 2105 return 0; 2106 } 2107 2108 static void mtk_dma_free(struct mtk_eth *eth) 2109 { 2110 int i; 2111 2112 for (i = 0; i < MTK_MAC_COUNT; i++) 2113 if (eth->netdev[i]) 2114 netdev_reset_queue(eth->netdev[i]); 2115 if (eth->scratch_ring) { 2116 dma_free_coherent(eth->dev, 2117 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 2118 eth->scratch_ring, 2119 eth->phy_scratch_ring); 2120 eth->scratch_ring = NULL; 2121 eth->phy_scratch_ring = 0; 2122 } 2123 mtk_tx_clean(eth); 2124 mtk_rx_clean(eth, ð->rx_ring[0]); 2125 mtk_rx_clean(eth, ð->rx_ring_qdma); 2126 2127 if (eth->hwlro) { 2128 mtk_hwlro_rx_uninit(eth); 2129 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2130 mtk_rx_clean(eth, ð->rx_ring[i]); 2131 } 2132 2133 kfree(eth->scratch_head); 2134 } 2135 2136 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 2137 { 2138 struct mtk_mac *mac = netdev_priv(dev); 2139 struct mtk_eth *eth = mac->hw; 2140 2141 eth->netdev[mac->id]->stats.tx_errors++; 2142 netif_err(eth, tx_err, dev, 2143 "transmit timed out\n"); 2144 schedule_work(ð->pending_work); 2145 } 2146 2147 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 2148 { 2149 struct mtk_eth *eth = _eth; 2150 2151 eth->rx_events++; 2152 if (likely(napi_schedule_prep(ð->rx_napi))) { 2153 __napi_schedule(ð->rx_napi); 2154 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2155 } 2156 2157 return IRQ_HANDLED; 2158 } 2159 2160 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 2161 { 2162 struct mtk_eth *eth = _eth; 2163 2164 eth->tx_events++; 2165 if (likely(napi_schedule_prep(ð->tx_napi))) { 2166 __napi_schedule(ð->tx_napi); 2167 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2168 } 2169 2170 return IRQ_HANDLED; 2171 } 2172 2173 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 2174 { 2175 struct mtk_eth *eth = _eth; 2176 2177 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { 2178 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) 2179 mtk_handle_irq_rx(irq, _eth); 2180 } 2181 if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) { 2182 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) 2183 mtk_handle_irq_tx(irq, _eth); 2184 } 2185 2186 return IRQ_HANDLED; 2187 } 2188 2189 #ifdef CONFIG_NET_POLL_CONTROLLER 2190 static void mtk_poll_controller(struct net_device *dev) 2191 { 2192 struct mtk_mac *mac = netdev_priv(dev); 2193 struct mtk_eth *eth = mac->hw; 2194 2195 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2196 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2197 mtk_handle_irq_rx(eth->irq[2], dev); 2198 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2199 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2200 } 2201 #endif 2202 2203 static int mtk_start_dma(struct mtk_eth *eth) 2204 { 2205 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 2206 int err; 2207 2208 err = mtk_dma_init(eth); 2209 if (err) { 2210 mtk_dma_free(eth); 2211 return err; 2212 } 2213 2214 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2215 mtk_w32(eth, 2216 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 2217 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 2218 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 2219 MTK_RX_BT_32DWORDS, 2220 MTK_QDMA_GLO_CFG); 2221 2222 mtk_w32(eth, 2223 MTK_RX_DMA_EN | rx_2b_offset | 2224 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 2225 MTK_PDMA_GLO_CFG); 2226 } else { 2227 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2228 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 2229 MTK_PDMA_GLO_CFG); 2230 } 2231 2232 return 0; 2233 } 2234 2235 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 2236 { 2237 int i; 2238 2239 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2240 return; 2241 2242 for (i = 0; i < MTK_MAC_COUNT; i++) { 2243 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 2244 2245 /* default setup the forward port to send frame to PDMA */ 2246 val &= ~0xffff; 2247 2248 /* Enable RX checksum */ 2249 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2250 2251 val |= config; 2252 2253 if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0])) 2254 val |= MTK_GDMA_SPECIAL_TAG; 2255 2256 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2257 } 2258 /* Reset and enable PSE */ 2259 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 2260 mtk_w32(eth, 0, MTK_RST_GL); 2261 } 2262 2263 static int mtk_open(struct net_device *dev) 2264 { 2265 struct mtk_mac *mac = netdev_priv(dev); 2266 struct mtk_eth *eth = mac->hw; 2267 int err; 2268 2269 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 2270 if (err) { 2271 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 2272 err); 2273 return err; 2274 } 2275 2276 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 2277 if (!refcount_read(ð->dma_refcnt)) { 2278 u32 gdm_config = MTK_GDMA_TO_PDMA; 2279 int err; 2280 2281 err = mtk_start_dma(eth); 2282 if (err) 2283 return err; 2284 2285 if (eth->soc->offload_version && mtk_ppe_start(ð->ppe) == 0) 2286 gdm_config = MTK_GDMA_TO_PPE; 2287 2288 mtk_gdm_config(eth, gdm_config); 2289 2290 napi_enable(ð->tx_napi); 2291 napi_enable(ð->rx_napi); 2292 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2293 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2294 refcount_set(ð->dma_refcnt, 1); 2295 } 2296 else 2297 refcount_inc(ð->dma_refcnt); 2298 2299 phylink_start(mac->phylink); 2300 netif_start_queue(dev); 2301 return 0; 2302 } 2303 2304 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 2305 { 2306 u32 val; 2307 int i; 2308 2309 /* stop the dma engine */ 2310 spin_lock_bh(ð->page_lock); 2311 val = mtk_r32(eth, glo_cfg); 2312 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 2313 glo_cfg); 2314 spin_unlock_bh(ð->page_lock); 2315 2316 /* wait for dma stop */ 2317 for (i = 0; i < 10; i++) { 2318 val = mtk_r32(eth, glo_cfg); 2319 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 2320 msleep(20); 2321 continue; 2322 } 2323 break; 2324 } 2325 } 2326 2327 static int mtk_stop(struct net_device *dev) 2328 { 2329 struct mtk_mac *mac = netdev_priv(dev); 2330 struct mtk_eth *eth = mac->hw; 2331 2332 phylink_stop(mac->phylink); 2333 2334 netif_tx_disable(dev); 2335 2336 phylink_disconnect_phy(mac->phylink); 2337 2338 /* only shutdown DMA if this is the last user */ 2339 if (!refcount_dec_and_test(ð->dma_refcnt)) 2340 return 0; 2341 2342 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 2343 2344 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2345 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2346 napi_disable(ð->tx_napi); 2347 napi_disable(ð->rx_napi); 2348 2349 cancel_work_sync(ð->rx_dim.work); 2350 cancel_work_sync(ð->tx_dim.work); 2351 2352 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2353 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 2354 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 2355 2356 mtk_dma_free(eth); 2357 2358 if (eth->soc->offload_version) 2359 mtk_ppe_stop(ð->ppe); 2360 2361 return 0; 2362 } 2363 2364 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 2365 { 2366 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2367 reset_bits, 2368 reset_bits); 2369 2370 usleep_range(1000, 1100); 2371 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2372 reset_bits, 2373 ~reset_bits); 2374 mdelay(10); 2375 } 2376 2377 static void mtk_clk_disable(struct mtk_eth *eth) 2378 { 2379 int clk; 2380 2381 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 2382 clk_disable_unprepare(eth->clks[clk]); 2383 } 2384 2385 static int mtk_clk_enable(struct mtk_eth *eth) 2386 { 2387 int clk, ret; 2388 2389 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 2390 ret = clk_prepare_enable(eth->clks[clk]); 2391 if (ret) 2392 goto err_disable_clks; 2393 } 2394 2395 return 0; 2396 2397 err_disable_clks: 2398 while (--clk >= 0) 2399 clk_disable_unprepare(eth->clks[clk]); 2400 2401 return ret; 2402 } 2403 2404 static void mtk_dim_rx(struct work_struct *work) 2405 { 2406 struct dim *dim = container_of(work, struct dim, work); 2407 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 2408 struct dim_cq_moder cur_profile; 2409 u32 val, cur; 2410 2411 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 2412 dim->profile_ix); 2413 spin_lock_bh(ð->dim_lock); 2414 2415 val = mtk_r32(eth, MTK_PDMA_DELAY_INT); 2416 val &= MTK_PDMA_DELAY_TX_MASK; 2417 val |= MTK_PDMA_DELAY_RX_EN; 2418 2419 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 2420 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 2421 2422 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 2423 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 2424 2425 mtk_w32(eth, val, MTK_PDMA_DELAY_INT); 2426 mtk_w32(eth, val, MTK_QDMA_DELAY_INT); 2427 2428 spin_unlock_bh(ð->dim_lock); 2429 2430 dim->state = DIM_START_MEASURE; 2431 } 2432 2433 static void mtk_dim_tx(struct work_struct *work) 2434 { 2435 struct dim *dim = container_of(work, struct dim, work); 2436 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 2437 struct dim_cq_moder cur_profile; 2438 u32 val, cur; 2439 2440 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 2441 dim->profile_ix); 2442 spin_lock_bh(ð->dim_lock); 2443 2444 val = mtk_r32(eth, MTK_PDMA_DELAY_INT); 2445 val &= MTK_PDMA_DELAY_RX_MASK; 2446 val |= MTK_PDMA_DELAY_TX_EN; 2447 2448 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 2449 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 2450 2451 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 2452 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 2453 2454 mtk_w32(eth, val, MTK_PDMA_DELAY_INT); 2455 mtk_w32(eth, val, MTK_QDMA_DELAY_INT); 2456 2457 spin_unlock_bh(ð->dim_lock); 2458 2459 dim->state = DIM_START_MEASURE; 2460 } 2461 2462 static int mtk_hw_init(struct mtk_eth *eth) 2463 { 2464 int i, val, ret; 2465 2466 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 2467 return 0; 2468 2469 pm_runtime_enable(eth->dev); 2470 pm_runtime_get_sync(eth->dev); 2471 2472 ret = mtk_clk_enable(eth); 2473 if (ret) 2474 goto err_disable_pm; 2475 2476 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2477 ret = device_reset(eth->dev); 2478 if (ret) { 2479 dev_err(eth->dev, "MAC reset failed!\n"); 2480 goto err_disable_pm; 2481 } 2482 2483 /* disable delay and normal interrupt */ 2484 mtk_tx_irq_disable(eth, ~0); 2485 mtk_rx_irq_disable(eth, ~0); 2486 2487 return 0; 2488 } 2489 2490 /* Non-MT7628 handling... */ 2491 ethsys_reset(eth, RSTCTRL_FE); 2492 ethsys_reset(eth, RSTCTRL_PPE); 2493 2494 if (eth->pctl) { 2495 /* Set GE2 driving and slew rate */ 2496 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 2497 2498 /* set GE2 TDSEL */ 2499 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 2500 2501 /* set GE2 TUNE */ 2502 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 2503 } 2504 2505 /* Set linkdown as the default for each GMAC. Its own MCR would be set 2506 * up with the more appropriate value when mtk_mac_config call is being 2507 * invoked. 2508 */ 2509 for (i = 0; i < MTK_MAC_COUNT; i++) 2510 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 2511 2512 /* Indicates CDM to parse the MTK special tag from CPU 2513 * which also is working out for untag packets. 2514 */ 2515 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 2516 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 2517 2518 /* Enable RX VLan Offloading */ 2519 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 2520 2521 /* set interrupt delays based on current Net DIM sample */ 2522 mtk_dim_rx(ð->rx_dim.work); 2523 mtk_dim_tx(ð->tx_dim.work); 2524 2525 /* disable delay and normal interrupt */ 2526 mtk_tx_irq_disable(eth, ~0); 2527 mtk_rx_irq_disable(eth, ~0); 2528 2529 /* FE int grouping */ 2530 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 2531 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 2532 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 2533 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 2534 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 2535 2536 return 0; 2537 2538 err_disable_pm: 2539 pm_runtime_put_sync(eth->dev); 2540 pm_runtime_disable(eth->dev); 2541 2542 return ret; 2543 } 2544 2545 static int mtk_hw_deinit(struct mtk_eth *eth) 2546 { 2547 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2548 return 0; 2549 2550 mtk_clk_disable(eth); 2551 2552 pm_runtime_put_sync(eth->dev); 2553 pm_runtime_disable(eth->dev); 2554 2555 return 0; 2556 } 2557 2558 static int __init mtk_init(struct net_device *dev) 2559 { 2560 struct mtk_mac *mac = netdev_priv(dev); 2561 struct mtk_eth *eth = mac->hw; 2562 int ret; 2563 2564 ret = of_get_mac_address(mac->of_node, dev->dev_addr); 2565 if (ret) { 2566 /* If the mac address is invalid, use random mac address */ 2567 eth_hw_addr_random(dev); 2568 dev_err(eth->dev, "generated random MAC address %pM\n", 2569 dev->dev_addr); 2570 } 2571 2572 return 0; 2573 } 2574 2575 static void mtk_uninit(struct net_device *dev) 2576 { 2577 struct mtk_mac *mac = netdev_priv(dev); 2578 struct mtk_eth *eth = mac->hw; 2579 2580 phylink_disconnect_phy(mac->phylink); 2581 mtk_tx_irq_disable(eth, ~0); 2582 mtk_rx_irq_disable(eth, ~0); 2583 } 2584 2585 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 2586 { 2587 int length = new_mtu + MTK_RX_ETH_HLEN; 2588 struct mtk_mac *mac = netdev_priv(dev); 2589 struct mtk_eth *eth = mac->hw; 2590 u32 mcr_cur, mcr_new; 2591 2592 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2593 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 2594 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 2595 2596 if (length <= 1518) 2597 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 2598 else if (length <= 1536) 2599 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 2600 else if (length <= 1552) 2601 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 2602 else 2603 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 2604 2605 if (mcr_new != mcr_cur) 2606 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 2607 } 2608 2609 dev->mtu = new_mtu; 2610 2611 return 0; 2612 } 2613 2614 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2615 { 2616 struct mtk_mac *mac = netdev_priv(dev); 2617 2618 switch (cmd) { 2619 case SIOCGMIIPHY: 2620 case SIOCGMIIREG: 2621 case SIOCSMIIREG: 2622 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 2623 default: 2624 break; 2625 } 2626 2627 return -EOPNOTSUPP; 2628 } 2629 2630 static void mtk_pending_work(struct work_struct *work) 2631 { 2632 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2633 int err, i; 2634 unsigned long restart = 0; 2635 2636 rtnl_lock(); 2637 2638 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2639 2640 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2641 cpu_relax(); 2642 2643 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2644 /* stop all devices to make sure that dma is properly shut down */ 2645 for (i = 0; i < MTK_MAC_COUNT; i++) { 2646 if (!eth->netdev[i]) 2647 continue; 2648 mtk_stop(eth->netdev[i]); 2649 __set_bit(i, &restart); 2650 } 2651 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2652 2653 /* restart underlying hardware such as power, clock, pin mux 2654 * and the connected phy 2655 */ 2656 mtk_hw_deinit(eth); 2657 2658 if (eth->dev->pins) 2659 pinctrl_select_state(eth->dev->pins->p, 2660 eth->dev->pins->default_state); 2661 mtk_hw_init(eth); 2662 2663 /* restart DMA and enable IRQs */ 2664 for (i = 0; i < MTK_MAC_COUNT; i++) { 2665 if (!test_bit(i, &restart)) 2666 continue; 2667 err = mtk_open(eth->netdev[i]); 2668 if (err) { 2669 netif_alert(eth, ifup, eth->netdev[i], 2670 "Driver up/down cycle failed, closing device.\n"); 2671 dev_close(eth->netdev[i]); 2672 } 2673 } 2674 2675 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2676 2677 clear_bit_unlock(MTK_RESETTING, ð->state); 2678 2679 rtnl_unlock(); 2680 } 2681 2682 static int mtk_free_dev(struct mtk_eth *eth) 2683 { 2684 int i; 2685 2686 for (i = 0; i < MTK_MAC_COUNT; i++) { 2687 if (!eth->netdev[i]) 2688 continue; 2689 free_netdev(eth->netdev[i]); 2690 } 2691 2692 return 0; 2693 } 2694 2695 static int mtk_unreg_dev(struct mtk_eth *eth) 2696 { 2697 int i; 2698 2699 for (i = 0; i < MTK_MAC_COUNT; i++) { 2700 if (!eth->netdev[i]) 2701 continue; 2702 unregister_netdev(eth->netdev[i]); 2703 } 2704 2705 return 0; 2706 } 2707 2708 static int mtk_cleanup(struct mtk_eth *eth) 2709 { 2710 mtk_unreg_dev(eth); 2711 mtk_free_dev(eth); 2712 cancel_work_sync(ð->pending_work); 2713 2714 return 0; 2715 } 2716 2717 static int mtk_get_link_ksettings(struct net_device *ndev, 2718 struct ethtool_link_ksettings *cmd) 2719 { 2720 struct mtk_mac *mac = netdev_priv(ndev); 2721 2722 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2723 return -EBUSY; 2724 2725 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 2726 } 2727 2728 static int mtk_set_link_ksettings(struct net_device *ndev, 2729 const struct ethtool_link_ksettings *cmd) 2730 { 2731 struct mtk_mac *mac = netdev_priv(ndev); 2732 2733 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2734 return -EBUSY; 2735 2736 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 2737 } 2738 2739 static void mtk_get_drvinfo(struct net_device *dev, 2740 struct ethtool_drvinfo *info) 2741 { 2742 struct mtk_mac *mac = netdev_priv(dev); 2743 2744 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2745 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2746 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2747 } 2748 2749 static u32 mtk_get_msglevel(struct net_device *dev) 2750 { 2751 struct mtk_mac *mac = netdev_priv(dev); 2752 2753 return mac->hw->msg_enable; 2754 } 2755 2756 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2757 { 2758 struct mtk_mac *mac = netdev_priv(dev); 2759 2760 mac->hw->msg_enable = value; 2761 } 2762 2763 static int mtk_nway_reset(struct net_device *dev) 2764 { 2765 struct mtk_mac *mac = netdev_priv(dev); 2766 2767 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2768 return -EBUSY; 2769 2770 if (!mac->phylink) 2771 return -ENOTSUPP; 2772 2773 return phylink_ethtool_nway_reset(mac->phylink); 2774 } 2775 2776 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2777 { 2778 int i; 2779 2780 switch (stringset) { 2781 case ETH_SS_STATS: 2782 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2783 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2784 data += ETH_GSTRING_LEN; 2785 } 2786 break; 2787 } 2788 } 2789 2790 static int mtk_get_sset_count(struct net_device *dev, int sset) 2791 { 2792 switch (sset) { 2793 case ETH_SS_STATS: 2794 return ARRAY_SIZE(mtk_ethtool_stats); 2795 default: 2796 return -EOPNOTSUPP; 2797 } 2798 } 2799 2800 static void mtk_get_ethtool_stats(struct net_device *dev, 2801 struct ethtool_stats *stats, u64 *data) 2802 { 2803 struct mtk_mac *mac = netdev_priv(dev); 2804 struct mtk_hw_stats *hwstats = mac->hw_stats; 2805 u64 *data_src, *data_dst; 2806 unsigned int start; 2807 int i; 2808 2809 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2810 return; 2811 2812 if (netif_running(dev) && netif_device_present(dev)) { 2813 if (spin_trylock_bh(&hwstats->stats_lock)) { 2814 mtk_stats_update_mac(mac); 2815 spin_unlock_bh(&hwstats->stats_lock); 2816 } 2817 } 2818 2819 data_src = (u64 *)hwstats; 2820 2821 do { 2822 data_dst = data; 2823 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2824 2825 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2826 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2827 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2828 } 2829 2830 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2831 u32 *rule_locs) 2832 { 2833 int ret = -EOPNOTSUPP; 2834 2835 switch (cmd->cmd) { 2836 case ETHTOOL_GRXRINGS: 2837 if (dev->hw_features & NETIF_F_LRO) { 2838 cmd->data = MTK_MAX_RX_RING_NUM; 2839 ret = 0; 2840 } 2841 break; 2842 case ETHTOOL_GRXCLSRLCNT: 2843 if (dev->hw_features & NETIF_F_LRO) { 2844 struct mtk_mac *mac = netdev_priv(dev); 2845 2846 cmd->rule_cnt = mac->hwlro_ip_cnt; 2847 ret = 0; 2848 } 2849 break; 2850 case ETHTOOL_GRXCLSRULE: 2851 if (dev->hw_features & NETIF_F_LRO) 2852 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2853 break; 2854 case ETHTOOL_GRXCLSRLALL: 2855 if (dev->hw_features & NETIF_F_LRO) 2856 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2857 rule_locs); 2858 break; 2859 default: 2860 break; 2861 } 2862 2863 return ret; 2864 } 2865 2866 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2867 { 2868 int ret = -EOPNOTSUPP; 2869 2870 switch (cmd->cmd) { 2871 case ETHTOOL_SRXCLSRLINS: 2872 if (dev->hw_features & NETIF_F_LRO) 2873 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2874 break; 2875 case ETHTOOL_SRXCLSRLDEL: 2876 if (dev->hw_features & NETIF_F_LRO) 2877 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2878 break; 2879 default: 2880 break; 2881 } 2882 2883 return ret; 2884 } 2885 2886 static const struct ethtool_ops mtk_ethtool_ops = { 2887 .get_link_ksettings = mtk_get_link_ksettings, 2888 .set_link_ksettings = mtk_set_link_ksettings, 2889 .get_drvinfo = mtk_get_drvinfo, 2890 .get_msglevel = mtk_get_msglevel, 2891 .set_msglevel = mtk_set_msglevel, 2892 .nway_reset = mtk_nway_reset, 2893 .get_link = ethtool_op_get_link, 2894 .get_strings = mtk_get_strings, 2895 .get_sset_count = mtk_get_sset_count, 2896 .get_ethtool_stats = mtk_get_ethtool_stats, 2897 .get_rxnfc = mtk_get_rxnfc, 2898 .set_rxnfc = mtk_set_rxnfc, 2899 }; 2900 2901 static const struct net_device_ops mtk_netdev_ops = { 2902 .ndo_init = mtk_init, 2903 .ndo_uninit = mtk_uninit, 2904 .ndo_open = mtk_open, 2905 .ndo_stop = mtk_stop, 2906 .ndo_start_xmit = mtk_start_xmit, 2907 .ndo_set_mac_address = mtk_set_mac_address, 2908 .ndo_validate_addr = eth_validate_addr, 2909 .ndo_do_ioctl = mtk_do_ioctl, 2910 .ndo_change_mtu = mtk_change_mtu, 2911 .ndo_tx_timeout = mtk_tx_timeout, 2912 .ndo_get_stats64 = mtk_get_stats64, 2913 .ndo_fix_features = mtk_fix_features, 2914 .ndo_set_features = mtk_set_features, 2915 #ifdef CONFIG_NET_POLL_CONTROLLER 2916 .ndo_poll_controller = mtk_poll_controller, 2917 #endif 2918 .ndo_setup_tc = mtk_eth_setup_tc, 2919 }; 2920 2921 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2922 { 2923 const __be32 *_id = of_get_property(np, "reg", NULL); 2924 phy_interface_t phy_mode; 2925 struct phylink *phylink; 2926 struct mtk_mac *mac; 2927 int id, err; 2928 2929 if (!_id) { 2930 dev_err(eth->dev, "missing mac id\n"); 2931 return -EINVAL; 2932 } 2933 2934 id = be32_to_cpup(_id); 2935 if (id >= MTK_MAC_COUNT) { 2936 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2937 return -EINVAL; 2938 } 2939 2940 if (eth->netdev[id]) { 2941 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2942 return -EINVAL; 2943 } 2944 2945 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2946 if (!eth->netdev[id]) { 2947 dev_err(eth->dev, "alloc_etherdev failed\n"); 2948 return -ENOMEM; 2949 } 2950 mac = netdev_priv(eth->netdev[id]); 2951 eth->mac[id] = mac; 2952 mac->id = id; 2953 mac->hw = eth; 2954 mac->of_node = np; 2955 2956 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2957 mac->hwlro_ip_cnt = 0; 2958 2959 mac->hw_stats = devm_kzalloc(eth->dev, 2960 sizeof(*mac->hw_stats), 2961 GFP_KERNEL); 2962 if (!mac->hw_stats) { 2963 dev_err(eth->dev, "failed to allocate counter memory\n"); 2964 err = -ENOMEM; 2965 goto free_netdev; 2966 } 2967 spin_lock_init(&mac->hw_stats->stats_lock); 2968 u64_stats_init(&mac->hw_stats->syncp); 2969 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2970 2971 /* phylink create */ 2972 err = of_get_phy_mode(np, &phy_mode); 2973 if (err) { 2974 dev_err(eth->dev, "incorrect phy-mode\n"); 2975 goto free_netdev; 2976 } 2977 2978 /* mac config is not set */ 2979 mac->interface = PHY_INTERFACE_MODE_NA; 2980 mac->mode = MLO_AN_PHY; 2981 mac->speed = SPEED_UNKNOWN; 2982 2983 mac->phylink_config.dev = ð->netdev[id]->dev; 2984 mac->phylink_config.type = PHYLINK_NETDEV; 2985 2986 phylink = phylink_create(&mac->phylink_config, 2987 of_fwnode_handle(mac->of_node), 2988 phy_mode, &mtk_phylink_ops); 2989 if (IS_ERR(phylink)) { 2990 err = PTR_ERR(phylink); 2991 goto free_netdev; 2992 } 2993 2994 mac->phylink = phylink; 2995 2996 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2997 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2998 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2999 eth->netdev[id]->base_addr = (unsigned long)eth->base; 3000 3001 eth->netdev[id]->hw_features = eth->soc->hw_features; 3002 if (eth->hwlro) 3003 eth->netdev[id]->hw_features |= NETIF_F_LRO; 3004 3005 eth->netdev[id]->vlan_features = eth->soc->hw_features & 3006 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 3007 eth->netdev[id]->features |= eth->soc->hw_features; 3008 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 3009 3010 eth->netdev[id]->irq = eth->irq[0]; 3011 eth->netdev[id]->dev.of_node = np; 3012 3013 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3014 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 3015 else 3016 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 3017 3018 return 0; 3019 3020 free_netdev: 3021 free_netdev(eth->netdev[id]); 3022 return err; 3023 } 3024 3025 static int mtk_probe(struct platform_device *pdev) 3026 { 3027 struct device_node *mac_np; 3028 struct mtk_eth *eth; 3029 int err, i; 3030 3031 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 3032 if (!eth) 3033 return -ENOMEM; 3034 3035 eth->soc = of_device_get_match_data(&pdev->dev); 3036 3037 eth->dev = &pdev->dev; 3038 eth->base = devm_platform_ioremap_resource(pdev, 0); 3039 if (IS_ERR(eth->base)) 3040 return PTR_ERR(eth->base); 3041 3042 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3043 eth->tx_int_mask_reg = MTK_QDMA_INT_MASK; 3044 eth->tx_int_status_reg = MTK_QDMA_INT_STATUS; 3045 } else { 3046 eth->tx_int_mask_reg = MTK_PDMA_INT_MASK; 3047 eth->tx_int_status_reg = MTK_PDMA_INT_STATUS; 3048 } 3049 3050 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3051 eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA; 3052 eth->ip_align = NET_IP_ALIGN; 3053 } else { 3054 eth->rx_dma_l4_valid = RX_DMA_L4_VALID; 3055 } 3056 3057 spin_lock_init(ð->page_lock); 3058 spin_lock_init(ð->tx_irq_lock); 3059 spin_lock_init(ð->rx_irq_lock); 3060 spin_lock_init(ð->dim_lock); 3061 3062 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3063 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 3064 3065 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3066 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 3067 3068 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3069 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3070 "mediatek,ethsys"); 3071 if (IS_ERR(eth->ethsys)) { 3072 dev_err(&pdev->dev, "no ethsys regmap found\n"); 3073 return PTR_ERR(eth->ethsys); 3074 } 3075 } 3076 3077 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 3078 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3079 "mediatek,infracfg"); 3080 if (IS_ERR(eth->infra)) { 3081 dev_err(&pdev->dev, "no infracfg regmap found\n"); 3082 return PTR_ERR(eth->infra); 3083 } 3084 } 3085 3086 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 3087 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 3088 GFP_KERNEL); 3089 if (!eth->sgmii) 3090 return -ENOMEM; 3091 3092 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 3093 eth->soc->ana_rgc3); 3094 3095 if (err) 3096 return err; 3097 } 3098 3099 if (eth->soc->required_pctl) { 3100 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3101 "mediatek,pctl"); 3102 if (IS_ERR(eth->pctl)) { 3103 dev_err(&pdev->dev, "no pctl regmap found\n"); 3104 return PTR_ERR(eth->pctl); 3105 } 3106 } 3107 3108 for (i = 0; i < 3; i++) { 3109 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 3110 eth->irq[i] = eth->irq[0]; 3111 else 3112 eth->irq[i] = platform_get_irq(pdev, i); 3113 if (eth->irq[i] < 0) { 3114 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 3115 return -ENXIO; 3116 } 3117 } 3118 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 3119 eth->clks[i] = devm_clk_get(eth->dev, 3120 mtk_clks_source_name[i]); 3121 if (IS_ERR(eth->clks[i])) { 3122 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 3123 return -EPROBE_DEFER; 3124 if (eth->soc->required_clks & BIT(i)) { 3125 dev_err(&pdev->dev, "clock %s not found\n", 3126 mtk_clks_source_name[i]); 3127 return -EINVAL; 3128 } 3129 eth->clks[i] = NULL; 3130 } 3131 } 3132 3133 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 3134 INIT_WORK(ð->pending_work, mtk_pending_work); 3135 3136 err = mtk_hw_init(eth); 3137 if (err) 3138 return err; 3139 3140 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 3141 3142 for_each_child_of_node(pdev->dev.of_node, mac_np) { 3143 if (!of_device_is_compatible(mac_np, 3144 "mediatek,eth-mac")) 3145 continue; 3146 3147 if (!of_device_is_available(mac_np)) 3148 continue; 3149 3150 err = mtk_add_mac(eth, mac_np); 3151 if (err) { 3152 of_node_put(mac_np); 3153 goto err_deinit_hw; 3154 } 3155 } 3156 3157 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 3158 err = devm_request_irq(eth->dev, eth->irq[0], 3159 mtk_handle_irq, 0, 3160 dev_name(eth->dev), eth); 3161 } else { 3162 err = devm_request_irq(eth->dev, eth->irq[1], 3163 mtk_handle_irq_tx, 0, 3164 dev_name(eth->dev), eth); 3165 if (err) 3166 goto err_free_dev; 3167 3168 err = devm_request_irq(eth->dev, eth->irq[2], 3169 mtk_handle_irq_rx, 0, 3170 dev_name(eth->dev), eth); 3171 } 3172 if (err) 3173 goto err_free_dev; 3174 3175 /* No MT7628/88 support yet */ 3176 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3177 err = mtk_mdio_init(eth); 3178 if (err) 3179 goto err_free_dev; 3180 } 3181 3182 if (eth->soc->offload_version) { 3183 err = mtk_ppe_init(ð->ppe, eth->dev, 3184 eth->base + MTK_ETH_PPE_BASE, 2); 3185 if (err) 3186 goto err_free_dev; 3187 3188 err = mtk_eth_offload_init(eth); 3189 if (err) 3190 goto err_free_dev; 3191 } 3192 3193 for (i = 0; i < MTK_MAX_DEVS; i++) { 3194 if (!eth->netdev[i]) 3195 continue; 3196 3197 err = register_netdev(eth->netdev[i]); 3198 if (err) { 3199 dev_err(eth->dev, "error bringing up device\n"); 3200 goto err_deinit_mdio; 3201 } else 3202 netif_info(eth, probe, eth->netdev[i], 3203 "mediatek frame engine at 0x%08lx, irq %d\n", 3204 eth->netdev[i]->base_addr, eth->irq[0]); 3205 } 3206 3207 /* we run 2 devices on the same DMA ring so we need a dummy device 3208 * for NAPI to work 3209 */ 3210 init_dummy_netdev(ð->dummy_dev); 3211 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 3212 MTK_NAPI_WEIGHT); 3213 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 3214 MTK_NAPI_WEIGHT); 3215 3216 platform_set_drvdata(pdev, eth); 3217 3218 return 0; 3219 3220 err_deinit_mdio: 3221 mtk_mdio_cleanup(eth); 3222 err_free_dev: 3223 mtk_free_dev(eth); 3224 err_deinit_hw: 3225 mtk_hw_deinit(eth); 3226 3227 return err; 3228 } 3229 3230 static int mtk_remove(struct platform_device *pdev) 3231 { 3232 struct mtk_eth *eth = platform_get_drvdata(pdev); 3233 struct mtk_mac *mac; 3234 int i; 3235 3236 /* stop all devices to make sure that dma is properly shut down */ 3237 for (i = 0; i < MTK_MAC_COUNT; i++) { 3238 if (!eth->netdev[i]) 3239 continue; 3240 mtk_stop(eth->netdev[i]); 3241 mac = netdev_priv(eth->netdev[i]); 3242 phylink_disconnect_phy(mac->phylink); 3243 } 3244 3245 mtk_hw_deinit(eth); 3246 3247 netif_napi_del(ð->tx_napi); 3248 netif_napi_del(ð->rx_napi); 3249 mtk_cleanup(eth); 3250 mtk_mdio_cleanup(eth); 3251 3252 return 0; 3253 } 3254 3255 static const struct mtk_soc_data mt2701_data = { 3256 .caps = MT7623_CAPS | MTK_HWLRO, 3257 .hw_features = MTK_HW_FEATURES, 3258 .required_clks = MT7623_CLKS_BITMAP, 3259 .required_pctl = true, 3260 }; 3261 3262 static const struct mtk_soc_data mt7621_data = { 3263 .caps = MT7621_CAPS, 3264 .hw_features = MTK_HW_FEATURES, 3265 .required_clks = MT7621_CLKS_BITMAP, 3266 .required_pctl = false, 3267 .offload_version = 2, 3268 }; 3269 3270 static const struct mtk_soc_data mt7622_data = { 3271 .ana_rgc3 = 0x2028, 3272 .caps = MT7622_CAPS | MTK_HWLRO, 3273 .hw_features = MTK_HW_FEATURES, 3274 .required_clks = MT7622_CLKS_BITMAP, 3275 .required_pctl = false, 3276 .offload_version = 2, 3277 }; 3278 3279 static const struct mtk_soc_data mt7623_data = { 3280 .caps = MT7623_CAPS | MTK_HWLRO, 3281 .hw_features = MTK_HW_FEATURES, 3282 .required_clks = MT7623_CLKS_BITMAP, 3283 .required_pctl = true, 3284 .offload_version = 2, 3285 }; 3286 3287 static const struct mtk_soc_data mt7629_data = { 3288 .ana_rgc3 = 0x128, 3289 .caps = MT7629_CAPS | MTK_HWLRO, 3290 .hw_features = MTK_HW_FEATURES, 3291 .required_clks = MT7629_CLKS_BITMAP, 3292 .required_pctl = false, 3293 }; 3294 3295 static const struct mtk_soc_data rt5350_data = { 3296 .caps = MT7628_CAPS, 3297 .hw_features = MTK_HW_FEATURES_MT7628, 3298 .required_clks = MT7628_CLKS_BITMAP, 3299 .required_pctl = false, 3300 }; 3301 3302 const struct of_device_id of_mtk_match[] = { 3303 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 3304 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 3305 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 3306 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 3307 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 3308 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 3309 {}, 3310 }; 3311 MODULE_DEVICE_TABLE(of, of_mtk_match); 3312 3313 static struct platform_driver mtk_driver = { 3314 .probe = mtk_probe, 3315 .remove = mtk_remove, 3316 .driver = { 3317 .name = "mtk_soc_eth", 3318 .of_match_table = of_mtk_match, 3319 }, 3320 }; 3321 3322 module_platform_driver(mtk_driver); 3323 3324 MODULE_LICENSE("GPL"); 3325 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 3326 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 3327