1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/regmap.h> 15 #include <linux/clk.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/if_vlan.h> 18 #include <linux/reset.h> 19 #include <linux/tcp.h> 20 #include <linux/interrupt.h> 21 #include <linux/pinctrl/devinfo.h> 22 #include <linux/phylink.h> 23 #include <linux/jhash.h> 24 #include <linux/bitfield.h> 25 #include <net/dsa.h> 26 27 #include "mtk_eth_soc.h" 28 #include "mtk_wed.h" 29 30 static int mtk_msg_level = -1; 31 module_param_named(msg_level, mtk_msg_level, int, 0); 32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 33 34 #define MTK_ETHTOOL_STAT(x) { #x, \ 35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 36 37 /* strings used by ethtool */ 38 static const struct mtk_ethtool_stats { 39 char str[ETH_GSTRING_LEN]; 40 u32 offset; 41 } mtk_ethtool_stats[] = { 42 MTK_ETHTOOL_STAT(tx_bytes), 43 MTK_ETHTOOL_STAT(tx_packets), 44 MTK_ETHTOOL_STAT(tx_skip), 45 MTK_ETHTOOL_STAT(tx_collisions), 46 MTK_ETHTOOL_STAT(rx_bytes), 47 MTK_ETHTOOL_STAT(rx_packets), 48 MTK_ETHTOOL_STAT(rx_overflow), 49 MTK_ETHTOOL_STAT(rx_fcs_errors), 50 MTK_ETHTOOL_STAT(rx_short_errors), 51 MTK_ETHTOOL_STAT(rx_long_errors), 52 MTK_ETHTOOL_STAT(rx_checksum_errors), 53 MTK_ETHTOOL_STAT(rx_flow_control_packets), 54 }; 55 56 static const char * const mtk_clks_source_name[] = { 57 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 58 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 59 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 60 "sgmii_ck", "eth2pll", 61 }; 62 63 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 64 { 65 __raw_writel(val, eth->base + reg); 66 } 67 68 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 69 { 70 return __raw_readl(eth->base + reg); 71 } 72 73 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 74 { 75 u32 val; 76 77 val = mtk_r32(eth, reg); 78 val &= ~mask; 79 val |= set; 80 mtk_w32(eth, val, reg); 81 return reg; 82 } 83 84 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 85 { 86 unsigned long t_start = jiffies; 87 88 while (1) { 89 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 90 return 0; 91 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 92 break; 93 cond_resched(); 94 } 95 96 dev_err(eth->dev, "mdio: MDIO timeout\n"); 97 return -ETIMEDOUT; 98 } 99 100 static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 101 u32 write_data) 102 { 103 int ret; 104 105 ret = mtk_mdio_busy_wait(eth); 106 if (ret < 0) 107 return ret; 108 109 if (phy_reg & MII_ADDR_C45) { 110 mtk_w32(eth, PHY_IAC_ACCESS | 111 PHY_IAC_START_C45 | 112 PHY_IAC_CMD_C45_ADDR | 113 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 114 PHY_IAC_ADDR(phy_addr) | 115 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 116 MTK_PHY_IAC); 117 118 ret = mtk_mdio_busy_wait(eth); 119 if (ret < 0) 120 return ret; 121 122 mtk_w32(eth, PHY_IAC_ACCESS | 123 PHY_IAC_START_C45 | 124 PHY_IAC_CMD_WRITE | 125 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 126 PHY_IAC_ADDR(phy_addr) | 127 PHY_IAC_DATA(write_data), 128 MTK_PHY_IAC); 129 } else { 130 mtk_w32(eth, PHY_IAC_ACCESS | 131 PHY_IAC_START_C22 | 132 PHY_IAC_CMD_WRITE | 133 PHY_IAC_REG(phy_reg) | 134 PHY_IAC_ADDR(phy_addr) | 135 PHY_IAC_DATA(write_data), 136 MTK_PHY_IAC); 137 } 138 139 ret = mtk_mdio_busy_wait(eth); 140 if (ret < 0) 141 return ret; 142 143 return 0; 144 } 145 146 static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 147 { 148 int ret; 149 150 ret = mtk_mdio_busy_wait(eth); 151 if (ret < 0) 152 return ret; 153 154 if (phy_reg & MII_ADDR_C45) { 155 mtk_w32(eth, PHY_IAC_ACCESS | 156 PHY_IAC_START_C45 | 157 PHY_IAC_CMD_C45_ADDR | 158 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 159 PHY_IAC_ADDR(phy_addr) | 160 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 161 MTK_PHY_IAC); 162 163 ret = mtk_mdio_busy_wait(eth); 164 if (ret < 0) 165 return ret; 166 167 mtk_w32(eth, PHY_IAC_ACCESS | 168 PHY_IAC_START_C45 | 169 PHY_IAC_CMD_C45_READ | 170 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 171 PHY_IAC_ADDR(phy_addr), 172 MTK_PHY_IAC); 173 } else { 174 mtk_w32(eth, PHY_IAC_ACCESS | 175 PHY_IAC_START_C22 | 176 PHY_IAC_CMD_C22_READ | 177 PHY_IAC_REG(phy_reg) | 178 PHY_IAC_ADDR(phy_addr), 179 MTK_PHY_IAC); 180 } 181 182 ret = mtk_mdio_busy_wait(eth); 183 if (ret < 0) 184 return ret; 185 186 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 187 } 188 189 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 190 int phy_reg, u16 val) 191 { 192 struct mtk_eth *eth = bus->priv; 193 194 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 195 } 196 197 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 198 { 199 struct mtk_eth *eth = bus->priv; 200 201 return _mtk_mdio_read(eth, phy_addr, phy_reg); 202 } 203 204 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 205 phy_interface_t interface) 206 { 207 u32 val; 208 209 /* Check DDR memory type. 210 * Currently TRGMII mode with DDR2 memory is not supported. 211 */ 212 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 213 if (interface == PHY_INTERFACE_MODE_TRGMII && 214 val & SYSCFG_DRAM_TYPE_DDR2) { 215 dev_err(eth->dev, 216 "TRGMII mode with DDR2 memory is not supported!\n"); 217 return -EOPNOTSUPP; 218 } 219 220 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 221 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 222 223 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 224 ETHSYS_TRGMII_MT7621_MASK, val); 225 226 return 0; 227 } 228 229 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 230 phy_interface_t interface, int speed) 231 { 232 u32 val; 233 int ret; 234 235 if (interface == PHY_INTERFACE_MODE_TRGMII) { 236 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 237 val = 500000000; 238 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 239 if (ret) 240 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 241 return; 242 } 243 244 val = (speed == SPEED_1000) ? 245 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 246 mtk_w32(eth, val, INTF_MODE); 247 248 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 249 ETHSYS_TRGMII_CLK_SEL362_5, 250 ETHSYS_TRGMII_CLK_SEL362_5); 251 252 val = (speed == SPEED_1000) ? 250000000 : 500000000; 253 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 254 if (ret) 255 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 256 257 val = (speed == SPEED_1000) ? 258 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 259 mtk_w32(eth, val, TRGMII_RCK_CTRL); 260 261 val = (speed == SPEED_1000) ? 262 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 263 mtk_w32(eth, val, TRGMII_TCK_CTRL); 264 } 265 266 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 267 const struct phylink_link_state *state) 268 { 269 struct mtk_mac *mac = container_of(config, struct mtk_mac, 270 phylink_config); 271 struct mtk_eth *eth = mac->hw; 272 u32 mcr_cur, mcr_new, sid, i; 273 int val, ge_mode, err = 0; 274 275 /* MT76x8 has no hardware settings between for the MAC */ 276 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 277 mac->interface != state->interface) { 278 /* Setup soc pin functions */ 279 switch (state->interface) { 280 case PHY_INTERFACE_MODE_TRGMII: 281 if (mac->id) 282 goto err_phy; 283 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 284 MTK_GMAC1_TRGMII)) 285 goto err_phy; 286 fallthrough; 287 case PHY_INTERFACE_MODE_RGMII_TXID: 288 case PHY_INTERFACE_MODE_RGMII_RXID: 289 case PHY_INTERFACE_MODE_RGMII_ID: 290 case PHY_INTERFACE_MODE_RGMII: 291 case PHY_INTERFACE_MODE_MII: 292 case PHY_INTERFACE_MODE_REVMII: 293 case PHY_INTERFACE_MODE_RMII: 294 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 295 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 296 if (err) 297 goto init_err; 298 } 299 break; 300 case PHY_INTERFACE_MODE_1000BASEX: 301 case PHY_INTERFACE_MODE_2500BASEX: 302 case PHY_INTERFACE_MODE_SGMII: 303 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 304 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 305 if (err) 306 goto init_err; 307 } 308 break; 309 case PHY_INTERFACE_MODE_GMII: 310 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 311 err = mtk_gmac_gephy_path_setup(eth, mac->id); 312 if (err) 313 goto init_err; 314 } 315 break; 316 default: 317 goto err_phy; 318 } 319 320 /* Setup clock for 1st gmac */ 321 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 322 !phy_interface_mode_is_8023z(state->interface) && 323 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 324 if (MTK_HAS_CAPS(mac->hw->soc->caps, 325 MTK_TRGMII_MT7621_CLK)) { 326 if (mt7621_gmac0_rgmii_adjust(mac->hw, 327 state->interface)) 328 goto err_phy; 329 } else { 330 mtk_gmac0_rgmii_adjust(mac->hw, 331 state->interface, 332 state->speed); 333 334 /* mt7623_pad_clk_setup */ 335 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 336 mtk_w32(mac->hw, 337 TD_DM_DRVP(8) | TD_DM_DRVN(8), 338 TRGMII_TD_ODT(i)); 339 340 /* Assert/release MT7623 RXC reset */ 341 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 342 TRGMII_RCK_CTRL); 343 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 344 } 345 } 346 347 ge_mode = 0; 348 switch (state->interface) { 349 case PHY_INTERFACE_MODE_MII: 350 case PHY_INTERFACE_MODE_GMII: 351 ge_mode = 1; 352 break; 353 case PHY_INTERFACE_MODE_REVMII: 354 ge_mode = 2; 355 break; 356 case PHY_INTERFACE_MODE_RMII: 357 if (mac->id) 358 goto err_phy; 359 ge_mode = 3; 360 break; 361 default: 362 break; 363 } 364 365 /* put the gmac into the right mode */ 366 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 367 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 368 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 369 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 370 371 mac->interface = state->interface; 372 } 373 374 /* SGMII */ 375 if (state->interface == PHY_INTERFACE_MODE_SGMII || 376 phy_interface_mode_is_8023z(state->interface)) { 377 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 378 * being setup done. 379 */ 380 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 381 382 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 383 SYSCFG0_SGMII_MASK, 384 ~(u32)SYSCFG0_SGMII_MASK); 385 386 /* Decide how GMAC and SGMIISYS be mapped */ 387 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 388 0 : mac->id; 389 390 /* Setup SGMIISYS with the determined property */ 391 if (state->interface != PHY_INTERFACE_MODE_SGMII) 392 err = mtk_sgmii_setup_mode_force(eth->sgmii, sid, 393 state); 394 else if (phylink_autoneg_inband(mode)) 395 err = mtk_sgmii_setup_mode_an(eth->sgmii, sid); 396 397 if (err) 398 goto init_err; 399 400 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 401 SYSCFG0_SGMII_MASK, val); 402 } else if (phylink_autoneg_inband(mode)) { 403 dev_err(eth->dev, 404 "In-band mode not supported in non SGMII mode!\n"); 405 return; 406 } 407 408 /* Setup gmac */ 409 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 410 mcr_new = mcr_cur; 411 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 412 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; 413 414 /* Only update control register when needed! */ 415 if (mcr_new != mcr_cur) 416 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 417 418 return; 419 420 err_phy: 421 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 422 mac->id, phy_modes(state->interface)); 423 return; 424 425 init_err: 426 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 427 mac->id, phy_modes(state->interface), err); 428 } 429 430 static void mtk_mac_pcs_get_state(struct phylink_config *config, 431 struct phylink_link_state *state) 432 { 433 struct mtk_mac *mac = container_of(config, struct mtk_mac, 434 phylink_config); 435 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 436 437 state->link = (pmsr & MAC_MSR_LINK); 438 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 439 440 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 441 case 0: 442 state->speed = SPEED_10; 443 break; 444 case MAC_MSR_SPEED_100: 445 state->speed = SPEED_100; 446 break; 447 case MAC_MSR_SPEED_1000: 448 state->speed = SPEED_1000; 449 break; 450 default: 451 state->speed = SPEED_UNKNOWN; 452 break; 453 } 454 455 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 456 if (pmsr & MAC_MSR_RX_FC) 457 state->pause |= MLO_PAUSE_RX; 458 if (pmsr & MAC_MSR_TX_FC) 459 state->pause |= MLO_PAUSE_TX; 460 } 461 462 static void mtk_mac_an_restart(struct phylink_config *config) 463 { 464 struct mtk_mac *mac = container_of(config, struct mtk_mac, 465 phylink_config); 466 467 mtk_sgmii_restart_an(mac->hw, mac->id); 468 } 469 470 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 471 phy_interface_t interface) 472 { 473 struct mtk_mac *mac = container_of(config, struct mtk_mac, 474 phylink_config); 475 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 476 477 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 478 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 479 } 480 481 static void mtk_mac_link_up(struct phylink_config *config, 482 struct phy_device *phy, 483 unsigned int mode, phy_interface_t interface, 484 int speed, int duplex, bool tx_pause, bool rx_pause) 485 { 486 struct mtk_mac *mac = container_of(config, struct mtk_mac, 487 phylink_config); 488 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 489 490 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 491 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 492 MAC_MCR_FORCE_RX_FC); 493 494 /* Configure speed */ 495 switch (speed) { 496 case SPEED_2500: 497 case SPEED_1000: 498 mcr |= MAC_MCR_SPEED_1000; 499 break; 500 case SPEED_100: 501 mcr |= MAC_MCR_SPEED_100; 502 break; 503 } 504 505 /* Configure duplex */ 506 if (duplex == DUPLEX_FULL) 507 mcr |= MAC_MCR_FORCE_DPX; 508 509 /* Configure pause modes - phylink will avoid these for half duplex */ 510 if (tx_pause) 511 mcr |= MAC_MCR_FORCE_TX_FC; 512 if (rx_pause) 513 mcr |= MAC_MCR_FORCE_RX_FC; 514 515 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 516 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 517 } 518 519 static const struct phylink_mac_ops mtk_phylink_ops = { 520 .validate = phylink_generic_validate, 521 .mac_pcs_get_state = mtk_mac_pcs_get_state, 522 .mac_an_restart = mtk_mac_an_restart, 523 .mac_config = mtk_mac_config, 524 .mac_link_down = mtk_mac_link_down, 525 .mac_link_up = mtk_mac_link_up, 526 }; 527 528 static int mtk_mdio_init(struct mtk_eth *eth) 529 { 530 struct device_node *mii_np; 531 int ret; 532 533 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 534 if (!mii_np) { 535 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 536 return -ENODEV; 537 } 538 539 if (!of_device_is_available(mii_np)) { 540 ret = -ENODEV; 541 goto err_put_node; 542 } 543 544 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 545 if (!eth->mii_bus) { 546 ret = -ENOMEM; 547 goto err_put_node; 548 } 549 550 eth->mii_bus->name = "mdio"; 551 eth->mii_bus->read = mtk_mdio_read; 552 eth->mii_bus->write = mtk_mdio_write; 553 eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; 554 eth->mii_bus->priv = eth; 555 eth->mii_bus->parent = eth->dev; 556 557 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 558 ret = of_mdiobus_register(eth->mii_bus, mii_np); 559 560 err_put_node: 561 of_node_put(mii_np); 562 return ret; 563 } 564 565 static void mtk_mdio_cleanup(struct mtk_eth *eth) 566 { 567 if (!eth->mii_bus) 568 return; 569 570 mdiobus_unregister(eth->mii_bus); 571 } 572 573 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 574 { 575 unsigned long flags; 576 u32 val; 577 578 spin_lock_irqsave(ð->tx_irq_lock, flags); 579 val = mtk_r32(eth, eth->tx_int_mask_reg); 580 mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg); 581 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 582 } 583 584 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 585 { 586 unsigned long flags; 587 u32 val; 588 589 spin_lock_irqsave(ð->tx_irq_lock, flags); 590 val = mtk_r32(eth, eth->tx_int_mask_reg); 591 mtk_w32(eth, val | mask, eth->tx_int_mask_reg); 592 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 593 } 594 595 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 596 { 597 unsigned long flags; 598 u32 val; 599 600 spin_lock_irqsave(ð->rx_irq_lock, flags); 601 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 602 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 603 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 604 } 605 606 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 607 { 608 unsigned long flags; 609 u32 val; 610 611 spin_lock_irqsave(ð->rx_irq_lock, flags); 612 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 613 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 614 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 615 } 616 617 static int mtk_set_mac_address(struct net_device *dev, void *p) 618 { 619 int ret = eth_mac_addr(dev, p); 620 struct mtk_mac *mac = netdev_priv(dev); 621 struct mtk_eth *eth = mac->hw; 622 const char *macaddr = dev->dev_addr; 623 624 if (ret) 625 return ret; 626 627 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 628 return -EBUSY; 629 630 spin_lock_bh(&mac->hw->page_lock); 631 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 632 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 633 MT7628_SDM_MAC_ADRH); 634 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 635 (macaddr[4] << 8) | macaddr[5], 636 MT7628_SDM_MAC_ADRL); 637 } else { 638 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 639 MTK_GDMA_MAC_ADRH(mac->id)); 640 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 641 (macaddr[4] << 8) | macaddr[5], 642 MTK_GDMA_MAC_ADRL(mac->id)); 643 } 644 spin_unlock_bh(&mac->hw->page_lock); 645 646 return 0; 647 } 648 649 void mtk_stats_update_mac(struct mtk_mac *mac) 650 { 651 struct mtk_hw_stats *hw_stats = mac->hw_stats; 652 struct mtk_eth *eth = mac->hw; 653 654 u64_stats_update_begin(&hw_stats->syncp); 655 656 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 657 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 658 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 659 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 660 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 661 hw_stats->rx_checksum_errors += 662 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 663 } else { 664 unsigned int offs = hw_stats->reg_offset; 665 u64 stats; 666 667 hw_stats->rx_bytes += mtk_r32(mac->hw, 668 MTK_GDM1_RX_GBCNT_L + offs); 669 stats = mtk_r32(mac->hw, MTK_GDM1_RX_GBCNT_H + offs); 670 if (stats) 671 hw_stats->rx_bytes += (stats << 32); 672 hw_stats->rx_packets += 673 mtk_r32(mac->hw, MTK_GDM1_RX_GPCNT + offs); 674 hw_stats->rx_overflow += 675 mtk_r32(mac->hw, MTK_GDM1_RX_OERCNT + offs); 676 hw_stats->rx_fcs_errors += 677 mtk_r32(mac->hw, MTK_GDM1_RX_FERCNT + offs); 678 hw_stats->rx_short_errors += 679 mtk_r32(mac->hw, MTK_GDM1_RX_SERCNT + offs); 680 hw_stats->rx_long_errors += 681 mtk_r32(mac->hw, MTK_GDM1_RX_LENCNT + offs); 682 hw_stats->rx_checksum_errors += 683 mtk_r32(mac->hw, MTK_GDM1_RX_CERCNT + offs); 684 hw_stats->rx_flow_control_packets += 685 mtk_r32(mac->hw, MTK_GDM1_RX_FCCNT + offs); 686 hw_stats->tx_skip += 687 mtk_r32(mac->hw, MTK_GDM1_TX_SKIPCNT + offs); 688 hw_stats->tx_collisions += 689 mtk_r32(mac->hw, MTK_GDM1_TX_COLCNT + offs); 690 hw_stats->tx_bytes += 691 mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_L + offs); 692 stats = mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_H + offs); 693 if (stats) 694 hw_stats->tx_bytes += (stats << 32); 695 hw_stats->tx_packets += 696 mtk_r32(mac->hw, MTK_GDM1_TX_GPCNT + offs); 697 } 698 699 u64_stats_update_end(&hw_stats->syncp); 700 } 701 702 static void mtk_stats_update(struct mtk_eth *eth) 703 { 704 int i; 705 706 for (i = 0; i < MTK_MAC_COUNT; i++) { 707 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 708 continue; 709 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 710 mtk_stats_update_mac(eth->mac[i]); 711 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 712 } 713 } 714 } 715 716 static void mtk_get_stats64(struct net_device *dev, 717 struct rtnl_link_stats64 *storage) 718 { 719 struct mtk_mac *mac = netdev_priv(dev); 720 struct mtk_hw_stats *hw_stats = mac->hw_stats; 721 unsigned int start; 722 723 if (netif_running(dev) && netif_device_present(dev)) { 724 if (spin_trylock_bh(&hw_stats->stats_lock)) { 725 mtk_stats_update_mac(mac); 726 spin_unlock_bh(&hw_stats->stats_lock); 727 } 728 } 729 730 do { 731 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 732 storage->rx_packets = hw_stats->rx_packets; 733 storage->tx_packets = hw_stats->tx_packets; 734 storage->rx_bytes = hw_stats->rx_bytes; 735 storage->tx_bytes = hw_stats->tx_bytes; 736 storage->collisions = hw_stats->tx_collisions; 737 storage->rx_length_errors = hw_stats->rx_short_errors + 738 hw_stats->rx_long_errors; 739 storage->rx_over_errors = hw_stats->rx_overflow; 740 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 741 storage->rx_errors = hw_stats->rx_checksum_errors; 742 storage->tx_aborted_errors = hw_stats->tx_skip; 743 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 744 745 storage->tx_errors = dev->stats.tx_errors; 746 storage->rx_dropped = dev->stats.rx_dropped; 747 storage->tx_dropped = dev->stats.tx_dropped; 748 } 749 750 static inline int mtk_max_frag_size(int mtu) 751 { 752 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 753 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 754 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 755 756 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 757 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 758 } 759 760 static inline int mtk_max_buf_size(int frag_size) 761 { 762 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 763 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 764 765 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 766 767 return buf_size; 768 } 769 770 static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd, 771 struct mtk_rx_dma *dma_rxd) 772 { 773 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 774 if (!(rxd->rxd2 & RX_DMA_DONE)) 775 return false; 776 777 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 778 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 779 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 780 781 return true; 782 } 783 784 /* the qdma core needs scratch memory to be setup */ 785 static int mtk_init_fq_dma(struct mtk_eth *eth) 786 { 787 dma_addr_t phy_ring_tail; 788 int cnt = MTK_DMA_SIZE; 789 dma_addr_t dma_addr; 790 int i; 791 792 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 793 cnt * sizeof(struct mtk_tx_dma), 794 ð->phy_scratch_ring, 795 GFP_ATOMIC); 796 if (unlikely(!eth->scratch_ring)) 797 return -ENOMEM; 798 799 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 800 GFP_KERNEL); 801 if (unlikely(!eth->scratch_head)) 802 return -ENOMEM; 803 804 dma_addr = dma_map_single(eth->dma_dev, 805 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 806 DMA_FROM_DEVICE); 807 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 808 return -ENOMEM; 809 810 phy_ring_tail = eth->phy_scratch_ring + 811 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 812 813 for (i = 0; i < cnt; i++) { 814 eth->scratch_ring[i].txd1 = 815 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 816 if (i < cnt - 1) 817 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 818 ((i + 1) * sizeof(struct mtk_tx_dma))); 819 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 820 } 821 822 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 823 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 824 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 825 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 826 827 return 0; 828 } 829 830 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 831 { 832 void *ret = ring->dma; 833 834 return ret + (desc - ring->phys); 835 } 836 837 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 838 struct mtk_tx_dma *txd) 839 { 840 int idx = txd - ring->dma; 841 842 return &ring->buf[idx]; 843 } 844 845 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 846 struct mtk_tx_dma *dma) 847 { 848 return ring->dma_pdma - ring->dma + dma; 849 } 850 851 static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma) 852 { 853 return ((void *)dma - (void *)ring->dma) / sizeof(*dma); 854 } 855 856 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 857 bool napi) 858 { 859 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 860 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 861 dma_unmap_single(eth->dma_dev, 862 dma_unmap_addr(tx_buf, dma_addr0), 863 dma_unmap_len(tx_buf, dma_len0), 864 DMA_TO_DEVICE); 865 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 866 dma_unmap_page(eth->dma_dev, 867 dma_unmap_addr(tx_buf, dma_addr0), 868 dma_unmap_len(tx_buf, dma_len0), 869 DMA_TO_DEVICE); 870 } 871 } else { 872 if (dma_unmap_len(tx_buf, dma_len0)) { 873 dma_unmap_page(eth->dma_dev, 874 dma_unmap_addr(tx_buf, dma_addr0), 875 dma_unmap_len(tx_buf, dma_len0), 876 DMA_TO_DEVICE); 877 } 878 879 if (dma_unmap_len(tx_buf, dma_len1)) { 880 dma_unmap_page(eth->dma_dev, 881 dma_unmap_addr(tx_buf, dma_addr1), 882 dma_unmap_len(tx_buf, dma_len1), 883 DMA_TO_DEVICE); 884 } 885 } 886 887 tx_buf->flags = 0; 888 if (tx_buf->skb && 889 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) { 890 if (napi) 891 napi_consume_skb(tx_buf->skb, napi); 892 else 893 dev_kfree_skb_any(tx_buf->skb); 894 } 895 tx_buf->skb = NULL; 896 } 897 898 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 899 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 900 size_t size, int idx) 901 { 902 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 903 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 904 dma_unmap_len_set(tx_buf, dma_len0, size); 905 } else { 906 if (idx & 1) { 907 txd->txd3 = mapped_addr; 908 txd->txd2 |= TX_DMA_PLEN1(size); 909 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 910 dma_unmap_len_set(tx_buf, dma_len1, size); 911 } else { 912 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 913 txd->txd1 = mapped_addr; 914 txd->txd2 = TX_DMA_PLEN0(size); 915 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 916 dma_unmap_len_set(tx_buf, dma_len0, size); 917 } 918 } 919 } 920 921 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 922 int tx_num, struct mtk_tx_ring *ring, bool gso) 923 { 924 struct mtk_mac *mac = netdev_priv(dev); 925 struct mtk_eth *eth = mac->hw; 926 struct mtk_tx_dma *itxd, *txd; 927 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 928 struct mtk_tx_buf *itx_buf, *tx_buf; 929 dma_addr_t mapped_addr; 930 unsigned int nr_frags; 931 int i, n_desc = 1; 932 u32 txd4 = 0, fport; 933 int k = 0; 934 935 itxd = ring->next_free; 936 itxd_pdma = qdma_to_pdma(ring, itxd); 937 if (itxd == ring->last_free) 938 return -ENOMEM; 939 940 /* set the forward port */ 941 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 942 txd4 |= fport; 943 944 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 945 memset(itx_buf, 0, sizeof(*itx_buf)); 946 947 if (gso) 948 txd4 |= TX_DMA_TSO; 949 950 /* TX Checksum offload */ 951 if (skb->ip_summed == CHECKSUM_PARTIAL) 952 txd4 |= TX_DMA_CHKSUM; 953 954 /* VLAN header offload */ 955 if (skb_vlan_tag_present(skb)) 956 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 957 958 mapped_addr = dma_map_single(eth->dma_dev, skb->data, 959 skb_headlen(skb), DMA_TO_DEVICE); 960 if (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr))) 961 return -ENOMEM; 962 963 WRITE_ONCE(itxd->txd1, mapped_addr); 964 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 965 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 966 MTK_TX_FLAGS_FPORT1; 967 setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb), 968 k++); 969 970 /* TX SG offload */ 971 txd = itxd; 972 txd_pdma = qdma_to_pdma(ring, txd); 973 nr_frags = skb_shinfo(skb)->nr_frags; 974 975 for (i = 0; i < nr_frags; i++) { 976 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 977 unsigned int offset = 0; 978 int frag_size = skb_frag_size(frag); 979 980 while (frag_size) { 981 bool last_frag = false; 982 unsigned int frag_map_size; 983 bool new_desc = true; 984 985 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) || 986 (i & 0x1)) { 987 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 988 txd_pdma = qdma_to_pdma(ring, txd); 989 if (txd == ring->last_free) 990 goto err_dma; 991 992 n_desc++; 993 } else { 994 new_desc = false; 995 } 996 997 998 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 999 mapped_addr = skb_frag_dma_map(eth->dma_dev, frag, offset, 1000 frag_map_size, 1001 DMA_TO_DEVICE); 1002 if (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr))) 1003 goto err_dma; 1004 1005 if (i == nr_frags - 1 && 1006 (frag_size - frag_map_size) == 0) 1007 last_frag = true; 1008 1009 WRITE_ONCE(txd->txd1, mapped_addr); 1010 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 1011 TX_DMA_PLEN0(frag_map_size) | 1012 last_frag * TX_DMA_LS0)); 1013 WRITE_ONCE(txd->txd4, fport); 1014 1015 tx_buf = mtk_desc_to_tx_buf(ring, txd); 1016 if (new_desc) 1017 memset(tx_buf, 0, sizeof(*tx_buf)); 1018 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 1019 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1020 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1021 MTK_TX_FLAGS_FPORT1; 1022 1023 setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr, 1024 frag_map_size, k++); 1025 1026 frag_size -= frag_map_size; 1027 offset += frag_map_size; 1028 } 1029 } 1030 1031 /* store skb to cleanup */ 1032 itx_buf->skb = skb; 1033 1034 WRITE_ONCE(itxd->txd4, txd4); 1035 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 1036 (!nr_frags * TX_DMA_LS0))); 1037 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1038 if (k & 0x1) 1039 txd_pdma->txd2 |= TX_DMA_LS0; 1040 else 1041 txd_pdma->txd2 |= TX_DMA_LS1; 1042 } 1043 1044 netdev_sent_queue(dev, skb->len); 1045 skb_tx_timestamp(skb); 1046 1047 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1048 atomic_sub(n_desc, &ring->free_count); 1049 1050 /* make sure that all changes to the dma ring are flushed before we 1051 * continue 1052 */ 1053 wmb(); 1054 1055 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1056 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 1057 !netdev_xmit_more()) 1058 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 1059 } else { 1060 int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd), 1061 ring->dma_size); 1062 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1063 } 1064 1065 return 0; 1066 1067 err_dma: 1068 do { 1069 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 1070 1071 /* unmap dma */ 1072 mtk_tx_unmap(eth, tx_buf, false); 1073 1074 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1075 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1076 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1077 1078 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1079 itxd_pdma = qdma_to_pdma(ring, itxd); 1080 } while (itxd != txd); 1081 1082 return -ENOMEM; 1083 } 1084 1085 static inline int mtk_cal_txd_req(struct sk_buff *skb) 1086 { 1087 int i, nfrags; 1088 skb_frag_t *frag; 1089 1090 nfrags = 1; 1091 if (skb_is_gso(skb)) { 1092 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1093 frag = &skb_shinfo(skb)->frags[i]; 1094 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1095 MTK_TX_DMA_BUF_LEN); 1096 } 1097 } else { 1098 nfrags += skb_shinfo(skb)->nr_frags; 1099 } 1100 1101 return nfrags; 1102 } 1103 1104 static int mtk_queue_stopped(struct mtk_eth *eth) 1105 { 1106 int i; 1107 1108 for (i = 0; i < MTK_MAC_COUNT; i++) { 1109 if (!eth->netdev[i]) 1110 continue; 1111 if (netif_queue_stopped(eth->netdev[i])) 1112 return 1; 1113 } 1114 1115 return 0; 1116 } 1117 1118 static void mtk_wake_queue(struct mtk_eth *eth) 1119 { 1120 int i; 1121 1122 for (i = 0; i < MTK_MAC_COUNT; i++) { 1123 if (!eth->netdev[i]) 1124 continue; 1125 netif_wake_queue(eth->netdev[i]); 1126 } 1127 } 1128 1129 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1130 { 1131 struct mtk_mac *mac = netdev_priv(dev); 1132 struct mtk_eth *eth = mac->hw; 1133 struct mtk_tx_ring *ring = ð->tx_ring; 1134 struct net_device_stats *stats = &dev->stats; 1135 bool gso = false; 1136 int tx_num; 1137 1138 /* normally we can rely on the stack not calling this more than once, 1139 * however we have 2 queues running on the same ring so we need to lock 1140 * the ring access 1141 */ 1142 spin_lock(ð->page_lock); 1143 1144 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1145 goto drop; 1146 1147 tx_num = mtk_cal_txd_req(skb); 1148 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1149 netif_stop_queue(dev); 1150 netif_err(eth, tx_queued, dev, 1151 "Tx Ring full when queue awake!\n"); 1152 spin_unlock(ð->page_lock); 1153 return NETDEV_TX_BUSY; 1154 } 1155 1156 /* TSO: fill MSS info in tcp checksum field */ 1157 if (skb_is_gso(skb)) { 1158 if (skb_cow_head(skb, 0)) { 1159 netif_warn(eth, tx_err, dev, 1160 "GSO expand head fail.\n"); 1161 goto drop; 1162 } 1163 1164 if (skb_shinfo(skb)->gso_type & 1165 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1166 gso = true; 1167 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1168 } 1169 } 1170 1171 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1172 goto drop; 1173 1174 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1175 netif_stop_queue(dev); 1176 1177 spin_unlock(ð->page_lock); 1178 1179 return NETDEV_TX_OK; 1180 1181 drop: 1182 spin_unlock(ð->page_lock); 1183 stats->tx_dropped++; 1184 dev_kfree_skb_any(skb); 1185 return NETDEV_TX_OK; 1186 } 1187 1188 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1189 { 1190 int i; 1191 struct mtk_rx_ring *ring; 1192 int idx; 1193 1194 if (!eth->hwlro) 1195 return ð->rx_ring[0]; 1196 1197 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1198 ring = ð->rx_ring[i]; 1199 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1200 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 1201 ring->calc_idx_update = true; 1202 return ring; 1203 } 1204 } 1205 1206 return NULL; 1207 } 1208 1209 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1210 { 1211 struct mtk_rx_ring *ring; 1212 int i; 1213 1214 if (!eth->hwlro) { 1215 ring = ð->rx_ring[0]; 1216 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1217 } else { 1218 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1219 ring = ð->rx_ring[i]; 1220 if (ring->calc_idx_update) { 1221 ring->calc_idx_update = false; 1222 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1223 } 1224 } 1225 } 1226 } 1227 1228 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1229 struct mtk_eth *eth) 1230 { 1231 struct dim_sample dim_sample = {}; 1232 struct mtk_rx_ring *ring; 1233 int idx; 1234 struct sk_buff *skb; 1235 u8 *data, *new_data; 1236 struct mtk_rx_dma *rxd, trxd; 1237 int done = 0, bytes = 0; 1238 1239 while (done < budget) { 1240 struct net_device *netdev; 1241 unsigned int pktlen; 1242 dma_addr_t dma_addr; 1243 u32 hash, reason; 1244 int mac; 1245 1246 ring = mtk_get_rx_ring(eth); 1247 if (unlikely(!ring)) 1248 goto rx_done; 1249 1250 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1251 rxd = &ring->dma[idx]; 1252 data = ring->data[idx]; 1253 1254 if (!mtk_rx_get_desc(&trxd, rxd)) 1255 break; 1256 1257 /* find out which mac the packet come from. values start at 1 */ 1258 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) || 1259 (trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 1260 mac = 0; 1261 else 1262 mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 1263 RX_DMA_FPORT_MASK) - 1; 1264 1265 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1266 !eth->netdev[mac])) 1267 goto release_desc; 1268 1269 netdev = eth->netdev[mac]; 1270 1271 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1272 goto release_desc; 1273 1274 /* alloc new buffer */ 1275 new_data = napi_alloc_frag(ring->frag_size); 1276 if (unlikely(!new_data)) { 1277 netdev->stats.rx_dropped++; 1278 goto release_desc; 1279 } 1280 dma_addr = dma_map_single(eth->dma_dev, 1281 new_data + NET_SKB_PAD + 1282 eth->ip_align, 1283 ring->buf_size, 1284 DMA_FROM_DEVICE); 1285 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) { 1286 skb_free_frag(new_data); 1287 netdev->stats.rx_dropped++; 1288 goto release_desc; 1289 } 1290 1291 dma_unmap_single(eth->dma_dev, trxd.rxd1, 1292 ring->buf_size, DMA_FROM_DEVICE); 1293 1294 /* receive data */ 1295 skb = build_skb(data, ring->frag_size); 1296 if (unlikely(!skb)) { 1297 skb_free_frag(data); 1298 netdev->stats.rx_dropped++; 1299 goto skip_rx; 1300 } 1301 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1302 1303 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1304 skb->dev = netdev; 1305 skb_put(skb, pktlen); 1306 if (trxd.rxd4 & eth->rx_dma_l4_valid) 1307 skb->ip_summed = CHECKSUM_UNNECESSARY; 1308 else 1309 skb_checksum_none_assert(skb); 1310 skb->protocol = eth_type_trans(skb, netdev); 1311 bytes += pktlen; 1312 1313 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 1314 if (hash != MTK_RXD4_FOE_ENTRY) { 1315 hash = jhash_1word(hash, 0); 1316 skb_set_hash(skb, hash, PKT_HASH_TYPE_L4); 1317 } 1318 1319 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 1320 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 1321 mtk_ppe_check_skb(eth->ppe, skb, 1322 trxd.rxd4 & MTK_RXD4_FOE_ENTRY); 1323 1324 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1325 (trxd.rxd2 & RX_DMA_VTAG)) 1326 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1327 RX_DMA_VID(trxd.rxd3)); 1328 skb_record_rx_queue(skb, 0); 1329 napi_gro_receive(napi, skb); 1330 1331 skip_rx: 1332 ring->data[idx] = new_data; 1333 rxd->rxd1 = (unsigned int)dma_addr; 1334 1335 release_desc: 1336 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1337 rxd->rxd2 = RX_DMA_LSO; 1338 else 1339 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1340 1341 ring->calc_idx = idx; 1342 1343 done++; 1344 } 1345 1346 rx_done: 1347 if (done) { 1348 /* make sure that all changes to the dma ring are flushed before 1349 * we continue 1350 */ 1351 wmb(); 1352 mtk_update_rx_cpu_idx(eth); 1353 } 1354 1355 eth->rx_packets += done; 1356 eth->rx_bytes += bytes; 1357 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 1358 &dim_sample); 1359 net_dim(ð->rx_dim, dim_sample); 1360 1361 return done; 1362 } 1363 1364 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 1365 unsigned int *done, unsigned int *bytes) 1366 { 1367 struct mtk_tx_ring *ring = ð->tx_ring; 1368 struct mtk_tx_dma *desc; 1369 struct sk_buff *skb; 1370 struct mtk_tx_buf *tx_buf; 1371 u32 cpu, dma; 1372 1373 cpu = ring->last_free_ptr; 1374 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1375 1376 desc = mtk_qdma_phys_to_virt(ring, cpu); 1377 1378 while ((cpu != dma) && budget) { 1379 u32 next_cpu = desc->txd2; 1380 int mac = 0; 1381 1382 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1383 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1384 break; 1385 1386 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1387 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1388 mac = 1; 1389 1390 skb = tx_buf->skb; 1391 if (!skb) 1392 break; 1393 1394 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1395 bytes[mac] += skb->len; 1396 done[mac]++; 1397 budget--; 1398 } 1399 mtk_tx_unmap(eth, tx_buf, true); 1400 1401 ring->last_free = desc; 1402 atomic_inc(&ring->free_count); 1403 1404 cpu = next_cpu; 1405 } 1406 1407 ring->last_free_ptr = cpu; 1408 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1409 1410 return budget; 1411 } 1412 1413 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 1414 unsigned int *done, unsigned int *bytes) 1415 { 1416 struct mtk_tx_ring *ring = ð->tx_ring; 1417 struct mtk_tx_dma *desc; 1418 struct sk_buff *skb; 1419 struct mtk_tx_buf *tx_buf; 1420 u32 cpu, dma; 1421 1422 cpu = ring->cpu_idx; 1423 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 1424 1425 while ((cpu != dma) && budget) { 1426 tx_buf = &ring->buf[cpu]; 1427 skb = tx_buf->skb; 1428 if (!skb) 1429 break; 1430 1431 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1432 bytes[0] += skb->len; 1433 done[0]++; 1434 budget--; 1435 } 1436 1437 mtk_tx_unmap(eth, tx_buf, true); 1438 1439 desc = &ring->dma[cpu]; 1440 ring->last_free = desc; 1441 atomic_inc(&ring->free_count); 1442 1443 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 1444 } 1445 1446 ring->cpu_idx = cpu; 1447 1448 return budget; 1449 } 1450 1451 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1452 { 1453 struct mtk_tx_ring *ring = ð->tx_ring; 1454 struct dim_sample dim_sample = {}; 1455 unsigned int done[MTK_MAX_DEVS]; 1456 unsigned int bytes[MTK_MAX_DEVS]; 1457 int total = 0, i; 1458 1459 memset(done, 0, sizeof(done)); 1460 memset(bytes, 0, sizeof(bytes)); 1461 1462 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1463 budget = mtk_poll_tx_qdma(eth, budget, done, bytes); 1464 else 1465 budget = mtk_poll_tx_pdma(eth, budget, done, bytes); 1466 1467 for (i = 0; i < MTK_MAC_COUNT; i++) { 1468 if (!eth->netdev[i] || !done[i]) 1469 continue; 1470 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1471 total += done[i]; 1472 eth->tx_packets += done[i]; 1473 eth->tx_bytes += bytes[i]; 1474 } 1475 1476 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 1477 &dim_sample); 1478 net_dim(ð->tx_dim, dim_sample); 1479 1480 if (mtk_queue_stopped(eth) && 1481 (atomic_read(&ring->free_count) > ring->thresh)) 1482 mtk_wake_queue(eth); 1483 1484 return total; 1485 } 1486 1487 static void mtk_handle_status_irq(struct mtk_eth *eth) 1488 { 1489 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1490 1491 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1492 mtk_stats_update(eth); 1493 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1494 MTK_INT_STATUS2); 1495 } 1496 } 1497 1498 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1499 { 1500 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1501 int tx_done = 0; 1502 1503 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1504 mtk_handle_status_irq(eth); 1505 mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg); 1506 tx_done = mtk_poll_tx(eth, budget); 1507 1508 if (unlikely(netif_msg_intr(eth))) { 1509 dev_info(eth->dev, 1510 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 1511 mtk_r32(eth, eth->tx_int_status_reg), 1512 mtk_r32(eth, eth->tx_int_mask_reg)); 1513 } 1514 1515 if (tx_done == budget) 1516 return budget; 1517 1518 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) 1519 return budget; 1520 1521 if (napi_complete_done(napi, tx_done)) 1522 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1523 1524 return tx_done; 1525 } 1526 1527 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1528 { 1529 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1530 int rx_done_total = 0; 1531 1532 mtk_handle_status_irq(eth); 1533 1534 do { 1535 int rx_done; 1536 1537 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1538 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 1539 rx_done_total += rx_done; 1540 1541 if (unlikely(netif_msg_intr(eth))) { 1542 dev_info(eth->dev, 1543 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 1544 mtk_r32(eth, MTK_PDMA_INT_STATUS), 1545 mtk_r32(eth, MTK_PDMA_INT_MASK)); 1546 } 1547 1548 if (rx_done_total == budget) 1549 return budget; 1550 1551 } while (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT); 1552 1553 if (napi_complete_done(napi, rx_done_total)) 1554 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1555 1556 return rx_done_total; 1557 } 1558 1559 static int mtk_tx_alloc(struct mtk_eth *eth) 1560 { 1561 struct mtk_tx_ring *ring = ð->tx_ring; 1562 int i, sz = sizeof(*ring->dma); 1563 1564 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1565 GFP_KERNEL); 1566 if (!ring->buf) 1567 goto no_tx_mem; 1568 1569 ring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, 1570 &ring->phys, GFP_ATOMIC); 1571 if (!ring->dma) 1572 goto no_tx_mem; 1573 1574 for (i = 0; i < MTK_DMA_SIZE; i++) { 1575 int next = (i + 1) % MTK_DMA_SIZE; 1576 u32 next_ptr = ring->phys + next * sz; 1577 1578 ring->dma[i].txd2 = next_ptr; 1579 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1580 } 1581 1582 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 1583 * only as the framework. The real HW descriptors are the PDMA 1584 * descriptors in ring->dma_pdma. 1585 */ 1586 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1587 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, 1588 &ring->phys_pdma, 1589 GFP_ATOMIC); 1590 if (!ring->dma_pdma) 1591 goto no_tx_mem; 1592 1593 for (i = 0; i < MTK_DMA_SIZE; i++) { 1594 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 1595 ring->dma_pdma[i].txd4 = 0; 1596 } 1597 } 1598 1599 ring->dma_size = MTK_DMA_SIZE; 1600 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1601 ring->next_free = &ring->dma[0]; 1602 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1603 ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz)); 1604 ring->thresh = MAX_SKB_FRAGS; 1605 1606 /* make sure that all changes to the dma ring are flushed before we 1607 * continue 1608 */ 1609 wmb(); 1610 1611 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1612 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1613 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1614 mtk_w32(eth, 1615 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1616 MTK_QTX_CRX_PTR); 1617 mtk_w32(eth, ring->last_free_ptr, MTK_QTX_DRX_PTR); 1618 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, 1619 MTK_QTX_CFG(0)); 1620 } else { 1621 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 1622 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); 1623 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 1624 mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX); 1625 } 1626 1627 return 0; 1628 1629 no_tx_mem: 1630 return -ENOMEM; 1631 } 1632 1633 static void mtk_tx_clean(struct mtk_eth *eth) 1634 { 1635 struct mtk_tx_ring *ring = ð->tx_ring; 1636 int i; 1637 1638 if (ring->buf) { 1639 for (i = 0; i < MTK_DMA_SIZE; i++) 1640 mtk_tx_unmap(eth, &ring->buf[i], false); 1641 kfree(ring->buf); 1642 ring->buf = NULL; 1643 } 1644 1645 if (ring->dma) { 1646 dma_free_coherent(eth->dma_dev, 1647 MTK_DMA_SIZE * sizeof(*ring->dma), 1648 ring->dma, 1649 ring->phys); 1650 ring->dma = NULL; 1651 } 1652 1653 if (ring->dma_pdma) { 1654 dma_free_coherent(eth->dma_dev, 1655 MTK_DMA_SIZE * sizeof(*ring->dma_pdma), 1656 ring->dma_pdma, 1657 ring->phys_pdma); 1658 ring->dma_pdma = NULL; 1659 } 1660 } 1661 1662 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1663 { 1664 struct mtk_rx_ring *ring; 1665 int rx_data_len, rx_dma_size; 1666 int i; 1667 u32 offset = 0; 1668 1669 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1670 if (ring_no) 1671 return -EINVAL; 1672 ring = ð->rx_ring_qdma; 1673 offset = 0x1000; 1674 } else { 1675 ring = ð->rx_ring[ring_no]; 1676 } 1677 1678 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1679 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1680 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1681 } else { 1682 rx_data_len = ETH_DATA_LEN; 1683 rx_dma_size = MTK_DMA_SIZE; 1684 } 1685 1686 ring->frag_size = mtk_max_frag_size(rx_data_len); 1687 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1688 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1689 GFP_KERNEL); 1690 if (!ring->data) 1691 return -ENOMEM; 1692 1693 for (i = 0; i < rx_dma_size; i++) { 1694 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1695 if (!ring->data[i]) 1696 return -ENOMEM; 1697 } 1698 1699 ring->dma = dma_alloc_coherent(eth->dma_dev, 1700 rx_dma_size * sizeof(*ring->dma), 1701 &ring->phys, GFP_ATOMIC); 1702 if (!ring->dma) 1703 return -ENOMEM; 1704 1705 for (i = 0; i < rx_dma_size; i++) { 1706 dma_addr_t dma_addr = dma_map_single(eth->dma_dev, 1707 ring->data[i] + NET_SKB_PAD + eth->ip_align, 1708 ring->buf_size, 1709 DMA_FROM_DEVICE); 1710 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1711 return -ENOMEM; 1712 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1713 1714 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1715 ring->dma[i].rxd2 = RX_DMA_LSO; 1716 else 1717 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1718 } 1719 ring->dma_size = rx_dma_size; 1720 ring->calc_idx_update = false; 1721 ring->calc_idx = rx_dma_size - 1; 1722 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1723 /* make sure that all changes to the dma ring are flushed before we 1724 * continue 1725 */ 1726 wmb(); 1727 1728 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1729 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1730 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1731 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1732 1733 return 0; 1734 } 1735 1736 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1737 { 1738 int i; 1739 1740 if (ring->data && ring->dma) { 1741 for (i = 0; i < ring->dma_size; i++) { 1742 if (!ring->data[i]) 1743 continue; 1744 if (!ring->dma[i].rxd1) 1745 continue; 1746 dma_unmap_single(eth->dma_dev, 1747 ring->dma[i].rxd1, 1748 ring->buf_size, 1749 DMA_FROM_DEVICE); 1750 skb_free_frag(ring->data[i]); 1751 } 1752 kfree(ring->data); 1753 ring->data = NULL; 1754 } 1755 1756 if (ring->dma) { 1757 dma_free_coherent(eth->dma_dev, 1758 ring->dma_size * sizeof(*ring->dma), 1759 ring->dma, 1760 ring->phys); 1761 ring->dma = NULL; 1762 } 1763 } 1764 1765 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1766 { 1767 int i; 1768 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1769 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1770 1771 /* set LRO rings to auto-learn modes */ 1772 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1773 1774 /* validate LRO ring */ 1775 ring_ctrl_dw2 |= MTK_RING_VLD; 1776 1777 /* set AGE timer (unit: 20us) */ 1778 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1779 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1780 1781 /* set max AGG timer (unit: 20us) */ 1782 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1783 1784 /* set max LRO AGG count */ 1785 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1786 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1787 1788 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1789 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1790 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1791 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1792 } 1793 1794 /* IPv4 checksum update enable */ 1795 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1796 1797 /* switch priority comparison to packet count mode */ 1798 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1799 1800 /* bandwidth threshold setting */ 1801 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1802 1803 /* auto-learn score delta setting */ 1804 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1805 1806 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1807 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1808 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1809 1810 /* set HW LRO mode & the max aggregation count for rx packets */ 1811 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1812 1813 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1814 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1815 1816 /* enable HW LRO */ 1817 lro_ctrl_dw0 |= MTK_LRO_EN; 1818 1819 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1820 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1821 1822 return 0; 1823 } 1824 1825 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1826 { 1827 int i; 1828 u32 val; 1829 1830 /* relinquish lro rings, flush aggregated packets */ 1831 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1832 1833 /* wait for relinquishments done */ 1834 for (i = 0; i < 10; i++) { 1835 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1836 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1837 msleep(20); 1838 continue; 1839 } 1840 break; 1841 } 1842 1843 /* invalidate lro rings */ 1844 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1845 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1846 1847 /* disable HW LRO */ 1848 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1849 } 1850 1851 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1852 { 1853 u32 reg_val; 1854 1855 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1856 1857 /* invalidate the IP setting */ 1858 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1859 1860 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1861 1862 /* validate the IP setting */ 1863 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1864 } 1865 1866 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1867 { 1868 u32 reg_val; 1869 1870 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1871 1872 /* invalidate the IP setting */ 1873 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1874 1875 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1876 } 1877 1878 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1879 { 1880 int cnt = 0; 1881 int i; 1882 1883 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1884 if (mac->hwlro_ip[i]) 1885 cnt++; 1886 } 1887 1888 return cnt; 1889 } 1890 1891 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1892 struct ethtool_rxnfc *cmd) 1893 { 1894 struct ethtool_rx_flow_spec *fsp = 1895 (struct ethtool_rx_flow_spec *)&cmd->fs; 1896 struct mtk_mac *mac = netdev_priv(dev); 1897 struct mtk_eth *eth = mac->hw; 1898 int hwlro_idx; 1899 1900 if ((fsp->flow_type != TCP_V4_FLOW) || 1901 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1902 (fsp->location > 1)) 1903 return -EINVAL; 1904 1905 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1906 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1907 1908 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1909 1910 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1911 1912 return 0; 1913 } 1914 1915 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1916 struct ethtool_rxnfc *cmd) 1917 { 1918 struct ethtool_rx_flow_spec *fsp = 1919 (struct ethtool_rx_flow_spec *)&cmd->fs; 1920 struct mtk_mac *mac = netdev_priv(dev); 1921 struct mtk_eth *eth = mac->hw; 1922 int hwlro_idx; 1923 1924 if (fsp->location > 1) 1925 return -EINVAL; 1926 1927 mac->hwlro_ip[fsp->location] = 0; 1928 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1929 1930 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1931 1932 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1933 1934 return 0; 1935 } 1936 1937 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1938 { 1939 struct mtk_mac *mac = netdev_priv(dev); 1940 struct mtk_eth *eth = mac->hw; 1941 int i, hwlro_idx; 1942 1943 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1944 mac->hwlro_ip[i] = 0; 1945 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1946 1947 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1948 } 1949 1950 mac->hwlro_ip_cnt = 0; 1951 } 1952 1953 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1954 struct ethtool_rxnfc *cmd) 1955 { 1956 struct mtk_mac *mac = netdev_priv(dev); 1957 struct ethtool_rx_flow_spec *fsp = 1958 (struct ethtool_rx_flow_spec *)&cmd->fs; 1959 1960 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1961 fsp->flow_type = TCP_V4_FLOW; 1962 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1963 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1964 1965 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1966 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1967 fsp->h_u.tcp_ip4_spec.psrc = 0; 1968 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1969 fsp->h_u.tcp_ip4_spec.pdst = 0; 1970 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1971 fsp->h_u.tcp_ip4_spec.tos = 0; 1972 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1973 1974 return 0; 1975 } 1976 1977 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1978 struct ethtool_rxnfc *cmd, 1979 u32 *rule_locs) 1980 { 1981 struct mtk_mac *mac = netdev_priv(dev); 1982 int cnt = 0; 1983 int i; 1984 1985 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1986 if (mac->hwlro_ip[i]) { 1987 rule_locs[cnt] = i; 1988 cnt++; 1989 } 1990 } 1991 1992 cmd->rule_cnt = cnt; 1993 1994 return 0; 1995 } 1996 1997 static netdev_features_t mtk_fix_features(struct net_device *dev, 1998 netdev_features_t features) 1999 { 2000 if (!(features & NETIF_F_LRO)) { 2001 struct mtk_mac *mac = netdev_priv(dev); 2002 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2003 2004 if (ip_cnt) { 2005 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 2006 2007 features |= NETIF_F_LRO; 2008 } 2009 } 2010 2011 return features; 2012 } 2013 2014 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2015 { 2016 int err = 0; 2017 2018 if (!((dev->features ^ features) & NETIF_F_LRO)) 2019 return 0; 2020 2021 if (!(features & NETIF_F_LRO)) 2022 mtk_hwlro_netdev_disable(dev); 2023 2024 return err; 2025 } 2026 2027 /* wait for DMA to finish whatever it is doing before we start using it again */ 2028 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2029 { 2030 unsigned int reg; 2031 int ret; 2032 u32 val; 2033 2034 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2035 reg = MTK_QDMA_GLO_CFG; 2036 else 2037 reg = MTK_PDMA_GLO_CFG; 2038 2039 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 2040 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 2041 5, MTK_DMA_BUSY_TIMEOUT_US); 2042 if (ret) 2043 dev_err(eth->dev, "DMA init timeout\n"); 2044 2045 return ret; 2046 } 2047 2048 static int mtk_dma_init(struct mtk_eth *eth) 2049 { 2050 int err; 2051 u32 i; 2052 2053 if (mtk_dma_busy_wait(eth)) 2054 return -EBUSY; 2055 2056 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2057 /* QDMA needs scratch memory for internal reordering of the 2058 * descriptors 2059 */ 2060 err = mtk_init_fq_dma(eth); 2061 if (err) 2062 return err; 2063 } 2064 2065 err = mtk_tx_alloc(eth); 2066 if (err) 2067 return err; 2068 2069 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2070 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2071 if (err) 2072 return err; 2073 } 2074 2075 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2076 if (err) 2077 return err; 2078 2079 if (eth->hwlro) { 2080 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2081 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2082 if (err) 2083 return err; 2084 } 2085 err = mtk_hwlro_rx_init(eth); 2086 if (err) 2087 return err; 2088 } 2089 2090 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2091 /* Enable random early drop and set drop threshold 2092 * automatically 2093 */ 2094 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2095 FC_THRES_MIN, MTK_QDMA_FC_THRES); 2096 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 2097 } 2098 2099 return 0; 2100 } 2101 2102 static void mtk_dma_free(struct mtk_eth *eth) 2103 { 2104 int i; 2105 2106 for (i = 0; i < MTK_MAC_COUNT; i++) 2107 if (eth->netdev[i]) 2108 netdev_reset_queue(eth->netdev[i]); 2109 if (eth->scratch_ring) { 2110 dma_free_coherent(eth->dma_dev, 2111 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 2112 eth->scratch_ring, 2113 eth->phy_scratch_ring); 2114 eth->scratch_ring = NULL; 2115 eth->phy_scratch_ring = 0; 2116 } 2117 mtk_tx_clean(eth); 2118 mtk_rx_clean(eth, ð->rx_ring[0]); 2119 mtk_rx_clean(eth, ð->rx_ring_qdma); 2120 2121 if (eth->hwlro) { 2122 mtk_hwlro_rx_uninit(eth); 2123 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2124 mtk_rx_clean(eth, ð->rx_ring[i]); 2125 } 2126 2127 kfree(eth->scratch_head); 2128 } 2129 2130 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 2131 { 2132 struct mtk_mac *mac = netdev_priv(dev); 2133 struct mtk_eth *eth = mac->hw; 2134 2135 eth->netdev[mac->id]->stats.tx_errors++; 2136 netif_err(eth, tx_err, dev, 2137 "transmit timed out\n"); 2138 schedule_work(ð->pending_work); 2139 } 2140 2141 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 2142 { 2143 struct mtk_eth *eth = _eth; 2144 2145 eth->rx_events++; 2146 if (likely(napi_schedule_prep(ð->rx_napi))) { 2147 __napi_schedule(ð->rx_napi); 2148 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2149 } 2150 2151 return IRQ_HANDLED; 2152 } 2153 2154 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 2155 { 2156 struct mtk_eth *eth = _eth; 2157 2158 eth->tx_events++; 2159 if (likely(napi_schedule_prep(ð->tx_napi))) { 2160 __napi_schedule(ð->tx_napi); 2161 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2162 } 2163 2164 return IRQ_HANDLED; 2165 } 2166 2167 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 2168 { 2169 struct mtk_eth *eth = _eth; 2170 2171 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { 2172 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) 2173 mtk_handle_irq_rx(irq, _eth); 2174 } 2175 if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) { 2176 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) 2177 mtk_handle_irq_tx(irq, _eth); 2178 } 2179 2180 return IRQ_HANDLED; 2181 } 2182 2183 #ifdef CONFIG_NET_POLL_CONTROLLER 2184 static void mtk_poll_controller(struct net_device *dev) 2185 { 2186 struct mtk_mac *mac = netdev_priv(dev); 2187 struct mtk_eth *eth = mac->hw; 2188 2189 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2190 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2191 mtk_handle_irq_rx(eth->irq[2], dev); 2192 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2193 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2194 } 2195 #endif 2196 2197 static int mtk_start_dma(struct mtk_eth *eth) 2198 { 2199 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 2200 int err; 2201 2202 err = mtk_dma_init(eth); 2203 if (err) { 2204 mtk_dma_free(eth); 2205 return err; 2206 } 2207 2208 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2209 mtk_w32(eth, 2210 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 2211 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 2212 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 2213 MTK_RX_BT_32DWORDS, 2214 MTK_QDMA_GLO_CFG); 2215 2216 mtk_w32(eth, 2217 MTK_RX_DMA_EN | rx_2b_offset | 2218 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 2219 MTK_PDMA_GLO_CFG); 2220 } else { 2221 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2222 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 2223 MTK_PDMA_GLO_CFG); 2224 } 2225 2226 return 0; 2227 } 2228 2229 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 2230 { 2231 int i; 2232 2233 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2234 return; 2235 2236 for (i = 0; i < MTK_MAC_COUNT; i++) { 2237 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 2238 2239 /* default setup the forward port to send frame to PDMA */ 2240 val &= ~0xffff; 2241 2242 /* Enable RX checksum */ 2243 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2244 2245 val |= config; 2246 2247 if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0])) 2248 val |= MTK_GDMA_SPECIAL_TAG; 2249 2250 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2251 } 2252 /* Reset and enable PSE */ 2253 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 2254 mtk_w32(eth, 0, MTK_RST_GL); 2255 } 2256 2257 static int mtk_open(struct net_device *dev) 2258 { 2259 struct mtk_mac *mac = netdev_priv(dev); 2260 struct mtk_eth *eth = mac->hw; 2261 int err; 2262 2263 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 2264 if (err) { 2265 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 2266 err); 2267 return err; 2268 } 2269 2270 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 2271 if (!refcount_read(ð->dma_refcnt)) { 2272 u32 gdm_config = MTK_GDMA_TO_PDMA; 2273 2274 err = mtk_start_dma(eth); 2275 if (err) 2276 return err; 2277 2278 if (eth->soc->offload_version && mtk_ppe_start(eth->ppe) == 0) 2279 gdm_config = MTK_GDMA_TO_PPE; 2280 2281 mtk_gdm_config(eth, gdm_config); 2282 2283 napi_enable(ð->tx_napi); 2284 napi_enable(ð->rx_napi); 2285 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2286 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2287 refcount_set(ð->dma_refcnt, 1); 2288 } 2289 else 2290 refcount_inc(ð->dma_refcnt); 2291 2292 phylink_start(mac->phylink); 2293 netif_start_queue(dev); 2294 return 0; 2295 } 2296 2297 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 2298 { 2299 u32 val; 2300 int i; 2301 2302 /* stop the dma engine */ 2303 spin_lock_bh(ð->page_lock); 2304 val = mtk_r32(eth, glo_cfg); 2305 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 2306 glo_cfg); 2307 spin_unlock_bh(ð->page_lock); 2308 2309 /* wait for dma stop */ 2310 for (i = 0; i < 10; i++) { 2311 val = mtk_r32(eth, glo_cfg); 2312 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 2313 msleep(20); 2314 continue; 2315 } 2316 break; 2317 } 2318 } 2319 2320 static int mtk_stop(struct net_device *dev) 2321 { 2322 struct mtk_mac *mac = netdev_priv(dev); 2323 struct mtk_eth *eth = mac->hw; 2324 2325 phylink_stop(mac->phylink); 2326 2327 netif_tx_disable(dev); 2328 2329 phylink_disconnect_phy(mac->phylink); 2330 2331 /* only shutdown DMA if this is the last user */ 2332 if (!refcount_dec_and_test(ð->dma_refcnt)) 2333 return 0; 2334 2335 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 2336 2337 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2338 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2339 napi_disable(ð->tx_napi); 2340 napi_disable(ð->rx_napi); 2341 2342 cancel_work_sync(ð->rx_dim.work); 2343 cancel_work_sync(ð->tx_dim.work); 2344 2345 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2346 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 2347 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 2348 2349 mtk_dma_free(eth); 2350 2351 if (eth->soc->offload_version) 2352 mtk_ppe_stop(eth->ppe); 2353 2354 return 0; 2355 } 2356 2357 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 2358 { 2359 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2360 reset_bits, 2361 reset_bits); 2362 2363 usleep_range(1000, 1100); 2364 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2365 reset_bits, 2366 ~reset_bits); 2367 mdelay(10); 2368 } 2369 2370 static void mtk_clk_disable(struct mtk_eth *eth) 2371 { 2372 int clk; 2373 2374 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 2375 clk_disable_unprepare(eth->clks[clk]); 2376 } 2377 2378 static int mtk_clk_enable(struct mtk_eth *eth) 2379 { 2380 int clk, ret; 2381 2382 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 2383 ret = clk_prepare_enable(eth->clks[clk]); 2384 if (ret) 2385 goto err_disable_clks; 2386 } 2387 2388 return 0; 2389 2390 err_disable_clks: 2391 while (--clk >= 0) 2392 clk_disable_unprepare(eth->clks[clk]); 2393 2394 return ret; 2395 } 2396 2397 static void mtk_dim_rx(struct work_struct *work) 2398 { 2399 struct dim *dim = container_of(work, struct dim, work); 2400 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 2401 struct dim_cq_moder cur_profile; 2402 u32 val, cur; 2403 2404 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 2405 dim->profile_ix); 2406 spin_lock_bh(ð->dim_lock); 2407 2408 val = mtk_r32(eth, MTK_PDMA_DELAY_INT); 2409 val &= MTK_PDMA_DELAY_TX_MASK; 2410 val |= MTK_PDMA_DELAY_RX_EN; 2411 2412 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 2413 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 2414 2415 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 2416 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 2417 2418 mtk_w32(eth, val, MTK_PDMA_DELAY_INT); 2419 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2420 mtk_w32(eth, val, MTK_QDMA_DELAY_INT); 2421 2422 spin_unlock_bh(ð->dim_lock); 2423 2424 dim->state = DIM_START_MEASURE; 2425 } 2426 2427 static void mtk_dim_tx(struct work_struct *work) 2428 { 2429 struct dim *dim = container_of(work, struct dim, work); 2430 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 2431 struct dim_cq_moder cur_profile; 2432 u32 val, cur; 2433 2434 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 2435 dim->profile_ix); 2436 spin_lock_bh(ð->dim_lock); 2437 2438 val = mtk_r32(eth, MTK_PDMA_DELAY_INT); 2439 val &= MTK_PDMA_DELAY_RX_MASK; 2440 val |= MTK_PDMA_DELAY_TX_EN; 2441 2442 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 2443 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 2444 2445 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 2446 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 2447 2448 mtk_w32(eth, val, MTK_PDMA_DELAY_INT); 2449 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2450 mtk_w32(eth, val, MTK_QDMA_DELAY_INT); 2451 2452 spin_unlock_bh(ð->dim_lock); 2453 2454 dim->state = DIM_START_MEASURE; 2455 } 2456 2457 static int mtk_hw_init(struct mtk_eth *eth) 2458 { 2459 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 2460 ETHSYS_DMA_AG_MAP_PPE; 2461 int i, val, ret; 2462 2463 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 2464 return 0; 2465 2466 pm_runtime_enable(eth->dev); 2467 pm_runtime_get_sync(eth->dev); 2468 2469 ret = mtk_clk_enable(eth); 2470 if (ret) 2471 goto err_disable_pm; 2472 2473 if (eth->ethsys) 2474 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 2475 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 2476 2477 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2478 ret = device_reset(eth->dev); 2479 if (ret) { 2480 dev_err(eth->dev, "MAC reset failed!\n"); 2481 goto err_disable_pm; 2482 } 2483 2484 /* set interrupt delays based on current Net DIM sample */ 2485 mtk_dim_rx(ð->rx_dim.work); 2486 mtk_dim_tx(ð->tx_dim.work); 2487 2488 /* disable delay and normal interrupt */ 2489 mtk_tx_irq_disable(eth, ~0); 2490 mtk_rx_irq_disable(eth, ~0); 2491 2492 return 0; 2493 } 2494 2495 /* Non-MT7628 handling... */ 2496 ethsys_reset(eth, RSTCTRL_FE); 2497 ethsys_reset(eth, RSTCTRL_PPE); 2498 2499 if (eth->pctl) { 2500 /* Set GE2 driving and slew rate */ 2501 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 2502 2503 /* set GE2 TDSEL */ 2504 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 2505 2506 /* set GE2 TUNE */ 2507 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 2508 } 2509 2510 /* Set linkdown as the default for each GMAC. Its own MCR would be set 2511 * up with the more appropriate value when mtk_mac_config call is being 2512 * invoked. 2513 */ 2514 for (i = 0; i < MTK_MAC_COUNT; i++) 2515 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 2516 2517 /* Indicates CDM to parse the MTK special tag from CPU 2518 * which also is working out for untag packets. 2519 */ 2520 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 2521 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 2522 2523 /* Enable RX VLan Offloading */ 2524 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 2525 2526 /* set interrupt delays based on current Net DIM sample */ 2527 mtk_dim_rx(ð->rx_dim.work); 2528 mtk_dim_tx(ð->tx_dim.work); 2529 2530 /* disable delay and normal interrupt */ 2531 mtk_tx_irq_disable(eth, ~0); 2532 mtk_rx_irq_disable(eth, ~0); 2533 2534 /* FE int grouping */ 2535 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 2536 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 2537 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 2538 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 2539 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 2540 2541 return 0; 2542 2543 err_disable_pm: 2544 pm_runtime_put_sync(eth->dev); 2545 pm_runtime_disable(eth->dev); 2546 2547 return ret; 2548 } 2549 2550 static int mtk_hw_deinit(struct mtk_eth *eth) 2551 { 2552 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2553 return 0; 2554 2555 mtk_clk_disable(eth); 2556 2557 pm_runtime_put_sync(eth->dev); 2558 pm_runtime_disable(eth->dev); 2559 2560 return 0; 2561 } 2562 2563 static int __init mtk_init(struct net_device *dev) 2564 { 2565 struct mtk_mac *mac = netdev_priv(dev); 2566 struct mtk_eth *eth = mac->hw; 2567 int ret; 2568 2569 ret = of_get_ethdev_address(mac->of_node, dev); 2570 if (ret) { 2571 /* If the mac address is invalid, use random mac address */ 2572 eth_hw_addr_random(dev); 2573 dev_err(eth->dev, "generated random MAC address %pM\n", 2574 dev->dev_addr); 2575 } 2576 2577 return 0; 2578 } 2579 2580 static void mtk_uninit(struct net_device *dev) 2581 { 2582 struct mtk_mac *mac = netdev_priv(dev); 2583 struct mtk_eth *eth = mac->hw; 2584 2585 phylink_disconnect_phy(mac->phylink); 2586 mtk_tx_irq_disable(eth, ~0); 2587 mtk_rx_irq_disable(eth, ~0); 2588 } 2589 2590 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 2591 { 2592 int length = new_mtu + MTK_RX_ETH_HLEN; 2593 struct mtk_mac *mac = netdev_priv(dev); 2594 struct mtk_eth *eth = mac->hw; 2595 u32 mcr_cur, mcr_new; 2596 2597 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2598 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 2599 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 2600 2601 if (length <= 1518) 2602 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 2603 else if (length <= 1536) 2604 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 2605 else if (length <= 1552) 2606 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 2607 else 2608 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 2609 2610 if (mcr_new != mcr_cur) 2611 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 2612 } 2613 2614 dev->mtu = new_mtu; 2615 2616 return 0; 2617 } 2618 2619 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2620 { 2621 struct mtk_mac *mac = netdev_priv(dev); 2622 2623 switch (cmd) { 2624 case SIOCGMIIPHY: 2625 case SIOCGMIIREG: 2626 case SIOCSMIIREG: 2627 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 2628 default: 2629 break; 2630 } 2631 2632 return -EOPNOTSUPP; 2633 } 2634 2635 static void mtk_pending_work(struct work_struct *work) 2636 { 2637 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2638 int err, i; 2639 unsigned long restart = 0; 2640 2641 rtnl_lock(); 2642 2643 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2644 2645 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2646 cpu_relax(); 2647 2648 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2649 /* stop all devices to make sure that dma is properly shut down */ 2650 for (i = 0; i < MTK_MAC_COUNT; i++) { 2651 if (!eth->netdev[i]) 2652 continue; 2653 mtk_stop(eth->netdev[i]); 2654 __set_bit(i, &restart); 2655 } 2656 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2657 2658 /* restart underlying hardware such as power, clock, pin mux 2659 * and the connected phy 2660 */ 2661 mtk_hw_deinit(eth); 2662 2663 if (eth->dev->pins) 2664 pinctrl_select_state(eth->dev->pins->p, 2665 eth->dev->pins->default_state); 2666 mtk_hw_init(eth); 2667 2668 /* restart DMA and enable IRQs */ 2669 for (i = 0; i < MTK_MAC_COUNT; i++) { 2670 if (!test_bit(i, &restart)) 2671 continue; 2672 err = mtk_open(eth->netdev[i]); 2673 if (err) { 2674 netif_alert(eth, ifup, eth->netdev[i], 2675 "Driver up/down cycle failed, closing device.\n"); 2676 dev_close(eth->netdev[i]); 2677 } 2678 } 2679 2680 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2681 2682 clear_bit_unlock(MTK_RESETTING, ð->state); 2683 2684 rtnl_unlock(); 2685 } 2686 2687 static int mtk_free_dev(struct mtk_eth *eth) 2688 { 2689 int i; 2690 2691 for (i = 0; i < MTK_MAC_COUNT; i++) { 2692 if (!eth->netdev[i]) 2693 continue; 2694 free_netdev(eth->netdev[i]); 2695 } 2696 2697 return 0; 2698 } 2699 2700 static int mtk_unreg_dev(struct mtk_eth *eth) 2701 { 2702 int i; 2703 2704 for (i = 0; i < MTK_MAC_COUNT; i++) { 2705 if (!eth->netdev[i]) 2706 continue; 2707 unregister_netdev(eth->netdev[i]); 2708 } 2709 2710 return 0; 2711 } 2712 2713 static int mtk_cleanup(struct mtk_eth *eth) 2714 { 2715 mtk_unreg_dev(eth); 2716 mtk_free_dev(eth); 2717 cancel_work_sync(ð->pending_work); 2718 2719 return 0; 2720 } 2721 2722 static int mtk_get_link_ksettings(struct net_device *ndev, 2723 struct ethtool_link_ksettings *cmd) 2724 { 2725 struct mtk_mac *mac = netdev_priv(ndev); 2726 2727 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2728 return -EBUSY; 2729 2730 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 2731 } 2732 2733 static int mtk_set_link_ksettings(struct net_device *ndev, 2734 const struct ethtool_link_ksettings *cmd) 2735 { 2736 struct mtk_mac *mac = netdev_priv(ndev); 2737 2738 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2739 return -EBUSY; 2740 2741 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 2742 } 2743 2744 static void mtk_get_drvinfo(struct net_device *dev, 2745 struct ethtool_drvinfo *info) 2746 { 2747 struct mtk_mac *mac = netdev_priv(dev); 2748 2749 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2750 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2751 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2752 } 2753 2754 static u32 mtk_get_msglevel(struct net_device *dev) 2755 { 2756 struct mtk_mac *mac = netdev_priv(dev); 2757 2758 return mac->hw->msg_enable; 2759 } 2760 2761 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2762 { 2763 struct mtk_mac *mac = netdev_priv(dev); 2764 2765 mac->hw->msg_enable = value; 2766 } 2767 2768 static int mtk_nway_reset(struct net_device *dev) 2769 { 2770 struct mtk_mac *mac = netdev_priv(dev); 2771 2772 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2773 return -EBUSY; 2774 2775 if (!mac->phylink) 2776 return -ENOTSUPP; 2777 2778 return phylink_ethtool_nway_reset(mac->phylink); 2779 } 2780 2781 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2782 { 2783 int i; 2784 2785 switch (stringset) { 2786 case ETH_SS_STATS: 2787 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2788 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2789 data += ETH_GSTRING_LEN; 2790 } 2791 break; 2792 } 2793 } 2794 2795 static int mtk_get_sset_count(struct net_device *dev, int sset) 2796 { 2797 switch (sset) { 2798 case ETH_SS_STATS: 2799 return ARRAY_SIZE(mtk_ethtool_stats); 2800 default: 2801 return -EOPNOTSUPP; 2802 } 2803 } 2804 2805 static void mtk_get_ethtool_stats(struct net_device *dev, 2806 struct ethtool_stats *stats, u64 *data) 2807 { 2808 struct mtk_mac *mac = netdev_priv(dev); 2809 struct mtk_hw_stats *hwstats = mac->hw_stats; 2810 u64 *data_src, *data_dst; 2811 unsigned int start; 2812 int i; 2813 2814 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2815 return; 2816 2817 if (netif_running(dev) && netif_device_present(dev)) { 2818 if (spin_trylock_bh(&hwstats->stats_lock)) { 2819 mtk_stats_update_mac(mac); 2820 spin_unlock_bh(&hwstats->stats_lock); 2821 } 2822 } 2823 2824 data_src = (u64 *)hwstats; 2825 2826 do { 2827 data_dst = data; 2828 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2829 2830 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2831 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2832 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2833 } 2834 2835 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2836 u32 *rule_locs) 2837 { 2838 int ret = -EOPNOTSUPP; 2839 2840 switch (cmd->cmd) { 2841 case ETHTOOL_GRXRINGS: 2842 if (dev->hw_features & NETIF_F_LRO) { 2843 cmd->data = MTK_MAX_RX_RING_NUM; 2844 ret = 0; 2845 } 2846 break; 2847 case ETHTOOL_GRXCLSRLCNT: 2848 if (dev->hw_features & NETIF_F_LRO) { 2849 struct mtk_mac *mac = netdev_priv(dev); 2850 2851 cmd->rule_cnt = mac->hwlro_ip_cnt; 2852 ret = 0; 2853 } 2854 break; 2855 case ETHTOOL_GRXCLSRULE: 2856 if (dev->hw_features & NETIF_F_LRO) 2857 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2858 break; 2859 case ETHTOOL_GRXCLSRLALL: 2860 if (dev->hw_features & NETIF_F_LRO) 2861 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2862 rule_locs); 2863 break; 2864 default: 2865 break; 2866 } 2867 2868 return ret; 2869 } 2870 2871 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2872 { 2873 int ret = -EOPNOTSUPP; 2874 2875 switch (cmd->cmd) { 2876 case ETHTOOL_SRXCLSRLINS: 2877 if (dev->hw_features & NETIF_F_LRO) 2878 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2879 break; 2880 case ETHTOOL_SRXCLSRLDEL: 2881 if (dev->hw_features & NETIF_F_LRO) 2882 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2883 break; 2884 default: 2885 break; 2886 } 2887 2888 return ret; 2889 } 2890 2891 static const struct ethtool_ops mtk_ethtool_ops = { 2892 .get_link_ksettings = mtk_get_link_ksettings, 2893 .set_link_ksettings = mtk_set_link_ksettings, 2894 .get_drvinfo = mtk_get_drvinfo, 2895 .get_msglevel = mtk_get_msglevel, 2896 .set_msglevel = mtk_set_msglevel, 2897 .nway_reset = mtk_nway_reset, 2898 .get_link = ethtool_op_get_link, 2899 .get_strings = mtk_get_strings, 2900 .get_sset_count = mtk_get_sset_count, 2901 .get_ethtool_stats = mtk_get_ethtool_stats, 2902 .get_rxnfc = mtk_get_rxnfc, 2903 .set_rxnfc = mtk_set_rxnfc, 2904 }; 2905 2906 static const struct net_device_ops mtk_netdev_ops = { 2907 .ndo_init = mtk_init, 2908 .ndo_uninit = mtk_uninit, 2909 .ndo_open = mtk_open, 2910 .ndo_stop = mtk_stop, 2911 .ndo_start_xmit = mtk_start_xmit, 2912 .ndo_set_mac_address = mtk_set_mac_address, 2913 .ndo_validate_addr = eth_validate_addr, 2914 .ndo_eth_ioctl = mtk_do_ioctl, 2915 .ndo_change_mtu = mtk_change_mtu, 2916 .ndo_tx_timeout = mtk_tx_timeout, 2917 .ndo_get_stats64 = mtk_get_stats64, 2918 .ndo_fix_features = mtk_fix_features, 2919 .ndo_set_features = mtk_set_features, 2920 #ifdef CONFIG_NET_POLL_CONTROLLER 2921 .ndo_poll_controller = mtk_poll_controller, 2922 #endif 2923 .ndo_setup_tc = mtk_eth_setup_tc, 2924 }; 2925 2926 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2927 { 2928 const __be32 *_id = of_get_property(np, "reg", NULL); 2929 phy_interface_t phy_mode; 2930 struct phylink *phylink; 2931 struct mtk_mac *mac; 2932 int id, err; 2933 2934 if (!_id) { 2935 dev_err(eth->dev, "missing mac id\n"); 2936 return -EINVAL; 2937 } 2938 2939 id = be32_to_cpup(_id); 2940 if (id >= MTK_MAC_COUNT) { 2941 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2942 return -EINVAL; 2943 } 2944 2945 if (eth->netdev[id]) { 2946 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2947 return -EINVAL; 2948 } 2949 2950 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2951 if (!eth->netdev[id]) { 2952 dev_err(eth->dev, "alloc_etherdev failed\n"); 2953 return -ENOMEM; 2954 } 2955 mac = netdev_priv(eth->netdev[id]); 2956 eth->mac[id] = mac; 2957 mac->id = id; 2958 mac->hw = eth; 2959 mac->of_node = np; 2960 2961 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2962 mac->hwlro_ip_cnt = 0; 2963 2964 mac->hw_stats = devm_kzalloc(eth->dev, 2965 sizeof(*mac->hw_stats), 2966 GFP_KERNEL); 2967 if (!mac->hw_stats) { 2968 dev_err(eth->dev, "failed to allocate counter memory\n"); 2969 err = -ENOMEM; 2970 goto free_netdev; 2971 } 2972 spin_lock_init(&mac->hw_stats->stats_lock); 2973 u64_stats_init(&mac->hw_stats->syncp); 2974 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2975 2976 /* phylink create */ 2977 err = of_get_phy_mode(np, &phy_mode); 2978 if (err) { 2979 dev_err(eth->dev, "incorrect phy-mode\n"); 2980 goto free_netdev; 2981 } 2982 2983 /* mac config is not set */ 2984 mac->interface = PHY_INTERFACE_MODE_NA; 2985 mac->mode = MLO_AN_PHY; 2986 mac->speed = SPEED_UNKNOWN; 2987 2988 mac->phylink_config.dev = ð->netdev[id]->dev; 2989 mac->phylink_config.type = PHYLINK_NETDEV; 2990 /* This driver makes use of state->speed/state->duplex in 2991 * mac_config 2992 */ 2993 mac->phylink_config.legacy_pre_march2020 = true; 2994 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2995 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 2996 2997 __set_bit(PHY_INTERFACE_MODE_MII, 2998 mac->phylink_config.supported_interfaces); 2999 __set_bit(PHY_INTERFACE_MODE_GMII, 3000 mac->phylink_config.supported_interfaces); 3001 3002 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 3003 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 3004 3005 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 3006 __set_bit(PHY_INTERFACE_MODE_TRGMII, 3007 mac->phylink_config.supported_interfaces); 3008 3009 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 3010 __set_bit(PHY_INTERFACE_MODE_SGMII, 3011 mac->phylink_config.supported_interfaces); 3012 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 3013 mac->phylink_config.supported_interfaces); 3014 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 3015 mac->phylink_config.supported_interfaces); 3016 } 3017 3018 phylink = phylink_create(&mac->phylink_config, 3019 of_fwnode_handle(mac->of_node), 3020 phy_mode, &mtk_phylink_ops); 3021 if (IS_ERR(phylink)) { 3022 err = PTR_ERR(phylink); 3023 goto free_netdev; 3024 } 3025 3026 mac->phylink = phylink; 3027 3028 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 3029 eth->netdev[id]->watchdog_timeo = 5 * HZ; 3030 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 3031 eth->netdev[id]->base_addr = (unsigned long)eth->base; 3032 3033 eth->netdev[id]->hw_features = eth->soc->hw_features; 3034 if (eth->hwlro) 3035 eth->netdev[id]->hw_features |= NETIF_F_LRO; 3036 3037 eth->netdev[id]->vlan_features = eth->soc->hw_features & 3038 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 3039 eth->netdev[id]->features |= eth->soc->hw_features; 3040 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 3041 3042 eth->netdev[id]->irq = eth->irq[0]; 3043 eth->netdev[id]->dev.of_node = np; 3044 3045 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3046 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 3047 else 3048 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 3049 3050 return 0; 3051 3052 free_netdev: 3053 free_netdev(eth->netdev[id]); 3054 return err; 3055 } 3056 3057 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 3058 { 3059 struct net_device *dev, *tmp; 3060 LIST_HEAD(dev_list); 3061 int i; 3062 3063 rtnl_lock(); 3064 3065 for (i = 0; i < MTK_MAC_COUNT; i++) { 3066 dev = eth->netdev[i]; 3067 3068 if (!dev || !(dev->flags & IFF_UP)) 3069 continue; 3070 3071 list_add_tail(&dev->close_list, &dev_list); 3072 } 3073 3074 dev_close_many(&dev_list, false); 3075 3076 eth->dma_dev = dma_dev; 3077 3078 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 3079 list_del_init(&dev->close_list); 3080 dev_open(dev, NULL); 3081 } 3082 3083 rtnl_unlock(); 3084 } 3085 3086 static int mtk_probe(struct platform_device *pdev) 3087 { 3088 struct device_node *mac_np; 3089 struct mtk_eth *eth; 3090 int err, i; 3091 3092 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 3093 if (!eth) 3094 return -ENOMEM; 3095 3096 eth->soc = of_device_get_match_data(&pdev->dev); 3097 3098 eth->dev = &pdev->dev; 3099 eth->dma_dev = &pdev->dev; 3100 eth->base = devm_platform_ioremap_resource(pdev, 0); 3101 if (IS_ERR(eth->base)) 3102 return PTR_ERR(eth->base); 3103 3104 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3105 eth->tx_int_mask_reg = MTK_QDMA_INT_MASK; 3106 eth->tx_int_status_reg = MTK_QDMA_INT_STATUS; 3107 } else { 3108 eth->tx_int_mask_reg = MTK_PDMA_INT_MASK; 3109 eth->tx_int_status_reg = MTK_PDMA_INT_STATUS; 3110 } 3111 3112 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3113 eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA; 3114 eth->ip_align = NET_IP_ALIGN; 3115 } else { 3116 eth->rx_dma_l4_valid = RX_DMA_L4_VALID; 3117 } 3118 3119 spin_lock_init(ð->page_lock); 3120 spin_lock_init(ð->tx_irq_lock); 3121 spin_lock_init(ð->rx_irq_lock); 3122 spin_lock_init(ð->dim_lock); 3123 3124 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3125 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 3126 3127 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3128 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 3129 3130 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3131 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3132 "mediatek,ethsys"); 3133 if (IS_ERR(eth->ethsys)) { 3134 dev_err(&pdev->dev, "no ethsys regmap found\n"); 3135 return PTR_ERR(eth->ethsys); 3136 } 3137 } 3138 3139 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 3140 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3141 "mediatek,infracfg"); 3142 if (IS_ERR(eth->infra)) { 3143 dev_err(&pdev->dev, "no infracfg regmap found\n"); 3144 return PTR_ERR(eth->infra); 3145 } 3146 } 3147 3148 if (of_dma_is_coherent(pdev->dev.of_node)) { 3149 struct regmap *cci; 3150 3151 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3152 "cci-control-port"); 3153 /* enable CPU/bus coherency */ 3154 if (!IS_ERR(cci)) 3155 regmap_write(cci, 0, 3); 3156 } 3157 3158 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 3159 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 3160 GFP_KERNEL); 3161 if (!eth->sgmii) 3162 return -ENOMEM; 3163 3164 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 3165 eth->soc->ana_rgc3); 3166 3167 if (err) 3168 return err; 3169 } 3170 3171 if (eth->soc->required_pctl) { 3172 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3173 "mediatek,pctl"); 3174 if (IS_ERR(eth->pctl)) { 3175 dev_err(&pdev->dev, "no pctl regmap found\n"); 3176 return PTR_ERR(eth->pctl); 3177 } 3178 } 3179 3180 for (i = 0;; i++) { 3181 struct device_node *np = of_parse_phandle(pdev->dev.of_node, 3182 "mediatek,wed", i); 3183 static const u32 wdma_regs[] = { 3184 MTK_WDMA0_BASE, 3185 MTK_WDMA1_BASE 3186 }; 3187 void __iomem *wdma; 3188 3189 if (!np || i >= ARRAY_SIZE(wdma_regs)) 3190 break; 3191 3192 wdma = eth->base + wdma_regs[i]; 3193 mtk_wed_add_hw(np, eth, wdma, i); 3194 } 3195 3196 for (i = 0; i < 3; i++) { 3197 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 3198 eth->irq[i] = eth->irq[0]; 3199 else 3200 eth->irq[i] = platform_get_irq(pdev, i); 3201 if (eth->irq[i] < 0) { 3202 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 3203 return -ENXIO; 3204 } 3205 } 3206 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 3207 eth->clks[i] = devm_clk_get(eth->dev, 3208 mtk_clks_source_name[i]); 3209 if (IS_ERR(eth->clks[i])) { 3210 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 3211 return -EPROBE_DEFER; 3212 if (eth->soc->required_clks & BIT(i)) { 3213 dev_err(&pdev->dev, "clock %s not found\n", 3214 mtk_clks_source_name[i]); 3215 return -EINVAL; 3216 } 3217 eth->clks[i] = NULL; 3218 } 3219 } 3220 3221 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 3222 INIT_WORK(ð->pending_work, mtk_pending_work); 3223 3224 err = mtk_hw_init(eth); 3225 if (err) 3226 return err; 3227 3228 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 3229 3230 for_each_child_of_node(pdev->dev.of_node, mac_np) { 3231 if (!of_device_is_compatible(mac_np, 3232 "mediatek,eth-mac")) 3233 continue; 3234 3235 if (!of_device_is_available(mac_np)) 3236 continue; 3237 3238 err = mtk_add_mac(eth, mac_np); 3239 if (err) { 3240 of_node_put(mac_np); 3241 goto err_deinit_hw; 3242 } 3243 } 3244 3245 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 3246 err = devm_request_irq(eth->dev, eth->irq[0], 3247 mtk_handle_irq, 0, 3248 dev_name(eth->dev), eth); 3249 } else { 3250 err = devm_request_irq(eth->dev, eth->irq[1], 3251 mtk_handle_irq_tx, 0, 3252 dev_name(eth->dev), eth); 3253 if (err) 3254 goto err_free_dev; 3255 3256 err = devm_request_irq(eth->dev, eth->irq[2], 3257 mtk_handle_irq_rx, 0, 3258 dev_name(eth->dev), eth); 3259 } 3260 if (err) 3261 goto err_free_dev; 3262 3263 /* No MT7628/88 support yet */ 3264 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3265 err = mtk_mdio_init(eth); 3266 if (err) 3267 goto err_free_dev; 3268 } 3269 3270 if (eth->soc->offload_version) { 3271 eth->ppe = mtk_ppe_init(eth, eth->base + MTK_ETH_PPE_BASE, 2); 3272 if (!eth->ppe) { 3273 err = -ENOMEM; 3274 goto err_free_dev; 3275 } 3276 3277 err = mtk_eth_offload_init(eth); 3278 if (err) 3279 goto err_free_dev; 3280 } 3281 3282 for (i = 0; i < MTK_MAX_DEVS; i++) { 3283 if (!eth->netdev[i]) 3284 continue; 3285 3286 err = register_netdev(eth->netdev[i]); 3287 if (err) { 3288 dev_err(eth->dev, "error bringing up device\n"); 3289 goto err_deinit_mdio; 3290 } else 3291 netif_info(eth, probe, eth->netdev[i], 3292 "mediatek frame engine at 0x%08lx, irq %d\n", 3293 eth->netdev[i]->base_addr, eth->irq[0]); 3294 } 3295 3296 /* we run 2 devices on the same DMA ring so we need a dummy device 3297 * for NAPI to work 3298 */ 3299 init_dummy_netdev(ð->dummy_dev); 3300 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 3301 NAPI_POLL_WEIGHT); 3302 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 3303 NAPI_POLL_WEIGHT); 3304 3305 platform_set_drvdata(pdev, eth); 3306 3307 return 0; 3308 3309 err_deinit_mdio: 3310 mtk_mdio_cleanup(eth); 3311 err_free_dev: 3312 mtk_free_dev(eth); 3313 err_deinit_hw: 3314 mtk_hw_deinit(eth); 3315 3316 return err; 3317 } 3318 3319 static int mtk_remove(struct platform_device *pdev) 3320 { 3321 struct mtk_eth *eth = platform_get_drvdata(pdev); 3322 struct mtk_mac *mac; 3323 int i; 3324 3325 /* stop all devices to make sure that dma is properly shut down */ 3326 for (i = 0; i < MTK_MAC_COUNT; i++) { 3327 if (!eth->netdev[i]) 3328 continue; 3329 mtk_stop(eth->netdev[i]); 3330 mac = netdev_priv(eth->netdev[i]); 3331 phylink_disconnect_phy(mac->phylink); 3332 } 3333 3334 mtk_hw_deinit(eth); 3335 3336 netif_napi_del(ð->tx_napi); 3337 netif_napi_del(ð->rx_napi); 3338 mtk_cleanup(eth); 3339 mtk_mdio_cleanup(eth); 3340 3341 return 0; 3342 } 3343 3344 static const struct mtk_soc_data mt2701_data = { 3345 .caps = MT7623_CAPS | MTK_HWLRO, 3346 .hw_features = MTK_HW_FEATURES, 3347 .required_clks = MT7623_CLKS_BITMAP, 3348 .required_pctl = true, 3349 }; 3350 3351 static const struct mtk_soc_data mt7621_data = { 3352 .caps = MT7621_CAPS, 3353 .hw_features = MTK_HW_FEATURES, 3354 .required_clks = MT7621_CLKS_BITMAP, 3355 .required_pctl = false, 3356 .offload_version = 2, 3357 }; 3358 3359 static const struct mtk_soc_data mt7622_data = { 3360 .ana_rgc3 = 0x2028, 3361 .caps = MT7622_CAPS | MTK_HWLRO, 3362 .hw_features = MTK_HW_FEATURES, 3363 .required_clks = MT7622_CLKS_BITMAP, 3364 .required_pctl = false, 3365 .offload_version = 2, 3366 }; 3367 3368 static const struct mtk_soc_data mt7623_data = { 3369 .caps = MT7623_CAPS | MTK_HWLRO, 3370 .hw_features = MTK_HW_FEATURES, 3371 .required_clks = MT7623_CLKS_BITMAP, 3372 .required_pctl = true, 3373 .offload_version = 2, 3374 }; 3375 3376 static const struct mtk_soc_data mt7629_data = { 3377 .ana_rgc3 = 0x128, 3378 .caps = MT7629_CAPS | MTK_HWLRO, 3379 .hw_features = MTK_HW_FEATURES, 3380 .required_clks = MT7629_CLKS_BITMAP, 3381 .required_pctl = false, 3382 }; 3383 3384 static const struct mtk_soc_data rt5350_data = { 3385 .caps = MT7628_CAPS, 3386 .hw_features = MTK_HW_FEATURES_MT7628, 3387 .required_clks = MT7628_CLKS_BITMAP, 3388 .required_pctl = false, 3389 }; 3390 3391 const struct of_device_id of_mtk_match[] = { 3392 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 3393 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 3394 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 3395 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 3396 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 3397 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 3398 {}, 3399 }; 3400 MODULE_DEVICE_TABLE(of, of_mtk_match); 3401 3402 static struct platform_driver mtk_driver = { 3403 .probe = mtk_probe, 3404 .remove = mtk_remove, 3405 .driver = { 3406 .name = "mtk_soc_eth", 3407 .of_match_table = of_mtk_match, 3408 }, 3409 }; 3410 3411 module_platform_driver(mtk_driver); 3412 3413 MODULE_LICENSE("GPL"); 3414 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 3415 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 3416