1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #include <linux/of_device.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/regmap.h> 20 #include <linux/clk.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/if_vlan.h> 23 #include <linux/reset.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 27 #include "mtk_eth_soc.h" 28 29 static int mtk_msg_level = -1; 30 module_param_named(msg_level, mtk_msg_level, int, 0); 31 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 32 33 #define MTK_ETHTOOL_STAT(x) { #x, \ 34 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 35 36 /* strings used by ethtool */ 37 static const struct mtk_ethtool_stats { 38 char str[ETH_GSTRING_LEN]; 39 u32 offset; 40 } mtk_ethtool_stats[] = { 41 MTK_ETHTOOL_STAT(tx_bytes), 42 MTK_ETHTOOL_STAT(tx_packets), 43 MTK_ETHTOOL_STAT(tx_skip), 44 MTK_ETHTOOL_STAT(tx_collisions), 45 MTK_ETHTOOL_STAT(rx_bytes), 46 MTK_ETHTOOL_STAT(rx_packets), 47 MTK_ETHTOOL_STAT(rx_overflow), 48 MTK_ETHTOOL_STAT(rx_fcs_errors), 49 MTK_ETHTOOL_STAT(rx_short_errors), 50 MTK_ETHTOOL_STAT(rx_long_errors), 51 MTK_ETHTOOL_STAT(rx_checksum_errors), 52 MTK_ETHTOOL_STAT(rx_flow_control_packets), 53 }; 54 55 static const char * const mtk_clks_source_name[] = { 56 "ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m", 57 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" 58 }; 59 60 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 61 { 62 __raw_writel(val, eth->base + reg); 63 } 64 65 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 66 { 67 return __raw_readl(eth->base + reg); 68 } 69 70 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 71 { 72 unsigned long t_start = jiffies; 73 74 while (1) { 75 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 76 return 0; 77 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 78 break; 79 usleep_range(10, 20); 80 } 81 82 dev_err(eth->dev, "mdio: MDIO timeout\n"); 83 return -1; 84 } 85 86 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 87 u32 phy_register, u32 write_data) 88 { 89 if (mtk_mdio_busy_wait(eth)) 90 return -1; 91 92 write_data &= 0xffff; 93 94 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 95 (phy_register << PHY_IAC_REG_SHIFT) | 96 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 97 MTK_PHY_IAC); 98 99 if (mtk_mdio_busy_wait(eth)) 100 return -1; 101 102 return 0; 103 } 104 105 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 106 { 107 u32 d; 108 109 if (mtk_mdio_busy_wait(eth)) 110 return 0xffff; 111 112 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 113 (phy_reg << PHY_IAC_REG_SHIFT) | 114 (phy_addr << PHY_IAC_ADDR_SHIFT), 115 MTK_PHY_IAC); 116 117 if (mtk_mdio_busy_wait(eth)) 118 return 0xffff; 119 120 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 121 122 return d; 123 } 124 125 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 126 int phy_reg, u16 val) 127 { 128 struct mtk_eth *eth = bus->priv; 129 130 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 131 } 132 133 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 134 { 135 struct mtk_eth *eth = bus->priv; 136 137 return _mtk_mdio_read(eth, phy_addr, phy_reg); 138 } 139 140 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 141 { 142 u32 val; 143 int ret; 144 145 val = (speed == SPEED_1000) ? 146 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 147 mtk_w32(eth, val, INTF_MODE); 148 149 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 150 ETHSYS_TRGMII_CLK_SEL362_5, 151 ETHSYS_TRGMII_CLK_SEL362_5); 152 153 val = (speed == SPEED_1000) ? 250000000 : 500000000; 154 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 155 if (ret) 156 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 157 158 val = (speed == SPEED_1000) ? 159 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 160 mtk_w32(eth, val, TRGMII_RCK_CTRL); 161 162 val = (speed == SPEED_1000) ? 163 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 164 mtk_w32(eth, val, TRGMII_TCK_CTRL); 165 } 166 167 static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id) 168 { 169 u32 val; 170 171 /* Setup the link timer and QPHY power up inside SGMIISYS */ 172 regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER, 173 SGMII_LINK_TIMER_DEFAULT); 174 175 regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val); 176 val |= SGMII_REMOTE_FAULT_DIS; 177 regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val); 178 179 regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val); 180 val |= SGMII_AN_RESTART; 181 regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val); 182 183 regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val); 184 val &= ~SGMII_PHYA_PWD; 185 regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val); 186 187 /* Determine MUX for which GMAC uses the SGMII interface */ 188 if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) { 189 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 190 val &= ~SYSCFG0_SGMII_MASK; 191 val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2; 192 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 193 194 dev_info(eth->dev, "setup shared sgmii for gmac=%d\n", 195 mac_id); 196 } 197 198 /* Setup the GMAC1 going through SGMII path when SoC also support 199 * ESW on GMAC1 200 */ 201 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) && 202 !mac_id) { 203 mtk_w32(eth, 0, MTK_MAC_MISC); 204 dev_info(eth->dev, "setup gmac1 going through sgmii"); 205 } 206 } 207 208 static void mtk_phy_link_adjust(struct net_device *dev) 209 { 210 struct mtk_mac *mac = netdev_priv(dev); 211 u16 lcl_adv = 0, rmt_adv = 0; 212 u8 flowctrl; 213 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 214 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 215 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 216 MAC_MCR_BACKPR_EN; 217 218 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 219 return; 220 221 switch (dev->phydev->speed) { 222 case SPEED_1000: 223 mcr |= MAC_MCR_SPEED_1000; 224 break; 225 case SPEED_100: 226 mcr |= MAC_MCR_SPEED_100; 227 break; 228 }; 229 230 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 231 !mac->id && !mac->trgmii) 232 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed); 233 234 if (dev->phydev->link) 235 mcr |= MAC_MCR_FORCE_LINK; 236 237 if (dev->phydev->duplex) { 238 mcr |= MAC_MCR_FORCE_DPX; 239 240 if (dev->phydev->pause) 241 rmt_adv = LPA_PAUSE_CAP; 242 if (dev->phydev->asym_pause) 243 rmt_adv |= LPA_PAUSE_ASYM; 244 245 if (dev->phydev->advertising & ADVERTISED_Pause) 246 lcl_adv |= ADVERTISE_PAUSE_CAP; 247 if (dev->phydev->advertising & ADVERTISED_Asym_Pause) 248 lcl_adv |= ADVERTISE_PAUSE_ASYM; 249 250 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 251 252 if (flowctrl & FLOW_CTRL_TX) 253 mcr |= MAC_MCR_FORCE_TX_FC; 254 if (flowctrl & FLOW_CTRL_RX) 255 mcr |= MAC_MCR_FORCE_RX_FC; 256 257 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 258 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 259 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 260 } 261 262 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 263 264 if (dev->phydev->link) 265 netif_carrier_on(dev); 266 else 267 netif_carrier_off(dev); 268 269 if (!of_phy_is_fixed_link(mac->of_node)) 270 phy_print_status(dev->phydev); 271 } 272 273 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 274 struct device_node *phy_node) 275 { 276 struct phy_device *phydev; 277 int phy_mode; 278 279 phy_mode = of_get_phy_mode(phy_node); 280 if (phy_mode < 0) { 281 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 282 return -EINVAL; 283 } 284 285 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 286 mtk_phy_link_adjust, 0, phy_mode); 287 if (!phydev) { 288 dev_err(eth->dev, "could not connect to PHY\n"); 289 return -ENODEV; 290 } 291 292 dev_info(eth->dev, 293 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 294 mac->id, phydev_name(phydev), phydev->phy_id, 295 phydev->drv->name); 296 297 return 0; 298 } 299 300 static int mtk_phy_connect(struct net_device *dev) 301 { 302 struct mtk_mac *mac = netdev_priv(dev); 303 struct mtk_eth *eth; 304 struct device_node *np; 305 u32 val; 306 307 eth = mac->hw; 308 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 309 if (!np && of_phy_is_fixed_link(mac->of_node)) 310 if (!of_phy_register_fixed_link(mac->of_node)) 311 np = of_node_get(mac->of_node); 312 if (!np) 313 return -ENODEV; 314 315 mac->ge_mode = 0; 316 switch (of_get_phy_mode(np)) { 317 case PHY_INTERFACE_MODE_TRGMII: 318 mac->trgmii = true; 319 case PHY_INTERFACE_MODE_RGMII_TXID: 320 case PHY_INTERFACE_MODE_RGMII_RXID: 321 case PHY_INTERFACE_MODE_RGMII_ID: 322 case PHY_INTERFACE_MODE_RGMII: 323 break; 324 case PHY_INTERFACE_MODE_SGMII: 325 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) 326 mtk_gmac_sgmii_hw_setup(eth, mac->id); 327 break; 328 case PHY_INTERFACE_MODE_MII: 329 mac->ge_mode = 1; 330 break; 331 case PHY_INTERFACE_MODE_REVMII: 332 mac->ge_mode = 2; 333 break; 334 case PHY_INTERFACE_MODE_RMII: 335 if (!mac->id) 336 goto err_phy; 337 mac->ge_mode = 3; 338 break; 339 default: 340 goto err_phy; 341 } 342 343 /* put the gmac into the right mode */ 344 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 345 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 346 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id); 347 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 348 349 /* couple phydev to net_device */ 350 if (mtk_phy_connect_node(eth, mac, np)) 351 goto err_phy; 352 353 dev->phydev->autoneg = AUTONEG_ENABLE; 354 dev->phydev->speed = 0; 355 dev->phydev->duplex = 0; 356 357 if (of_phy_is_fixed_link(mac->of_node)) 358 dev->phydev->supported |= 359 SUPPORTED_Pause | SUPPORTED_Asym_Pause; 360 361 dev->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause | 362 SUPPORTED_Asym_Pause; 363 dev->phydev->advertising = dev->phydev->supported | 364 ADVERTISED_Autoneg; 365 phy_start_aneg(dev->phydev); 366 367 of_node_put(np); 368 369 return 0; 370 371 err_phy: 372 if (of_phy_is_fixed_link(mac->of_node)) 373 of_phy_deregister_fixed_link(mac->of_node); 374 of_node_put(np); 375 dev_err(eth->dev, "%s: invalid phy\n", __func__); 376 return -EINVAL; 377 } 378 379 static int mtk_mdio_init(struct mtk_eth *eth) 380 { 381 struct device_node *mii_np; 382 int ret; 383 384 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 385 if (!mii_np) { 386 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 387 return -ENODEV; 388 } 389 390 if (!of_device_is_available(mii_np)) { 391 ret = -ENODEV; 392 goto err_put_node; 393 } 394 395 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 396 if (!eth->mii_bus) { 397 ret = -ENOMEM; 398 goto err_put_node; 399 } 400 401 eth->mii_bus->name = "mdio"; 402 eth->mii_bus->read = mtk_mdio_read; 403 eth->mii_bus->write = mtk_mdio_write; 404 eth->mii_bus->priv = eth; 405 eth->mii_bus->parent = eth->dev; 406 407 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name); 408 ret = of_mdiobus_register(eth->mii_bus, mii_np); 409 410 err_put_node: 411 of_node_put(mii_np); 412 return ret; 413 } 414 415 static void mtk_mdio_cleanup(struct mtk_eth *eth) 416 { 417 if (!eth->mii_bus) 418 return; 419 420 mdiobus_unregister(eth->mii_bus); 421 } 422 423 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 424 { 425 unsigned long flags; 426 u32 val; 427 428 spin_lock_irqsave(ð->tx_irq_lock, flags); 429 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 430 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); 431 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 432 } 433 434 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 435 { 436 unsigned long flags; 437 u32 val; 438 439 spin_lock_irqsave(ð->tx_irq_lock, flags); 440 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 441 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); 442 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 443 } 444 445 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 446 { 447 unsigned long flags; 448 u32 val; 449 450 spin_lock_irqsave(ð->rx_irq_lock, flags); 451 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 452 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 453 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 454 } 455 456 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 457 { 458 unsigned long flags; 459 u32 val; 460 461 spin_lock_irqsave(ð->rx_irq_lock, flags); 462 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 463 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 464 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 465 } 466 467 static int mtk_set_mac_address(struct net_device *dev, void *p) 468 { 469 int ret = eth_mac_addr(dev, p); 470 struct mtk_mac *mac = netdev_priv(dev); 471 const char *macaddr = dev->dev_addr; 472 473 if (ret) 474 return ret; 475 476 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 477 return -EBUSY; 478 479 spin_lock_bh(&mac->hw->page_lock); 480 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 481 MTK_GDMA_MAC_ADRH(mac->id)); 482 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 483 (macaddr[4] << 8) | macaddr[5], 484 MTK_GDMA_MAC_ADRL(mac->id)); 485 spin_unlock_bh(&mac->hw->page_lock); 486 487 return 0; 488 } 489 490 void mtk_stats_update_mac(struct mtk_mac *mac) 491 { 492 struct mtk_hw_stats *hw_stats = mac->hw_stats; 493 unsigned int base = MTK_GDM1_TX_GBCNT; 494 u64 stats; 495 496 base += hw_stats->reg_offset; 497 498 u64_stats_update_begin(&hw_stats->syncp); 499 500 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 501 stats = mtk_r32(mac->hw, base + 0x04); 502 if (stats) 503 hw_stats->rx_bytes += (stats << 32); 504 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 505 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 506 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 507 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 508 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 509 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 510 hw_stats->rx_flow_control_packets += 511 mtk_r32(mac->hw, base + 0x24); 512 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 513 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 514 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 515 stats = mtk_r32(mac->hw, base + 0x34); 516 if (stats) 517 hw_stats->tx_bytes += (stats << 32); 518 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 519 u64_stats_update_end(&hw_stats->syncp); 520 } 521 522 static void mtk_stats_update(struct mtk_eth *eth) 523 { 524 int i; 525 526 for (i = 0; i < MTK_MAC_COUNT; i++) { 527 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 528 continue; 529 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 530 mtk_stats_update_mac(eth->mac[i]); 531 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 532 } 533 } 534 } 535 536 static void mtk_get_stats64(struct net_device *dev, 537 struct rtnl_link_stats64 *storage) 538 { 539 struct mtk_mac *mac = netdev_priv(dev); 540 struct mtk_hw_stats *hw_stats = mac->hw_stats; 541 unsigned int start; 542 543 if (netif_running(dev) && netif_device_present(dev)) { 544 if (spin_trylock_bh(&hw_stats->stats_lock)) { 545 mtk_stats_update_mac(mac); 546 spin_unlock_bh(&hw_stats->stats_lock); 547 } 548 } 549 550 do { 551 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 552 storage->rx_packets = hw_stats->rx_packets; 553 storage->tx_packets = hw_stats->tx_packets; 554 storage->rx_bytes = hw_stats->rx_bytes; 555 storage->tx_bytes = hw_stats->tx_bytes; 556 storage->collisions = hw_stats->tx_collisions; 557 storage->rx_length_errors = hw_stats->rx_short_errors + 558 hw_stats->rx_long_errors; 559 storage->rx_over_errors = hw_stats->rx_overflow; 560 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 561 storage->rx_errors = hw_stats->rx_checksum_errors; 562 storage->tx_aborted_errors = hw_stats->tx_skip; 563 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 564 565 storage->tx_errors = dev->stats.tx_errors; 566 storage->rx_dropped = dev->stats.rx_dropped; 567 storage->tx_dropped = dev->stats.tx_dropped; 568 } 569 570 static inline int mtk_max_frag_size(int mtu) 571 { 572 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 573 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 574 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 575 576 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 577 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 578 } 579 580 static inline int mtk_max_buf_size(int frag_size) 581 { 582 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 583 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 584 585 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 586 587 return buf_size; 588 } 589 590 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 591 struct mtk_rx_dma *dma_rxd) 592 { 593 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 594 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 595 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 596 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 597 } 598 599 /* the qdma core needs scratch memory to be setup */ 600 static int mtk_init_fq_dma(struct mtk_eth *eth) 601 { 602 dma_addr_t phy_ring_tail; 603 int cnt = MTK_DMA_SIZE; 604 dma_addr_t dma_addr; 605 int i; 606 607 eth->scratch_ring = dma_alloc_coherent(eth->dev, 608 cnt * sizeof(struct mtk_tx_dma), 609 ð->phy_scratch_ring, 610 GFP_ATOMIC | __GFP_ZERO); 611 if (unlikely(!eth->scratch_ring)) 612 return -ENOMEM; 613 614 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 615 GFP_KERNEL); 616 if (unlikely(!eth->scratch_head)) 617 return -ENOMEM; 618 619 dma_addr = dma_map_single(eth->dev, 620 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 621 DMA_FROM_DEVICE); 622 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 623 return -ENOMEM; 624 625 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt); 626 phy_ring_tail = eth->phy_scratch_ring + 627 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 628 629 for (i = 0; i < cnt; i++) { 630 eth->scratch_ring[i].txd1 = 631 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 632 if (i < cnt - 1) 633 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 634 ((i + 1) * sizeof(struct mtk_tx_dma))); 635 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 636 } 637 638 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 639 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 640 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 641 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 642 643 return 0; 644 } 645 646 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 647 { 648 void *ret = ring->dma; 649 650 return ret + (desc - ring->phys); 651 } 652 653 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 654 struct mtk_tx_dma *txd) 655 { 656 int idx = txd - ring->dma; 657 658 return &ring->buf[idx]; 659 } 660 661 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 662 { 663 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 664 dma_unmap_single(eth->dev, 665 dma_unmap_addr(tx_buf, dma_addr0), 666 dma_unmap_len(tx_buf, dma_len0), 667 DMA_TO_DEVICE); 668 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 669 dma_unmap_page(eth->dev, 670 dma_unmap_addr(tx_buf, dma_addr0), 671 dma_unmap_len(tx_buf, dma_len0), 672 DMA_TO_DEVICE); 673 } 674 tx_buf->flags = 0; 675 if (tx_buf->skb && 676 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 677 dev_kfree_skb_any(tx_buf->skb); 678 tx_buf->skb = NULL; 679 } 680 681 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 682 int tx_num, struct mtk_tx_ring *ring, bool gso) 683 { 684 struct mtk_mac *mac = netdev_priv(dev); 685 struct mtk_eth *eth = mac->hw; 686 struct mtk_tx_dma *itxd, *txd; 687 struct mtk_tx_buf *itx_buf, *tx_buf; 688 dma_addr_t mapped_addr; 689 unsigned int nr_frags; 690 int i, n_desc = 1; 691 u32 txd4 = 0, fport; 692 693 itxd = ring->next_free; 694 if (itxd == ring->last_free) 695 return -ENOMEM; 696 697 /* set the forward port */ 698 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 699 txd4 |= fport; 700 701 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 702 memset(itx_buf, 0, sizeof(*itx_buf)); 703 704 if (gso) 705 txd4 |= TX_DMA_TSO; 706 707 /* TX Checksum offload */ 708 if (skb->ip_summed == CHECKSUM_PARTIAL) 709 txd4 |= TX_DMA_CHKSUM; 710 711 /* VLAN header offload */ 712 if (skb_vlan_tag_present(skb)) 713 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 714 715 mapped_addr = dma_map_single(eth->dev, skb->data, 716 skb_headlen(skb), DMA_TO_DEVICE); 717 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 718 return -ENOMEM; 719 720 WRITE_ONCE(itxd->txd1, mapped_addr); 721 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 722 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 723 MTK_TX_FLAGS_FPORT1; 724 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr); 725 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb)); 726 727 /* TX SG offload */ 728 txd = itxd; 729 nr_frags = skb_shinfo(skb)->nr_frags; 730 for (i = 0; i < nr_frags; i++) { 731 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 732 unsigned int offset = 0; 733 int frag_size = skb_frag_size(frag); 734 735 while (frag_size) { 736 bool last_frag = false; 737 unsigned int frag_map_size; 738 739 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 740 if (txd == ring->last_free) 741 goto err_dma; 742 743 n_desc++; 744 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 745 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 746 frag_map_size, 747 DMA_TO_DEVICE); 748 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 749 goto err_dma; 750 751 if (i == nr_frags - 1 && 752 (frag_size - frag_map_size) == 0) 753 last_frag = true; 754 755 WRITE_ONCE(txd->txd1, mapped_addr); 756 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 757 TX_DMA_PLEN0(frag_map_size) | 758 last_frag * TX_DMA_LS0)); 759 WRITE_ONCE(txd->txd4, fport); 760 761 tx_buf = mtk_desc_to_tx_buf(ring, txd); 762 memset(tx_buf, 0, sizeof(*tx_buf)); 763 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 764 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 765 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 766 MTK_TX_FLAGS_FPORT1; 767 768 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 769 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 770 frag_size -= frag_map_size; 771 offset += frag_map_size; 772 } 773 } 774 775 /* store skb to cleanup */ 776 itx_buf->skb = skb; 777 778 WRITE_ONCE(itxd->txd4, txd4); 779 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 780 (!nr_frags * TX_DMA_LS0))); 781 782 netdev_sent_queue(dev, skb->len); 783 skb_tx_timestamp(skb); 784 785 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 786 atomic_sub(n_desc, &ring->free_count); 787 788 /* make sure that all changes to the dma ring are flushed before we 789 * continue 790 */ 791 wmb(); 792 793 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more) 794 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 795 796 return 0; 797 798 err_dma: 799 do { 800 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 801 802 /* unmap dma */ 803 mtk_tx_unmap(eth, tx_buf); 804 805 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 806 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 807 } while (itxd != txd); 808 809 return -ENOMEM; 810 } 811 812 static inline int mtk_cal_txd_req(struct sk_buff *skb) 813 { 814 int i, nfrags; 815 struct skb_frag_struct *frag; 816 817 nfrags = 1; 818 if (skb_is_gso(skb)) { 819 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 820 frag = &skb_shinfo(skb)->frags[i]; 821 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); 822 } 823 } else { 824 nfrags += skb_shinfo(skb)->nr_frags; 825 } 826 827 return nfrags; 828 } 829 830 static int mtk_queue_stopped(struct mtk_eth *eth) 831 { 832 int i; 833 834 for (i = 0; i < MTK_MAC_COUNT; i++) { 835 if (!eth->netdev[i]) 836 continue; 837 if (netif_queue_stopped(eth->netdev[i])) 838 return 1; 839 } 840 841 return 0; 842 } 843 844 static void mtk_wake_queue(struct mtk_eth *eth) 845 { 846 int i; 847 848 for (i = 0; i < MTK_MAC_COUNT; i++) { 849 if (!eth->netdev[i]) 850 continue; 851 netif_wake_queue(eth->netdev[i]); 852 } 853 } 854 855 static void mtk_stop_queue(struct mtk_eth *eth) 856 { 857 int i; 858 859 for (i = 0; i < MTK_MAC_COUNT; i++) { 860 if (!eth->netdev[i]) 861 continue; 862 netif_stop_queue(eth->netdev[i]); 863 } 864 } 865 866 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 867 { 868 struct mtk_mac *mac = netdev_priv(dev); 869 struct mtk_eth *eth = mac->hw; 870 struct mtk_tx_ring *ring = ð->tx_ring; 871 struct net_device_stats *stats = &dev->stats; 872 bool gso = false; 873 int tx_num; 874 875 /* normally we can rely on the stack not calling this more than once, 876 * however we have 2 queues running on the same ring so we need to lock 877 * the ring access 878 */ 879 spin_lock(ð->page_lock); 880 881 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 882 goto drop; 883 884 tx_num = mtk_cal_txd_req(skb); 885 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 886 mtk_stop_queue(eth); 887 netif_err(eth, tx_queued, dev, 888 "Tx Ring full when queue awake!\n"); 889 spin_unlock(ð->page_lock); 890 return NETDEV_TX_BUSY; 891 } 892 893 /* TSO: fill MSS info in tcp checksum field */ 894 if (skb_is_gso(skb)) { 895 if (skb_cow_head(skb, 0)) { 896 netif_warn(eth, tx_err, dev, 897 "GSO expand head fail.\n"); 898 goto drop; 899 } 900 901 if (skb_shinfo(skb)->gso_type & 902 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 903 gso = true; 904 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 905 } 906 } 907 908 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 909 goto drop; 910 911 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 912 mtk_stop_queue(eth); 913 914 spin_unlock(ð->page_lock); 915 916 return NETDEV_TX_OK; 917 918 drop: 919 spin_unlock(ð->page_lock); 920 stats->tx_dropped++; 921 dev_kfree_skb_any(skb); 922 return NETDEV_TX_OK; 923 } 924 925 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 926 { 927 int i; 928 struct mtk_rx_ring *ring; 929 int idx; 930 931 if (!eth->hwlro) 932 return ð->rx_ring[0]; 933 934 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 935 ring = ð->rx_ring[i]; 936 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 937 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 938 ring->calc_idx_update = true; 939 return ring; 940 } 941 } 942 943 return NULL; 944 } 945 946 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 947 { 948 struct mtk_rx_ring *ring; 949 int i; 950 951 if (!eth->hwlro) { 952 ring = ð->rx_ring[0]; 953 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 954 } else { 955 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 956 ring = ð->rx_ring[i]; 957 if (ring->calc_idx_update) { 958 ring->calc_idx_update = false; 959 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 960 } 961 } 962 } 963 } 964 965 static int mtk_poll_rx(struct napi_struct *napi, int budget, 966 struct mtk_eth *eth) 967 { 968 struct mtk_rx_ring *ring; 969 int idx; 970 struct sk_buff *skb; 971 u8 *data, *new_data; 972 struct mtk_rx_dma *rxd, trxd; 973 int done = 0; 974 975 while (done < budget) { 976 struct net_device *netdev; 977 unsigned int pktlen; 978 dma_addr_t dma_addr; 979 int mac = 0; 980 981 ring = mtk_get_rx_ring(eth); 982 if (unlikely(!ring)) 983 goto rx_done; 984 985 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 986 rxd = &ring->dma[idx]; 987 data = ring->data[idx]; 988 989 mtk_rx_get_desc(&trxd, rxd); 990 if (!(trxd.rxd2 & RX_DMA_DONE)) 991 break; 992 993 /* find out which mac the packet come from. values start at 1 */ 994 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 995 RX_DMA_FPORT_MASK; 996 mac--; 997 998 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 999 !eth->netdev[mac])) 1000 goto release_desc; 1001 1002 netdev = eth->netdev[mac]; 1003 1004 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1005 goto release_desc; 1006 1007 /* alloc new buffer */ 1008 new_data = napi_alloc_frag(ring->frag_size); 1009 if (unlikely(!new_data)) { 1010 netdev->stats.rx_dropped++; 1011 goto release_desc; 1012 } 1013 dma_addr = dma_map_single(eth->dev, 1014 new_data + NET_SKB_PAD, 1015 ring->buf_size, 1016 DMA_FROM_DEVICE); 1017 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 1018 skb_free_frag(new_data); 1019 netdev->stats.rx_dropped++; 1020 goto release_desc; 1021 } 1022 1023 /* receive data */ 1024 skb = build_skb(data, ring->frag_size); 1025 if (unlikely(!skb)) { 1026 skb_free_frag(new_data); 1027 netdev->stats.rx_dropped++; 1028 goto release_desc; 1029 } 1030 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1031 1032 dma_unmap_single(eth->dev, trxd.rxd1, 1033 ring->buf_size, DMA_FROM_DEVICE); 1034 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1035 skb->dev = netdev; 1036 skb_put(skb, pktlen); 1037 if (trxd.rxd4 & RX_DMA_L4_VALID) 1038 skb->ip_summed = CHECKSUM_UNNECESSARY; 1039 else 1040 skb_checksum_none_assert(skb); 1041 skb->protocol = eth_type_trans(skb, netdev); 1042 1043 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1044 RX_DMA_VID(trxd.rxd3)) 1045 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1046 RX_DMA_VID(trxd.rxd3)); 1047 skb_record_rx_queue(skb, 0); 1048 napi_gro_receive(napi, skb); 1049 1050 ring->data[idx] = new_data; 1051 rxd->rxd1 = (unsigned int)dma_addr; 1052 1053 release_desc: 1054 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1055 1056 ring->calc_idx = idx; 1057 1058 done++; 1059 } 1060 1061 rx_done: 1062 if (done) { 1063 /* make sure that all changes to the dma ring are flushed before 1064 * we continue 1065 */ 1066 wmb(); 1067 mtk_update_rx_cpu_idx(eth); 1068 } 1069 1070 return done; 1071 } 1072 1073 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1074 { 1075 struct mtk_tx_ring *ring = ð->tx_ring; 1076 struct mtk_tx_dma *desc; 1077 struct sk_buff *skb; 1078 struct mtk_tx_buf *tx_buf; 1079 unsigned int done[MTK_MAX_DEVS]; 1080 unsigned int bytes[MTK_MAX_DEVS]; 1081 u32 cpu, dma; 1082 int total = 0, i; 1083 1084 memset(done, 0, sizeof(done)); 1085 memset(bytes, 0, sizeof(bytes)); 1086 1087 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1088 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1089 1090 desc = mtk_qdma_phys_to_virt(ring, cpu); 1091 1092 while ((cpu != dma) && budget) { 1093 u32 next_cpu = desc->txd2; 1094 int mac = 0; 1095 1096 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1097 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1098 break; 1099 1100 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1101 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1102 mac = 1; 1103 1104 skb = tx_buf->skb; 1105 if (!skb) 1106 break; 1107 1108 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1109 bytes[mac] += skb->len; 1110 done[mac]++; 1111 budget--; 1112 } 1113 mtk_tx_unmap(eth, tx_buf); 1114 1115 ring->last_free = desc; 1116 atomic_inc(&ring->free_count); 1117 1118 cpu = next_cpu; 1119 } 1120 1121 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1122 1123 for (i = 0; i < MTK_MAC_COUNT; i++) { 1124 if (!eth->netdev[i] || !done[i]) 1125 continue; 1126 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1127 total += done[i]; 1128 } 1129 1130 if (mtk_queue_stopped(eth) && 1131 (atomic_read(&ring->free_count) > ring->thresh)) 1132 mtk_wake_queue(eth); 1133 1134 return total; 1135 } 1136 1137 static void mtk_handle_status_irq(struct mtk_eth *eth) 1138 { 1139 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1140 1141 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1142 mtk_stats_update(eth); 1143 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1144 MTK_INT_STATUS2); 1145 } 1146 } 1147 1148 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1149 { 1150 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1151 u32 status, mask; 1152 int tx_done = 0; 1153 1154 mtk_handle_status_irq(eth); 1155 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 1156 tx_done = mtk_poll_tx(eth, budget); 1157 1158 if (unlikely(netif_msg_intr(eth))) { 1159 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1160 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 1161 dev_info(eth->dev, 1162 "done tx %d, intr 0x%08x/0x%x\n", 1163 tx_done, status, mask); 1164 } 1165 1166 if (tx_done == budget) 1167 return budget; 1168 1169 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1170 if (status & MTK_TX_DONE_INT) 1171 return budget; 1172 1173 napi_complete(napi); 1174 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1175 1176 return tx_done; 1177 } 1178 1179 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1180 { 1181 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1182 u32 status, mask; 1183 int rx_done = 0; 1184 int remain_budget = budget; 1185 1186 mtk_handle_status_irq(eth); 1187 1188 poll_again: 1189 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1190 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1191 1192 if (unlikely(netif_msg_intr(eth))) { 1193 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1194 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1195 dev_info(eth->dev, 1196 "done rx %d, intr 0x%08x/0x%x\n", 1197 rx_done, status, mask); 1198 } 1199 if (rx_done == remain_budget) 1200 return budget; 1201 1202 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1203 if (status & MTK_RX_DONE_INT) { 1204 remain_budget -= rx_done; 1205 goto poll_again; 1206 } 1207 napi_complete(napi); 1208 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1209 1210 return rx_done + budget - remain_budget; 1211 } 1212 1213 static int mtk_tx_alloc(struct mtk_eth *eth) 1214 { 1215 struct mtk_tx_ring *ring = ð->tx_ring; 1216 int i, sz = sizeof(*ring->dma); 1217 1218 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1219 GFP_KERNEL); 1220 if (!ring->buf) 1221 goto no_tx_mem; 1222 1223 ring->dma = dma_alloc_coherent(eth->dev, 1224 MTK_DMA_SIZE * sz, 1225 &ring->phys, 1226 GFP_ATOMIC | __GFP_ZERO); 1227 if (!ring->dma) 1228 goto no_tx_mem; 1229 1230 memset(ring->dma, 0, MTK_DMA_SIZE * sz); 1231 for (i = 0; i < MTK_DMA_SIZE; i++) { 1232 int next = (i + 1) % MTK_DMA_SIZE; 1233 u32 next_ptr = ring->phys + next * sz; 1234 1235 ring->dma[i].txd2 = next_ptr; 1236 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1237 } 1238 1239 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1240 ring->next_free = &ring->dma[0]; 1241 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1242 ring->thresh = MAX_SKB_FRAGS; 1243 1244 /* make sure that all changes to the dma ring are flushed before we 1245 * continue 1246 */ 1247 wmb(); 1248 1249 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1250 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1251 mtk_w32(eth, 1252 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1253 MTK_QTX_CRX_PTR); 1254 mtk_w32(eth, 1255 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1256 MTK_QTX_DRX_PTR); 1257 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1258 1259 return 0; 1260 1261 no_tx_mem: 1262 return -ENOMEM; 1263 } 1264 1265 static void mtk_tx_clean(struct mtk_eth *eth) 1266 { 1267 struct mtk_tx_ring *ring = ð->tx_ring; 1268 int i; 1269 1270 if (ring->buf) { 1271 for (i = 0; i < MTK_DMA_SIZE; i++) 1272 mtk_tx_unmap(eth, &ring->buf[i]); 1273 kfree(ring->buf); 1274 ring->buf = NULL; 1275 } 1276 1277 if (ring->dma) { 1278 dma_free_coherent(eth->dev, 1279 MTK_DMA_SIZE * sizeof(*ring->dma), 1280 ring->dma, 1281 ring->phys); 1282 ring->dma = NULL; 1283 } 1284 } 1285 1286 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1287 { 1288 struct mtk_rx_ring *ring; 1289 int rx_data_len, rx_dma_size; 1290 int i; 1291 u32 offset = 0; 1292 1293 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1294 if (ring_no) 1295 return -EINVAL; 1296 ring = ð->rx_ring_qdma; 1297 offset = 0x1000; 1298 } else { 1299 ring = ð->rx_ring[ring_no]; 1300 } 1301 1302 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1303 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1304 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1305 } else { 1306 rx_data_len = ETH_DATA_LEN; 1307 rx_dma_size = MTK_DMA_SIZE; 1308 } 1309 1310 ring->frag_size = mtk_max_frag_size(rx_data_len); 1311 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1312 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1313 GFP_KERNEL); 1314 if (!ring->data) 1315 return -ENOMEM; 1316 1317 for (i = 0; i < rx_dma_size; i++) { 1318 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1319 if (!ring->data[i]) 1320 return -ENOMEM; 1321 } 1322 1323 ring->dma = dma_alloc_coherent(eth->dev, 1324 rx_dma_size * sizeof(*ring->dma), 1325 &ring->phys, 1326 GFP_ATOMIC | __GFP_ZERO); 1327 if (!ring->dma) 1328 return -ENOMEM; 1329 1330 for (i = 0; i < rx_dma_size; i++) { 1331 dma_addr_t dma_addr = dma_map_single(eth->dev, 1332 ring->data[i] + NET_SKB_PAD, 1333 ring->buf_size, 1334 DMA_FROM_DEVICE); 1335 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1336 return -ENOMEM; 1337 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1338 1339 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1340 } 1341 ring->dma_size = rx_dma_size; 1342 ring->calc_idx_update = false; 1343 ring->calc_idx = rx_dma_size - 1; 1344 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1345 /* make sure that all changes to the dma ring are flushed before we 1346 * continue 1347 */ 1348 wmb(); 1349 1350 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1351 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1352 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1353 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1354 1355 return 0; 1356 } 1357 1358 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1359 { 1360 int i; 1361 1362 if (ring->data && ring->dma) { 1363 for (i = 0; i < ring->dma_size; i++) { 1364 if (!ring->data[i]) 1365 continue; 1366 if (!ring->dma[i].rxd1) 1367 continue; 1368 dma_unmap_single(eth->dev, 1369 ring->dma[i].rxd1, 1370 ring->buf_size, 1371 DMA_FROM_DEVICE); 1372 skb_free_frag(ring->data[i]); 1373 } 1374 kfree(ring->data); 1375 ring->data = NULL; 1376 } 1377 1378 if (ring->dma) { 1379 dma_free_coherent(eth->dev, 1380 ring->dma_size * sizeof(*ring->dma), 1381 ring->dma, 1382 ring->phys); 1383 ring->dma = NULL; 1384 } 1385 } 1386 1387 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1388 { 1389 int i; 1390 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1391 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1392 1393 /* set LRO rings to auto-learn modes */ 1394 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1395 1396 /* validate LRO ring */ 1397 ring_ctrl_dw2 |= MTK_RING_VLD; 1398 1399 /* set AGE timer (unit: 20us) */ 1400 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1401 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1402 1403 /* set max AGG timer (unit: 20us) */ 1404 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1405 1406 /* set max LRO AGG count */ 1407 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1408 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1409 1410 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1411 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1412 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1413 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1414 } 1415 1416 /* IPv4 checksum update enable */ 1417 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1418 1419 /* switch priority comparison to packet count mode */ 1420 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1421 1422 /* bandwidth threshold setting */ 1423 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1424 1425 /* auto-learn score delta setting */ 1426 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1427 1428 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1429 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1430 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1431 1432 /* set HW LRO mode & the max aggregation count for rx packets */ 1433 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1434 1435 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1436 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1437 1438 /* enable HW LRO */ 1439 lro_ctrl_dw0 |= MTK_LRO_EN; 1440 1441 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1442 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1443 1444 return 0; 1445 } 1446 1447 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1448 { 1449 int i; 1450 u32 val; 1451 1452 /* relinquish lro rings, flush aggregated packets */ 1453 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1454 1455 /* wait for relinquishments done */ 1456 for (i = 0; i < 10; i++) { 1457 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1458 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1459 msleep(20); 1460 continue; 1461 } 1462 break; 1463 } 1464 1465 /* invalidate lro rings */ 1466 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1467 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1468 1469 /* disable HW LRO */ 1470 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1471 } 1472 1473 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1474 { 1475 u32 reg_val; 1476 1477 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1478 1479 /* invalidate the IP setting */ 1480 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1481 1482 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1483 1484 /* validate the IP setting */ 1485 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1486 } 1487 1488 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1489 { 1490 u32 reg_val; 1491 1492 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1493 1494 /* invalidate the IP setting */ 1495 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1496 1497 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1498 } 1499 1500 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1501 { 1502 int cnt = 0; 1503 int i; 1504 1505 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1506 if (mac->hwlro_ip[i]) 1507 cnt++; 1508 } 1509 1510 return cnt; 1511 } 1512 1513 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1514 struct ethtool_rxnfc *cmd) 1515 { 1516 struct ethtool_rx_flow_spec *fsp = 1517 (struct ethtool_rx_flow_spec *)&cmd->fs; 1518 struct mtk_mac *mac = netdev_priv(dev); 1519 struct mtk_eth *eth = mac->hw; 1520 int hwlro_idx; 1521 1522 if ((fsp->flow_type != TCP_V4_FLOW) || 1523 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1524 (fsp->location > 1)) 1525 return -EINVAL; 1526 1527 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1528 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1529 1530 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1531 1532 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1533 1534 return 0; 1535 } 1536 1537 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1538 struct ethtool_rxnfc *cmd) 1539 { 1540 struct ethtool_rx_flow_spec *fsp = 1541 (struct ethtool_rx_flow_spec *)&cmd->fs; 1542 struct mtk_mac *mac = netdev_priv(dev); 1543 struct mtk_eth *eth = mac->hw; 1544 int hwlro_idx; 1545 1546 if (fsp->location > 1) 1547 return -EINVAL; 1548 1549 mac->hwlro_ip[fsp->location] = 0; 1550 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1551 1552 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1553 1554 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1555 1556 return 0; 1557 } 1558 1559 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1560 { 1561 struct mtk_mac *mac = netdev_priv(dev); 1562 struct mtk_eth *eth = mac->hw; 1563 int i, hwlro_idx; 1564 1565 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1566 mac->hwlro_ip[i] = 0; 1567 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1568 1569 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1570 } 1571 1572 mac->hwlro_ip_cnt = 0; 1573 } 1574 1575 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1576 struct ethtool_rxnfc *cmd) 1577 { 1578 struct mtk_mac *mac = netdev_priv(dev); 1579 struct ethtool_rx_flow_spec *fsp = 1580 (struct ethtool_rx_flow_spec *)&cmd->fs; 1581 1582 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1583 fsp->flow_type = TCP_V4_FLOW; 1584 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1585 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1586 1587 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1588 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1589 fsp->h_u.tcp_ip4_spec.psrc = 0; 1590 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1591 fsp->h_u.tcp_ip4_spec.pdst = 0; 1592 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1593 fsp->h_u.tcp_ip4_spec.tos = 0; 1594 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1595 1596 return 0; 1597 } 1598 1599 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1600 struct ethtool_rxnfc *cmd, 1601 u32 *rule_locs) 1602 { 1603 struct mtk_mac *mac = netdev_priv(dev); 1604 int cnt = 0; 1605 int i; 1606 1607 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1608 if (mac->hwlro_ip[i]) { 1609 rule_locs[cnt] = i; 1610 cnt++; 1611 } 1612 } 1613 1614 cmd->rule_cnt = cnt; 1615 1616 return 0; 1617 } 1618 1619 static netdev_features_t mtk_fix_features(struct net_device *dev, 1620 netdev_features_t features) 1621 { 1622 if (!(features & NETIF_F_LRO)) { 1623 struct mtk_mac *mac = netdev_priv(dev); 1624 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1625 1626 if (ip_cnt) { 1627 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1628 1629 features |= NETIF_F_LRO; 1630 } 1631 } 1632 1633 return features; 1634 } 1635 1636 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1637 { 1638 int err = 0; 1639 1640 if (!((dev->features ^ features) & NETIF_F_LRO)) 1641 return 0; 1642 1643 if (!(features & NETIF_F_LRO)) 1644 mtk_hwlro_netdev_disable(dev); 1645 1646 return err; 1647 } 1648 1649 /* wait for DMA to finish whatever it is doing before we start using it again */ 1650 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1651 { 1652 unsigned long t_start = jiffies; 1653 1654 while (1) { 1655 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1656 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1657 return 0; 1658 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1659 break; 1660 } 1661 1662 dev_err(eth->dev, "DMA init timeout\n"); 1663 return -1; 1664 } 1665 1666 static int mtk_dma_init(struct mtk_eth *eth) 1667 { 1668 int err; 1669 u32 i; 1670 1671 if (mtk_dma_busy_wait(eth)) 1672 return -EBUSY; 1673 1674 /* QDMA needs scratch memory for internal reordering of the 1675 * descriptors 1676 */ 1677 err = mtk_init_fq_dma(eth); 1678 if (err) 1679 return err; 1680 1681 err = mtk_tx_alloc(eth); 1682 if (err) 1683 return err; 1684 1685 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 1686 if (err) 1687 return err; 1688 1689 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 1690 if (err) 1691 return err; 1692 1693 if (eth->hwlro) { 1694 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1695 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 1696 if (err) 1697 return err; 1698 } 1699 err = mtk_hwlro_rx_init(eth); 1700 if (err) 1701 return err; 1702 } 1703 1704 /* Enable random early drop and set drop threshold automatically */ 1705 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1706 MTK_QDMA_FC_THRES); 1707 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1708 1709 return 0; 1710 } 1711 1712 static void mtk_dma_free(struct mtk_eth *eth) 1713 { 1714 int i; 1715 1716 for (i = 0; i < MTK_MAC_COUNT; i++) 1717 if (eth->netdev[i]) 1718 netdev_reset_queue(eth->netdev[i]); 1719 if (eth->scratch_ring) { 1720 dma_free_coherent(eth->dev, 1721 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 1722 eth->scratch_ring, 1723 eth->phy_scratch_ring); 1724 eth->scratch_ring = NULL; 1725 eth->phy_scratch_ring = 0; 1726 } 1727 mtk_tx_clean(eth); 1728 mtk_rx_clean(eth, ð->rx_ring[0]); 1729 mtk_rx_clean(eth, ð->rx_ring_qdma); 1730 1731 if (eth->hwlro) { 1732 mtk_hwlro_rx_uninit(eth); 1733 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1734 mtk_rx_clean(eth, ð->rx_ring[i]); 1735 } 1736 1737 kfree(eth->scratch_head); 1738 } 1739 1740 static void mtk_tx_timeout(struct net_device *dev) 1741 { 1742 struct mtk_mac *mac = netdev_priv(dev); 1743 struct mtk_eth *eth = mac->hw; 1744 1745 eth->netdev[mac->id]->stats.tx_errors++; 1746 netif_err(eth, tx_err, dev, 1747 "transmit timed out\n"); 1748 schedule_work(ð->pending_work); 1749 } 1750 1751 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 1752 { 1753 struct mtk_eth *eth = _eth; 1754 1755 if (likely(napi_schedule_prep(ð->rx_napi))) { 1756 __napi_schedule(ð->rx_napi); 1757 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1758 } 1759 1760 return IRQ_HANDLED; 1761 } 1762 1763 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 1764 { 1765 struct mtk_eth *eth = _eth; 1766 1767 if (likely(napi_schedule_prep(ð->tx_napi))) { 1768 __napi_schedule(ð->tx_napi); 1769 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1770 } 1771 1772 return IRQ_HANDLED; 1773 } 1774 1775 #ifdef CONFIG_NET_POLL_CONTROLLER 1776 static void mtk_poll_controller(struct net_device *dev) 1777 { 1778 struct mtk_mac *mac = netdev_priv(dev); 1779 struct mtk_eth *eth = mac->hw; 1780 1781 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1782 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1783 mtk_handle_irq_rx(eth->irq[2], dev); 1784 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1785 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1786 } 1787 #endif 1788 1789 static int mtk_start_dma(struct mtk_eth *eth) 1790 { 1791 int err; 1792 1793 err = mtk_dma_init(eth); 1794 if (err) { 1795 mtk_dma_free(eth); 1796 return err; 1797 } 1798 1799 mtk_w32(eth, 1800 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 1801 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | 1802 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1803 MTK_RX_BT_32DWORDS, 1804 MTK_QDMA_GLO_CFG); 1805 1806 mtk_w32(eth, 1807 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1808 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 1809 MTK_PDMA_GLO_CFG); 1810 1811 return 0; 1812 } 1813 1814 static int mtk_open(struct net_device *dev) 1815 { 1816 struct mtk_mac *mac = netdev_priv(dev); 1817 struct mtk_eth *eth = mac->hw; 1818 1819 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1820 if (!refcount_read(ð->dma_refcnt)) { 1821 int err = mtk_start_dma(eth); 1822 1823 if (err) 1824 return err; 1825 1826 napi_enable(ð->tx_napi); 1827 napi_enable(ð->rx_napi); 1828 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1829 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1830 refcount_set(ð->dma_refcnt, 1); 1831 } 1832 else 1833 refcount_inc(ð->dma_refcnt); 1834 1835 phy_start(dev->phydev); 1836 netif_start_queue(dev); 1837 1838 return 0; 1839 } 1840 1841 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1842 { 1843 u32 val; 1844 int i; 1845 1846 /* stop the dma engine */ 1847 spin_lock_bh(ð->page_lock); 1848 val = mtk_r32(eth, glo_cfg); 1849 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1850 glo_cfg); 1851 spin_unlock_bh(ð->page_lock); 1852 1853 /* wait for dma stop */ 1854 for (i = 0; i < 10; i++) { 1855 val = mtk_r32(eth, glo_cfg); 1856 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1857 msleep(20); 1858 continue; 1859 } 1860 break; 1861 } 1862 } 1863 1864 static int mtk_stop(struct net_device *dev) 1865 { 1866 struct mtk_mac *mac = netdev_priv(dev); 1867 struct mtk_eth *eth = mac->hw; 1868 1869 netif_tx_disable(dev); 1870 phy_stop(dev->phydev); 1871 1872 /* only shutdown DMA if this is the last user */ 1873 if (!refcount_dec_and_test(ð->dma_refcnt)) 1874 return 0; 1875 1876 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1877 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1878 napi_disable(ð->tx_napi); 1879 napi_disable(ð->rx_napi); 1880 1881 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1882 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 1883 1884 mtk_dma_free(eth); 1885 1886 return 0; 1887 } 1888 1889 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 1890 { 1891 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1892 reset_bits, 1893 reset_bits); 1894 1895 usleep_range(1000, 1100); 1896 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1897 reset_bits, 1898 ~reset_bits); 1899 mdelay(10); 1900 } 1901 1902 static void mtk_clk_disable(struct mtk_eth *eth) 1903 { 1904 int clk; 1905 1906 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 1907 clk_disable_unprepare(eth->clks[clk]); 1908 } 1909 1910 static int mtk_clk_enable(struct mtk_eth *eth) 1911 { 1912 int clk, ret; 1913 1914 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 1915 ret = clk_prepare_enable(eth->clks[clk]); 1916 if (ret) 1917 goto err_disable_clks; 1918 } 1919 1920 return 0; 1921 1922 err_disable_clks: 1923 while (--clk >= 0) 1924 clk_disable_unprepare(eth->clks[clk]); 1925 1926 return ret; 1927 } 1928 1929 static int mtk_hw_init(struct mtk_eth *eth) 1930 { 1931 int i, val, ret; 1932 1933 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 1934 return 0; 1935 1936 pm_runtime_enable(eth->dev); 1937 pm_runtime_get_sync(eth->dev); 1938 1939 ret = mtk_clk_enable(eth); 1940 if (ret) 1941 goto err_disable_pm; 1942 1943 ethsys_reset(eth, RSTCTRL_FE); 1944 ethsys_reset(eth, RSTCTRL_PPE); 1945 1946 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 1947 for (i = 0; i < MTK_MAC_COUNT; i++) { 1948 if (!eth->mac[i]) 1949 continue; 1950 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id); 1951 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id); 1952 } 1953 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 1954 1955 /* Set GE2 driving and slew rate */ 1956 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1957 1958 /* set GE2 TDSEL */ 1959 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1960 1961 /* set GE2 TUNE */ 1962 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1963 1964 /* GE1, Force 1000M/FD, FC ON */ 1965 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0)); 1966 1967 /* GE2, Force 1000M/FD, FC ON */ 1968 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1)); 1969 1970 /* Indicates CDM to parse the MTK special tag from CPU 1971 * which also is working out for untag packets. 1972 */ 1973 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 1974 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 1975 1976 /* Enable RX VLan Offloading */ 1977 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1978 1979 /* enable interrupt delay for RX */ 1980 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 1981 1982 /* disable delay and normal interrupt */ 1983 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1984 mtk_tx_irq_disable(eth, ~0); 1985 mtk_rx_irq_disable(eth, ~0); 1986 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1987 mtk_w32(eth, 0, MTK_RST_GL); 1988 1989 /* FE int grouping */ 1990 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 1991 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 1992 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 1993 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 1994 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 1995 1996 for (i = 0; i < 2; i++) { 1997 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1998 1999 /* setup the forward port to send frame to PDMA */ 2000 val &= ~0xffff; 2001 2002 /* Enable RX checksum */ 2003 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2004 2005 /* setup the mac dma */ 2006 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2007 } 2008 2009 return 0; 2010 2011 err_disable_pm: 2012 pm_runtime_put_sync(eth->dev); 2013 pm_runtime_disable(eth->dev); 2014 2015 return ret; 2016 } 2017 2018 static int mtk_hw_deinit(struct mtk_eth *eth) 2019 { 2020 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2021 return 0; 2022 2023 mtk_clk_disable(eth); 2024 2025 pm_runtime_put_sync(eth->dev); 2026 pm_runtime_disable(eth->dev); 2027 2028 return 0; 2029 } 2030 2031 static int __init mtk_init(struct net_device *dev) 2032 { 2033 struct mtk_mac *mac = netdev_priv(dev); 2034 struct mtk_eth *eth = mac->hw; 2035 const char *mac_addr; 2036 2037 mac_addr = of_get_mac_address(mac->of_node); 2038 if (mac_addr) 2039 ether_addr_copy(dev->dev_addr, mac_addr); 2040 2041 /* If the mac address is invalid, use random mac address */ 2042 if (!is_valid_ether_addr(dev->dev_addr)) { 2043 eth_hw_addr_random(dev); 2044 dev_err(eth->dev, "generated random MAC address %pM\n", 2045 dev->dev_addr); 2046 } 2047 2048 return mtk_phy_connect(dev); 2049 } 2050 2051 static void mtk_uninit(struct net_device *dev) 2052 { 2053 struct mtk_mac *mac = netdev_priv(dev); 2054 struct mtk_eth *eth = mac->hw; 2055 2056 phy_disconnect(dev->phydev); 2057 if (of_phy_is_fixed_link(mac->of_node)) 2058 of_phy_deregister_fixed_link(mac->of_node); 2059 mtk_tx_irq_disable(eth, ~0); 2060 mtk_rx_irq_disable(eth, ~0); 2061 } 2062 2063 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2064 { 2065 switch (cmd) { 2066 case SIOCGMIIPHY: 2067 case SIOCGMIIREG: 2068 case SIOCSMIIREG: 2069 return phy_mii_ioctl(dev->phydev, ifr, cmd); 2070 default: 2071 break; 2072 } 2073 2074 return -EOPNOTSUPP; 2075 } 2076 2077 static void mtk_pending_work(struct work_struct *work) 2078 { 2079 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2080 int err, i; 2081 unsigned long restart = 0; 2082 2083 rtnl_lock(); 2084 2085 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2086 2087 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2088 cpu_relax(); 2089 2090 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2091 /* stop all devices to make sure that dma is properly shut down */ 2092 for (i = 0; i < MTK_MAC_COUNT; i++) { 2093 if (!eth->netdev[i]) 2094 continue; 2095 mtk_stop(eth->netdev[i]); 2096 __set_bit(i, &restart); 2097 } 2098 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2099 2100 /* restart underlying hardware such as power, clock, pin mux 2101 * and the connected phy 2102 */ 2103 mtk_hw_deinit(eth); 2104 2105 if (eth->dev->pins) 2106 pinctrl_select_state(eth->dev->pins->p, 2107 eth->dev->pins->default_state); 2108 mtk_hw_init(eth); 2109 2110 for (i = 0; i < MTK_MAC_COUNT; i++) { 2111 if (!eth->mac[i] || 2112 of_phy_is_fixed_link(eth->mac[i]->of_node)) 2113 continue; 2114 err = phy_init_hw(eth->netdev[i]->phydev); 2115 if (err) 2116 dev_err(eth->dev, "%s: PHY init failed.\n", 2117 eth->netdev[i]->name); 2118 } 2119 2120 /* restart DMA and enable IRQs */ 2121 for (i = 0; i < MTK_MAC_COUNT; i++) { 2122 if (!test_bit(i, &restart)) 2123 continue; 2124 err = mtk_open(eth->netdev[i]); 2125 if (err) { 2126 netif_alert(eth, ifup, eth->netdev[i], 2127 "Driver up/down cycle failed, closing device.\n"); 2128 dev_close(eth->netdev[i]); 2129 } 2130 } 2131 2132 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2133 2134 clear_bit_unlock(MTK_RESETTING, ð->state); 2135 2136 rtnl_unlock(); 2137 } 2138 2139 static int mtk_free_dev(struct mtk_eth *eth) 2140 { 2141 int i; 2142 2143 for (i = 0; i < MTK_MAC_COUNT; i++) { 2144 if (!eth->netdev[i]) 2145 continue; 2146 free_netdev(eth->netdev[i]); 2147 } 2148 2149 return 0; 2150 } 2151 2152 static int mtk_unreg_dev(struct mtk_eth *eth) 2153 { 2154 int i; 2155 2156 for (i = 0; i < MTK_MAC_COUNT; i++) { 2157 if (!eth->netdev[i]) 2158 continue; 2159 unregister_netdev(eth->netdev[i]); 2160 } 2161 2162 return 0; 2163 } 2164 2165 static int mtk_cleanup(struct mtk_eth *eth) 2166 { 2167 mtk_unreg_dev(eth); 2168 mtk_free_dev(eth); 2169 cancel_work_sync(ð->pending_work); 2170 2171 return 0; 2172 } 2173 2174 static int mtk_get_link_ksettings(struct net_device *ndev, 2175 struct ethtool_link_ksettings *cmd) 2176 { 2177 struct mtk_mac *mac = netdev_priv(ndev); 2178 2179 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2180 return -EBUSY; 2181 2182 phy_ethtool_ksettings_get(ndev->phydev, cmd); 2183 2184 return 0; 2185 } 2186 2187 static int mtk_set_link_ksettings(struct net_device *ndev, 2188 const struct ethtool_link_ksettings *cmd) 2189 { 2190 struct mtk_mac *mac = netdev_priv(ndev); 2191 2192 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2193 return -EBUSY; 2194 2195 return phy_ethtool_ksettings_set(ndev->phydev, cmd); 2196 } 2197 2198 static void mtk_get_drvinfo(struct net_device *dev, 2199 struct ethtool_drvinfo *info) 2200 { 2201 struct mtk_mac *mac = netdev_priv(dev); 2202 2203 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2204 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2205 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2206 } 2207 2208 static u32 mtk_get_msglevel(struct net_device *dev) 2209 { 2210 struct mtk_mac *mac = netdev_priv(dev); 2211 2212 return mac->hw->msg_enable; 2213 } 2214 2215 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2216 { 2217 struct mtk_mac *mac = netdev_priv(dev); 2218 2219 mac->hw->msg_enable = value; 2220 } 2221 2222 static int mtk_nway_reset(struct net_device *dev) 2223 { 2224 struct mtk_mac *mac = netdev_priv(dev); 2225 2226 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2227 return -EBUSY; 2228 2229 return genphy_restart_aneg(dev->phydev); 2230 } 2231 2232 static u32 mtk_get_link(struct net_device *dev) 2233 { 2234 struct mtk_mac *mac = netdev_priv(dev); 2235 int err; 2236 2237 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2238 return -EBUSY; 2239 2240 err = genphy_update_link(dev->phydev); 2241 if (err) 2242 return ethtool_op_get_link(dev); 2243 2244 return dev->phydev->link; 2245 } 2246 2247 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2248 { 2249 int i; 2250 2251 switch (stringset) { 2252 case ETH_SS_STATS: 2253 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2254 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2255 data += ETH_GSTRING_LEN; 2256 } 2257 break; 2258 } 2259 } 2260 2261 static int mtk_get_sset_count(struct net_device *dev, int sset) 2262 { 2263 switch (sset) { 2264 case ETH_SS_STATS: 2265 return ARRAY_SIZE(mtk_ethtool_stats); 2266 default: 2267 return -EOPNOTSUPP; 2268 } 2269 } 2270 2271 static void mtk_get_ethtool_stats(struct net_device *dev, 2272 struct ethtool_stats *stats, u64 *data) 2273 { 2274 struct mtk_mac *mac = netdev_priv(dev); 2275 struct mtk_hw_stats *hwstats = mac->hw_stats; 2276 u64 *data_src, *data_dst; 2277 unsigned int start; 2278 int i; 2279 2280 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2281 return; 2282 2283 if (netif_running(dev) && netif_device_present(dev)) { 2284 if (spin_trylock_bh(&hwstats->stats_lock)) { 2285 mtk_stats_update_mac(mac); 2286 spin_unlock_bh(&hwstats->stats_lock); 2287 } 2288 } 2289 2290 data_src = (u64 *)hwstats; 2291 2292 do { 2293 data_dst = data; 2294 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2295 2296 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2297 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2298 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2299 } 2300 2301 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2302 u32 *rule_locs) 2303 { 2304 int ret = -EOPNOTSUPP; 2305 2306 switch (cmd->cmd) { 2307 case ETHTOOL_GRXRINGS: 2308 if (dev->features & NETIF_F_LRO) { 2309 cmd->data = MTK_MAX_RX_RING_NUM; 2310 ret = 0; 2311 } 2312 break; 2313 case ETHTOOL_GRXCLSRLCNT: 2314 if (dev->features & NETIF_F_LRO) { 2315 struct mtk_mac *mac = netdev_priv(dev); 2316 2317 cmd->rule_cnt = mac->hwlro_ip_cnt; 2318 ret = 0; 2319 } 2320 break; 2321 case ETHTOOL_GRXCLSRULE: 2322 if (dev->features & NETIF_F_LRO) 2323 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2324 break; 2325 case ETHTOOL_GRXCLSRLALL: 2326 if (dev->features & NETIF_F_LRO) 2327 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2328 rule_locs); 2329 break; 2330 default: 2331 break; 2332 } 2333 2334 return ret; 2335 } 2336 2337 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2338 { 2339 int ret = -EOPNOTSUPP; 2340 2341 switch (cmd->cmd) { 2342 case ETHTOOL_SRXCLSRLINS: 2343 if (dev->features & NETIF_F_LRO) 2344 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2345 break; 2346 case ETHTOOL_SRXCLSRLDEL: 2347 if (dev->features & NETIF_F_LRO) 2348 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2349 break; 2350 default: 2351 break; 2352 } 2353 2354 return ret; 2355 } 2356 2357 static const struct ethtool_ops mtk_ethtool_ops = { 2358 .get_link_ksettings = mtk_get_link_ksettings, 2359 .set_link_ksettings = mtk_set_link_ksettings, 2360 .get_drvinfo = mtk_get_drvinfo, 2361 .get_msglevel = mtk_get_msglevel, 2362 .set_msglevel = mtk_set_msglevel, 2363 .nway_reset = mtk_nway_reset, 2364 .get_link = mtk_get_link, 2365 .get_strings = mtk_get_strings, 2366 .get_sset_count = mtk_get_sset_count, 2367 .get_ethtool_stats = mtk_get_ethtool_stats, 2368 .get_rxnfc = mtk_get_rxnfc, 2369 .set_rxnfc = mtk_set_rxnfc, 2370 }; 2371 2372 static const struct net_device_ops mtk_netdev_ops = { 2373 .ndo_init = mtk_init, 2374 .ndo_uninit = mtk_uninit, 2375 .ndo_open = mtk_open, 2376 .ndo_stop = mtk_stop, 2377 .ndo_start_xmit = mtk_start_xmit, 2378 .ndo_set_mac_address = mtk_set_mac_address, 2379 .ndo_validate_addr = eth_validate_addr, 2380 .ndo_do_ioctl = mtk_do_ioctl, 2381 .ndo_tx_timeout = mtk_tx_timeout, 2382 .ndo_get_stats64 = mtk_get_stats64, 2383 .ndo_fix_features = mtk_fix_features, 2384 .ndo_set_features = mtk_set_features, 2385 #ifdef CONFIG_NET_POLL_CONTROLLER 2386 .ndo_poll_controller = mtk_poll_controller, 2387 #endif 2388 }; 2389 2390 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2391 { 2392 struct mtk_mac *mac; 2393 const __be32 *_id = of_get_property(np, "reg", NULL); 2394 int id, err; 2395 2396 if (!_id) { 2397 dev_err(eth->dev, "missing mac id\n"); 2398 return -EINVAL; 2399 } 2400 2401 id = be32_to_cpup(_id); 2402 if (id >= MTK_MAC_COUNT) { 2403 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2404 return -EINVAL; 2405 } 2406 2407 if (eth->netdev[id]) { 2408 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2409 return -EINVAL; 2410 } 2411 2412 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2413 if (!eth->netdev[id]) { 2414 dev_err(eth->dev, "alloc_etherdev failed\n"); 2415 return -ENOMEM; 2416 } 2417 mac = netdev_priv(eth->netdev[id]); 2418 eth->mac[id] = mac; 2419 mac->id = id; 2420 mac->hw = eth; 2421 mac->of_node = np; 2422 2423 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2424 mac->hwlro_ip_cnt = 0; 2425 2426 mac->hw_stats = devm_kzalloc(eth->dev, 2427 sizeof(*mac->hw_stats), 2428 GFP_KERNEL); 2429 if (!mac->hw_stats) { 2430 dev_err(eth->dev, "failed to allocate counter memory\n"); 2431 err = -ENOMEM; 2432 goto free_netdev; 2433 } 2434 spin_lock_init(&mac->hw_stats->stats_lock); 2435 u64_stats_init(&mac->hw_stats->syncp); 2436 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2437 2438 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2439 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2440 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2441 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2442 2443 eth->netdev[id]->hw_features = MTK_HW_FEATURES; 2444 if (eth->hwlro) 2445 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2446 2447 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 2448 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2449 eth->netdev[id]->features |= MTK_HW_FEATURES; 2450 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2451 2452 eth->netdev[id]->irq = eth->irq[0]; 2453 eth->netdev[id]->dev.of_node = np; 2454 2455 return 0; 2456 2457 free_netdev: 2458 free_netdev(eth->netdev[id]); 2459 return err; 2460 } 2461 2462 static int mtk_get_chip_id(struct mtk_eth *eth, u32 *chip_id) 2463 { 2464 u32 val[2], id[4]; 2465 2466 regmap_read(eth->ethsys, ETHSYS_CHIPID0_3, &val[0]); 2467 regmap_read(eth->ethsys, ETHSYS_CHIPID4_7, &val[1]); 2468 2469 id[3] = ((val[0] >> 16) & 0xff) - '0'; 2470 id[2] = ((val[0] >> 24) & 0xff) - '0'; 2471 id[1] = (val[1] & 0xff) - '0'; 2472 id[0] = ((val[1] >> 8) & 0xff) - '0'; 2473 2474 *chip_id = (id[3] * 1000) + (id[2] * 100) + 2475 (id[1] * 10) + id[0]; 2476 2477 if (!(*chip_id)) { 2478 dev_err(eth->dev, "failed to get chip id\n"); 2479 return -ENODEV; 2480 } 2481 2482 dev_info(eth->dev, "chip id = %d\n", *chip_id); 2483 2484 return 0; 2485 } 2486 2487 static bool mtk_is_hwlro_supported(struct mtk_eth *eth) 2488 { 2489 switch (eth->chip_id) { 2490 case MT7622_ETH: 2491 case MT7623_ETH: 2492 return true; 2493 } 2494 2495 return false; 2496 } 2497 2498 static int mtk_probe(struct platform_device *pdev) 2499 { 2500 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2501 struct device_node *mac_np; 2502 const struct of_device_id *match; 2503 struct mtk_eth *eth; 2504 int err; 2505 int i; 2506 2507 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2508 if (!eth) 2509 return -ENOMEM; 2510 2511 match = of_match_device(of_mtk_match, &pdev->dev); 2512 eth->soc = (struct mtk_soc_data *)match->data; 2513 2514 eth->dev = &pdev->dev; 2515 eth->base = devm_ioremap_resource(&pdev->dev, res); 2516 if (IS_ERR(eth->base)) 2517 return PTR_ERR(eth->base); 2518 2519 spin_lock_init(ð->page_lock); 2520 spin_lock_init(ð->tx_irq_lock); 2521 spin_lock_init(ð->rx_irq_lock); 2522 2523 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2524 "mediatek,ethsys"); 2525 if (IS_ERR(eth->ethsys)) { 2526 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2527 return PTR_ERR(eth->ethsys); 2528 } 2529 2530 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 2531 eth->sgmiisys = 2532 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2533 "mediatek,sgmiisys"); 2534 if (IS_ERR(eth->sgmiisys)) { 2535 dev_err(&pdev->dev, "no sgmiisys regmap found\n"); 2536 return PTR_ERR(eth->sgmiisys); 2537 } 2538 } 2539 2540 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2541 "mediatek,pctl"); 2542 if (IS_ERR(eth->pctl)) { 2543 dev_err(&pdev->dev, "no pctl regmap found\n"); 2544 return PTR_ERR(eth->pctl); 2545 } 2546 2547 for (i = 0; i < 3; i++) { 2548 eth->irq[i] = platform_get_irq(pdev, i); 2549 if (eth->irq[i] < 0) { 2550 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2551 return -ENXIO; 2552 } 2553 } 2554 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2555 eth->clks[i] = devm_clk_get(eth->dev, 2556 mtk_clks_source_name[i]); 2557 if (IS_ERR(eth->clks[i])) { 2558 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2559 return -EPROBE_DEFER; 2560 if (eth->soc->required_clks & BIT(i)) { 2561 dev_err(&pdev->dev, "clock %s not found\n", 2562 mtk_clks_source_name[i]); 2563 return -EINVAL; 2564 } 2565 eth->clks[i] = NULL; 2566 } 2567 } 2568 2569 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 2570 INIT_WORK(ð->pending_work, mtk_pending_work); 2571 2572 err = mtk_hw_init(eth); 2573 if (err) 2574 return err; 2575 2576 err = mtk_get_chip_id(eth, ð->chip_id); 2577 if (err) 2578 return err; 2579 2580 eth->hwlro = mtk_is_hwlro_supported(eth); 2581 2582 for_each_child_of_node(pdev->dev.of_node, mac_np) { 2583 if (!of_device_is_compatible(mac_np, 2584 "mediatek,eth-mac")) 2585 continue; 2586 2587 if (!of_device_is_available(mac_np)) 2588 continue; 2589 2590 err = mtk_add_mac(eth, mac_np); 2591 if (err) 2592 goto err_deinit_hw; 2593 } 2594 2595 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0, 2596 dev_name(eth->dev), eth); 2597 if (err) 2598 goto err_free_dev; 2599 2600 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0, 2601 dev_name(eth->dev), eth); 2602 if (err) 2603 goto err_free_dev; 2604 2605 err = mtk_mdio_init(eth); 2606 if (err) 2607 goto err_free_dev; 2608 2609 for (i = 0; i < MTK_MAX_DEVS; i++) { 2610 if (!eth->netdev[i]) 2611 continue; 2612 2613 err = register_netdev(eth->netdev[i]); 2614 if (err) { 2615 dev_err(eth->dev, "error bringing up device\n"); 2616 goto err_deinit_mdio; 2617 } else 2618 netif_info(eth, probe, eth->netdev[i], 2619 "mediatek frame engine at 0x%08lx, irq %d\n", 2620 eth->netdev[i]->base_addr, eth->irq[0]); 2621 } 2622 2623 /* we run 2 devices on the same DMA ring so we need a dummy device 2624 * for NAPI to work 2625 */ 2626 init_dummy_netdev(ð->dummy_dev); 2627 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 2628 MTK_NAPI_WEIGHT); 2629 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 2630 MTK_NAPI_WEIGHT); 2631 2632 platform_set_drvdata(pdev, eth); 2633 2634 return 0; 2635 2636 err_deinit_mdio: 2637 mtk_mdio_cleanup(eth); 2638 err_free_dev: 2639 mtk_free_dev(eth); 2640 err_deinit_hw: 2641 mtk_hw_deinit(eth); 2642 2643 return err; 2644 } 2645 2646 static int mtk_remove(struct platform_device *pdev) 2647 { 2648 struct mtk_eth *eth = platform_get_drvdata(pdev); 2649 int i; 2650 2651 /* stop all devices to make sure that dma is properly shut down */ 2652 for (i = 0; i < MTK_MAC_COUNT; i++) { 2653 if (!eth->netdev[i]) 2654 continue; 2655 mtk_stop(eth->netdev[i]); 2656 } 2657 2658 mtk_hw_deinit(eth); 2659 2660 netif_napi_del(ð->tx_napi); 2661 netif_napi_del(ð->rx_napi); 2662 mtk_cleanup(eth); 2663 mtk_mdio_cleanup(eth); 2664 2665 return 0; 2666 } 2667 2668 static const struct mtk_soc_data mt2701_data = { 2669 .caps = MTK_GMAC1_TRGMII, 2670 .required_clks = MT7623_CLKS_BITMAP 2671 }; 2672 2673 static const struct mtk_soc_data mt7622_data = { 2674 .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW, 2675 .required_clks = MT7622_CLKS_BITMAP 2676 }; 2677 2678 static const struct mtk_soc_data mt7623_data = { 2679 .caps = MTK_GMAC1_TRGMII, 2680 .required_clks = MT7623_CLKS_BITMAP 2681 }; 2682 2683 const struct of_device_id of_mtk_match[] = { 2684 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 2685 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 2686 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 2687 {}, 2688 }; 2689 MODULE_DEVICE_TABLE(of, of_mtk_match); 2690 2691 static struct platform_driver mtk_driver = { 2692 .probe = mtk_probe, 2693 .remove = mtk_remove, 2694 .driver = { 2695 .name = "mtk_soc_eth", 2696 .of_match_table = of_mtk_match, 2697 }, 2698 }; 2699 2700 module_platform_driver(mtk_driver); 2701 2702 MODULE_LICENSE("GPL"); 2703 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 2704 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 2705