1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/regmap.h> 14 #include <linux/clk.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/if_vlan.h> 17 #include <linux/reset.h> 18 #include <linux/tcp.h> 19 #include <linux/interrupt.h> 20 #include <linux/pinctrl/devinfo.h> 21 #include <linux/phylink.h> 22 23 #include "mtk_eth_soc.h" 24 25 static int mtk_msg_level = -1; 26 module_param_named(msg_level, mtk_msg_level, int, 0); 27 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 28 29 #define MTK_ETHTOOL_STAT(x) { #x, \ 30 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 31 32 /* strings used by ethtool */ 33 static const struct mtk_ethtool_stats { 34 char str[ETH_GSTRING_LEN]; 35 u32 offset; 36 } mtk_ethtool_stats[] = { 37 MTK_ETHTOOL_STAT(tx_bytes), 38 MTK_ETHTOOL_STAT(tx_packets), 39 MTK_ETHTOOL_STAT(tx_skip), 40 MTK_ETHTOOL_STAT(tx_collisions), 41 MTK_ETHTOOL_STAT(rx_bytes), 42 MTK_ETHTOOL_STAT(rx_packets), 43 MTK_ETHTOOL_STAT(rx_overflow), 44 MTK_ETHTOOL_STAT(rx_fcs_errors), 45 MTK_ETHTOOL_STAT(rx_short_errors), 46 MTK_ETHTOOL_STAT(rx_long_errors), 47 MTK_ETHTOOL_STAT(rx_checksum_errors), 48 MTK_ETHTOOL_STAT(rx_flow_control_packets), 49 }; 50 51 static const char * const mtk_clks_source_name[] = { 52 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 53 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 54 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 55 "sgmii_ck", "eth2pll", 56 }; 57 58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 59 { 60 __raw_writel(val, eth->base + reg); 61 } 62 63 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 64 { 65 return __raw_readl(eth->base + reg); 66 } 67 68 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 69 { 70 u32 val; 71 72 val = mtk_r32(eth, reg); 73 val &= ~mask; 74 val |= set; 75 mtk_w32(eth, val, reg); 76 return reg; 77 } 78 79 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 80 { 81 unsigned long t_start = jiffies; 82 83 while (1) { 84 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 85 return 0; 86 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 87 break; 88 usleep_range(10, 20); 89 } 90 91 dev_err(eth->dev, "mdio: MDIO timeout\n"); 92 return -1; 93 } 94 95 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 96 u32 phy_register, u32 write_data) 97 { 98 if (mtk_mdio_busy_wait(eth)) 99 return -1; 100 101 write_data &= 0xffff; 102 103 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 104 (phy_register << PHY_IAC_REG_SHIFT) | 105 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 106 MTK_PHY_IAC); 107 108 if (mtk_mdio_busy_wait(eth)) 109 return -1; 110 111 return 0; 112 } 113 114 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 115 { 116 u32 d; 117 118 if (mtk_mdio_busy_wait(eth)) 119 return 0xffff; 120 121 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 122 (phy_reg << PHY_IAC_REG_SHIFT) | 123 (phy_addr << PHY_IAC_ADDR_SHIFT), 124 MTK_PHY_IAC); 125 126 if (mtk_mdio_busy_wait(eth)) 127 return 0xffff; 128 129 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 130 131 return d; 132 } 133 134 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 135 int phy_reg, u16 val) 136 { 137 struct mtk_eth *eth = bus->priv; 138 139 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 140 } 141 142 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 143 { 144 struct mtk_eth *eth = bus->priv; 145 146 return _mtk_mdio_read(eth, phy_addr, phy_reg); 147 } 148 149 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 150 phy_interface_t interface) 151 { 152 u32 val; 153 154 /* Check DDR memory type. 155 * Currently TRGMII mode with DDR2 memory is not supported. 156 */ 157 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 158 if (interface == PHY_INTERFACE_MODE_TRGMII && 159 val & SYSCFG_DRAM_TYPE_DDR2) { 160 dev_err(eth->dev, 161 "TRGMII mode with DDR2 memory is not supported!\n"); 162 return -EOPNOTSUPP; 163 } 164 165 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 166 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 167 168 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 169 ETHSYS_TRGMII_MT7621_MASK, val); 170 171 return 0; 172 } 173 174 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 175 { 176 u32 val; 177 int ret; 178 179 val = (speed == SPEED_1000) ? 180 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 181 mtk_w32(eth, val, INTF_MODE); 182 183 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 184 ETHSYS_TRGMII_CLK_SEL362_5, 185 ETHSYS_TRGMII_CLK_SEL362_5); 186 187 val = (speed == SPEED_1000) ? 250000000 : 500000000; 188 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 189 if (ret) 190 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 191 192 val = (speed == SPEED_1000) ? 193 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 194 mtk_w32(eth, val, TRGMII_RCK_CTRL); 195 196 val = (speed == SPEED_1000) ? 197 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 198 mtk_w32(eth, val, TRGMII_TCK_CTRL); 199 } 200 201 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 202 const struct phylink_link_state *state) 203 { 204 struct mtk_mac *mac = container_of(config, struct mtk_mac, 205 phylink_config); 206 struct mtk_eth *eth = mac->hw; 207 u32 mcr_cur, mcr_new, sid, i; 208 int val, ge_mode, err; 209 210 /* MT76x8 has no hardware settings between for the MAC */ 211 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 212 mac->interface != state->interface) { 213 /* Setup soc pin functions */ 214 switch (state->interface) { 215 case PHY_INTERFACE_MODE_TRGMII: 216 if (mac->id) 217 goto err_phy; 218 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 219 MTK_GMAC1_TRGMII)) 220 goto err_phy; 221 /* fall through */ 222 case PHY_INTERFACE_MODE_RGMII_TXID: 223 case PHY_INTERFACE_MODE_RGMII_RXID: 224 case PHY_INTERFACE_MODE_RGMII_ID: 225 case PHY_INTERFACE_MODE_RGMII: 226 case PHY_INTERFACE_MODE_MII: 227 case PHY_INTERFACE_MODE_REVMII: 228 case PHY_INTERFACE_MODE_RMII: 229 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 230 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 231 if (err) 232 goto init_err; 233 } 234 break; 235 case PHY_INTERFACE_MODE_1000BASEX: 236 case PHY_INTERFACE_MODE_2500BASEX: 237 case PHY_INTERFACE_MODE_SGMII: 238 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 239 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 240 if (err) 241 goto init_err; 242 } 243 break; 244 case PHY_INTERFACE_MODE_GMII: 245 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 246 err = mtk_gmac_gephy_path_setup(eth, mac->id); 247 if (err) 248 goto init_err; 249 } 250 break; 251 default: 252 goto err_phy; 253 } 254 255 /* Setup clock for 1st gmac */ 256 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 257 !phy_interface_mode_is_8023z(state->interface) && 258 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 259 if (MTK_HAS_CAPS(mac->hw->soc->caps, 260 MTK_TRGMII_MT7621_CLK)) { 261 if (mt7621_gmac0_rgmii_adjust(mac->hw, 262 state->interface)) 263 goto err_phy; 264 } else { 265 if (state->interface != 266 PHY_INTERFACE_MODE_TRGMII) 267 mtk_gmac0_rgmii_adjust(mac->hw, 268 state->speed); 269 270 /* mt7623_pad_clk_setup */ 271 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 272 mtk_w32(mac->hw, 273 TD_DM_DRVP(8) | TD_DM_DRVN(8), 274 TRGMII_TD_ODT(i)); 275 276 /* Assert/release MT7623 RXC reset */ 277 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 278 TRGMII_RCK_CTRL); 279 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 280 } 281 } 282 283 ge_mode = 0; 284 switch (state->interface) { 285 case PHY_INTERFACE_MODE_MII: 286 case PHY_INTERFACE_MODE_GMII: 287 ge_mode = 1; 288 break; 289 case PHY_INTERFACE_MODE_REVMII: 290 ge_mode = 2; 291 break; 292 case PHY_INTERFACE_MODE_RMII: 293 if (mac->id) 294 goto err_phy; 295 ge_mode = 3; 296 break; 297 default: 298 break; 299 } 300 301 /* put the gmac into the right mode */ 302 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 303 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 304 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 305 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 306 307 mac->interface = state->interface; 308 } 309 310 /* SGMII */ 311 if (state->interface == PHY_INTERFACE_MODE_SGMII || 312 phy_interface_mode_is_8023z(state->interface)) { 313 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 314 * being setup done. 315 */ 316 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 317 318 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 319 SYSCFG0_SGMII_MASK, 320 ~(u32)SYSCFG0_SGMII_MASK); 321 322 /* Decide how GMAC and SGMIISYS be mapped */ 323 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 324 0 : mac->id; 325 326 /* Setup SGMIISYS with the determined property */ 327 if (state->interface != PHY_INTERFACE_MODE_SGMII) 328 err = mtk_sgmii_setup_mode_force(eth->sgmii, sid, 329 state); 330 else if (phylink_autoneg_inband(mode)) 331 err = mtk_sgmii_setup_mode_an(eth->sgmii, sid); 332 333 if (err) 334 goto init_err; 335 336 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 337 SYSCFG0_SGMII_MASK, val); 338 } else if (phylink_autoneg_inband(mode)) { 339 dev_err(eth->dev, 340 "In-band mode not supported in non SGMII mode!\n"); 341 return; 342 } 343 344 /* Setup gmac */ 345 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 346 mcr_new = mcr_cur; 347 mcr_new |= MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 348 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; 349 350 /* Only update control register when needed! */ 351 if (mcr_new != mcr_cur) 352 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 353 354 return; 355 356 err_phy: 357 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 358 mac->id, phy_modes(state->interface)); 359 return; 360 361 init_err: 362 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 363 mac->id, phy_modes(state->interface), err); 364 } 365 366 static void mtk_mac_pcs_get_state(struct phylink_config *config, 367 struct phylink_link_state *state) 368 { 369 struct mtk_mac *mac = container_of(config, struct mtk_mac, 370 phylink_config); 371 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 372 373 state->link = (pmsr & MAC_MSR_LINK); 374 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 375 376 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 377 case 0: 378 state->speed = SPEED_10; 379 break; 380 case MAC_MSR_SPEED_100: 381 state->speed = SPEED_100; 382 break; 383 case MAC_MSR_SPEED_1000: 384 state->speed = SPEED_1000; 385 break; 386 default: 387 state->speed = SPEED_UNKNOWN; 388 break; 389 } 390 391 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 392 if (pmsr & MAC_MSR_RX_FC) 393 state->pause |= MLO_PAUSE_RX; 394 if (pmsr & MAC_MSR_TX_FC) 395 state->pause |= MLO_PAUSE_TX; 396 } 397 398 static void mtk_mac_an_restart(struct phylink_config *config) 399 { 400 struct mtk_mac *mac = container_of(config, struct mtk_mac, 401 phylink_config); 402 403 mtk_sgmii_restart_an(mac->hw, mac->id); 404 } 405 406 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 407 phy_interface_t interface) 408 { 409 struct mtk_mac *mac = container_of(config, struct mtk_mac, 410 phylink_config); 411 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 412 413 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 414 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 415 } 416 417 static void mtk_mac_link_up(struct phylink_config *config, 418 struct phy_device *phy, 419 unsigned int mode, phy_interface_t interface, 420 int speed, int duplex, bool tx_pause, bool rx_pause) 421 { 422 struct mtk_mac *mac = container_of(config, struct mtk_mac, 423 phylink_config); 424 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 425 426 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 427 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 428 MAC_MCR_FORCE_RX_FC); 429 430 /* Configure speed */ 431 switch (speed) { 432 case SPEED_2500: 433 case SPEED_1000: 434 mcr |= MAC_MCR_SPEED_1000; 435 break; 436 case SPEED_100: 437 mcr |= MAC_MCR_SPEED_100; 438 break; 439 } 440 441 /* Configure duplex */ 442 if (duplex == DUPLEX_FULL) 443 mcr |= MAC_MCR_FORCE_DPX; 444 445 /* Configure pause modes - phylink will avoid these for half duplex */ 446 if (tx_pause) 447 mcr |= MAC_MCR_FORCE_TX_FC; 448 if (rx_pause) 449 mcr |= MAC_MCR_FORCE_RX_FC; 450 451 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 452 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 453 } 454 455 static void mtk_validate(struct phylink_config *config, 456 unsigned long *supported, 457 struct phylink_link_state *state) 458 { 459 struct mtk_mac *mac = container_of(config, struct mtk_mac, 460 phylink_config); 461 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 462 463 if (state->interface != PHY_INTERFACE_MODE_NA && 464 state->interface != PHY_INTERFACE_MODE_MII && 465 state->interface != PHY_INTERFACE_MODE_GMII && 466 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) && 467 phy_interface_mode_is_rgmii(state->interface)) && 468 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && 469 !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) && 470 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) && 471 (state->interface == PHY_INTERFACE_MODE_SGMII || 472 phy_interface_mode_is_8023z(state->interface)))) { 473 linkmode_zero(supported); 474 return; 475 } 476 477 phylink_set_port_modes(mask); 478 phylink_set(mask, Autoneg); 479 480 switch (state->interface) { 481 case PHY_INTERFACE_MODE_TRGMII: 482 phylink_set(mask, 1000baseT_Full); 483 break; 484 case PHY_INTERFACE_MODE_1000BASEX: 485 case PHY_INTERFACE_MODE_2500BASEX: 486 phylink_set(mask, 1000baseX_Full); 487 phylink_set(mask, 2500baseX_Full); 488 break; 489 case PHY_INTERFACE_MODE_GMII: 490 case PHY_INTERFACE_MODE_RGMII: 491 case PHY_INTERFACE_MODE_RGMII_ID: 492 case PHY_INTERFACE_MODE_RGMII_RXID: 493 case PHY_INTERFACE_MODE_RGMII_TXID: 494 phylink_set(mask, 1000baseT_Half); 495 /* fall through */ 496 case PHY_INTERFACE_MODE_SGMII: 497 phylink_set(mask, 1000baseT_Full); 498 phylink_set(mask, 1000baseX_Full); 499 /* fall through */ 500 case PHY_INTERFACE_MODE_MII: 501 case PHY_INTERFACE_MODE_RMII: 502 case PHY_INTERFACE_MODE_REVMII: 503 case PHY_INTERFACE_MODE_NA: 504 default: 505 phylink_set(mask, 10baseT_Half); 506 phylink_set(mask, 10baseT_Full); 507 phylink_set(mask, 100baseT_Half); 508 phylink_set(mask, 100baseT_Full); 509 break; 510 } 511 512 if (state->interface == PHY_INTERFACE_MODE_NA) { 513 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 514 phylink_set(mask, 1000baseT_Full); 515 phylink_set(mask, 1000baseX_Full); 516 phylink_set(mask, 2500baseX_Full); 517 } 518 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) { 519 phylink_set(mask, 1000baseT_Full); 520 phylink_set(mask, 1000baseT_Half); 521 phylink_set(mask, 1000baseX_Full); 522 } 523 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) { 524 phylink_set(mask, 1000baseT_Full); 525 phylink_set(mask, 1000baseT_Half); 526 } 527 } 528 529 phylink_set(mask, Pause); 530 phylink_set(mask, Asym_Pause); 531 532 linkmode_and(supported, supported, mask); 533 linkmode_and(state->advertising, state->advertising, mask); 534 535 /* We can only operate at 2500BaseX or 1000BaseX. If requested 536 * to advertise both, only report advertising at 2500BaseX. 537 */ 538 phylink_helper_basex_speed(state); 539 } 540 541 static const struct phylink_mac_ops mtk_phylink_ops = { 542 .validate = mtk_validate, 543 .mac_pcs_get_state = mtk_mac_pcs_get_state, 544 .mac_an_restart = mtk_mac_an_restart, 545 .mac_config = mtk_mac_config, 546 .mac_link_down = mtk_mac_link_down, 547 .mac_link_up = mtk_mac_link_up, 548 }; 549 550 static int mtk_mdio_init(struct mtk_eth *eth) 551 { 552 struct device_node *mii_np; 553 int ret; 554 555 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 556 if (!mii_np) { 557 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 558 return -ENODEV; 559 } 560 561 if (!of_device_is_available(mii_np)) { 562 ret = -ENODEV; 563 goto err_put_node; 564 } 565 566 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 567 if (!eth->mii_bus) { 568 ret = -ENOMEM; 569 goto err_put_node; 570 } 571 572 eth->mii_bus->name = "mdio"; 573 eth->mii_bus->read = mtk_mdio_read; 574 eth->mii_bus->write = mtk_mdio_write; 575 eth->mii_bus->priv = eth; 576 eth->mii_bus->parent = eth->dev; 577 578 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 579 ret = of_mdiobus_register(eth->mii_bus, mii_np); 580 581 err_put_node: 582 of_node_put(mii_np); 583 return ret; 584 } 585 586 static void mtk_mdio_cleanup(struct mtk_eth *eth) 587 { 588 if (!eth->mii_bus) 589 return; 590 591 mdiobus_unregister(eth->mii_bus); 592 } 593 594 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 595 { 596 unsigned long flags; 597 u32 val; 598 599 spin_lock_irqsave(ð->tx_irq_lock, flags); 600 val = mtk_r32(eth, eth->tx_int_mask_reg); 601 mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg); 602 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 603 } 604 605 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 606 { 607 unsigned long flags; 608 u32 val; 609 610 spin_lock_irqsave(ð->tx_irq_lock, flags); 611 val = mtk_r32(eth, eth->tx_int_mask_reg); 612 mtk_w32(eth, val | mask, eth->tx_int_mask_reg); 613 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 614 } 615 616 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 617 { 618 unsigned long flags; 619 u32 val; 620 621 spin_lock_irqsave(ð->rx_irq_lock, flags); 622 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 623 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 624 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 625 } 626 627 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 628 { 629 unsigned long flags; 630 u32 val; 631 632 spin_lock_irqsave(ð->rx_irq_lock, flags); 633 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 634 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 635 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 636 } 637 638 static int mtk_set_mac_address(struct net_device *dev, void *p) 639 { 640 int ret = eth_mac_addr(dev, p); 641 struct mtk_mac *mac = netdev_priv(dev); 642 struct mtk_eth *eth = mac->hw; 643 const char *macaddr = dev->dev_addr; 644 645 if (ret) 646 return ret; 647 648 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 649 return -EBUSY; 650 651 spin_lock_bh(&mac->hw->page_lock); 652 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 653 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 654 MT7628_SDM_MAC_ADRH); 655 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 656 (macaddr[4] << 8) | macaddr[5], 657 MT7628_SDM_MAC_ADRL); 658 } else { 659 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 660 MTK_GDMA_MAC_ADRH(mac->id)); 661 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 662 (macaddr[4] << 8) | macaddr[5], 663 MTK_GDMA_MAC_ADRL(mac->id)); 664 } 665 spin_unlock_bh(&mac->hw->page_lock); 666 667 return 0; 668 } 669 670 void mtk_stats_update_mac(struct mtk_mac *mac) 671 { 672 struct mtk_hw_stats *hw_stats = mac->hw_stats; 673 unsigned int base = MTK_GDM1_TX_GBCNT; 674 u64 stats; 675 676 base += hw_stats->reg_offset; 677 678 u64_stats_update_begin(&hw_stats->syncp); 679 680 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 681 stats = mtk_r32(mac->hw, base + 0x04); 682 if (stats) 683 hw_stats->rx_bytes += (stats << 32); 684 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 685 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 686 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 687 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 688 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 689 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 690 hw_stats->rx_flow_control_packets += 691 mtk_r32(mac->hw, base + 0x24); 692 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 693 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 694 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 695 stats = mtk_r32(mac->hw, base + 0x34); 696 if (stats) 697 hw_stats->tx_bytes += (stats << 32); 698 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 699 u64_stats_update_end(&hw_stats->syncp); 700 } 701 702 static void mtk_stats_update(struct mtk_eth *eth) 703 { 704 int i; 705 706 for (i = 0; i < MTK_MAC_COUNT; i++) { 707 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 708 continue; 709 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 710 mtk_stats_update_mac(eth->mac[i]); 711 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 712 } 713 } 714 } 715 716 static void mtk_get_stats64(struct net_device *dev, 717 struct rtnl_link_stats64 *storage) 718 { 719 struct mtk_mac *mac = netdev_priv(dev); 720 struct mtk_hw_stats *hw_stats = mac->hw_stats; 721 unsigned int start; 722 723 if (netif_running(dev) && netif_device_present(dev)) { 724 if (spin_trylock_bh(&hw_stats->stats_lock)) { 725 mtk_stats_update_mac(mac); 726 spin_unlock_bh(&hw_stats->stats_lock); 727 } 728 } 729 730 do { 731 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 732 storage->rx_packets = hw_stats->rx_packets; 733 storage->tx_packets = hw_stats->tx_packets; 734 storage->rx_bytes = hw_stats->rx_bytes; 735 storage->tx_bytes = hw_stats->tx_bytes; 736 storage->collisions = hw_stats->tx_collisions; 737 storage->rx_length_errors = hw_stats->rx_short_errors + 738 hw_stats->rx_long_errors; 739 storage->rx_over_errors = hw_stats->rx_overflow; 740 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 741 storage->rx_errors = hw_stats->rx_checksum_errors; 742 storage->tx_aborted_errors = hw_stats->tx_skip; 743 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 744 745 storage->tx_errors = dev->stats.tx_errors; 746 storage->rx_dropped = dev->stats.rx_dropped; 747 storage->tx_dropped = dev->stats.tx_dropped; 748 } 749 750 static inline int mtk_max_frag_size(int mtu) 751 { 752 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 753 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 754 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 755 756 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 757 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 758 } 759 760 static inline int mtk_max_buf_size(int frag_size) 761 { 762 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 763 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 764 765 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 766 767 return buf_size; 768 } 769 770 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 771 struct mtk_rx_dma *dma_rxd) 772 { 773 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 774 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 775 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 776 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 777 } 778 779 /* the qdma core needs scratch memory to be setup */ 780 static int mtk_init_fq_dma(struct mtk_eth *eth) 781 { 782 dma_addr_t phy_ring_tail; 783 int cnt = MTK_DMA_SIZE; 784 dma_addr_t dma_addr; 785 int i; 786 787 eth->scratch_ring = dma_alloc_coherent(eth->dev, 788 cnt * sizeof(struct mtk_tx_dma), 789 ð->phy_scratch_ring, 790 GFP_ATOMIC); 791 if (unlikely(!eth->scratch_ring)) 792 return -ENOMEM; 793 794 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 795 GFP_KERNEL); 796 if (unlikely(!eth->scratch_head)) 797 return -ENOMEM; 798 799 dma_addr = dma_map_single(eth->dev, 800 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 801 DMA_FROM_DEVICE); 802 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 803 return -ENOMEM; 804 805 phy_ring_tail = eth->phy_scratch_ring + 806 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 807 808 for (i = 0; i < cnt; i++) { 809 eth->scratch_ring[i].txd1 = 810 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 811 if (i < cnt - 1) 812 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 813 ((i + 1) * sizeof(struct mtk_tx_dma))); 814 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 815 } 816 817 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 818 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 819 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 820 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 821 822 return 0; 823 } 824 825 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 826 { 827 void *ret = ring->dma; 828 829 return ret + (desc - ring->phys); 830 } 831 832 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 833 struct mtk_tx_dma *txd) 834 { 835 int idx = txd - ring->dma; 836 837 return &ring->buf[idx]; 838 } 839 840 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 841 struct mtk_tx_dma *dma) 842 { 843 return ring->dma_pdma - ring->dma + dma; 844 } 845 846 static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma) 847 { 848 return ((void *)dma - (void *)ring->dma) / sizeof(*dma); 849 } 850 851 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 852 { 853 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 854 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 855 dma_unmap_single(eth->dev, 856 dma_unmap_addr(tx_buf, dma_addr0), 857 dma_unmap_len(tx_buf, dma_len0), 858 DMA_TO_DEVICE); 859 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 860 dma_unmap_page(eth->dev, 861 dma_unmap_addr(tx_buf, dma_addr0), 862 dma_unmap_len(tx_buf, dma_len0), 863 DMA_TO_DEVICE); 864 } 865 } else { 866 if (dma_unmap_len(tx_buf, dma_len0)) { 867 dma_unmap_page(eth->dev, 868 dma_unmap_addr(tx_buf, dma_addr0), 869 dma_unmap_len(tx_buf, dma_len0), 870 DMA_TO_DEVICE); 871 } 872 873 if (dma_unmap_len(tx_buf, dma_len1)) { 874 dma_unmap_page(eth->dev, 875 dma_unmap_addr(tx_buf, dma_addr1), 876 dma_unmap_len(tx_buf, dma_len1), 877 DMA_TO_DEVICE); 878 } 879 } 880 881 tx_buf->flags = 0; 882 if (tx_buf->skb && 883 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 884 dev_kfree_skb_any(tx_buf->skb); 885 tx_buf->skb = NULL; 886 } 887 888 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 889 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 890 size_t size, int idx) 891 { 892 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 893 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 894 dma_unmap_len_set(tx_buf, dma_len0, size); 895 } else { 896 if (idx & 1) { 897 txd->txd3 = mapped_addr; 898 txd->txd2 |= TX_DMA_PLEN1(size); 899 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 900 dma_unmap_len_set(tx_buf, dma_len1, size); 901 } else { 902 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 903 txd->txd1 = mapped_addr; 904 txd->txd2 = TX_DMA_PLEN0(size); 905 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 906 dma_unmap_len_set(tx_buf, dma_len0, size); 907 } 908 } 909 } 910 911 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 912 int tx_num, struct mtk_tx_ring *ring, bool gso) 913 { 914 struct mtk_mac *mac = netdev_priv(dev); 915 struct mtk_eth *eth = mac->hw; 916 struct mtk_tx_dma *itxd, *txd; 917 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 918 struct mtk_tx_buf *itx_buf, *tx_buf; 919 dma_addr_t mapped_addr; 920 unsigned int nr_frags; 921 int i, n_desc = 1; 922 u32 txd4 = 0, fport; 923 int k = 0; 924 925 itxd = ring->next_free; 926 itxd_pdma = qdma_to_pdma(ring, itxd); 927 if (itxd == ring->last_free) 928 return -ENOMEM; 929 930 /* set the forward port */ 931 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 932 txd4 |= fport; 933 934 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 935 memset(itx_buf, 0, sizeof(*itx_buf)); 936 937 if (gso) 938 txd4 |= TX_DMA_TSO; 939 940 /* TX Checksum offload */ 941 if (skb->ip_summed == CHECKSUM_PARTIAL) 942 txd4 |= TX_DMA_CHKSUM; 943 944 /* VLAN header offload */ 945 if (skb_vlan_tag_present(skb)) 946 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 947 948 mapped_addr = dma_map_single(eth->dev, skb->data, 949 skb_headlen(skb), DMA_TO_DEVICE); 950 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 951 return -ENOMEM; 952 953 WRITE_ONCE(itxd->txd1, mapped_addr); 954 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 955 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 956 MTK_TX_FLAGS_FPORT1; 957 setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb), 958 k++); 959 960 /* TX SG offload */ 961 txd = itxd; 962 txd_pdma = qdma_to_pdma(ring, txd); 963 nr_frags = skb_shinfo(skb)->nr_frags; 964 965 for (i = 0; i < nr_frags; i++) { 966 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 967 unsigned int offset = 0; 968 int frag_size = skb_frag_size(frag); 969 970 while (frag_size) { 971 bool last_frag = false; 972 unsigned int frag_map_size; 973 bool new_desc = true; 974 975 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) || 976 (i & 0x1)) { 977 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 978 txd_pdma = qdma_to_pdma(ring, txd); 979 if (txd == ring->last_free) 980 goto err_dma; 981 982 n_desc++; 983 } else { 984 new_desc = false; 985 } 986 987 988 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 989 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 990 frag_map_size, 991 DMA_TO_DEVICE); 992 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 993 goto err_dma; 994 995 if (i == nr_frags - 1 && 996 (frag_size - frag_map_size) == 0) 997 last_frag = true; 998 999 WRITE_ONCE(txd->txd1, mapped_addr); 1000 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 1001 TX_DMA_PLEN0(frag_map_size) | 1002 last_frag * TX_DMA_LS0)); 1003 WRITE_ONCE(txd->txd4, fport); 1004 1005 tx_buf = mtk_desc_to_tx_buf(ring, txd); 1006 if (new_desc) 1007 memset(tx_buf, 0, sizeof(*tx_buf)); 1008 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 1009 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1010 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1011 MTK_TX_FLAGS_FPORT1; 1012 1013 setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr, 1014 frag_map_size, k++); 1015 1016 frag_size -= frag_map_size; 1017 offset += frag_map_size; 1018 } 1019 } 1020 1021 /* store skb to cleanup */ 1022 itx_buf->skb = skb; 1023 1024 WRITE_ONCE(itxd->txd4, txd4); 1025 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 1026 (!nr_frags * TX_DMA_LS0))); 1027 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1028 if (k & 0x1) 1029 txd_pdma->txd2 |= TX_DMA_LS0; 1030 else 1031 txd_pdma->txd2 |= TX_DMA_LS1; 1032 } 1033 1034 netdev_sent_queue(dev, skb->len); 1035 skb_tx_timestamp(skb); 1036 1037 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1038 atomic_sub(n_desc, &ring->free_count); 1039 1040 /* make sure that all changes to the dma ring are flushed before we 1041 * continue 1042 */ 1043 wmb(); 1044 1045 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1046 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 1047 !netdev_xmit_more()) 1048 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 1049 } else { 1050 int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd), 1051 ring->dma_size); 1052 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1053 } 1054 1055 return 0; 1056 1057 err_dma: 1058 do { 1059 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 1060 1061 /* unmap dma */ 1062 mtk_tx_unmap(eth, tx_buf); 1063 1064 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1065 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1066 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1067 1068 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1069 itxd_pdma = qdma_to_pdma(ring, itxd); 1070 } while (itxd != txd); 1071 1072 return -ENOMEM; 1073 } 1074 1075 static inline int mtk_cal_txd_req(struct sk_buff *skb) 1076 { 1077 int i, nfrags; 1078 skb_frag_t *frag; 1079 1080 nfrags = 1; 1081 if (skb_is_gso(skb)) { 1082 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1083 frag = &skb_shinfo(skb)->frags[i]; 1084 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1085 MTK_TX_DMA_BUF_LEN); 1086 } 1087 } else { 1088 nfrags += skb_shinfo(skb)->nr_frags; 1089 } 1090 1091 return nfrags; 1092 } 1093 1094 static int mtk_queue_stopped(struct mtk_eth *eth) 1095 { 1096 int i; 1097 1098 for (i = 0; i < MTK_MAC_COUNT; i++) { 1099 if (!eth->netdev[i]) 1100 continue; 1101 if (netif_queue_stopped(eth->netdev[i])) 1102 return 1; 1103 } 1104 1105 return 0; 1106 } 1107 1108 static void mtk_wake_queue(struct mtk_eth *eth) 1109 { 1110 int i; 1111 1112 for (i = 0; i < MTK_MAC_COUNT; i++) { 1113 if (!eth->netdev[i]) 1114 continue; 1115 netif_wake_queue(eth->netdev[i]); 1116 } 1117 } 1118 1119 static void mtk_stop_queue(struct mtk_eth *eth) 1120 { 1121 int i; 1122 1123 for (i = 0; i < MTK_MAC_COUNT; i++) { 1124 if (!eth->netdev[i]) 1125 continue; 1126 netif_stop_queue(eth->netdev[i]); 1127 } 1128 } 1129 1130 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1131 { 1132 struct mtk_mac *mac = netdev_priv(dev); 1133 struct mtk_eth *eth = mac->hw; 1134 struct mtk_tx_ring *ring = ð->tx_ring; 1135 struct net_device_stats *stats = &dev->stats; 1136 bool gso = false; 1137 int tx_num; 1138 1139 /* normally we can rely on the stack not calling this more than once, 1140 * however we have 2 queues running on the same ring so we need to lock 1141 * the ring access 1142 */ 1143 spin_lock(ð->page_lock); 1144 1145 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1146 goto drop; 1147 1148 tx_num = mtk_cal_txd_req(skb); 1149 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1150 mtk_stop_queue(eth); 1151 netif_err(eth, tx_queued, dev, 1152 "Tx Ring full when queue awake!\n"); 1153 spin_unlock(ð->page_lock); 1154 return NETDEV_TX_BUSY; 1155 } 1156 1157 /* TSO: fill MSS info in tcp checksum field */ 1158 if (skb_is_gso(skb)) { 1159 if (skb_cow_head(skb, 0)) { 1160 netif_warn(eth, tx_err, dev, 1161 "GSO expand head fail.\n"); 1162 goto drop; 1163 } 1164 1165 if (skb_shinfo(skb)->gso_type & 1166 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1167 gso = true; 1168 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1169 } 1170 } 1171 1172 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1173 goto drop; 1174 1175 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1176 mtk_stop_queue(eth); 1177 1178 spin_unlock(ð->page_lock); 1179 1180 return NETDEV_TX_OK; 1181 1182 drop: 1183 spin_unlock(ð->page_lock); 1184 stats->tx_dropped++; 1185 dev_kfree_skb_any(skb); 1186 return NETDEV_TX_OK; 1187 } 1188 1189 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1190 { 1191 int i; 1192 struct mtk_rx_ring *ring; 1193 int idx; 1194 1195 if (!eth->hwlro) 1196 return ð->rx_ring[0]; 1197 1198 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1199 ring = ð->rx_ring[i]; 1200 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1201 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 1202 ring->calc_idx_update = true; 1203 return ring; 1204 } 1205 } 1206 1207 return NULL; 1208 } 1209 1210 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1211 { 1212 struct mtk_rx_ring *ring; 1213 int i; 1214 1215 if (!eth->hwlro) { 1216 ring = ð->rx_ring[0]; 1217 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1218 } else { 1219 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1220 ring = ð->rx_ring[i]; 1221 if (ring->calc_idx_update) { 1222 ring->calc_idx_update = false; 1223 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1224 } 1225 } 1226 } 1227 } 1228 1229 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1230 struct mtk_eth *eth) 1231 { 1232 struct mtk_rx_ring *ring; 1233 int idx; 1234 struct sk_buff *skb; 1235 u8 *data, *new_data; 1236 struct mtk_rx_dma *rxd, trxd; 1237 int done = 0; 1238 1239 while (done < budget) { 1240 struct net_device *netdev; 1241 unsigned int pktlen; 1242 dma_addr_t dma_addr; 1243 int mac; 1244 1245 ring = mtk_get_rx_ring(eth); 1246 if (unlikely(!ring)) 1247 goto rx_done; 1248 1249 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1250 rxd = &ring->dma[idx]; 1251 data = ring->data[idx]; 1252 1253 mtk_rx_get_desc(&trxd, rxd); 1254 if (!(trxd.rxd2 & RX_DMA_DONE)) 1255 break; 1256 1257 /* find out which mac the packet come from. values start at 1 */ 1258 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 1259 mac = 0; 1260 } else { 1261 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 1262 RX_DMA_FPORT_MASK; 1263 mac--; 1264 } 1265 1266 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1267 !eth->netdev[mac])) 1268 goto release_desc; 1269 1270 netdev = eth->netdev[mac]; 1271 1272 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1273 goto release_desc; 1274 1275 /* alloc new buffer */ 1276 new_data = napi_alloc_frag(ring->frag_size); 1277 if (unlikely(!new_data)) { 1278 netdev->stats.rx_dropped++; 1279 goto release_desc; 1280 } 1281 dma_addr = dma_map_single(eth->dev, 1282 new_data + NET_SKB_PAD + 1283 eth->ip_align, 1284 ring->buf_size, 1285 DMA_FROM_DEVICE); 1286 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 1287 skb_free_frag(new_data); 1288 netdev->stats.rx_dropped++; 1289 goto release_desc; 1290 } 1291 1292 /* receive data */ 1293 skb = build_skb(data, ring->frag_size); 1294 if (unlikely(!skb)) { 1295 skb_free_frag(new_data); 1296 netdev->stats.rx_dropped++; 1297 goto release_desc; 1298 } 1299 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1300 1301 dma_unmap_single(eth->dev, trxd.rxd1, 1302 ring->buf_size, DMA_FROM_DEVICE); 1303 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1304 skb->dev = netdev; 1305 skb_put(skb, pktlen); 1306 if (trxd.rxd4 & eth->rx_dma_l4_valid) 1307 skb->ip_summed = CHECKSUM_UNNECESSARY; 1308 else 1309 skb_checksum_none_assert(skb); 1310 skb->protocol = eth_type_trans(skb, netdev); 1311 1312 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1313 RX_DMA_VID(trxd.rxd3)) 1314 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1315 RX_DMA_VID(trxd.rxd3)); 1316 skb_record_rx_queue(skb, 0); 1317 napi_gro_receive(napi, skb); 1318 1319 ring->data[idx] = new_data; 1320 rxd->rxd1 = (unsigned int)dma_addr; 1321 1322 release_desc: 1323 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1324 rxd->rxd2 = RX_DMA_LSO; 1325 else 1326 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1327 1328 ring->calc_idx = idx; 1329 1330 done++; 1331 } 1332 1333 rx_done: 1334 if (done) { 1335 /* make sure that all changes to the dma ring are flushed before 1336 * we continue 1337 */ 1338 wmb(); 1339 mtk_update_rx_cpu_idx(eth); 1340 } 1341 1342 return done; 1343 } 1344 1345 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 1346 unsigned int *done, unsigned int *bytes) 1347 { 1348 struct mtk_tx_ring *ring = ð->tx_ring; 1349 struct mtk_tx_dma *desc; 1350 struct sk_buff *skb; 1351 struct mtk_tx_buf *tx_buf; 1352 u32 cpu, dma; 1353 1354 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1355 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1356 1357 desc = mtk_qdma_phys_to_virt(ring, cpu); 1358 1359 while ((cpu != dma) && budget) { 1360 u32 next_cpu = desc->txd2; 1361 int mac = 0; 1362 1363 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1364 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1365 break; 1366 1367 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1368 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1369 mac = 1; 1370 1371 skb = tx_buf->skb; 1372 if (!skb) 1373 break; 1374 1375 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1376 bytes[mac] += skb->len; 1377 done[mac]++; 1378 budget--; 1379 } 1380 mtk_tx_unmap(eth, tx_buf); 1381 1382 ring->last_free = desc; 1383 atomic_inc(&ring->free_count); 1384 1385 cpu = next_cpu; 1386 } 1387 1388 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1389 1390 return budget; 1391 } 1392 1393 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 1394 unsigned int *done, unsigned int *bytes) 1395 { 1396 struct mtk_tx_ring *ring = ð->tx_ring; 1397 struct mtk_tx_dma *desc; 1398 struct sk_buff *skb; 1399 struct mtk_tx_buf *tx_buf; 1400 u32 cpu, dma; 1401 1402 cpu = ring->cpu_idx; 1403 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 1404 1405 while ((cpu != dma) && budget) { 1406 tx_buf = &ring->buf[cpu]; 1407 skb = tx_buf->skb; 1408 if (!skb) 1409 break; 1410 1411 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1412 bytes[0] += skb->len; 1413 done[0]++; 1414 budget--; 1415 } 1416 1417 mtk_tx_unmap(eth, tx_buf); 1418 1419 desc = &ring->dma[cpu]; 1420 ring->last_free = desc; 1421 atomic_inc(&ring->free_count); 1422 1423 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 1424 } 1425 1426 ring->cpu_idx = cpu; 1427 1428 return budget; 1429 } 1430 1431 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1432 { 1433 struct mtk_tx_ring *ring = ð->tx_ring; 1434 unsigned int done[MTK_MAX_DEVS]; 1435 unsigned int bytes[MTK_MAX_DEVS]; 1436 int total = 0, i; 1437 1438 memset(done, 0, sizeof(done)); 1439 memset(bytes, 0, sizeof(bytes)); 1440 1441 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1442 budget = mtk_poll_tx_qdma(eth, budget, done, bytes); 1443 else 1444 budget = mtk_poll_tx_pdma(eth, budget, done, bytes); 1445 1446 for (i = 0; i < MTK_MAC_COUNT; i++) { 1447 if (!eth->netdev[i] || !done[i]) 1448 continue; 1449 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1450 total += done[i]; 1451 } 1452 1453 if (mtk_queue_stopped(eth) && 1454 (atomic_read(&ring->free_count) > ring->thresh)) 1455 mtk_wake_queue(eth); 1456 1457 return total; 1458 } 1459 1460 static void mtk_handle_status_irq(struct mtk_eth *eth) 1461 { 1462 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1463 1464 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1465 mtk_stats_update(eth); 1466 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1467 MTK_INT_STATUS2); 1468 } 1469 } 1470 1471 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1472 { 1473 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1474 u32 status, mask; 1475 int tx_done = 0; 1476 1477 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1478 mtk_handle_status_irq(eth); 1479 mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg); 1480 tx_done = mtk_poll_tx(eth, budget); 1481 1482 if (unlikely(netif_msg_intr(eth))) { 1483 status = mtk_r32(eth, eth->tx_int_status_reg); 1484 mask = mtk_r32(eth, eth->tx_int_mask_reg); 1485 dev_info(eth->dev, 1486 "done tx %d, intr 0x%08x/0x%x\n", 1487 tx_done, status, mask); 1488 } 1489 1490 if (tx_done == budget) 1491 return budget; 1492 1493 status = mtk_r32(eth, eth->tx_int_status_reg); 1494 if (status & MTK_TX_DONE_INT) 1495 return budget; 1496 1497 napi_complete(napi); 1498 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1499 1500 return tx_done; 1501 } 1502 1503 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1504 { 1505 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1506 u32 status, mask; 1507 int rx_done = 0; 1508 int remain_budget = budget; 1509 1510 mtk_handle_status_irq(eth); 1511 1512 poll_again: 1513 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1514 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1515 1516 if (unlikely(netif_msg_intr(eth))) { 1517 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1518 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1519 dev_info(eth->dev, 1520 "done rx %d, intr 0x%08x/0x%x\n", 1521 rx_done, status, mask); 1522 } 1523 if (rx_done == remain_budget) 1524 return budget; 1525 1526 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1527 if (status & MTK_RX_DONE_INT) { 1528 remain_budget -= rx_done; 1529 goto poll_again; 1530 } 1531 napi_complete(napi); 1532 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1533 1534 return rx_done + budget - remain_budget; 1535 } 1536 1537 static int mtk_tx_alloc(struct mtk_eth *eth) 1538 { 1539 struct mtk_tx_ring *ring = ð->tx_ring; 1540 int i, sz = sizeof(*ring->dma); 1541 1542 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1543 GFP_KERNEL); 1544 if (!ring->buf) 1545 goto no_tx_mem; 1546 1547 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1548 &ring->phys, GFP_ATOMIC); 1549 if (!ring->dma) 1550 goto no_tx_mem; 1551 1552 for (i = 0; i < MTK_DMA_SIZE; i++) { 1553 int next = (i + 1) % MTK_DMA_SIZE; 1554 u32 next_ptr = ring->phys + next * sz; 1555 1556 ring->dma[i].txd2 = next_ptr; 1557 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1558 } 1559 1560 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 1561 * only as the framework. The real HW descriptors are the PDMA 1562 * descriptors in ring->dma_pdma. 1563 */ 1564 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1565 ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1566 &ring->phys_pdma, 1567 GFP_ATOMIC); 1568 if (!ring->dma_pdma) 1569 goto no_tx_mem; 1570 1571 for (i = 0; i < MTK_DMA_SIZE; i++) { 1572 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 1573 ring->dma_pdma[i].txd4 = 0; 1574 } 1575 } 1576 1577 ring->dma_size = MTK_DMA_SIZE; 1578 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1579 ring->next_free = &ring->dma[0]; 1580 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1581 ring->thresh = MAX_SKB_FRAGS; 1582 1583 /* make sure that all changes to the dma ring are flushed before we 1584 * continue 1585 */ 1586 wmb(); 1587 1588 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1589 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1590 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1591 mtk_w32(eth, 1592 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1593 MTK_QTX_CRX_PTR); 1594 mtk_w32(eth, 1595 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1596 MTK_QTX_DRX_PTR); 1597 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, 1598 MTK_QTX_CFG(0)); 1599 } else { 1600 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 1601 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); 1602 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 1603 mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX); 1604 } 1605 1606 return 0; 1607 1608 no_tx_mem: 1609 return -ENOMEM; 1610 } 1611 1612 static void mtk_tx_clean(struct mtk_eth *eth) 1613 { 1614 struct mtk_tx_ring *ring = ð->tx_ring; 1615 int i; 1616 1617 if (ring->buf) { 1618 for (i = 0; i < MTK_DMA_SIZE; i++) 1619 mtk_tx_unmap(eth, &ring->buf[i]); 1620 kfree(ring->buf); 1621 ring->buf = NULL; 1622 } 1623 1624 if (ring->dma) { 1625 dma_free_coherent(eth->dev, 1626 MTK_DMA_SIZE * sizeof(*ring->dma), 1627 ring->dma, 1628 ring->phys); 1629 ring->dma = NULL; 1630 } 1631 1632 if (ring->dma_pdma) { 1633 dma_free_coherent(eth->dev, 1634 MTK_DMA_SIZE * sizeof(*ring->dma_pdma), 1635 ring->dma_pdma, 1636 ring->phys_pdma); 1637 ring->dma_pdma = NULL; 1638 } 1639 } 1640 1641 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1642 { 1643 struct mtk_rx_ring *ring; 1644 int rx_data_len, rx_dma_size; 1645 int i; 1646 u32 offset = 0; 1647 1648 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1649 if (ring_no) 1650 return -EINVAL; 1651 ring = ð->rx_ring_qdma; 1652 offset = 0x1000; 1653 } else { 1654 ring = ð->rx_ring[ring_no]; 1655 } 1656 1657 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1658 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1659 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1660 } else { 1661 rx_data_len = ETH_DATA_LEN; 1662 rx_dma_size = MTK_DMA_SIZE; 1663 } 1664 1665 ring->frag_size = mtk_max_frag_size(rx_data_len); 1666 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1667 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1668 GFP_KERNEL); 1669 if (!ring->data) 1670 return -ENOMEM; 1671 1672 for (i = 0; i < rx_dma_size; i++) { 1673 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1674 if (!ring->data[i]) 1675 return -ENOMEM; 1676 } 1677 1678 ring->dma = dma_alloc_coherent(eth->dev, 1679 rx_dma_size * sizeof(*ring->dma), 1680 &ring->phys, GFP_ATOMIC); 1681 if (!ring->dma) 1682 return -ENOMEM; 1683 1684 for (i = 0; i < rx_dma_size; i++) { 1685 dma_addr_t dma_addr = dma_map_single(eth->dev, 1686 ring->data[i] + NET_SKB_PAD + eth->ip_align, 1687 ring->buf_size, 1688 DMA_FROM_DEVICE); 1689 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1690 return -ENOMEM; 1691 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1692 1693 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1694 ring->dma[i].rxd2 = RX_DMA_LSO; 1695 else 1696 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1697 } 1698 ring->dma_size = rx_dma_size; 1699 ring->calc_idx_update = false; 1700 ring->calc_idx = rx_dma_size - 1; 1701 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1702 /* make sure that all changes to the dma ring are flushed before we 1703 * continue 1704 */ 1705 wmb(); 1706 1707 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1708 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1709 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1710 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1711 1712 return 0; 1713 } 1714 1715 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1716 { 1717 int i; 1718 1719 if (ring->data && ring->dma) { 1720 for (i = 0; i < ring->dma_size; i++) { 1721 if (!ring->data[i]) 1722 continue; 1723 if (!ring->dma[i].rxd1) 1724 continue; 1725 dma_unmap_single(eth->dev, 1726 ring->dma[i].rxd1, 1727 ring->buf_size, 1728 DMA_FROM_DEVICE); 1729 skb_free_frag(ring->data[i]); 1730 } 1731 kfree(ring->data); 1732 ring->data = NULL; 1733 } 1734 1735 if (ring->dma) { 1736 dma_free_coherent(eth->dev, 1737 ring->dma_size * sizeof(*ring->dma), 1738 ring->dma, 1739 ring->phys); 1740 ring->dma = NULL; 1741 } 1742 } 1743 1744 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1745 { 1746 int i; 1747 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1748 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1749 1750 /* set LRO rings to auto-learn modes */ 1751 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1752 1753 /* validate LRO ring */ 1754 ring_ctrl_dw2 |= MTK_RING_VLD; 1755 1756 /* set AGE timer (unit: 20us) */ 1757 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1758 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1759 1760 /* set max AGG timer (unit: 20us) */ 1761 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1762 1763 /* set max LRO AGG count */ 1764 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1765 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1766 1767 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1768 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1769 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1770 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1771 } 1772 1773 /* IPv4 checksum update enable */ 1774 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1775 1776 /* switch priority comparison to packet count mode */ 1777 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1778 1779 /* bandwidth threshold setting */ 1780 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1781 1782 /* auto-learn score delta setting */ 1783 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1784 1785 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1786 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1787 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1788 1789 /* set HW LRO mode & the max aggregation count for rx packets */ 1790 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1791 1792 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1793 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1794 1795 /* enable HW LRO */ 1796 lro_ctrl_dw0 |= MTK_LRO_EN; 1797 1798 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1799 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1800 1801 return 0; 1802 } 1803 1804 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1805 { 1806 int i; 1807 u32 val; 1808 1809 /* relinquish lro rings, flush aggregated packets */ 1810 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1811 1812 /* wait for relinquishments done */ 1813 for (i = 0; i < 10; i++) { 1814 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1815 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1816 msleep(20); 1817 continue; 1818 } 1819 break; 1820 } 1821 1822 /* invalidate lro rings */ 1823 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1824 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1825 1826 /* disable HW LRO */ 1827 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1828 } 1829 1830 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1831 { 1832 u32 reg_val; 1833 1834 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1835 1836 /* invalidate the IP setting */ 1837 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1838 1839 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1840 1841 /* validate the IP setting */ 1842 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1843 } 1844 1845 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1846 { 1847 u32 reg_val; 1848 1849 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1850 1851 /* invalidate the IP setting */ 1852 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1853 1854 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1855 } 1856 1857 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1858 { 1859 int cnt = 0; 1860 int i; 1861 1862 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1863 if (mac->hwlro_ip[i]) 1864 cnt++; 1865 } 1866 1867 return cnt; 1868 } 1869 1870 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1871 struct ethtool_rxnfc *cmd) 1872 { 1873 struct ethtool_rx_flow_spec *fsp = 1874 (struct ethtool_rx_flow_spec *)&cmd->fs; 1875 struct mtk_mac *mac = netdev_priv(dev); 1876 struct mtk_eth *eth = mac->hw; 1877 int hwlro_idx; 1878 1879 if ((fsp->flow_type != TCP_V4_FLOW) || 1880 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1881 (fsp->location > 1)) 1882 return -EINVAL; 1883 1884 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1885 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1886 1887 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1888 1889 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1890 1891 return 0; 1892 } 1893 1894 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1895 struct ethtool_rxnfc *cmd) 1896 { 1897 struct ethtool_rx_flow_spec *fsp = 1898 (struct ethtool_rx_flow_spec *)&cmd->fs; 1899 struct mtk_mac *mac = netdev_priv(dev); 1900 struct mtk_eth *eth = mac->hw; 1901 int hwlro_idx; 1902 1903 if (fsp->location > 1) 1904 return -EINVAL; 1905 1906 mac->hwlro_ip[fsp->location] = 0; 1907 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1908 1909 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1910 1911 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1912 1913 return 0; 1914 } 1915 1916 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1917 { 1918 struct mtk_mac *mac = netdev_priv(dev); 1919 struct mtk_eth *eth = mac->hw; 1920 int i, hwlro_idx; 1921 1922 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1923 mac->hwlro_ip[i] = 0; 1924 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1925 1926 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1927 } 1928 1929 mac->hwlro_ip_cnt = 0; 1930 } 1931 1932 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1933 struct ethtool_rxnfc *cmd) 1934 { 1935 struct mtk_mac *mac = netdev_priv(dev); 1936 struct ethtool_rx_flow_spec *fsp = 1937 (struct ethtool_rx_flow_spec *)&cmd->fs; 1938 1939 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1940 fsp->flow_type = TCP_V4_FLOW; 1941 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1942 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1943 1944 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1945 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1946 fsp->h_u.tcp_ip4_spec.psrc = 0; 1947 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1948 fsp->h_u.tcp_ip4_spec.pdst = 0; 1949 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1950 fsp->h_u.tcp_ip4_spec.tos = 0; 1951 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1952 1953 return 0; 1954 } 1955 1956 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1957 struct ethtool_rxnfc *cmd, 1958 u32 *rule_locs) 1959 { 1960 struct mtk_mac *mac = netdev_priv(dev); 1961 int cnt = 0; 1962 int i; 1963 1964 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1965 if (mac->hwlro_ip[i]) { 1966 rule_locs[cnt] = i; 1967 cnt++; 1968 } 1969 } 1970 1971 cmd->rule_cnt = cnt; 1972 1973 return 0; 1974 } 1975 1976 static netdev_features_t mtk_fix_features(struct net_device *dev, 1977 netdev_features_t features) 1978 { 1979 if (!(features & NETIF_F_LRO)) { 1980 struct mtk_mac *mac = netdev_priv(dev); 1981 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1982 1983 if (ip_cnt) { 1984 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1985 1986 features |= NETIF_F_LRO; 1987 } 1988 } 1989 1990 return features; 1991 } 1992 1993 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1994 { 1995 int err = 0; 1996 1997 if (!((dev->features ^ features) & NETIF_F_LRO)) 1998 return 0; 1999 2000 if (!(features & NETIF_F_LRO)) 2001 mtk_hwlro_netdev_disable(dev); 2002 2003 return err; 2004 } 2005 2006 /* wait for DMA to finish whatever it is doing before we start using it again */ 2007 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2008 { 2009 unsigned long t_start = jiffies; 2010 2011 while (1) { 2012 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2013 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 2014 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 2015 return 0; 2016 } else { 2017 if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) & 2018 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 2019 return 0; 2020 } 2021 2022 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 2023 break; 2024 } 2025 2026 dev_err(eth->dev, "DMA init timeout\n"); 2027 return -1; 2028 } 2029 2030 static int mtk_dma_init(struct mtk_eth *eth) 2031 { 2032 int err; 2033 u32 i; 2034 2035 if (mtk_dma_busy_wait(eth)) 2036 return -EBUSY; 2037 2038 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2039 /* QDMA needs scratch memory for internal reordering of the 2040 * descriptors 2041 */ 2042 err = mtk_init_fq_dma(eth); 2043 if (err) 2044 return err; 2045 } 2046 2047 err = mtk_tx_alloc(eth); 2048 if (err) 2049 return err; 2050 2051 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2052 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2053 if (err) 2054 return err; 2055 } 2056 2057 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2058 if (err) 2059 return err; 2060 2061 if (eth->hwlro) { 2062 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2063 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2064 if (err) 2065 return err; 2066 } 2067 err = mtk_hwlro_rx_init(eth); 2068 if (err) 2069 return err; 2070 } 2071 2072 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2073 /* Enable random early drop and set drop threshold 2074 * automatically 2075 */ 2076 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2077 FC_THRES_MIN, MTK_QDMA_FC_THRES); 2078 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 2079 } 2080 2081 return 0; 2082 } 2083 2084 static void mtk_dma_free(struct mtk_eth *eth) 2085 { 2086 int i; 2087 2088 for (i = 0; i < MTK_MAC_COUNT; i++) 2089 if (eth->netdev[i]) 2090 netdev_reset_queue(eth->netdev[i]); 2091 if (eth->scratch_ring) { 2092 dma_free_coherent(eth->dev, 2093 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 2094 eth->scratch_ring, 2095 eth->phy_scratch_ring); 2096 eth->scratch_ring = NULL; 2097 eth->phy_scratch_ring = 0; 2098 } 2099 mtk_tx_clean(eth); 2100 mtk_rx_clean(eth, ð->rx_ring[0]); 2101 mtk_rx_clean(eth, ð->rx_ring_qdma); 2102 2103 if (eth->hwlro) { 2104 mtk_hwlro_rx_uninit(eth); 2105 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2106 mtk_rx_clean(eth, ð->rx_ring[i]); 2107 } 2108 2109 kfree(eth->scratch_head); 2110 } 2111 2112 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 2113 { 2114 struct mtk_mac *mac = netdev_priv(dev); 2115 struct mtk_eth *eth = mac->hw; 2116 2117 eth->netdev[mac->id]->stats.tx_errors++; 2118 netif_err(eth, tx_err, dev, 2119 "transmit timed out\n"); 2120 schedule_work(ð->pending_work); 2121 } 2122 2123 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 2124 { 2125 struct mtk_eth *eth = _eth; 2126 2127 if (likely(napi_schedule_prep(ð->rx_napi))) { 2128 __napi_schedule(ð->rx_napi); 2129 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2130 } 2131 2132 return IRQ_HANDLED; 2133 } 2134 2135 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 2136 { 2137 struct mtk_eth *eth = _eth; 2138 2139 if (likely(napi_schedule_prep(ð->tx_napi))) { 2140 __napi_schedule(ð->tx_napi); 2141 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2142 } 2143 2144 return IRQ_HANDLED; 2145 } 2146 2147 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 2148 { 2149 struct mtk_eth *eth = _eth; 2150 2151 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { 2152 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) 2153 mtk_handle_irq_rx(irq, _eth); 2154 } 2155 if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) { 2156 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) 2157 mtk_handle_irq_tx(irq, _eth); 2158 } 2159 2160 return IRQ_HANDLED; 2161 } 2162 2163 #ifdef CONFIG_NET_POLL_CONTROLLER 2164 static void mtk_poll_controller(struct net_device *dev) 2165 { 2166 struct mtk_mac *mac = netdev_priv(dev); 2167 struct mtk_eth *eth = mac->hw; 2168 2169 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2170 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2171 mtk_handle_irq_rx(eth->irq[2], dev); 2172 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2173 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2174 } 2175 #endif 2176 2177 static int mtk_start_dma(struct mtk_eth *eth) 2178 { 2179 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 2180 int err; 2181 2182 err = mtk_dma_init(eth); 2183 if (err) { 2184 mtk_dma_free(eth); 2185 return err; 2186 } 2187 2188 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2189 mtk_w32(eth, 2190 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 2191 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | 2192 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 2193 MTK_RX_BT_32DWORDS, 2194 MTK_QDMA_GLO_CFG); 2195 2196 mtk_w32(eth, 2197 MTK_RX_DMA_EN | rx_2b_offset | 2198 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 2199 MTK_PDMA_GLO_CFG); 2200 } else { 2201 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2202 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 2203 MTK_PDMA_GLO_CFG); 2204 } 2205 2206 return 0; 2207 } 2208 2209 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 2210 { 2211 int i; 2212 2213 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2214 return; 2215 2216 for (i = 0; i < MTK_MAC_COUNT; i++) { 2217 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 2218 2219 /* default setup the forward port to send frame to PDMA */ 2220 val &= ~0xffff; 2221 2222 /* Enable RX checksum */ 2223 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2224 2225 val |= config; 2226 2227 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2228 } 2229 /* Reset and enable PSE */ 2230 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 2231 mtk_w32(eth, 0, MTK_RST_GL); 2232 } 2233 2234 static int mtk_open(struct net_device *dev) 2235 { 2236 struct mtk_mac *mac = netdev_priv(dev); 2237 struct mtk_eth *eth = mac->hw; 2238 int err; 2239 2240 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 2241 if (err) { 2242 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 2243 err); 2244 return err; 2245 } 2246 2247 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 2248 if (!refcount_read(ð->dma_refcnt)) { 2249 int err = mtk_start_dma(eth); 2250 2251 if (err) 2252 return err; 2253 2254 mtk_gdm_config(eth, MTK_GDMA_TO_PDMA); 2255 2256 napi_enable(ð->tx_napi); 2257 napi_enable(ð->rx_napi); 2258 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2259 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2260 refcount_set(ð->dma_refcnt, 1); 2261 } 2262 else 2263 refcount_inc(ð->dma_refcnt); 2264 2265 phylink_start(mac->phylink); 2266 netif_start_queue(dev); 2267 return 0; 2268 } 2269 2270 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 2271 { 2272 u32 val; 2273 int i; 2274 2275 /* stop the dma engine */ 2276 spin_lock_bh(ð->page_lock); 2277 val = mtk_r32(eth, glo_cfg); 2278 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 2279 glo_cfg); 2280 spin_unlock_bh(ð->page_lock); 2281 2282 /* wait for dma stop */ 2283 for (i = 0; i < 10; i++) { 2284 val = mtk_r32(eth, glo_cfg); 2285 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 2286 msleep(20); 2287 continue; 2288 } 2289 break; 2290 } 2291 } 2292 2293 static int mtk_stop(struct net_device *dev) 2294 { 2295 struct mtk_mac *mac = netdev_priv(dev); 2296 struct mtk_eth *eth = mac->hw; 2297 2298 phylink_stop(mac->phylink); 2299 2300 netif_tx_disable(dev); 2301 2302 phylink_disconnect_phy(mac->phylink); 2303 2304 /* only shutdown DMA if this is the last user */ 2305 if (!refcount_dec_and_test(ð->dma_refcnt)) 2306 return 0; 2307 2308 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 2309 2310 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2311 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2312 napi_disable(ð->tx_napi); 2313 napi_disable(ð->rx_napi); 2314 2315 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2316 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 2317 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 2318 2319 mtk_dma_free(eth); 2320 2321 return 0; 2322 } 2323 2324 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 2325 { 2326 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2327 reset_bits, 2328 reset_bits); 2329 2330 usleep_range(1000, 1100); 2331 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2332 reset_bits, 2333 ~reset_bits); 2334 mdelay(10); 2335 } 2336 2337 static void mtk_clk_disable(struct mtk_eth *eth) 2338 { 2339 int clk; 2340 2341 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 2342 clk_disable_unprepare(eth->clks[clk]); 2343 } 2344 2345 static int mtk_clk_enable(struct mtk_eth *eth) 2346 { 2347 int clk, ret; 2348 2349 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 2350 ret = clk_prepare_enable(eth->clks[clk]); 2351 if (ret) 2352 goto err_disable_clks; 2353 } 2354 2355 return 0; 2356 2357 err_disable_clks: 2358 while (--clk >= 0) 2359 clk_disable_unprepare(eth->clks[clk]); 2360 2361 return ret; 2362 } 2363 2364 static int mtk_hw_init(struct mtk_eth *eth) 2365 { 2366 int i, val, ret; 2367 2368 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 2369 return 0; 2370 2371 pm_runtime_enable(eth->dev); 2372 pm_runtime_get_sync(eth->dev); 2373 2374 ret = mtk_clk_enable(eth); 2375 if (ret) 2376 goto err_disable_pm; 2377 2378 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2379 ret = device_reset(eth->dev); 2380 if (ret) { 2381 dev_err(eth->dev, "MAC reset failed!\n"); 2382 goto err_disable_pm; 2383 } 2384 2385 /* enable interrupt delay for RX */ 2386 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 2387 2388 /* disable delay and normal interrupt */ 2389 mtk_tx_irq_disable(eth, ~0); 2390 mtk_rx_irq_disable(eth, ~0); 2391 2392 return 0; 2393 } 2394 2395 /* Non-MT7628 handling... */ 2396 ethsys_reset(eth, RSTCTRL_FE); 2397 ethsys_reset(eth, RSTCTRL_PPE); 2398 2399 if (eth->pctl) { 2400 /* Set GE2 driving and slew rate */ 2401 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 2402 2403 /* set GE2 TDSEL */ 2404 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 2405 2406 /* set GE2 TUNE */ 2407 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 2408 } 2409 2410 /* Set linkdown as the default for each GMAC. Its own MCR would be set 2411 * up with the more appropriate value when mtk_mac_config call is being 2412 * invoked. 2413 */ 2414 for (i = 0; i < MTK_MAC_COUNT; i++) 2415 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 2416 2417 /* Indicates CDM to parse the MTK special tag from CPU 2418 * which also is working out for untag packets. 2419 */ 2420 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 2421 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 2422 2423 /* Enable RX VLan Offloading */ 2424 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 2425 2426 /* enable interrupt delay for RX */ 2427 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 2428 2429 /* disable delay and normal interrupt */ 2430 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 2431 mtk_tx_irq_disable(eth, ~0); 2432 mtk_rx_irq_disable(eth, ~0); 2433 2434 /* FE int grouping */ 2435 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 2436 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 2437 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 2438 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 2439 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 2440 2441 return 0; 2442 2443 err_disable_pm: 2444 pm_runtime_put_sync(eth->dev); 2445 pm_runtime_disable(eth->dev); 2446 2447 return ret; 2448 } 2449 2450 static int mtk_hw_deinit(struct mtk_eth *eth) 2451 { 2452 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2453 return 0; 2454 2455 mtk_clk_disable(eth); 2456 2457 pm_runtime_put_sync(eth->dev); 2458 pm_runtime_disable(eth->dev); 2459 2460 return 0; 2461 } 2462 2463 static int __init mtk_init(struct net_device *dev) 2464 { 2465 struct mtk_mac *mac = netdev_priv(dev); 2466 struct mtk_eth *eth = mac->hw; 2467 const char *mac_addr; 2468 2469 mac_addr = of_get_mac_address(mac->of_node); 2470 if (!IS_ERR(mac_addr)) 2471 ether_addr_copy(dev->dev_addr, mac_addr); 2472 2473 /* If the mac address is invalid, use random mac address */ 2474 if (!is_valid_ether_addr(dev->dev_addr)) { 2475 eth_hw_addr_random(dev); 2476 dev_err(eth->dev, "generated random MAC address %pM\n", 2477 dev->dev_addr); 2478 } 2479 2480 return 0; 2481 } 2482 2483 static void mtk_uninit(struct net_device *dev) 2484 { 2485 struct mtk_mac *mac = netdev_priv(dev); 2486 struct mtk_eth *eth = mac->hw; 2487 2488 phylink_disconnect_phy(mac->phylink); 2489 mtk_tx_irq_disable(eth, ~0); 2490 mtk_rx_irq_disable(eth, ~0); 2491 } 2492 2493 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2494 { 2495 struct mtk_mac *mac = netdev_priv(dev); 2496 2497 switch (cmd) { 2498 case SIOCGMIIPHY: 2499 case SIOCGMIIREG: 2500 case SIOCSMIIREG: 2501 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 2502 default: 2503 break; 2504 } 2505 2506 return -EOPNOTSUPP; 2507 } 2508 2509 static void mtk_pending_work(struct work_struct *work) 2510 { 2511 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2512 int err, i; 2513 unsigned long restart = 0; 2514 2515 rtnl_lock(); 2516 2517 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2518 2519 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2520 cpu_relax(); 2521 2522 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2523 /* stop all devices to make sure that dma is properly shut down */ 2524 for (i = 0; i < MTK_MAC_COUNT; i++) { 2525 if (!eth->netdev[i]) 2526 continue; 2527 mtk_stop(eth->netdev[i]); 2528 __set_bit(i, &restart); 2529 } 2530 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2531 2532 /* restart underlying hardware such as power, clock, pin mux 2533 * and the connected phy 2534 */ 2535 mtk_hw_deinit(eth); 2536 2537 if (eth->dev->pins) 2538 pinctrl_select_state(eth->dev->pins->p, 2539 eth->dev->pins->default_state); 2540 mtk_hw_init(eth); 2541 2542 /* restart DMA and enable IRQs */ 2543 for (i = 0; i < MTK_MAC_COUNT; i++) { 2544 if (!test_bit(i, &restart)) 2545 continue; 2546 err = mtk_open(eth->netdev[i]); 2547 if (err) { 2548 netif_alert(eth, ifup, eth->netdev[i], 2549 "Driver up/down cycle failed, closing device.\n"); 2550 dev_close(eth->netdev[i]); 2551 } 2552 } 2553 2554 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2555 2556 clear_bit_unlock(MTK_RESETTING, ð->state); 2557 2558 rtnl_unlock(); 2559 } 2560 2561 static int mtk_free_dev(struct mtk_eth *eth) 2562 { 2563 int i; 2564 2565 for (i = 0; i < MTK_MAC_COUNT; i++) { 2566 if (!eth->netdev[i]) 2567 continue; 2568 free_netdev(eth->netdev[i]); 2569 } 2570 2571 return 0; 2572 } 2573 2574 static int mtk_unreg_dev(struct mtk_eth *eth) 2575 { 2576 int i; 2577 2578 for (i = 0; i < MTK_MAC_COUNT; i++) { 2579 if (!eth->netdev[i]) 2580 continue; 2581 unregister_netdev(eth->netdev[i]); 2582 } 2583 2584 return 0; 2585 } 2586 2587 static int mtk_cleanup(struct mtk_eth *eth) 2588 { 2589 mtk_unreg_dev(eth); 2590 mtk_free_dev(eth); 2591 cancel_work_sync(ð->pending_work); 2592 2593 return 0; 2594 } 2595 2596 static int mtk_get_link_ksettings(struct net_device *ndev, 2597 struct ethtool_link_ksettings *cmd) 2598 { 2599 struct mtk_mac *mac = netdev_priv(ndev); 2600 2601 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2602 return -EBUSY; 2603 2604 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 2605 } 2606 2607 static int mtk_set_link_ksettings(struct net_device *ndev, 2608 const struct ethtool_link_ksettings *cmd) 2609 { 2610 struct mtk_mac *mac = netdev_priv(ndev); 2611 2612 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2613 return -EBUSY; 2614 2615 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 2616 } 2617 2618 static void mtk_get_drvinfo(struct net_device *dev, 2619 struct ethtool_drvinfo *info) 2620 { 2621 struct mtk_mac *mac = netdev_priv(dev); 2622 2623 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2624 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2625 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2626 } 2627 2628 static u32 mtk_get_msglevel(struct net_device *dev) 2629 { 2630 struct mtk_mac *mac = netdev_priv(dev); 2631 2632 return mac->hw->msg_enable; 2633 } 2634 2635 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2636 { 2637 struct mtk_mac *mac = netdev_priv(dev); 2638 2639 mac->hw->msg_enable = value; 2640 } 2641 2642 static int mtk_nway_reset(struct net_device *dev) 2643 { 2644 struct mtk_mac *mac = netdev_priv(dev); 2645 2646 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2647 return -EBUSY; 2648 2649 if (!mac->phylink) 2650 return -ENOTSUPP; 2651 2652 return phylink_ethtool_nway_reset(mac->phylink); 2653 } 2654 2655 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2656 { 2657 int i; 2658 2659 switch (stringset) { 2660 case ETH_SS_STATS: 2661 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2662 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2663 data += ETH_GSTRING_LEN; 2664 } 2665 break; 2666 } 2667 } 2668 2669 static int mtk_get_sset_count(struct net_device *dev, int sset) 2670 { 2671 switch (sset) { 2672 case ETH_SS_STATS: 2673 return ARRAY_SIZE(mtk_ethtool_stats); 2674 default: 2675 return -EOPNOTSUPP; 2676 } 2677 } 2678 2679 static void mtk_get_ethtool_stats(struct net_device *dev, 2680 struct ethtool_stats *stats, u64 *data) 2681 { 2682 struct mtk_mac *mac = netdev_priv(dev); 2683 struct mtk_hw_stats *hwstats = mac->hw_stats; 2684 u64 *data_src, *data_dst; 2685 unsigned int start; 2686 int i; 2687 2688 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2689 return; 2690 2691 if (netif_running(dev) && netif_device_present(dev)) { 2692 if (spin_trylock_bh(&hwstats->stats_lock)) { 2693 mtk_stats_update_mac(mac); 2694 spin_unlock_bh(&hwstats->stats_lock); 2695 } 2696 } 2697 2698 data_src = (u64 *)hwstats; 2699 2700 do { 2701 data_dst = data; 2702 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2703 2704 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2705 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2706 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2707 } 2708 2709 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2710 u32 *rule_locs) 2711 { 2712 int ret = -EOPNOTSUPP; 2713 2714 switch (cmd->cmd) { 2715 case ETHTOOL_GRXRINGS: 2716 if (dev->hw_features & NETIF_F_LRO) { 2717 cmd->data = MTK_MAX_RX_RING_NUM; 2718 ret = 0; 2719 } 2720 break; 2721 case ETHTOOL_GRXCLSRLCNT: 2722 if (dev->hw_features & NETIF_F_LRO) { 2723 struct mtk_mac *mac = netdev_priv(dev); 2724 2725 cmd->rule_cnt = mac->hwlro_ip_cnt; 2726 ret = 0; 2727 } 2728 break; 2729 case ETHTOOL_GRXCLSRULE: 2730 if (dev->hw_features & NETIF_F_LRO) 2731 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2732 break; 2733 case ETHTOOL_GRXCLSRLALL: 2734 if (dev->hw_features & NETIF_F_LRO) 2735 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2736 rule_locs); 2737 break; 2738 default: 2739 break; 2740 } 2741 2742 return ret; 2743 } 2744 2745 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2746 { 2747 int ret = -EOPNOTSUPP; 2748 2749 switch (cmd->cmd) { 2750 case ETHTOOL_SRXCLSRLINS: 2751 if (dev->hw_features & NETIF_F_LRO) 2752 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2753 break; 2754 case ETHTOOL_SRXCLSRLDEL: 2755 if (dev->hw_features & NETIF_F_LRO) 2756 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2757 break; 2758 default: 2759 break; 2760 } 2761 2762 return ret; 2763 } 2764 2765 static const struct ethtool_ops mtk_ethtool_ops = { 2766 .get_link_ksettings = mtk_get_link_ksettings, 2767 .set_link_ksettings = mtk_set_link_ksettings, 2768 .get_drvinfo = mtk_get_drvinfo, 2769 .get_msglevel = mtk_get_msglevel, 2770 .set_msglevel = mtk_set_msglevel, 2771 .nway_reset = mtk_nway_reset, 2772 .get_link = ethtool_op_get_link, 2773 .get_strings = mtk_get_strings, 2774 .get_sset_count = mtk_get_sset_count, 2775 .get_ethtool_stats = mtk_get_ethtool_stats, 2776 .get_rxnfc = mtk_get_rxnfc, 2777 .set_rxnfc = mtk_set_rxnfc, 2778 }; 2779 2780 static const struct net_device_ops mtk_netdev_ops = { 2781 .ndo_init = mtk_init, 2782 .ndo_uninit = mtk_uninit, 2783 .ndo_open = mtk_open, 2784 .ndo_stop = mtk_stop, 2785 .ndo_start_xmit = mtk_start_xmit, 2786 .ndo_set_mac_address = mtk_set_mac_address, 2787 .ndo_validate_addr = eth_validate_addr, 2788 .ndo_do_ioctl = mtk_do_ioctl, 2789 .ndo_tx_timeout = mtk_tx_timeout, 2790 .ndo_get_stats64 = mtk_get_stats64, 2791 .ndo_fix_features = mtk_fix_features, 2792 .ndo_set_features = mtk_set_features, 2793 #ifdef CONFIG_NET_POLL_CONTROLLER 2794 .ndo_poll_controller = mtk_poll_controller, 2795 #endif 2796 }; 2797 2798 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2799 { 2800 const __be32 *_id = of_get_property(np, "reg", NULL); 2801 phy_interface_t phy_mode; 2802 struct phylink *phylink; 2803 struct mtk_mac *mac; 2804 int id, err; 2805 2806 if (!_id) { 2807 dev_err(eth->dev, "missing mac id\n"); 2808 return -EINVAL; 2809 } 2810 2811 id = be32_to_cpup(_id); 2812 if (id >= MTK_MAC_COUNT) { 2813 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2814 return -EINVAL; 2815 } 2816 2817 if (eth->netdev[id]) { 2818 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2819 return -EINVAL; 2820 } 2821 2822 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2823 if (!eth->netdev[id]) { 2824 dev_err(eth->dev, "alloc_etherdev failed\n"); 2825 return -ENOMEM; 2826 } 2827 mac = netdev_priv(eth->netdev[id]); 2828 eth->mac[id] = mac; 2829 mac->id = id; 2830 mac->hw = eth; 2831 mac->of_node = np; 2832 2833 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2834 mac->hwlro_ip_cnt = 0; 2835 2836 mac->hw_stats = devm_kzalloc(eth->dev, 2837 sizeof(*mac->hw_stats), 2838 GFP_KERNEL); 2839 if (!mac->hw_stats) { 2840 dev_err(eth->dev, "failed to allocate counter memory\n"); 2841 err = -ENOMEM; 2842 goto free_netdev; 2843 } 2844 spin_lock_init(&mac->hw_stats->stats_lock); 2845 u64_stats_init(&mac->hw_stats->syncp); 2846 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2847 2848 /* phylink create */ 2849 err = of_get_phy_mode(np, &phy_mode); 2850 if (err) { 2851 dev_err(eth->dev, "incorrect phy-mode\n"); 2852 goto free_netdev; 2853 } 2854 2855 /* mac config is not set */ 2856 mac->interface = PHY_INTERFACE_MODE_NA; 2857 mac->mode = MLO_AN_PHY; 2858 mac->speed = SPEED_UNKNOWN; 2859 2860 mac->phylink_config.dev = ð->netdev[id]->dev; 2861 mac->phylink_config.type = PHYLINK_NETDEV; 2862 2863 phylink = phylink_create(&mac->phylink_config, 2864 of_fwnode_handle(mac->of_node), 2865 phy_mode, &mtk_phylink_ops); 2866 if (IS_ERR(phylink)) { 2867 err = PTR_ERR(phylink); 2868 goto free_netdev; 2869 } 2870 2871 mac->phylink = phylink; 2872 2873 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2874 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2875 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2876 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2877 2878 eth->netdev[id]->hw_features = eth->soc->hw_features; 2879 if (eth->hwlro) 2880 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2881 2882 eth->netdev[id]->vlan_features = eth->soc->hw_features & 2883 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2884 eth->netdev[id]->features |= eth->soc->hw_features; 2885 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2886 2887 eth->netdev[id]->irq = eth->irq[0]; 2888 eth->netdev[id]->dev.of_node = np; 2889 2890 return 0; 2891 2892 free_netdev: 2893 free_netdev(eth->netdev[id]); 2894 return err; 2895 } 2896 2897 static int mtk_probe(struct platform_device *pdev) 2898 { 2899 struct device_node *mac_np; 2900 struct mtk_eth *eth; 2901 int err, i; 2902 2903 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2904 if (!eth) 2905 return -ENOMEM; 2906 2907 eth->soc = of_device_get_match_data(&pdev->dev); 2908 2909 eth->dev = &pdev->dev; 2910 eth->base = devm_platform_ioremap_resource(pdev, 0); 2911 if (IS_ERR(eth->base)) 2912 return PTR_ERR(eth->base); 2913 2914 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2915 eth->tx_int_mask_reg = MTK_QDMA_INT_MASK; 2916 eth->tx_int_status_reg = MTK_QDMA_INT_STATUS; 2917 } else { 2918 eth->tx_int_mask_reg = MTK_PDMA_INT_MASK; 2919 eth->tx_int_status_reg = MTK_PDMA_INT_STATUS; 2920 } 2921 2922 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2923 eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA; 2924 eth->ip_align = NET_IP_ALIGN; 2925 } else { 2926 eth->rx_dma_l4_valid = RX_DMA_L4_VALID; 2927 } 2928 2929 spin_lock_init(ð->page_lock); 2930 spin_lock_init(ð->tx_irq_lock); 2931 spin_lock_init(ð->rx_irq_lock); 2932 2933 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2934 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2935 "mediatek,ethsys"); 2936 if (IS_ERR(eth->ethsys)) { 2937 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2938 return PTR_ERR(eth->ethsys); 2939 } 2940 } 2941 2942 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 2943 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2944 "mediatek,infracfg"); 2945 if (IS_ERR(eth->infra)) { 2946 dev_err(&pdev->dev, "no infracfg regmap found\n"); 2947 return PTR_ERR(eth->infra); 2948 } 2949 } 2950 2951 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 2952 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 2953 GFP_KERNEL); 2954 if (!eth->sgmii) 2955 return -ENOMEM; 2956 2957 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 2958 eth->soc->ana_rgc3); 2959 2960 if (err) 2961 return err; 2962 } 2963 2964 if (eth->soc->required_pctl) { 2965 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2966 "mediatek,pctl"); 2967 if (IS_ERR(eth->pctl)) { 2968 dev_err(&pdev->dev, "no pctl regmap found\n"); 2969 return PTR_ERR(eth->pctl); 2970 } 2971 } 2972 2973 for (i = 0; i < 3; i++) { 2974 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 2975 eth->irq[i] = eth->irq[0]; 2976 else 2977 eth->irq[i] = platform_get_irq(pdev, i); 2978 if (eth->irq[i] < 0) { 2979 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2980 return -ENXIO; 2981 } 2982 } 2983 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2984 eth->clks[i] = devm_clk_get(eth->dev, 2985 mtk_clks_source_name[i]); 2986 if (IS_ERR(eth->clks[i])) { 2987 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2988 return -EPROBE_DEFER; 2989 if (eth->soc->required_clks & BIT(i)) { 2990 dev_err(&pdev->dev, "clock %s not found\n", 2991 mtk_clks_source_name[i]); 2992 return -EINVAL; 2993 } 2994 eth->clks[i] = NULL; 2995 } 2996 } 2997 2998 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 2999 INIT_WORK(ð->pending_work, mtk_pending_work); 3000 3001 err = mtk_hw_init(eth); 3002 if (err) 3003 return err; 3004 3005 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 3006 3007 for_each_child_of_node(pdev->dev.of_node, mac_np) { 3008 if (!of_device_is_compatible(mac_np, 3009 "mediatek,eth-mac")) 3010 continue; 3011 3012 if (!of_device_is_available(mac_np)) 3013 continue; 3014 3015 err = mtk_add_mac(eth, mac_np); 3016 if (err) { 3017 of_node_put(mac_np); 3018 goto err_deinit_hw; 3019 } 3020 } 3021 3022 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 3023 err = devm_request_irq(eth->dev, eth->irq[0], 3024 mtk_handle_irq, 0, 3025 dev_name(eth->dev), eth); 3026 } else { 3027 err = devm_request_irq(eth->dev, eth->irq[1], 3028 mtk_handle_irq_tx, 0, 3029 dev_name(eth->dev), eth); 3030 if (err) 3031 goto err_free_dev; 3032 3033 err = devm_request_irq(eth->dev, eth->irq[2], 3034 mtk_handle_irq_rx, 0, 3035 dev_name(eth->dev), eth); 3036 } 3037 if (err) 3038 goto err_free_dev; 3039 3040 /* No MT7628/88 support yet */ 3041 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3042 err = mtk_mdio_init(eth); 3043 if (err) 3044 goto err_free_dev; 3045 } 3046 3047 for (i = 0; i < MTK_MAX_DEVS; i++) { 3048 if (!eth->netdev[i]) 3049 continue; 3050 3051 err = register_netdev(eth->netdev[i]); 3052 if (err) { 3053 dev_err(eth->dev, "error bringing up device\n"); 3054 goto err_deinit_mdio; 3055 } else 3056 netif_info(eth, probe, eth->netdev[i], 3057 "mediatek frame engine at 0x%08lx, irq %d\n", 3058 eth->netdev[i]->base_addr, eth->irq[0]); 3059 } 3060 3061 /* we run 2 devices on the same DMA ring so we need a dummy device 3062 * for NAPI to work 3063 */ 3064 init_dummy_netdev(ð->dummy_dev); 3065 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 3066 MTK_NAPI_WEIGHT); 3067 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 3068 MTK_NAPI_WEIGHT); 3069 3070 platform_set_drvdata(pdev, eth); 3071 3072 return 0; 3073 3074 err_deinit_mdio: 3075 mtk_mdio_cleanup(eth); 3076 err_free_dev: 3077 mtk_free_dev(eth); 3078 err_deinit_hw: 3079 mtk_hw_deinit(eth); 3080 3081 return err; 3082 } 3083 3084 static int mtk_remove(struct platform_device *pdev) 3085 { 3086 struct mtk_eth *eth = platform_get_drvdata(pdev); 3087 struct mtk_mac *mac; 3088 int i; 3089 3090 /* stop all devices to make sure that dma is properly shut down */ 3091 for (i = 0; i < MTK_MAC_COUNT; i++) { 3092 if (!eth->netdev[i]) 3093 continue; 3094 mtk_stop(eth->netdev[i]); 3095 mac = netdev_priv(eth->netdev[i]); 3096 phylink_disconnect_phy(mac->phylink); 3097 } 3098 3099 mtk_hw_deinit(eth); 3100 3101 netif_napi_del(ð->tx_napi); 3102 netif_napi_del(ð->rx_napi); 3103 mtk_cleanup(eth); 3104 mtk_mdio_cleanup(eth); 3105 3106 return 0; 3107 } 3108 3109 static const struct mtk_soc_data mt2701_data = { 3110 .caps = MT7623_CAPS | MTK_HWLRO, 3111 .hw_features = MTK_HW_FEATURES, 3112 .required_clks = MT7623_CLKS_BITMAP, 3113 .required_pctl = true, 3114 }; 3115 3116 static const struct mtk_soc_data mt7621_data = { 3117 .caps = MT7621_CAPS, 3118 .hw_features = MTK_HW_FEATURES, 3119 .required_clks = MT7621_CLKS_BITMAP, 3120 .required_pctl = false, 3121 }; 3122 3123 static const struct mtk_soc_data mt7622_data = { 3124 .ana_rgc3 = 0x2028, 3125 .caps = MT7622_CAPS | MTK_HWLRO, 3126 .hw_features = MTK_HW_FEATURES, 3127 .required_clks = MT7622_CLKS_BITMAP, 3128 .required_pctl = false, 3129 }; 3130 3131 static const struct mtk_soc_data mt7623_data = { 3132 .caps = MT7623_CAPS | MTK_HWLRO, 3133 .hw_features = MTK_HW_FEATURES, 3134 .required_clks = MT7623_CLKS_BITMAP, 3135 .required_pctl = true, 3136 }; 3137 3138 static const struct mtk_soc_data mt7629_data = { 3139 .ana_rgc3 = 0x128, 3140 .caps = MT7629_CAPS | MTK_HWLRO, 3141 .hw_features = MTK_HW_FEATURES, 3142 .required_clks = MT7629_CLKS_BITMAP, 3143 .required_pctl = false, 3144 }; 3145 3146 static const struct mtk_soc_data rt5350_data = { 3147 .caps = MT7628_CAPS, 3148 .hw_features = MTK_HW_FEATURES_MT7628, 3149 .required_clks = MT7628_CLKS_BITMAP, 3150 .required_pctl = false, 3151 }; 3152 3153 const struct of_device_id of_mtk_match[] = { 3154 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 3155 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 3156 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 3157 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 3158 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 3159 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 3160 {}, 3161 }; 3162 MODULE_DEVICE_TABLE(of, of_mtk_match); 3163 3164 static struct platform_driver mtk_driver = { 3165 .probe = mtk_probe, 3166 .remove = mtk_remove, 3167 .driver = { 3168 .name = "mtk_soc_eth", 3169 .of_match_table = of_mtk_match, 3170 }, 3171 }; 3172 3173 module_platform_driver(mtk_driver); 3174 3175 MODULE_LICENSE("GPL"); 3176 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 3177 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 3178