1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #include <linux/of_device.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/regmap.h> 20 #include <linux/clk.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/if_vlan.h> 23 #include <linux/reset.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/pinctrl/devinfo.h> 27 28 #include "mtk_eth_soc.h" 29 30 static int mtk_msg_level = -1; 31 module_param_named(msg_level, mtk_msg_level, int, 0); 32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 33 34 #define MTK_ETHTOOL_STAT(x) { #x, \ 35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 36 37 /* strings used by ethtool */ 38 static const struct mtk_ethtool_stats { 39 char str[ETH_GSTRING_LEN]; 40 u32 offset; 41 } mtk_ethtool_stats[] = { 42 MTK_ETHTOOL_STAT(tx_bytes), 43 MTK_ETHTOOL_STAT(tx_packets), 44 MTK_ETHTOOL_STAT(tx_skip), 45 MTK_ETHTOOL_STAT(tx_collisions), 46 MTK_ETHTOOL_STAT(rx_bytes), 47 MTK_ETHTOOL_STAT(rx_packets), 48 MTK_ETHTOOL_STAT(rx_overflow), 49 MTK_ETHTOOL_STAT(rx_fcs_errors), 50 MTK_ETHTOOL_STAT(rx_short_errors), 51 MTK_ETHTOOL_STAT(rx_long_errors), 52 MTK_ETHTOOL_STAT(rx_checksum_errors), 53 MTK_ETHTOOL_STAT(rx_flow_control_packets), 54 }; 55 56 static const char * const mtk_clks_source_name[] = { 57 "ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m", 58 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" 59 }; 60 61 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 62 { 63 __raw_writel(val, eth->base + reg); 64 } 65 66 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 67 { 68 return __raw_readl(eth->base + reg); 69 } 70 71 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 72 { 73 unsigned long t_start = jiffies; 74 75 while (1) { 76 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 77 return 0; 78 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 79 break; 80 usleep_range(10, 20); 81 } 82 83 dev_err(eth->dev, "mdio: MDIO timeout\n"); 84 return -1; 85 } 86 87 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 88 u32 phy_register, u32 write_data) 89 { 90 if (mtk_mdio_busy_wait(eth)) 91 return -1; 92 93 write_data &= 0xffff; 94 95 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 96 (phy_register << PHY_IAC_REG_SHIFT) | 97 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 98 MTK_PHY_IAC); 99 100 if (mtk_mdio_busy_wait(eth)) 101 return -1; 102 103 return 0; 104 } 105 106 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 107 { 108 u32 d; 109 110 if (mtk_mdio_busy_wait(eth)) 111 return 0xffff; 112 113 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 114 (phy_reg << PHY_IAC_REG_SHIFT) | 115 (phy_addr << PHY_IAC_ADDR_SHIFT), 116 MTK_PHY_IAC); 117 118 if (mtk_mdio_busy_wait(eth)) 119 return 0xffff; 120 121 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 122 123 return d; 124 } 125 126 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 127 int phy_reg, u16 val) 128 { 129 struct mtk_eth *eth = bus->priv; 130 131 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 132 } 133 134 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 135 { 136 struct mtk_eth *eth = bus->priv; 137 138 return _mtk_mdio_read(eth, phy_addr, phy_reg); 139 } 140 141 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 142 { 143 u32 val; 144 int ret; 145 146 val = (speed == SPEED_1000) ? 147 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 148 mtk_w32(eth, val, INTF_MODE); 149 150 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 151 ETHSYS_TRGMII_CLK_SEL362_5, 152 ETHSYS_TRGMII_CLK_SEL362_5); 153 154 val = (speed == SPEED_1000) ? 250000000 : 500000000; 155 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 156 if (ret) 157 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 158 159 val = (speed == SPEED_1000) ? 160 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 161 mtk_w32(eth, val, TRGMII_RCK_CTRL); 162 163 val = (speed == SPEED_1000) ? 164 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 165 mtk_w32(eth, val, TRGMII_TCK_CTRL); 166 } 167 168 static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id) 169 { 170 u32 val; 171 172 /* Setup the link timer and QPHY power up inside SGMIISYS */ 173 regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER, 174 SGMII_LINK_TIMER_DEFAULT); 175 176 regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val); 177 val |= SGMII_REMOTE_FAULT_DIS; 178 regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val); 179 180 regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val); 181 val |= SGMII_AN_RESTART; 182 regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val); 183 184 regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val); 185 val &= ~SGMII_PHYA_PWD; 186 regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val); 187 188 /* Determine MUX for which GMAC uses the SGMII interface */ 189 if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) { 190 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 191 val &= ~SYSCFG0_SGMII_MASK; 192 val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2; 193 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 194 195 dev_info(eth->dev, "setup shared sgmii for gmac=%d\n", 196 mac_id); 197 } 198 199 /* Setup the GMAC1 going through SGMII path when SoC also support 200 * ESW on GMAC1 201 */ 202 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) && 203 !mac_id) { 204 mtk_w32(eth, 0, MTK_MAC_MISC); 205 dev_info(eth->dev, "setup gmac1 going through sgmii"); 206 } 207 } 208 209 static void mtk_phy_link_adjust(struct net_device *dev) 210 { 211 struct mtk_mac *mac = netdev_priv(dev); 212 u16 lcl_adv = 0, rmt_adv = 0; 213 u8 flowctrl; 214 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 215 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 216 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 217 MAC_MCR_BACKPR_EN; 218 219 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 220 return; 221 222 switch (dev->phydev->speed) { 223 case SPEED_1000: 224 mcr |= MAC_MCR_SPEED_1000; 225 break; 226 case SPEED_100: 227 mcr |= MAC_MCR_SPEED_100; 228 break; 229 } 230 231 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 232 !mac->id && !mac->trgmii) 233 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed); 234 235 if (dev->phydev->link) 236 mcr |= MAC_MCR_FORCE_LINK; 237 238 if (dev->phydev->duplex) { 239 mcr |= MAC_MCR_FORCE_DPX; 240 241 if (dev->phydev->pause) 242 rmt_adv = LPA_PAUSE_CAP; 243 if (dev->phydev->asym_pause) 244 rmt_adv |= LPA_PAUSE_ASYM; 245 246 lcl_adv = linkmode_adv_to_lcl_adv_t(dev->phydev->advertising); 247 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 248 249 if (flowctrl & FLOW_CTRL_TX) 250 mcr |= MAC_MCR_FORCE_TX_FC; 251 if (flowctrl & FLOW_CTRL_RX) 252 mcr |= MAC_MCR_FORCE_RX_FC; 253 254 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 255 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 256 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 257 } 258 259 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 260 261 if (!of_phy_is_fixed_link(mac->of_node)) 262 phy_print_status(dev->phydev); 263 } 264 265 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 266 struct device_node *phy_node) 267 { 268 struct phy_device *phydev; 269 int phy_mode; 270 271 phy_mode = of_get_phy_mode(phy_node); 272 if (phy_mode < 0) { 273 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 274 return -EINVAL; 275 } 276 277 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 278 mtk_phy_link_adjust, 0, phy_mode); 279 if (!phydev) { 280 dev_err(eth->dev, "could not connect to PHY\n"); 281 return -ENODEV; 282 } 283 284 dev_info(eth->dev, 285 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 286 mac->id, phydev_name(phydev), phydev->phy_id, 287 phydev->drv->name); 288 289 return 0; 290 } 291 292 static int mtk_phy_connect(struct net_device *dev) 293 { 294 struct mtk_mac *mac = netdev_priv(dev); 295 struct mtk_eth *eth; 296 struct device_node *np; 297 u32 val; 298 299 eth = mac->hw; 300 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 301 if (!np && of_phy_is_fixed_link(mac->of_node)) 302 if (!of_phy_register_fixed_link(mac->of_node)) 303 np = of_node_get(mac->of_node); 304 if (!np) 305 return -ENODEV; 306 307 mac->ge_mode = 0; 308 switch (of_get_phy_mode(np)) { 309 case PHY_INTERFACE_MODE_TRGMII: 310 mac->trgmii = true; 311 case PHY_INTERFACE_MODE_RGMII_TXID: 312 case PHY_INTERFACE_MODE_RGMII_RXID: 313 case PHY_INTERFACE_MODE_RGMII_ID: 314 case PHY_INTERFACE_MODE_RGMII: 315 break; 316 case PHY_INTERFACE_MODE_SGMII: 317 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) 318 mtk_gmac_sgmii_hw_setup(eth, mac->id); 319 break; 320 case PHY_INTERFACE_MODE_MII: 321 mac->ge_mode = 1; 322 break; 323 case PHY_INTERFACE_MODE_REVMII: 324 mac->ge_mode = 2; 325 break; 326 case PHY_INTERFACE_MODE_RMII: 327 if (!mac->id) 328 goto err_phy; 329 mac->ge_mode = 3; 330 break; 331 default: 332 goto err_phy; 333 } 334 335 /* put the gmac into the right mode */ 336 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 337 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 338 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id); 339 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 340 341 /* couple phydev to net_device */ 342 if (mtk_phy_connect_node(eth, mac, np)) 343 goto err_phy; 344 345 of_node_put(np); 346 347 return 0; 348 349 err_phy: 350 if (of_phy_is_fixed_link(mac->of_node)) 351 of_phy_deregister_fixed_link(mac->of_node); 352 of_node_put(np); 353 dev_err(eth->dev, "%s: invalid phy\n", __func__); 354 return -EINVAL; 355 } 356 357 static int mtk_mdio_init(struct mtk_eth *eth) 358 { 359 struct device_node *mii_np; 360 int ret; 361 362 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 363 if (!mii_np) { 364 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 365 return -ENODEV; 366 } 367 368 if (!of_device_is_available(mii_np)) { 369 ret = -ENODEV; 370 goto err_put_node; 371 } 372 373 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 374 if (!eth->mii_bus) { 375 ret = -ENOMEM; 376 goto err_put_node; 377 } 378 379 eth->mii_bus->name = "mdio"; 380 eth->mii_bus->read = mtk_mdio_read; 381 eth->mii_bus->write = mtk_mdio_write; 382 eth->mii_bus->priv = eth; 383 eth->mii_bus->parent = eth->dev; 384 385 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 386 ret = of_mdiobus_register(eth->mii_bus, mii_np); 387 388 err_put_node: 389 of_node_put(mii_np); 390 return ret; 391 } 392 393 static void mtk_mdio_cleanup(struct mtk_eth *eth) 394 { 395 if (!eth->mii_bus) 396 return; 397 398 mdiobus_unregister(eth->mii_bus); 399 } 400 401 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 402 { 403 unsigned long flags; 404 u32 val; 405 406 spin_lock_irqsave(ð->tx_irq_lock, flags); 407 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 408 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); 409 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 410 } 411 412 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 413 { 414 unsigned long flags; 415 u32 val; 416 417 spin_lock_irqsave(ð->tx_irq_lock, flags); 418 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 419 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); 420 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 421 } 422 423 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 424 { 425 unsigned long flags; 426 u32 val; 427 428 spin_lock_irqsave(ð->rx_irq_lock, flags); 429 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 430 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 431 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 432 } 433 434 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 435 { 436 unsigned long flags; 437 u32 val; 438 439 spin_lock_irqsave(ð->rx_irq_lock, flags); 440 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 441 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 442 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 443 } 444 445 static int mtk_set_mac_address(struct net_device *dev, void *p) 446 { 447 int ret = eth_mac_addr(dev, p); 448 struct mtk_mac *mac = netdev_priv(dev); 449 const char *macaddr = dev->dev_addr; 450 451 if (ret) 452 return ret; 453 454 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 455 return -EBUSY; 456 457 spin_lock_bh(&mac->hw->page_lock); 458 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 459 MTK_GDMA_MAC_ADRH(mac->id)); 460 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 461 (macaddr[4] << 8) | macaddr[5], 462 MTK_GDMA_MAC_ADRL(mac->id)); 463 spin_unlock_bh(&mac->hw->page_lock); 464 465 return 0; 466 } 467 468 void mtk_stats_update_mac(struct mtk_mac *mac) 469 { 470 struct mtk_hw_stats *hw_stats = mac->hw_stats; 471 unsigned int base = MTK_GDM1_TX_GBCNT; 472 u64 stats; 473 474 base += hw_stats->reg_offset; 475 476 u64_stats_update_begin(&hw_stats->syncp); 477 478 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 479 stats = mtk_r32(mac->hw, base + 0x04); 480 if (stats) 481 hw_stats->rx_bytes += (stats << 32); 482 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 483 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 484 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 485 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 486 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 487 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 488 hw_stats->rx_flow_control_packets += 489 mtk_r32(mac->hw, base + 0x24); 490 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 491 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 492 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 493 stats = mtk_r32(mac->hw, base + 0x34); 494 if (stats) 495 hw_stats->tx_bytes += (stats << 32); 496 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 497 u64_stats_update_end(&hw_stats->syncp); 498 } 499 500 static void mtk_stats_update(struct mtk_eth *eth) 501 { 502 int i; 503 504 for (i = 0; i < MTK_MAC_COUNT; i++) { 505 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 506 continue; 507 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 508 mtk_stats_update_mac(eth->mac[i]); 509 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 510 } 511 } 512 } 513 514 static void mtk_get_stats64(struct net_device *dev, 515 struct rtnl_link_stats64 *storage) 516 { 517 struct mtk_mac *mac = netdev_priv(dev); 518 struct mtk_hw_stats *hw_stats = mac->hw_stats; 519 unsigned int start; 520 521 if (netif_running(dev) && netif_device_present(dev)) { 522 if (spin_trylock_bh(&hw_stats->stats_lock)) { 523 mtk_stats_update_mac(mac); 524 spin_unlock_bh(&hw_stats->stats_lock); 525 } 526 } 527 528 do { 529 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 530 storage->rx_packets = hw_stats->rx_packets; 531 storage->tx_packets = hw_stats->tx_packets; 532 storage->rx_bytes = hw_stats->rx_bytes; 533 storage->tx_bytes = hw_stats->tx_bytes; 534 storage->collisions = hw_stats->tx_collisions; 535 storage->rx_length_errors = hw_stats->rx_short_errors + 536 hw_stats->rx_long_errors; 537 storage->rx_over_errors = hw_stats->rx_overflow; 538 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 539 storage->rx_errors = hw_stats->rx_checksum_errors; 540 storage->tx_aborted_errors = hw_stats->tx_skip; 541 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 542 543 storage->tx_errors = dev->stats.tx_errors; 544 storage->rx_dropped = dev->stats.rx_dropped; 545 storage->tx_dropped = dev->stats.tx_dropped; 546 } 547 548 static inline int mtk_max_frag_size(int mtu) 549 { 550 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 551 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 552 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 553 554 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 555 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 556 } 557 558 static inline int mtk_max_buf_size(int frag_size) 559 { 560 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 561 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 562 563 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 564 565 return buf_size; 566 } 567 568 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 569 struct mtk_rx_dma *dma_rxd) 570 { 571 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 572 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 573 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 574 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 575 } 576 577 /* the qdma core needs scratch memory to be setup */ 578 static int mtk_init_fq_dma(struct mtk_eth *eth) 579 { 580 dma_addr_t phy_ring_tail; 581 int cnt = MTK_DMA_SIZE; 582 dma_addr_t dma_addr; 583 int i; 584 585 eth->scratch_ring = dma_alloc_coherent(eth->dev, 586 cnt * sizeof(struct mtk_tx_dma), 587 ð->phy_scratch_ring, 588 GFP_ATOMIC); 589 if (unlikely(!eth->scratch_ring)) 590 return -ENOMEM; 591 592 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 593 GFP_KERNEL); 594 if (unlikely(!eth->scratch_head)) 595 return -ENOMEM; 596 597 dma_addr = dma_map_single(eth->dev, 598 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 599 DMA_FROM_DEVICE); 600 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 601 return -ENOMEM; 602 603 phy_ring_tail = eth->phy_scratch_ring + 604 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 605 606 for (i = 0; i < cnt; i++) { 607 eth->scratch_ring[i].txd1 = 608 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 609 if (i < cnt - 1) 610 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 611 ((i + 1) * sizeof(struct mtk_tx_dma))); 612 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 613 } 614 615 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 616 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 617 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 618 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 619 620 return 0; 621 } 622 623 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 624 { 625 void *ret = ring->dma; 626 627 return ret + (desc - ring->phys); 628 } 629 630 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 631 struct mtk_tx_dma *txd) 632 { 633 int idx = txd - ring->dma; 634 635 return &ring->buf[idx]; 636 } 637 638 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 639 { 640 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 641 dma_unmap_single(eth->dev, 642 dma_unmap_addr(tx_buf, dma_addr0), 643 dma_unmap_len(tx_buf, dma_len0), 644 DMA_TO_DEVICE); 645 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 646 dma_unmap_page(eth->dev, 647 dma_unmap_addr(tx_buf, dma_addr0), 648 dma_unmap_len(tx_buf, dma_len0), 649 DMA_TO_DEVICE); 650 } 651 tx_buf->flags = 0; 652 if (tx_buf->skb && 653 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 654 dev_kfree_skb_any(tx_buf->skb); 655 tx_buf->skb = NULL; 656 } 657 658 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 659 int tx_num, struct mtk_tx_ring *ring, bool gso) 660 { 661 struct mtk_mac *mac = netdev_priv(dev); 662 struct mtk_eth *eth = mac->hw; 663 struct mtk_tx_dma *itxd, *txd; 664 struct mtk_tx_buf *itx_buf, *tx_buf; 665 dma_addr_t mapped_addr; 666 unsigned int nr_frags; 667 int i, n_desc = 1; 668 u32 txd4 = 0, fport; 669 670 itxd = ring->next_free; 671 if (itxd == ring->last_free) 672 return -ENOMEM; 673 674 /* set the forward port */ 675 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 676 txd4 |= fport; 677 678 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 679 memset(itx_buf, 0, sizeof(*itx_buf)); 680 681 if (gso) 682 txd4 |= TX_DMA_TSO; 683 684 /* TX Checksum offload */ 685 if (skb->ip_summed == CHECKSUM_PARTIAL) 686 txd4 |= TX_DMA_CHKSUM; 687 688 /* VLAN header offload */ 689 if (skb_vlan_tag_present(skb)) 690 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 691 692 mapped_addr = dma_map_single(eth->dev, skb->data, 693 skb_headlen(skb), DMA_TO_DEVICE); 694 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 695 return -ENOMEM; 696 697 WRITE_ONCE(itxd->txd1, mapped_addr); 698 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 699 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 700 MTK_TX_FLAGS_FPORT1; 701 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr); 702 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb)); 703 704 /* TX SG offload */ 705 txd = itxd; 706 nr_frags = skb_shinfo(skb)->nr_frags; 707 for (i = 0; i < nr_frags; i++) { 708 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 709 unsigned int offset = 0; 710 int frag_size = skb_frag_size(frag); 711 712 while (frag_size) { 713 bool last_frag = false; 714 unsigned int frag_map_size; 715 716 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 717 if (txd == ring->last_free) 718 goto err_dma; 719 720 n_desc++; 721 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 722 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 723 frag_map_size, 724 DMA_TO_DEVICE); 725 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 726 goto err_dma; 727 728 if (i == nr_frags - 1 && 729 (frag_size - frag_map_size) == 0) 730 last_frag = true; 731 732 WRITE_ONCE(txd->txd1, mapped_addr); 733 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 734 TX_DMA_PLEN0(frag_map_size) | 735 last_frag * TX_DMA_LS0)); 736 WRITE_ONCE(txd->txd4, fport); 737 738 tx_buf = mtk_desc_to_tx_buf(ring, txd); 739 memset(tx_buf, 0, sizeof(*tx_buf)); 740 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 741 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 742 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 743 MTK_TX_FLAGS_FPORT1; 744 745 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 746 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 747 frag_size -= frag_map_size; 748 offset += frag_map_size; 749 } 750 } 751 752 /* store skb to cleanup */ 753 itx_buf->skb = skb; 754 755 WRITE_ONCE(itxd->txd4, txd4); 756 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 757 (!nr_frags * TX_DMA_LS0))); 758 759 netdev_sent_queue(dev, skb->len); 760 skb_tx_timestamp(skb); 761 762 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 763 atomic_sub(n_desc, &ring->free_count); 764 765 /* make sure that all changes to the dma ring are flushed before we 766 * continue 767 */ 768 wmb(); 769 770 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more) 771 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 772 773 return 0; 774 775 err_dma: 776 do { 777 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 778 779 /* unmap dma */ 780 mtk_tx_unmap(eth, tx_buf); 781 782 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 783 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 784 } while (itxd != txd); 785 786 return -ENOMEM; 787 } 788 789 static inline int mtk_cal_txd_req(struct sk_buff *skb) 790 { 791 int i, nfrags; 792 struct skb_frag_struct *frag; 793 794 nfrags = 1; 795 if (skb_is_gso(skb)) { 796 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 797 frag = &skb_shinfo(skb)->frags[i]; 798 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); 799 } 800 } else { 801 nfrags += skb_shinfo(skb)->nr_frags; 802 } 803 804 return nfrags; 805 } 806 807 static int mtk_queue_stopped(struct mtk_eth *eth) 808 { 809 int i; 810 811 for (i = 0; i < MTK_MAC_COUNT; i++) { 812 if (!eth->netdev[i]) 813 continue; 814 if (netif_queue_stopped(eth->netdev[i])) 815 return 1; 816 } 817 818 return 0; 819 } 820 821 static void mtk_wake_queue(struct mtk_eth *eth) 822 { 823 int i; 824 825 for (i = 0; i < MTK_MAC_COUNT; i++) { 826 if (!eth->netdev[i]) 827 continue; 828 netif_wake_queue(eth->netdev[i]); 829 } 830 } 831 832 static void mtk_stop_queue(struct mtk_eth *eth) 833 { 834 int i; 835 836 for (i = 0; i < MTK_MAC_COUNT; i++) { 837 if (!eth->netdev[i]) 838 continue; 839 netif_stop_queue(eth->netdev[i]); 840 } 841 } 842 843 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 844 { 845 struct mtk_mac *mac = netdev_priv(dev); 846 struct mtk_eth *eth = mac->hw; 847 struct mtk_tx_ring *ring = ð->tx_ring; 848 struct net_device_stats *stats = &dev->stats; 849 bool gso = false; 850 int tx_num; 851 852 /* normally we can rely on the stack not calling this more than once, 853 * however we have 2 queues running on the same ring so we need to lock 854 * the ring access 855 */ 856 spin_lock(ð->page_lock); 857 858 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 859 goto drop; 860 861 tx_num = mtk_cal_txd_req(skb); 862 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 863 mtk_stop_queue(eth); 864 netif_err(eth, tx_queued, dev, 865 "Tx Ring full when queue awake!\n"); 866 spin_unlock(ð->page_lock); 867 return NETDEV_TX_BUSY; 868 } 869 870 /* TSO: fill MSS info in tcp checksum field */ 871 if (skb_is_gso(skb)) { 872 if (skb_cow_head(skb, 0)) { 873 netif_warn(eth, tx_err, dev, 874 "GSO expand head fail.\n"); 875 goto drop; 876 } 877 878 if (skb_shinfo(skb)->gso_type & 879 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 880 gso = true; 881 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 882 } 883 } 884 885 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 886 goto drop; 887 888 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 889 mtk_stop_queue(eth); 890 891 spin_unlock(ð->page_lock); 892 893 return NETDEV_TX_OK; 894 895 drop: 896 spin_unlock(ð->page_lock); 897 stats->tx_dropped++; 898 dev_kfree_skb_any(skb); 899 return NETDEV_TX_OK; 900 } 901 902 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 903 { 904 int i; 905 struct mtk_rx_ring *ring; 906 int idx; 907 908 if (!eth->hwlro) 909 return ð->rx_ring[0]; 910 911 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 912 ring = ð->rx_ring[i]; 913 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 914 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 915 ring->calc_idx_update = true; 916 return ring; 917 } 918 } 919 920 return NULL; 921 } 922 923 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 924 { 925 struct mtk_rx_ring *ring; 926 int i; 927 928 if (!eth->hwlro) { 929 ring = ð->rx_ring[0]; 930 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 931 } else { 932 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 933 ring = ð->rx_ring[i]; 934 if (ring->calc_idx_update) { 935 ring->calc_idx_update = false; 936 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 937 } 938 } 939 } 940 } 941 942 static int mtk_poll_rx(struct napi_struct *napi, int budget, 943 struct mtk_eth *eth) 944 { 945 struct mtk_rx_ring *ring; 946 int idx; 947 struct sk_buff *skb; 948 u8 *data, *new_data; 949 struct mtk_rx_dma *rxd, trxd; 950 int done = 0; 951 952 while (done < budget) { 953 struct net_device *netdev; 954 unsigned int pktlen; 955 dma_addr_t dma_addr; 956 int mac = 0; 957 958 ring = mtk_get_rx_ring(eth); 959 if (unlikely(!ring)) 960 goto rx_done; 961 962 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 963 rxd = &ring->dma[idx]; 964 data = ring->data[idx]; 965 966 mtk_rx_get_desc(&trxd, rxd); 967 if (!(trxd.rxd2 & RX_DMA_DONE)) 968 break; 969 970 /* find out which mac the packet come from. values start at 1 */ 971 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 972 RX_DMA_FPORT_MASK; 973 mac--; 974 975 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 976 !eth->netdev[mac])) 977 goto release_desc; 978 979 netdev = eth->netdev[mac]; 980 981 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 982 goto release_desc; 983 984 /* alloc new buffer */ 985 new_data = napi_alloc_frag(ring->frag_size); 986 if (unlikely(!new_data)) { 987 netdev->stats.rx_dropped++; 988 goto release_desc; 989 } 990 dma_addr = dma_map_single(eth->dev, 991 new_data + NET_SKB_PAD, 992 ring->buf_size, 993 DMA_FROM_DEVICE); 994 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 995 skb_free_frag(new_data); 996 netdev->stats.rx_dropped++; 997 goto release_desc; 998 } 999 1000 /* receive data */ 1001 skb = build_skb(data, ring->frag_size); 1002 if (unlikely(!skb)) { 1003 skb_free_frag(new_data); 1004 netdev->stats.rx_dropped++; 1005 goto release_desc; 1006 } 1007 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1008 1009 dma_unmap_single(eth->dev, trxd.rxd1, 1010 ring->buf_size, DMA_FROM_DEVICE); 1011 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1012 skb->dev = netdev; 1013 skb_put(skb, pktlen); 1014 if (trxd.rxd4 & RX_DMA_L4_VALID) 1015 skb->ip_summed = CHECKSUM_UNNECESSARY; 1016 else 1017 skb_checksum_none_assert(skb); 1018 skb->protocol = eth_type_trans(skb, netdev); 1019 1020 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1021 RX_DMA_VID(trxd.rxd3)) 1022 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1023 RX_DMA_VID(trxd.rxd3)); 1024 skb_record_rx_queue(skb, 0); 1025 napi_gro_receive(napi, skb); 1026 1027 ring->data[idx] = new_data; 1028 rxd->rxd1 = (unsigned int)dma_addr; 1029 1030 release_desc: 1031 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1032 1033 ring->calc_idx = idx; 1034 1035 done++; 1036 } 1037 1038 rx_done: 1039 if (done) { 1040 /* make sure that all changes to the dma ring are flushed before 1041 * we continue 1042 */ 1043 wmb(); 1044 mtk_update_rx_cpu_idx(eth); 1045 } 1046 1047 return done; 1048 } 1049 1050 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1051 { 1052 struct mtk_tx_ring *ring = ð->tx_ring; 1053 struct mtk_tx_dma *desc; 1054 struct sk_buff *skb; 1055 struct mtk_tx_buf *tx_buf; 1056 unsigned int done[MTK_MAX_DEVS]; 1057 unsigned int bytes[MTK_MAX_DEVS]; 1058 u32 cpu, dma; 1059 int total = 0, i; 1060 1061 memset(done, 0, sizeof(done)); 1062 memset(bytes, 0, sizeof(bytes)); 1063 1064 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1065 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1066 1067 desc = mtk_qdma_phys_to_virt(ring, cpu); 1068 1069 while ((cpu != dma) && budget) { 1070 u32 next_cpu = desc->txd2; 1071 int mac = 0; 1072 1073 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1074 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1075 break; 1076 1077 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1078 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1079 mac = 1; 1080 1081 skb = tx_buf->skb; 1082 if (!skb) 1083 break; 1084 1085 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1086 bytes[mac] += skb->len; 1087 done[mac]++; 1088 budget--; 1089 } 1090 mtk_tx_unmap(eth, tx_buf); 1091 1092 ring->last_free = desc; 1093 atomic_inc(&ring->free_count); 1094 1095 cpu = next_cpu; 1096 } 1097 1098 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1099 1100 for (i = 0; i < MTK_MAC_COUNT; i++) { 1101 if (!eth->netdev[i] || !done[i]) 1102 continue; 1103 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1104 total += done[i]; 1105 } 1106 1107 if (mtk_queue_stopped(eth) && 1108 (atomic_read(&ring->free_count) > ring->thresh)) 1109 mtk_wake_queue(eth); 1110 1111 return total; 1112 } 1113 1114 static void mtk_handle_status_irq(struct mtk_eth *eth) 1115 { 1116 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1117 1118 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1119 mtk_stats_update(eth); 1120 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1121 MTK_INT_STATUS2); 1122 } 1123 } 1124 1125 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1126 { 1127 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1128 u32 status, mask; 1129 int tx_done = 0; 1130 1131 mtk_handle_status_irq(eth); 1132 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 1133 tx_done = mtk_poll_tx(eth, budget); 1134 1135 if (unlikely(netif_msg_intr(eth))) { 1136 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1137 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 1138 dev_info(eth->dev, 1139 "done tx %d, intr 0x%08x/0x%x\n", 1140 tx_done, status, mask); 1141 } 1142 1143 if (tx_done == budget) 1144 return budget; 1145 1146 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1147 if (status & MTK_TX_DONE_INT) 1148 return budget; 1149 1150 napi_complete(napi); 1151 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1152 1153 return tx_done; 1154 } 1155 1156 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1157 { 1158 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1159 u32 status, mask; 1160 int rx_done = 0; 1161 int remain_budget = budget; 1162 1163 mtk_handle_status_irq(eth); 1164 1165 poll_again: 1166 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1167 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1168 1169 if (unlikely(netif_msg_intr(eth))) { 1170 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1171 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1172 dev_info(eth->dev, 1173 "done rx %d, intr 0x%08x/0x%x\n", 1174 rx_done, status, mask); 1175 } 1176 if (rx_done == remain_budget) 1177 return budget; 1178 1179 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1180 if (status & MTK_RX_DONE_INT) { 1181 remain_budget -= rx_done; 1182 goto poll_again; 1183 } 1184 napi_complete(napi); 1185 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1186 1187 return rx_done + budget - remain_budget; 1188 } 1189 1190 static int mtk_tx_alloc(struct mtk_eth *eth) 1191 { 1192 struct mtk_tx_ring *ring = ð->tx_ring; 1193 int i, sz = sizeof(*ring->dma); 1194 1195 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1196 GFP_KERNEL); 1197 if (!ring->buf) 1198 goto no_tx_mem; 1199 1200 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1201 &ring->phys, GFP_ATOMIC); 1202 if (!ring->dma) 1203 goto no_tx_mem; 1204 1205 for (i = 0; i < MTK_DMA_SIZE; i++) { 1206 int next = (i + 1) % MTK_DMA_SIZE; 1207 u32 next_ptr = ring->phys + next * sz; 1208 1209 ring->dma[i].txd2 = next_ptr; 1210 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1211 } 1212 1213 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1214 ring->next_free = &ring->dma[0]; 1215 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1216 ring->thresh = MAX_SKB_FRAGS; 1217 1218 /* make sure that all changes to the dma ring are flushed before we 1219 * continue 1220 */ 1221 wmb(); 1222 1223 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1224 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1225 mtk_w32(eth, 1226 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1227 MTK_QTX_CRX_PTR); 1228 mtk_w32(eth, 1229 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1230 MTK_QTX_DRX_PTR); 1231 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1232 1233 return 0; 1234 1235 no_tx_mem: 1236 return -ENOMEM; 1237 } 1238 1239 static void mtk_tx_clean(struct mtk_eth *eth) 1240 { 1241 struct mtk_tx_ring *ring = ð->tx_ring; 1242 int i; 1243 1244 if (ring->buf) { 1245 for (i = 0; i < MTK_DMA_SIZE; i++) 1246 mtk_tx_unmap(eth, &ring->buf[i]); 1247 kfree(ring->buf); 1248 ring->buf = NULL; 1249 } 1250 1251 if (ring->dma) { 1252 dma_free_coherent(eth->dev, 1253 MTK_DMA_SIZE * sizeof(*ring->dma), 1254 ring->dma, 1255 ring->phys); 1256 ring->dma = NULL; 1257 } 1258 } 1259 1260 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1261 { 1262 struct mtk_rx_ring *ring; 1263 int rx_data_len, rx_dma_size; 1264 int i; 1265 u32 offset = 0; 1266 1267 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1268 if (ring_no) 1269 return -EINVAL; 1270 ring = ð->rx_ring_qdma; 1271 offset = 0x1000; 1272 } else { 1273 ring = ð->rx_ring[ring_no]; 1274 } 1275 1276 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1277 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1278 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1279 } else { 1280 rx_data_len = ETH_DATA_LEN; 1281 rx_dma_size = MTK_DMA_SIZE; 1282 } 1283 1284 ring->frag_size = mtk_max_frag_size(rx_data_len); 1285 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1286 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1287 GFP_KERNEL); 1288 if (!ring->data) 1289 return -ENOMEM; 1290 1291 for (i = 0; i < rx_dma_size; i++) { 1292 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1293 if (!ring->data[i]) 1294 return -ENOMEM; 1295 } 1296 1297 ring->dma = dma_alloc_coherent(eth->dev, 1298 rx_dma_size * sizeof(*ring->dma), 1299 &ring->phys, GFP_ATOMIC); 1300 if (!ring->dma) 1301 return -ENOMEM; 1302 1303 for (i = 0; i < rx_dma_size; i++) { 1304 dma_addr_t dma_addr = dma_map_single(eth->dev, 1305 ring->data[i] + NET_SKB_PAD, 1306 ring->buf_size, 1307 DMA_FROM_DEVICE); 1308 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1309 return -ENOMEM; 1310 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1311 1312 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1313 } 1314 ring->dma_size = rx_dma_size; 1315 ring->calc_idx_update = false; 1316 ring->calc_idx = rx_dma_size - 1; 1317 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1318 /* make sure that all changes to the dma ring are flushed before we 1319 * continue 1320 */ 1321 wmb(); 1322 1323 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1324 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1325 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1326 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1327 1328 return 0; 1329 } 1330 1331 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1332 { 1333 int i; 1334 1335 if (ring->data && ring->dma) { 1336 for (i = 0; i < ring->dma_size; i++) { 1337 if (!ring->data[i]) 1338 continue; 1339 if (!ring->dma[i].rxd1) 1340 continue; 1341 dma_unmap_single(eth->dev, 1342 ring->dma[i].rxd1, 1343 ring->buf_size, 1344 DMA_FROM_DEVICE); 1345 skb_free_frag(ring->data[i]); 1346 } 1347 kfree(ring->data); 1348 ring->data = NULL; 1349 } 1350 1351 if (ring->dma) { 1352 dma_free_coherent(eth->dev, 1353 ring->dma_size * sizeof(*ring->dma), 1354 ring->dma, 1355 ring->phys); 1356 ring->dma = NULL; 1357 } 1358 } 1359 1360 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1361 { 1362 int i; 1363 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1364 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1365 1366 /* set LRO rings to auto-learn modes */ 1367 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1368 1369 /* validate LRO ring */ 1370 ring_ctrl_dw2 |= MTK_RING_VLD; 1371 1372 /* set AGE timer (unit: 20us) */ 1373 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1374 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1375 1376 /* set max AGG timer (unit: 20us) */ 1377 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1378 1379 /* set max LRO AGG count */ 1380 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1381 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1382 1383 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1384 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1385 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1386 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1387 } 1388 1389 /* IPv4 checksum update enable */ 1390 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1391 1392 /* switch priority comparison to packet count mode */ 1393 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1394 1395 /* bandwidth threshold setting */ 1396 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1397 1398 /* auto-learn score delta setting */ 1399 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1400 1401 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1402 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1403 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1404 1405 /* set HW LRO mode & the max aggregation count for rx packets */ 1406 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1407 1408 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1409 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1410 1411 /* enable HW LRO */ 1412 lro_ctrl_dw0 |= MTK_LRO_EN; 1413 1414 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1415 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1416 1417 return 0; 1418 } 1419 1420 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1421 { 1422 int i; 1423 u32 val; 1424 1425 /* relinquish lro rings, flush aggregated packets */ 1426 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1427 1428 /* wait for relinquishments done */ 1429 for (i = 0; i < 10; i++) { 1430 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1431 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1432 msleep(20); 1433 continue; 1434 } 1435 break; 1436 } 1437 1438 /* invalidate lro rings */ 1439 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1440 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1441 1442 /* disable HW LRO */ 1443 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1444 } 1445 1446 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1447 { 1448 u32 reg_val; 1449 1450 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1451 1452 /* invalidate the IP setting */ 1453 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1454 1455 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1456 1457 /* validate the IP setting */ 1458 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1459 } 1460 1461 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1462 { 1463 u32 reg_val; 1464 1465 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1466 1467 /* invalidate the IP setting */ 1468 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1469 1470 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1471 } 1472 1473 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1474 { 1475 int cnt = 0; 1476 int i; 1477 1478 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1479 if (mac->hwlro_ip[i]) 1480 cnt++; 1481 } 1482 1483 return cnt; 1484 } 1485 1486 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1487 struct ethtool_rxnfc *cmd) 1488 { 1489 struct ethtool_rx_flow_spec *fsp = 1490 (struct ethtool_rx_flow_spec *)&cmd->fs; 1491 struct mtk_mac *mac = netdev_priv(dev); 1492 struct mtk_eth *eth = mac->hw; 1493 int hwlro_idx; 1494 1495 if ((fsp->flow_type != TCP_V4_FLOW) || 1496 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1497 (fsp->location > 1)) 1498 return -EINVAL; 1499 1500 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1501 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1502 1503 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1504 1505 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1506 1507 return 0; 1508 } 1509 1510 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1511 struct ethtool_rxnfc *cmd) 1512 { 1513 struct ethtool_rx_flow_spec *fsp = 1514 (struct ethtool_rx_flow_spec *)&cmd->fs; 1515 struct mtk_mac *mac = netdev_priv(dev); 1516 struct mtk_eth *eth = mac->hw; 1517 int hwlro_idx; 1518 1519 if (fsp->location > 1) 1520 return -EINVAL; 1521 1522 mac->hwlro_ip[fsp->location] = 0; 1523 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1524 1525 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1526 1527 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1528 1529 return 0; 1530 } 1531 1532 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1533 { 1534 struct mtk_mac *mac = netdev_priv(dev); 1535 struct mtk_eth *eth = mac->hw; 1536 int i, hwlro_idx; 1537 1538 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1539 mac->hwlro_ip[i] = 0; 1540 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1541 1542 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1543 } 1544 1545 mac->hwlro_ip_cnt = 0; 1546 } 1547 1548 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1549 struct ethtool_rxnfc *cmd) 1550 { 1551 struct mtk_mac *mac = netdev_priv(dev); 1552 struct ethtool_rx_flow_spec *fsp = 1553 (struct ethtool_rx_flow_spec *)&cmd->fs; 1554 1555 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1556 fsp->flow_type = TCP_V4_FLOW; 1557 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1558 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1559 1560 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1561 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1562 fsp->h_u.tcp_ip4_spec.psrc = 0; 1563 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1564 fsp->h_u.tcp_ip4_spec.pdst = 0; 1565 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1566 fsp->h_u.tcp_ip4_spec.tos = 0; 1567 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1568 1569 return 0; 1570 } 1571 1572 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1573 struct ethtool_rxnfc *cmd, 1574 u32 *rule_locs) 1575 { 1576 struct mtk_mac *mac = netdev_priv(dev); 1577 int cnt = 0; 1578 int i; 1579 1580 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1581 if (mac->hwlro_ip[i]) { 1582 rule_locs[cnt] = i; 1583 cnt++; 1584 } 1585 } 1586 1587 cmd->rule_cnt = cnt; 1588 1589 return 0; 1590 } 1591 1592 static netdev_features_t mtk_fix_features(struct net_device *dev, 1593 netdev_features_t features) 1594 { 1595 if (!(features & NETIF_F_LRO)) { 1596 struct mtk_mac *mac = netdev_priv(dev); 1597 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1598 1599 if (ip_cnt) { 1600 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1601 1602 features |= NETIF_F_LRO; 1603 } 1604 } 1605 1606 return features; 1607 } 1608 1609 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1610 { 1611 int err = 0; 1612 1613 if (!((dev->features ^ features) & NETIF_F_LRO)) 1614 return 0; 1615 1616 if (!(features & NETIF_F_LRO)) 1617 mtk_hwlro_netdev_disable(dev); 1618 1619 return err; 1620 } 1621 1622 /* wait for DMA to finish whatever it is doing before we start using it again */ 1623 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1624 { 1625 unsigned long t_start = jiffies; 1626 1627 while (1) { 1628 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1629 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1630 return 0; 1631 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1632 break; 1633 } 1634 1635 dev_err(eth->dev, "DMA init timeout\n"); 1636 return -1; 1637 } 1638 1639 static int mtk_dma_init(struct mtk_eth *eth) 1640 { 1641 int err; 1642 u32 i; 1643 1644 if (mtk_dma_busy_wait(eth)) 1645 return -EBUSY; 1646 1647 /* QDMA needs scratch memory for internal reordering of the 1648 * descriptors 1649 */ 1650 err = mtk_init_fq_dma(eth); 1651 if (err) 1652 return err; 1653 1654 err = mtk_tx_alloc(eth); 1655 if (err) 1656 return err; 1657 1658 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 1659 if (err) 1660 return err; 1661 1662 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 1663 if (err) 1664 return err; 1665 1666 if (eth->hwlro) { 1667 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1668 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 1669 if (err) 1670 return err; 1671 } 1672 err = mtk_hwlro_rx_init(eth); 1673 if (err) 1674 return err; 1675 } 1676 1677 /* Enable random early drop and set drop threshold automatically */ 1678 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1679 MTK_QDMA_FC_THRES); 1680 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1681 1682 return 0; 1683 } 1684 1685 static void mtk_dma_free(struct mtk_eth *eth) 1686 { 1687 int i; 1688 1689 for (i = 0; i < MTK_MAC_COUNT; i++) 1690 if (eth->netdev[i]) 1691 netdev_reset_queue(eth->netdev[i]); 1692 if (eth->scratch_ring) { 1693 dma_free_coherent(eth->dev, 1694 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 1695 eth->scratch_ring, 1696 eth->phy_scratch_ring); 1697 eth->scratch_ring = NULL; 1698 eth->phy_scratch_ring = 0; 1699 } 1700 mtk_tx_clean(eth); 1701 mtk_rx_clean(eth, ð->rx_ring[0]); 1702 mtk_rx_clean(eth, ð->rx_ring_qdma); 1703 1704 if (eth->hwlro) { 1705 mtk_hwlro_rx_uninit(eth); 1706 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1707 mtk_rx_clean(eth, ð->rx_ring[i]); 1708 } 1709 1710 kfree(eth->scratch_head); 1711 } 1712 1713 static void mtk_tx_timeout(struct net_device *dev) 1714 { 1715 struct mtk_mac *mac = netdev_priv(dev); 1716 struct mtk_eth *eth = mac->hw; 1717 1718 eth->netdev[mac->id]->stats.tx_errors++; 1719 netif_err(eth, tx_err, dev, 1720 "transmit timed out\n"); 1721 schedule_work(ð->pending_work); 1722 } 1723 1724 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 1725 { 1726 struct mtk_eth *eth = _eth; 1727 1728 if (likely(napi_schedule_prep(ð->rx_napi))) { 1729 __napi_schedule(ð->rx_napi); 1730 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1731 } 1732 1733 return IRQ_HANDLED; 1734 } 1735 1736 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 1737 { 1738 struct mtk_eth *eth = _eth; 1739 1740 if (likely(napi_schedule_prep(ð->tx_napi))) { 1741 __napi_schedule(ð->tx_napi); 1742 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1743 } 1744 1745 return IRQ_HANDLED; 1746 } 1747 1748 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 1749 { 1750 struct mtk_eth *eth = _eth; 1751 1752 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { 1753 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) 1754 mtk_handle_irq_rx(irq, _eth); 1755 } 1756 if (mtk_r32(eth, MTK_QDMA_INT_MASK) & MTK_TX_DONE_INT) { 1757 if (mtk_r32(eth, MTK_QMTK_INT_STATUS) & MTK_TX_DONE_INT) 1758 mtk_handle_irq_tx(irq, _eth); 1759 } 1760 1761 return IRQ_HANDLED; 1762 } 1763 1764 #ifdef CONFIG_NET_POLL_CONTROLLER 1765 static void mtk_poll_controller(struct net_device *dev) 1766 { 1767 struct mtk_mac *mac = netdev_priv(dev); 1768 struct mtk_eth *eth = mac->hw; 1769 1770 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1771 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1772 mtk_handle_irq_rx(eth->irq[2], dev); 1773 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1774 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1775 } 1776 #endif 1777 1778 static int mtk_start_dma(struct mtk_eth *eth) 1779 { 1780 int err; 1781 1782 err = mtk_dma_init(eth); 1783 if (err) { 1784 mtk_dma_free(eth); 1785 return err; 1786 } 1787 1788 mtk_w32(eth, 1789 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 1790 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | 1791 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1792 MTK_RX_BT_32DWORDS, 1793 MTK_QDMA_GLO_CFG); 1794 1795 mtk_w32(eth, 1796 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1797 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 1798 MTK_PDMA_GLO_CFG); 1799 1800 return 0; 1801 } 1802 1803 static int mtk_open(struct net_device *dev) 1804 { 1805 struct mtk_mac *mac = netdev_priv(dev); 1806 struct mtk_eth *eth = mac->hw; 1807 1808 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1809 if (!refcount_read(ð->dma_refcnt)) { 1810 int err = mtk_start_dma(eth); 1811 1812 if (err) 1813 return err; 1814 1815 napi_enable(ð->tx_napi); 1816 napi_enable(ð->rx_napi); 1817 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1818 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1819 refcount_set(ð->dma_refcnt, 1); 1820 } 1821 else 1822 refcount_inc(ð->dma_refcnt); 1823 1824 phy_start(dev->phydev); 1825 netif_start_queue(dev); 1826 1827 return 0; 1828 } 1829 1830 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1831 { 1832 u32 val; 1833 int i; 1834 1835 /* stop the dma engine */ 1836 spin_lock_bh(ð->page_lock); 1837 val = mtk_r32(eth, glo_cfg); 1838 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1839 glo_cfg); 1840 spin_unlock_bh(ð->page_lock); 1841 1842 /* wait for dma stop */ 1843 for (i = 0; i < 10; i++) { 1844 val = mtk_r32(eth, glo_cfg); 1845 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1846 msleep(20); 1847 continue; 1848 } 1849 break; 1850 } 1851 } 1852 1853 static int mtk_stop(struct net_device *dev) 1854 { 1855 struct mtk_mac *mac = netdev_priv(dev); 1856 struct mtk_eth *eth = mac->hw; 1857 1858 netif_tx_disable(dev); 1859 phy_stop(dev->phydev); 1860 1861 /* only shutdown DMA if this is the last user */ 1862 if (!refcount_dec_and_test(ð->dma_refcnt)) 1863 return 0; 1864 1865 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1866 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1867 napi_disable(ð->tx_napi); 1868 napi_disable(ð->rx_napi); 1869 1870 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1871 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 1872 1873 mtk_dma_free(eth); 1874 1875 return 0; 1876 } 1877 1878 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 1879 { 1880 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1881 reset_bits, 1882 reset_bits); 1883 1884 usleep_range(1000, 1100); 1885 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1886 reset_bits, 1887 ~reset_bits); 1888 mdelay(10); 1889 } 1890 1891 static void mtk_clk_disable(struct mtk_eth *eth) 1892 { 1893 int clk; 1894 1895 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 1896 clk_disable_unprepare(eth->clks[clk]); 1897 } 1898 1899 static int mtk_clk_enable(struct mtk_eth *eth) 1900 { 1901 int clk, ret; 1902 1903 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 1904 ret = clk_prepare_enable(eth->clks[clk]); 1905 if (ret) 1906 goto err_disable_clks; 1907 } 1908 1909 return 0; 1910 1911 err_disable_clks: 1912 while (--clk >= 0) 1913 clk_disable_unprepare(eth->clks[clk]); 1914 1915 return ret; 1916 } 1917 1918 static int mtk_hw_init(struct mtk_eth *eth) 1919 { 1920 int i, val, ret; 1921 1922 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 1923 return 0; 1924 1925 pm_runtime_enable(eth->dev); 1926 pm_runtime_get_sync(eth->dev); 1927 1928 ret = mtk_clk_enable(eth); 1929 if (ret) 1930 goto err_disable_pm; 1931 1932 ethsys_reset(eth, RSTCTRL_FE); 1933 ethsys_reset(eth, RSTCTRL_PPE); 1934 1935 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 1936 for (i = 0; i < MTK_MAC_COUNT; i++) { 1937 if (!eth->mac[i]) 1938 continue; 1939 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id); 1940 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id); 1941 } 1942 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 1943 1944 if (eth->pctl) { 1945 /* Set GE2 driving and slew rate */ 1946 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1947 1948 /* set GE2 TDSEL */ 1949 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1950 1951 /* set GE2 TUNE */ 1952 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1953 } 1954 1955 /* Set linkdown as the default for each GMAC. Its own MCR would be set 1956 * up with the more appropriate value when mtk_phy_link_adjust call is 1957 * being invoked. 1958 */ 1959 for (i = 0; i < MTK_MAC_COUNT; i++) 1960 mtk_w32(eth, 0, MTK_MAC_MCR(i)); 1961 1962 /* Indicates CDM to parse the MTK special tag from CPU 1963 * which also is working out for untag packets. 1964 */ 1965 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 1966 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 1967 1968 /* Enable RX VLan Offloading */ 1969 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1970 1971 /* enable interrupt delay for RX */ 1972 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 1973 1974 /* disable delay and normal interrupt */ 1975 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1976 mtk_tx_irq_disable(eth, ~0); 1977 mtk_rx_irq_disable(eth, ~0); 1978 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1979 mtk_w32(eth, 0, MTK_RST_GL); 1980 1981 /* FE int grouping */ 1982 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 1983 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 1984 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 1985 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 1986 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 1987 1988 for (i = 0; i < 2; i++) { 1989 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1990 1991 /* setup the forward port to send frame to PDMA */ 1992 val &= ~0xffff; 1993 1994 /* Enable RX checksum */ 1995 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 1996 1997 /* setup the mac dma */ 1998 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 1999 } 2000 2001 return 0; 2002 2003 err_disable_pm: 2004 pm_runtime_put_sync(eth->dev); 2005 pm_runtime_disable(eth->dev); 2006 2007 return ret; 2008 } 2009 2010 static int mtk_hw_deinit(struct mtk_eth *eth) 2011 { 2012 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2013 return 0; 2014 2015 mtk_clk_disable(eth); 2016 2017 pm_runtime_put_sync(eth->dev); 2018 pm_runtime_disable(eth->dev); 2019 2020 return 0; 2021 } 2022 2023 static int __init mtk_init(struct net_device *dev) 2024 { 2025 struct mtk_mac *mac = netdev_priv(dev); 2026 struct mtk_eth *eth = mac->hw; 2027 const char *mac_addr; 2028 2029 mac_addr = of_get_mac_address(mac->of_node); 2030 if (mac_addr) 2031 ether_addr_copy(dev->dev_addr, mac_addr); 2032 2033 /* If the mac address is invalid, use random mac address */ 2034 if (!is_valid_ether_addr(dev->dev_addr)) { 2035 eth_hw_addr_random(dev); 2036 dev_err(eth->dev, "generated random MAC address %pM\n", 2037 dev->dev_addr); 2038 } 2039 2040 return mtk_phy_connect(dev); 2041 } 2042 2043 static void mtk_uninit(struct net_device *dev) 2044 { 2045 struct mtk_mac *mac = netdev_priv(dev); 2046 struct mtk_eth *eth = mac->hw; 2047 2048 phy_disconnect(dev->phydev); 2049 if (of_phy_is_fixed_link(mac->of_node)) 2050 of_phy_deregister_fixed_link(mac->of_node); 2051 mtk_tx_irq_disable(eth, ~0); 2052 mtk_rx_irq_disable(eth, ~0); 2053 } 2054 2055 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2056 { 2057 switch (cmd) { 2058 case SIOCGMIIPHY: 2059 case SIOCGMIIREG: 2060 case SIOCSMIIREG: 2061 return phy_mii_ioctl(dev->phydev, ifr, cmd); 2062 default: 2063 break; 2064 } 2065 2066 return -EOPNOTSUPP; 2067 } 2068 2069 static void mtk_pending_work(struct work_struct *work) 2070 { 2071 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2072 int err, i; 2073 unsigned long restart = 0; 2074 2075 rtnl_lock(); 2076 2077 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2078 2079 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2080 cpu_relax(); 2081 2082 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2083 /* stop all devices to make sure that dma is properly shut down */ 2084 for (i = 0; i < MTK_MAC_COUNT; i++) { 2085 if (!eth->netdev[i]) 2086 continue; 2087 mtk_stop(eth->netdev[i]); 2088 __set_bit(i, &restart); 2089 } 2090 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2091 2092 /* restart underlying hardware such as power, clock, pin mux 2093 * and the connected phy 2094 */ 2095 mtk_hw_deinit(eth); 2096 2097 if (eth->dev->pins) 2098 pinctrl_select_state(eth->dev->pins->p, 2099 eth->dev->pins->default_state); 2100 mtk_hw_init(eth); 2101 2102 for (i = 0; i < MTK_MAC_COUNT; i++) { 2103 if (!eth->mac[i] || 2104 of_phy_is_fixed_link(eth->mac[i]->of_node)) 2105 continue; 2106 err = phy_init_hw(eth->netdev[i]->phydev); 2107 if (err) 2108 dev_err(eth->dev, "%s: PHY init failed.\n", 2109 eth->netdev[i]->name); 2110 } 2111 2112 /* restart DMA and enable IRQs */ 2113 for (i = 0; i < MTK_MAC_COUNT; i++) { 2114 if (!test_bit(i, &restart)) 2115 continue; 2116 err = mtk_open(eth->netdev[i]); 2117 if (err) { 2118 netif_alert(eth, ifup, eth->netdev[i], 2119 "Driver up/down cycle failed, closing device.\n"); 2120 dev_close(eth->netdev[i]); 2121 } 2122 } 2123 2124 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2125 2126 clear_bit_unlock(MTK_RESETTING, ð->state); 2127 2128 rtnl_unlock(); 2129 } 2130 2131 static int mtk_free_dev(struct mtk_eth *eth) 2132 { 2133 int i; 2134 2135 for (i = 0; i < MTK_MAC_COUNT; i++) { 2136 if (!eth->netdev[i]) 2137 continue; 2138 free_netdev(eth->netdev[i]); 2139 } 2140 2141 return 0; 2142 } 2143 2144 static int mtk_unreg_dev(struct mtk_eth *eth) 2145 { 2146 int i; 2147 2148 for (i = 0; i < MTK_MAC_COUNT; i++) { 2149 if (!eth->netdev[i]) 2150 continue; 2151 unregister_netdev(eth->netdev[i]); 2152 } 2153 2154 return 0; 2155 } 2156 2157 static int mtk_cleanup(struct mtk_eth *eth) 2158 { 2159 mtk_unreg_dev(eth); 2160 mtk_free_dev(eth); 2161 cancel_work_sync(ð->pending_work); 2162 2163 return 0; 2164 } 2165 2166 static int mtk_get_link_ksettings(struct net_device *ndev, 2167 struct ethtool_link_ksettings *cmd) 2168 { 2169 struct mtk_mac *mac = netdev_priv(ndev); 2170 2171 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2172 return -EBUSY; 2173 2174 phy_ethtool_ksettings_get(ndev->phydev, cmd); 2175 2176 return 0; 2177 } 2178 2179 static int mtk_set_link_ksettings(struct net_device *ndev, 2180 const struct ethtool_link_ksettings *cmd) 2181 { 2182 struct mtk_mac *mac = netdev_priv(ndev); 2183 2184 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2185 return -EBUSY; 2186 2187 return phy_ethtool_ksettings_set(ndev->phydev, cmd); 2188 } 2189 2190 static void mtk_get_drvinfo(struct net_device *dev, 2191 struct ethtool_drvinfo *info) 2192 { 2193 struct mtk_mac *mac = netdev_priv(dev); 2194 2195 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2196 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2197 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2198 } 2199 2200 static u32 mtk_get_msglevel(struct net_device *dev) 2201 { 2202 struct mtk_mac *mac = netdev_priv(dev); 2203 2204 return mac->hw->msg_enable; 2205 } 2206 2207 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2208 { 2209 struct mtk_mac *mac = netdev_priv(dev); 2210 2211 mac->hw->msg_enable = value; 2212 } 2213 2214 static int mtk_nway_reset(struct net_device *dev) 2215 { 2216 struct mtk_mac *mac = netdev_priv(dev); 2217 2218 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2219 return -EBUSY; 2220 2221 return genphy_restart_aneg(dev->phydev); 2222 } 2223 2224 static u32 mtk_get_link(struct net_device *dev) 2225 { 2226 struct mtk_mac *mac = netdev_priv(dev); 2227 int err; 2228 2229 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2230 return -EBUSY; 2231 2232 err = genphy_update_link(dev->phydev); 2233 if (err) 2234 return ethtool_op_get_link(dev); 2235 2236 return dev->phydev->link; 2237 } 2238 2239 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2240 { 2241 int i; 2242 2243 switch (stringset) { 2244 case ETH_SS_STATS: 2245 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2246 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2247 data += ETH_GSTRING_LEN; 2248 } 2249 break; 2250 } 2251 } 2252 2253 static int mtk_get_sset_count(struct net_device *dev, int sset) 2254 { 2255 switch (sset) { 2256 case ETH_SS_STATS: 2257 return ARRAY_SIZE(mtk_ethtool_stats); 2258 default: 2259 return -EOPNOTSUPP; 2260 } 2261 } 2262 2263 static void mtk_get_ethtool_stats(struct net_device *dev, 2264 struct ethtool_stats *stats, u64 *data) 2265 { 2266 struct mtk_mac *mac = netdev_priv(dev); 2267 struct mtk_hw_stats *hwstats = mac->hw_stats; 2268 u64 *data_src, *data_dst; 2269 unsigned int start; 2270 int i; 2271 2272 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2273 return; 2274 2275 if (netif_running(dev) && netif_device_present(dev)) { 2276 if (spin_trylock_bh(&hwstats->stats_lock)) { 2277 mtk_stats_update_mac(mac); 2278 spin_unlock_bh(&hwstats->stats_lock); 2279 } 2280 } 2281 2282 data_src = (u64 *)hwstats; 2283 2284 do { 2285 data_dst = data; 2286 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2287 2288 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2289 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2290 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2291 } 2292 2293 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2294 u32 *rule_locs) 2295 { 2296 int ret = -EOPNOTSUPP; 2297 2298 switch (cmd->cmd) { 2299 case ETHTOOL_GRXRINGS: 2300 if (dev->features & NETIF_F_LRO) { 2301 cmd->data = MTK_MAX_RX_RING_NUM; 2302 ret = 0; 2303 } 2304 break; 2305 case ETHTOOL_GRXCLSRLCNT: 2306 if (dev->features & NETIF_F_LRO) { 2307 struct mtk_mac *mac = netdev_priv(dev); 2308 2309 cmd->rule_cnt = mac->hwlro_ip_cnt; 2310 ret = 0; 2311 } 2312 break; 2313 case ETHTOOL_GRXCLSRULE: 2314 if (dev->features & NETIF_F_LRO) 2315 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2316 break; 2317 case ETHTOOL_GRXCLSRLALL: 2318 if (dev->features & NETIF_F_LRO) 2319 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2320 rule_locs); 2321 break; 2322 default: 2323 break; 2324 } 2325 2326 return ret; 2327 } 2328 2329 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2330 { 2331 int ret = -EOPNOTSUPP; 2332 2333 switch (cmd->cmd) { 2334 case ETHTOOL_SRXCLSRLINS: 2335 if (dev->features & NETIF_F_LRO) 2336 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2337 break; 2338 case ETHTOOL_SRXCLSRLDEL: 2339 if (dev->features & NETIF_F_LRO) 2340 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2341 break; 2342 default: 2343 break; 2344 } 2345 2346 return ret; 2347 } 2348 2349 static const struct ethtool_ops mtk_ethtool_ops = { 2350 .get_link_ksettings = mtk_get_link_ksettings, 2351 .set_link_ksettings = mtk_set_link_ksettings, 2352 .get_drvinfo = mtk_get_drvinfo, 2353 .get_msglevel = mtk_get_msglevel, 2354 .set_msglevel = mtk_set_msglevel, 2355 .nway_reset = mtk_nway_reset, 2356 .get_link = mtk_get_link, 2357 .get_strings = mtk_get_strings, 2358 .get_sset_count = mtk_get_sset_count, 2359 .get_ethtool_stats = mtk_get_ethtool_stats, 2360 .get_rxnfc = mtk_get_rxnfc, 2361 .set_rxnfc = mtk_set_rxnfc, 2362 }; 2363 2364 static const struct net_device_ops mtk_netdev_ops = { 2365 .ndo_init = mtk_init, 2366 .ndo_uninit = mtk_uninit, 2367 .ndo_open = mtk_open, 2368 .ndo_stop = mtk_stop, 2369 .ndo_start_xmit = mtk_start_xmit, 2370 .ndo_set_mac_address = mtk_set_mac_address, 2371 .ndo_validate_addr = eth_validate_addr, 2372 .ndo_do_ioctl = mtk_do_ioctl, 2373 .ndo_tx_timeout = mtk_tx_timeout, 2374 .ndo_get_stats64 = mtk_get_stats64, 2375 .ndo_fix_features = mtk_fix_features, 2376 .ndo_set_features = mtk_set_features, 2377 #ifdef CONFIG_NET_POLL_CONTROLLER 2378 .ndo_poll_controller = mtk_poll_controller, 2379 #endif 2380 }; 2381 2382 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2383 { 2384 struct mtk_mac *mac; 2385 const __be32 *_id = of_get_property(np, "reg", NULL); 2386 int id, err; 2387 2388 if (!_id) { 2389 dev_err(eth->dev, "missing mac id\n"); 2390 return -EINVAL; 2391 } 2392 2393 id = be32_to_cpup(_id); 2394 if (id >= MTK_MAC_COUNT) { 2395 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2396 return -EINVAL; 2397 } 2398 2399 if (eth->netdev[id]) { 2400 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2401 return -EINVAL; 2402 } 2403 2404 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2405 if (!eth->netdev[id]) { 2406 dev_err(eth->dev, "alloc_etherdev failed\n"); 2407 return -ENOMEM; 2408 } 2409 mac = netdev_priv(eth->netdev[id]); 2410 eth->mac[id] = mac; 2411 mac->id = id; 2412 mac->hw = eth; 2413 mac->of_node = np; 2414 2415 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2416 mac->hwlro_ip_cnt = 0; 2417 2418 mac->hw_stats = devm_kzalloc(eth->dev, 2419 sizeof(*mac->hw_stats), 2420 GFP_KERNEL); 2421 if (!mac->hw_stats) { 2422 dev_err(eth->dev, "failed to allocate counter memory\n"); 2423 err = -ENOMEM; 2424 goto free_netdev; 2425 } 2426 spin_lock_init(&mac->hw_stats->stats_lock); 2427 u64_stats_init(&mac->hw_stats->syncp); 2428 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2429 2430 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2431 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2432 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2433 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2434 2435 eth->netdev[id]->hw_features = MTK_HW_FEATURES; 2436 if (eth->hwlro) 2437 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2438 2439 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 2440 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2441 eth->netdev[id]->features |= MTK_HW_FEATURES; 2442 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2443 2444 eth->netdev[id]->irq = eth->irq[0]; 2445 eth->netdev[id]->dev.of_node = np; 2446 2447 return 0; 2448 2449 free_netdev: 2450 free_netdev(eth->netdev[id]); 2451 return err; 2452 } 2453 2454 static int mtk_probe(struct platform_device *pdev) 2455 { 2456 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2457 struct device_node *mac_np; 2458 struct mtk_eth *eth; 2459 int err; 2460 int i; 2461 2462 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2463 if (!eth) 2464 return -ENOMEM; 2465 2466 eth->soc = of_device_get_match_data(&pdev->dev); 2467 2468 eth->dev = &pdev->dev; 2469 eth->base = devm_ioremap_resource(&pdev->dev, res); 2470 if (IS_ERR(eth->base)) 2471 return PTR_ERR(eth->base); 2472 2473 spin_lock_init(ð->page_lock); 2474 spin_lock_init(ð->tx_irq_lock); 2475 spin_lock_init(ð->rx_irq_lock); 2476 2477 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2478 "mediatek,ethsys"); 2479 if (IS_ERR(eth->ethsys)) { 2480 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2481 return PTR_ERR(eth->ethsys); 2482 } 2483 2484 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 2485 eth->sgmiisys = 2486 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2487 "mediatek,sgmiisys"); 2488 if (IS_ERR(eth->sgmiisys)) { 2489 dev_err(&pdev->dev, "no sgmiisys regmap found\n"); 2490 return PTR_ERR(eth->sgmiisys); 2491 } 2492 } 2493 2494 if (eth->soc->required_pctl) { 2495 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2496 "mediatek,pctl"); 2497 if (IS_ERR(eth->pctl)) { 2498 dev_err(&pdev->dev, "no pctl regmap found\n"); 2499 return PTR_ERR(eth->pctl); 2500 } 2501 } 2502 2503 for (i = 0; i < 3; i++) { 2504 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 2505 eth->irq[i] = eth->irq[0]; 2506 else 2507 eth->irq[i] = platform_get_irq(pdev, i); 2508 if (eth->irq[i] < 0) { 2509 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2510 return -ENXIO; 2511 } 2512 } 2513 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2514 eth->clks[i] = devm_clk_get(eth->dev, 2515 mtk_clks_source_name[i]); 2516 if (IS_ERR(eth->clks[i])) { 2517 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2518 return -EPROBE_DEFER; 2519 if (eth->soc->required_clks & BIT(i)) { 2520 dev_err(&pdev->dev, "clock %s not found\n", 2521 mtk_clks_source_name[i]); 2522 return -EINVAL; 2523 } 2524 eth->clks[i] = NULL; 2525 } 2526 } 2527 2528 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 2529 INIT_WORK(ð->pending_work, mtk_pending_work); 2530 2531 err = mtk_hw_init(eth); 2532 if (err) 2533 return err; 2534 2535 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 2536 2537 for_each_child_of_node(pdev->dev.of_node, mac_np) { 2538 if (!of_device_is_compatible(mac_np, 2539 "mediatek,eth-mac")) 2540 continue; 2541 2542 if (!of_device_is_available(mac_np)) 2543 continue; 2544 2545 err = mtk_add_mac(eth, mac_np); 2546 if (err) 2547 goto err_deinit_hw; 2548 } 2549 2550 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 2551 err = devm_request_irq(eth->dev, eth->irq[0], 2552 mtk_handle_irq, 0, 2553 dev_name(eth->dev), eth); 2554 } else { 2555 err = devm_request_irq(eth->dev, eth->irq[1], 2556 mtk_handle_irq_tx, 0, 2557 dev_name(eth->dev), eth); 2558 if (err) 2559 goto err_free_dev; 2560 2561 err = devm_request_irq(eth->dev, eth->irq[2], 2562 mtk_handle_irq_rx, 0, 2563 dev_name(eth->dev), eth); 2564 } 2565 if (err) 2566 goto err_free_dev; 2567 2568 err = mtk_mdio_init(eth); 2569 if (err) 2570 goto err_free_dev; 2571 2572 for (i = 0; i < MTK_MAX_DEVS; i++) { 2573 if (!eth->netdev[i]) 2574 continue; 2575 2576 err = register_netdev(eth->netdev[i]); 2577 if (err) { 2578 dev_err(eth->dev, "error bringing up device\n"); 2579 goto err_deinit_mdio; 2580 } else 2581 netif_info(eth, probe, eth->netdev[i], 2582 "mediatek frame engine at 0x%08lx, irq %d\n", 2583 eth->netdev[i]->base_addr, eth->irq[0]); 2584 } 2585 2586 /* we run 2 devices on the same DMA ring so we need a dummy device 2587 * for NAPI to work 2588 */ 2589 init_dummy_netdev(ð->dummy_dev); 2590 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 2591 MTK_NAPI_WEIGHT); 2592 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 2593 MTK_NAPI_WEIGHT); 2594 2595 platform_set_drvdata(pdev, eth); 2596 2597 return 0; 2598 2599 err_deinit_mdio: 2600 mtk_mdio_cleanup(eth); 2601 err_free_dev: 2602 mtk_free_dev(eth); 2603 err_deinit_hw: 2604 mtk_hw_deinit(eth); 2605 2606 return err; 2607 } 2608 2609 static int mtk_remove(struct platform_device *pdev) 2610 { 2611 struct mtk_eth *eth = platform_get_drvdata(pdev); 2612 int i; 2613 2614 /* stop all devices to make sure that dma is properly shut down */ 2615 for (i = 0; i < MTK_MAC_COUNT; i++) { 2616 if (!eth->netdev[i]) 2617 continue; 2618 mtk_stop(eth->netdev[i]); 2619 } 2620 2621 mtk_hw_deinit(eth); 2622 2623 netif_napi_del(ð->tx_napi); 2624 netif_napi_del(ð->rx_napi); 2625 mtk_cleanup(eth); 2626 mtk_mdio_cleanup(eth); 2627 2628 return 0; 2629 } 2630 2631 static const struct mtk_soc_data mt2701_data = { 2632 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO, 2633 .required_clks = MT7623_CLKS_BITMAP, 2634 .required_pctl = true, 2635 }; 2636 2637 static const struct mtk_soc_data mt7621_data = { 2638 .caps = MTK_SHARED_INT, 2639 .required_clks = MT7621_CLKS_BITMAP, 2640 .required_pctl = false, 2641 }; 2642 2643 static const struct mtk_soc_data mt7622_data = { 2644 .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW | MTK_HWLRO, 2645 .required_clks = MT7622_CLKS_BITMAP, 2646 .required_pctl = false, 2647 }; 2648 2649 static const struct mtk_soc_data mt7623_data = { 2650 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO, 2651 .required_clks = MT7623_CLKS_BITMAP, 2652 .required_pctl = true, 2653 }; 2654 2655 const struct of_device_id of_mtk_match[] = { 2656 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 2657 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 2658 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 2659 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 2660 {}, 2661 }; 2662 MODULE_DEVICE_TABLE(of, of_mtk_match); 2663 2664 static struct platform_driver mtk_driver = { 2665 .probe = mtk_probe, 2666 .remove = mtk_remove, 2667 .driver = { 2668 .name = "mtk_soc_eth", 2669 .of_match_table = of_mtk_match, 2670 }, 2671 }; 2672 2673 module_platform_driver(mtk_driver); 2674 2675 MODULE_LICENSE("GPL"); 2676 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 2677 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 2678