1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #include <linux/of_device.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/regmap.h> 20 #include <linux/clk.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/if_vlan.h> 23 #include <linux/reset.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/pinctrl/devinfo.h> 27 28 #include "mtk_eth_soc.h" 29 30 static int mtk_msg_level = -1; 31 module_param_named(msg_level, mtk_msg_level, int, 0); 32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 33 34 #define MTK_ETHTOOL_STAT(x) { #x, \ 35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 36 37 /* strings used by ethtool */ 38 static const struct mtk_ethtool_stats { 39 char str[ETH_GSTRING_LEN]; 40 u32 offset; 41 } mtk_ethtool_stats[] = { 42 MTK_ETHTOOL_STAT(tx_bytes), 43 MTK_ETHTOOL_STAT(tx_packets), 44 MTK_ETHTOOL_STAT(tx_skip), 45 MTK_ETHTOOL_STAT(tx_collisions), 46 MTK_ETHTOOL_STAT(rx_bytes), 47 MTK_ETHTOOL_STAT(rx_packets), 48 MTK_ETHTOOL_STAT(rx_overflow), 49 MTK_ETHTOOL_STAT(rx_fcs_errors), 50 MTK_ETHTOOL_STAT(rx_short_errors), 51 MTK_ETHTOOL_STAT(rx_long_errors), 52 MTK_ETHTOOL_STAT(rx_checksum_errors), 53 MTK_ETHTOOL_STAT(rx_flow_control_packets), 54 }; 55 56 static const char * const mtk_clks_source_name[] = { 57 "ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m", 58 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" 59 }; 60 61 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 62 { 63 __raw_writel(val, eth->base + reg); 64 } 65 66 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 67 { 68 return __raw_readl(eth->base + reg); 69 } 70 71 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 72 { 73 unsigned long t_start = jiffies; 74 75 while (1) { 76 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 77 return 0; 78 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 79 break; 80 usleep_range(10, 20); 81 } 82 83 dev_err(eth->dev, "mdio: MDIO timeout\n"); 84 return -1; 85 } 86 87 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 88 u32 phy_register, u32 write_data) 89 { 90 if (mtk_mdio_busy_wait(eth)) 91 return -1; 92 93 write_data &= 0xffff; 94 95 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 96 (phy_register << PHY_IAC_REG_SHIFT) | 97 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 98 MTK_PHY_IAC); 99 100 if (mtk_mdio_busy_wait(eth)) 101 return -1; 102 103 return 0; 104 } 105 106 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 107 { 108 u32 d; 109 110 if (mtk_mdio_busy_wait(eth)) 111 return 0xffff; 112 113 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 114 (phy_reg << PHY_IAC_REG_SHIFT) | 115 (phy_addr << PHY_IAC_ADDR_SHIFT), 116 MTK_PHY_IAC); 117 118 if (mtk_mdio_busy_wait(eth)) 119 return 0xffff; 120 121 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 122 123 return d; 124 } 125 126 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 127 int phy_reg, u16 val) 128 { 129 struct mtk_eth *eth = bus->priv; 130 131 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 132 } 133 134 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 135 { 136 struct mtk_eth *eth = bus->priv; 137 138 return _mtk_mdio_read(eth, phy_addr, phy_reg); 139 } 140 141 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 142 { 143 u32 val; 144 int ret; 145 146 val = (speed == SPEED_1000) ? 147 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 148 mtk_w32(eth, val, INTF_MODE); 149 150 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 151 ETHSYS_TRGMII_CLK_SEL362_5, 152 ETHSYS_TRGMII_CLK_SEL362_5); 153 154 val = (speed == SPEED_1000) ? 250000000 : 500000000; 155 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 156 if (ret) 157 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 158 159 val = (speed == SPEED_1000) ? 160 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 161 mtk_w32(eth, val, TRGMII_RCK_CTRL); 162 163 val = (speed == SPEED_1000) ? 164 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 165 mtk_w32(eth, val, TRGMII_TCK_CTRL); 166 } 167 168 static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id) 169 { 170 u32 val; 171 172 /* Setup the link timer and QPHY power up inside SGMIISYS */ 173 regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER, 174 SGMII_LINK_TIMER_DEFAULT); 175 176 regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val); 177 val |= SGMII_REMOTE_FAULT_DIS; 178 regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val); 179 180 regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val); 181 val |= SGMII_AN_RESTART; 182 regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val); 183 184 regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val); 185 val &= ~SGMII_PHYA_PWD; 186 regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val); 187 188 /* Determine MUX for which GMAC uses the SGMII interface */ 189 if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) { 190 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 191 val &= ~SYSCFG0_SGMII_MASK; 192 val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2; 193 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 194 195 dev_info(eth->dev, "setup shared sgmii for gmac=%d\n", 196 mac_id); 197 } 198 199 /* Setup the GMAC1 going through SGMII path when SoC also support 200 * ESW on GMAC1 201 */ 202 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) && 203 !mac_id) { 204 mtk_w32(eth, 0, MTK_MAC_MISC); 205 dev_info(eth->dev, "setup gmac1 going through sgmii"); 206 } 207 } 208 209 static void mtk_phy_link_adjust(struct net_device *dev) 210 { 211 struct mtk_mac *mac = netdev_priv(dev); 212 u16 lcl_adv = 0, rmt_adv = 0; 213 u8 flowctrl; 214 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 215 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 216 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 217 MAC_MCR_BACKPR_EN; 218 219 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 220 return; 221 222 switch (dev->phydev->speed) { 223 case SPEED_1000: 224 mcr |= MAC_MCR_SPEED_1000; 225 break; 226 case SPEED_100: 227 mcr |= MAC_MCR_SPEED_100; 228 break; 229 }; 230 231 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 232 !mac->id && !mac->trgmii) 233 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed); 234 235 if (dev->phydev->link) 236 mcr |= MAC_MCR_FORCE_LINK; 237 238 if (dev->phydev->duplex) { 239 mcr |= MAC_MCR_FORCE_DPX; 240 241 if (dev->phydev->pause) 242 rmt_adv = LPA_PAUSE_CAP; 243 if (dev->phydev->asym_pause) 244 rmt_adv |= LPA_PAUSE_ASYM; 245 246 lcl_adv = linkmode_adv_to_lcl_adv_t(dev->phydev->advertising); 247 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 248 249 if (flowctrl & FLOW_CTRL_TX) 250 mcr |= MAC_MCR_FORCE_TX_FC; 251 if (flowctrl & FLOW_CTRL_RX) 252 mcr |= MAC_MCR_FORCE_RX_FC; 253 254 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 255 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 256 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 257 } 258 259 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 260 261 if (dev->phydev->link) 262 netif_carrier_on(dev); 263 else 264 netif_carrier_off(dev); 265 266 if (!of_phy_is_fixed_link(mac->of_node)) 267 phy_print_status(dev->phydev); 268 } 269 270 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 271 struct device_node *phy_node) 272 { 273 struct phy_device *phydev; 274 int phy_mode; 275 276 phy_mode = of_get_phy_mode(phy_node); 277 if (phy_mode < 0) { 278 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 279 return -EINVAL; 280 } 281 282 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 283 mtk_phy_link_adjust, 0, phy_mode); 284 if (!phydev) { 285 dev_err(eth->dev, "could not connect to PHY\n"); 286 return -ENODEV; 287 } 288 289 dev_info(eth->dev, 290 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 291 mac->id, phydev_name(phydev), phydev->phy_id, 292 phydev->drv->name); 293 294 return 0; 295 } 296 297 static int mtk_phy_connect(struct net_device *dev) 298 { 299 struct mtk_mac *mac = netdev_priv(dev); 300 struct mtk_eth *eth; 301 struct device_node *np; 302 u32 val; 303 304 eth = mac->hw; 305 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 306 if (!np && of_phy_is_fixed_link(mac->of_node)) 307 if (!of_phy_register_fixed_link(mac->of_node)) 308 np = of_node_get(mac->of_node); 309 if (!np) 310 return -ENODEV; 311 312 mac->ge_mode = 0; 313 switch (of_get_phy_mode(np)) { 314 case PHY_INTERFACE_MODE_TRGMII: 315 mac->trgmii = true; 316 case PHY_INTERFACE_MODE_RGMII_TXID: 317 case PHY_INTERFACE_MODE_RGMII_RXID: 318 case PHY_INTERFACE_MODE_RGMII_ID: 319 case PHY_INTERFACE_MODE_RGMII: 320 break; 321 case PHY_INTERFACE_MODE_SGMII: 322 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) 323 mtk_gmac_sgmii_hw_setup(eth, mac->id); 324 break; 325 case PHY_INTERFACE_MODE_MII: 326 mac->ge_mode = 1; 327 break; 328 case PHY_INTERFACE_MODE_REVMII: 329 mac->ge_mode = 2; 330 break; 331 case PHY_INTERFACE_MODE_RMII: 332 if (!mac->id) 333 goto err_phy; 334 mac->ge_mode = 3; 335 break; 336 default: 337 goto err_phy; 338 } 339 340 /* put the gmac into the right mode */ 341 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 342 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 343 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id); 344 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 345 346 /* couple phydev to net_device */ 347 if (mtk_phy_connect_node(eth, mac, np)) 348 goto err_phy; 349 350 dev->phydev->autoneg = AUTONEG_ENABLE; 351 dev->phydev->speed = 0; 352 dev->phydev->duplex = 0; 353 354 phy_set_max_speed(dev->phydev, SPEED_1000); 355 phy_support_asym_pause(dev->phydev); 356 linkmode_copy(dev->phydev->advertising, dev->phydev->supported); 357 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 358 dev->phydev->advertising); 359 phy_start_aneg(dev->phydev); 360 361 of_node_put(np); 362 363 return 0; 364 365 err_phy: 366 if (of_phy_is_fixed_link(mac->of_node)) 367 of_phy_deregister_fixed_link(mac->of_node); 368 of_node_put(np); 369 dev_err(eth->dev, "%s: invalid phy\n", __func__); 370 return -EINVAL; 371 } 372 373 static int mtk_mdio_init(struct mtk_eth *eth) 374 { 375 struct device_node *mii_np; 376 int ret; 377 378 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 379 if (!mii_np) { 380 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 381 return -ENODEV; 382 } 383 384 if (!of_device_is_available(mii_np)) { 385 ret = -ENODEV; 386 goto err_put_node; 387 } 388 389 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 390 if (!eth->mii_bus) { 391 ret = -ENOMEM; 392 goto err_put_node; 393 } 394 395 eth->mii_bus->name = "mdio"; 396 eth->mii_bus->read = mtk_mdio_read; 397 eth->mii_bus->write = mtk_mdio_write; 398 eth->mii_bus->priv = eth; 399 eth->mii_bus->parent = eth->dev; 400 401 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 402 ret = of_mdiobus_register(eth->mii_bus, mii_np); 403 404 err_put_node: 405 of_node_put(mii_np); 406 return ret; 407 } 408 409 static void mtk_mdio_cleanup(struct mtk_eth *eth) 410 { 411 if (!eth->mii_bus) 412 return; 413 414 mdiobus_unregister(eth->mii_bus); 415 } 416 417 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 418 { 419 unsigned long flags; 420 u32 val; 421 422 spin_lock_irqsave(ð->tx_irq_lock, flags); 423 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 424 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); 425 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 426 } 427 428 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 429 { 430 unsigned long flags; 431 u32 val; 432 433 spin_lock_irqsave(ð->tx_irq_lock, flags); 434 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 435 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); 436 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 437 } 438 439 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 440 { 441 unsigned long flags; 442 u32 val; 443 444 spin_lock_irqsave(ð->rx_irq_lock, flags); 445 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 446 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 447 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 448 } 449 450 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 451 { 452 unsigned long flags; 453 u32 val; 454 455 spin_lock_irqsave(ð->rx_irq_lock, flags); 456 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 457 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 458 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 459 } 460 461 static int mtk_set_mac_address(struct net_device *dev, void *p) 462 { 463 int ret = eth_mac_addr(dev, p); 464 struct mtk_mac *mac = netdev_priv(dev); 465 const char *macaddr = dev->dev_addr; 466 467 if (ret) 468 return ret; 469 470 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 471 return -EBUSY; 472 473 spin_lock_bh(&mac->hw->page_lock); 474 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 475 MTK_GDMA_MAC_ADRH(mac->id)); 476 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 477 (macaddr[4] << 8) | macaddr[5], 478 MTK_GDMA_MAC_ADRL(mac->id)); 479 spin_unlock_bh(&mac->hw->page_lock); 480 481 return 0; 482 } 483 484 void mtk_stats_update_mac(struct mtk_mac *mac) 485 { 486 struct mtk_hw_stats *hw_stats = mac->hw_stats; 487 unsigned int base = MTK_GDM1_TX_GBCNT; 488 u64 stats; 489 490 base += hw_stats->reg_offset; 491 492 u64_stats_update_begin(&hw_stats->syncp); 493 494 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 495 stats = mtk_r32(mac->hw, base + 0x04); 496 if (stats) 497 hw_stats->rx_bytes += (stats << 32); 498 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 499 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 500 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 501 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 502 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 503 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 504 hw_stats->rx_flow_control_packets += 505 mtk_r32(mac->hw, base + 0x24); 506 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 507 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 508 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 509 stats = mtk_r32(mac->hw, base + 0x34); 510 if (stats) 511 hw_stats->tx_bytes += (stats << 32); 512 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 513 u64_stats_update_end(&hw_stats->syncp); 514 } 515 516 static void mtk_stats_update(struct mtk_eth *eth) 517 { 518 int i; 519 520 for (i = 0; i < MTK_MAC_COUNT; i++) { 521 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 522 continue; 523 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 524 mtk_stats_update_mac(eth->mac[i]); 525 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 526 } 527 } 528 } 529 530 static void mtk_get_stats64(struct net_device *dev, 531 struct rtnl_link_stats64 *storage) 532 { 533 struct mtk_mac *mac = netdev_priv(dev); 534 struct mtk_hw_stats *hw_stats = mac->hw_stats; 535 unsigned int start; 536 537 if (netif_running(dev) && netif_device_present(dev)) { 538 if (spin_trylock_bh(&hw_stats->stats_lock)) { 539 mtk_stats_update_mac(mac); 540 spin_unlock_bh(&hw_stats->stats_lock); 541 } 542 } 543 544 do { 545 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 546 storage->rx_packets = hw_stats->rx_packets; 547 storage->tx_packets = hw_stats->tx_packets; 548 storage->rx_bytes = hw_stats->rx_bytes; 549 storage->tx_bytes = hw_stats->tx_bytes; 550 storage->collisions = hw_stats->tx_collisions; 551 storage->rx_length_errors = hw_stats->rx_short_errors + 552 hw_stats->rx_long_errors; 553 storage->rx_over_errors = hw_stats->rx_overflow; 554 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 555 storage->rx_errors = hw_stats->rx_checksum_errors; 556 storage->tx_aborted_errors = hw_stats->tx_skip; 557 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 558 559 storage->tx_errors = dev->stats.tx_errors; 560 storage->rx_dropped = dev->stats.rx_dropped; 561 storage->tx_dropped = dev->stats.tx_dropped; 562 } 563 564 static inline int mtk_max_frag_size(int mtu) 565 { 566 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 567 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 568 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 569 570 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 571 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 572 } 573 574 static inline int mtk_max_buf_size(int frag_size) 575 { 576 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 577 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 578 579 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 580 581 return buf_size; 582 } 583 584 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 585 struct mtk_rx_dma *dma_rxd) 586 { 587 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 588 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 589 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 590 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 591 } 592 593 /* the qdma core needs scratch memory to be setup */ 594 static int mtk_init_fq_dma(struct mtk_eth *eth) 595 { 596 dma_addr_t phy_ring_tail; 597 int cnt = MTK_DMA_SIZE; 598 dma_addr_t dma_addr; 599 int i; 600 601 eth->scratch_ring = dma_alloc_coherent(eth->dev, 602 cnt * sizeof(struct mtk_tx_dma), 603 ð->phy_scratch_ring, 604 GFP_ATOMIC); 605 if (unlikely(!eth->scratch_ring)) 606 return -ENOMEM; 607 608 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 609 GFP_KERNEL); 610 if (unlikely(!eth->scratch_head)) 611 return -ENOMEM; 612 613 dma_addr = dma_map_single(eth->dev, 614 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 615 DMA_FROM_DEVICE); 616 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 617 return -ENOMEM; 618 619 phy_ring_tail = eth->phy_scratch_ring + 620 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 621 622 for (i = 0; i < cnt; i++) { 623 eth->scratch_ring[i].txd1 = 624 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 625 if (i < cnt - 1) 626 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 627 ((i + 1) * sizeof(struct mtk_tx_dma))); 628 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 629 } 630 631 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 632 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 633 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 634 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 635 636 return 0; 637 } 638 639 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 640 { 641 void *ret = ring->dma; 642 643 return ret + (desc - ring->phys); 644 } 645 646 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 647 struct mtk_tx_dma *txd) 648 { 649 int idx = txd - ring->dma; 650 651 return &ring->buf[idx]; 652 } 653 654 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 655 { 656 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 657 dma_unmap_single(eth->dev, 658 dma_unmap_addr(tx_buf, dma_addr0), 659 dma_unmap_len(tx_buf, dma_len0), 660 DMA_TO_DEVICE); 661 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 662 dma_unmap_page(eth->dev, 663 dma_unmap_addr(tx_buf, dma_addr0), 664 dma_unmap_len(tx_buf, dma_len0), 665 DMA_TO_DEVICE); 666 } 667 tx_buf->flags = 0; 668 if (tx_buf->skb && 669 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 670 dev_kfree_skb_any(tx_buf->skb); 671 tx_buf->skb = NULL; 672 } 673 674 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 675 int tx_num, struct mtk_tx_ring *ring, bool gso) 676 { 677 struct mtk_mac *mac = netdev_priv(dev); 678 struct mtk_eth *eth = mac->hw; 679 struct mtk_tx_dma *itxd, *txd; 680 struct mtk_tx_buf *itx_buf, *tx_buf; 681 dma_addr_t mapped_addr; 682 unsigned int nr_frags; 683 int i, n_desc = 1; 684 u32 txd4 = 0, fport; 685 686 itxd = ring->next_free; 687 if (itxd == ring->last_free) 688 return -ENOMEM; 689 690 /* set the forward port */ 691 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 692 txd4 |= fport; 693 694 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 695 memset(itx_buf, 0, sizeof(*itx_buf)); 696 697 if (gso) 698 txd4 |= TX_DMA_TSO; 699 700 /* TX Checksum offload */ 701 if (skb->ip_summed == CHECKSUM_PARTIAL) 702 txd4 |= TX_DMA_CHKSUM; 703 704 /* VLAN header offload */ 705 if (skb_vlan_tag_present(skb)) 706 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 707 708 mapped_addr = dma_map_single(eth->dev, skb->data, 709 skb_headlen(skb), DMA_TO_DEVICE); 710 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 711 return -ENOMEM; 712 713 WRITE_ONCE(itxd->txd1, mapped_addr); 714 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 715 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 716 MTK_TX_FLAGS_FPORT1; 717 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr); 718 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb)); 719 720 /* TX SG offload */ 721 txd = itxd; 722 nr_frags = skb_shinfo(skb)->nr_frags; 723 for (i = 0; i < nr_frags; i++) { 724 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 725 unsigned int offset = 0; 726 int frag_size = skb_frag_size(frag); 727 728 while (frag_size) { 729 bool last_frag = false; 730 unsigned int frag_map_size; 731 732 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 733 if (txd == ring->last_free) 734 goto err_dma; 735 736 n_desc++; 737 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 738 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 739 frag_map_size, 740 DMA_TO_DEVICE); 741 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 742 goto err_dma; 743 744 if (i == nr_frags - 1 && 745 (frag_size - frag_map_size) == 0) 746 last_frag = true; 747 748 WRITE_ONCE(txd->txd1, mapped_addr); 749 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 750 TX_DMA_PLEN0(frag_map_size) | 751 last_frag * TX_DMA_LS0)); 752 WRITE_ONCE(txd->txd4, fport); 753 754 tx_buf = mtk_desc_to_tx_buf(ring, txd); 755 memset(tx_buf, 0, sizeof(*tx_buf)); 756 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 757 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 758 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 759 MTK_TX_FLAGS_FPORT1; 760 761 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 762 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 763 frag_size -= frag_map_size; 764 offset += frag_map_size; 765 } 766 } 767 768 /* store skb to cleanup */ 769 itx_buf->skb = skb; 770 771 WRITE_ONCE(itxd->txd4, txd4); 772 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 773 (!nr_frags * TX_DMA_LS0))); 774 775 netdev_sent_queue(dev, skb->len); 776 skb_tx_timestamp(skb); 777 778 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 779 atomic_sub(n_desc, &ring->free_count); 780 781 /* make sure that all changes to the dma ring are flushed before we 782 * continue 783 */ 784 wmb(); 785 786 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more) 787 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 788 789 return 0; 790 791 err_dma: 792 do { 793 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 794 795 /* unmap dma */ 796 mtk_tx_unmap(eth, tx_buf); 797 798 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 799 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 800 } while (itxd != txd); 801 802 return -ENOMEM; 803 } 804 805 static inline int mtk_cal_txd_req(struct sk_buff *skb) 806 { 807 int i, nfrags; 808 struct skb_frag_struct *frag; 809 810 nfrags = 1; 811 if (skb_is_gso(skb)) { 812 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 813 frag = &skb_shinfo(skb)->frags[i]; 814 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); 815 } 816 } else { 817 nfrags += skb_shinfo(skb)->nr_frags; 818 } 819 820 return nfrags; 821 } 822 823 static int mtk_queue_stopped(struct mtk_eth *eth) 824 { 825 int i; 826 827 for (i = 0; i < MTK_MAC_COUNT; i++) { 828 if (!eth->netdev[i]) 829 continue; 830 if (netif_queue_stopped(eth->netdev[i])) 831 return 1; 832 } 833 834 return 0; 835 } 836 837 static void mtk_wake_queue(struct mtk_eth *eth) 838 { 839 int i; 840 841 for (i = 0; i < MTK_MAC_COUNT; i++) { 842 if (!eth->netdev[i]) 843 continue; 844 netif_wake_queue(eth->netdev[i]); 845 } 846 } 847 848 static void mtk_stop_queue(struct mtk_eth *eth) 849 { 850 int i; 851 852 for (i = 0; i < MTK_MAC_COUNT; i++) { 853 if (!eth->netdev[i]) 854 continue; 855 netif_stop_queue(eth->netdev[i]); 856 } 857 } 858 859 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 860 { 861 struct mtk_mac *mac = netdev_priv(dev); 862 struct mtk_eth *eth = mac->hw; 863 struct mtk_tx_ring *ring = ð->tx_ring; 864 struct net_device_stats *stats = &dev->stats; 865 bool gso = false; 866 int tx_num; 867 868 /* normally we can rely on the stack not calling this more than once, 869 * however we have 2 queues running on the same ring so we need to lock 870 * the ring access 871 */ 872 spin_lock(ð->page_lock); 873 874 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 875 goto drop; 876 877 tx_num = mtk_cal_txd_req(skb); 878 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 879 mtk_stop_queue(eth); 880 netif_err(eth, tx_queued, dev, 881 "Tx Ring full when queue awake!\n"); 882 spin_unlock(ð->page_lock); 883 return NETDEV_TX_BUSY; 884 } 885 886 /* TSO: fill MSS info in tcp checksum field */ 887 if (skb_is_gso(skb)) { 888 if (skb_cow_head(skb, 0)) { 889 netif_warn(eth, tx_err, dev, 890 "GSO expand head fail.\n"); 891 goto drop; 892 } 893 894 if (skb_shinfo(skb)->gso_type & 895 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 896 gso = true; 897 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 898 } 899 } 900 901 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 902 goto drop; 903 904 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 905 mtk_stop_queue(eth); 906 907 spin_unlock(ð->page_lock); 908 909 return NETDEV_TX_OK; 910 911 drop: 912 spin_unlock(ð->page_lock); 913 stats->tx_dropped++; 914 dev_kfree_skb_any(skb); 915 return NETDEV_TX_OK; 916 } 917 918 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 919 { 920 int i; 921 struct mtk_rx_ring *ring; 922 int idx; 923 924 if (!eth->hwlro) 925 return ð->rx_ring[0]; 926 927 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 928 ring = ð->rx_ring[i]; 929 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 930 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 931 ring->calc_idx_update = true; 932 return ring; 933 } 934 } 935 936 return NULL; 937 } 938 939 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 940 { 941 struct mtk_rx_ring *ring; 942 int i; 943 944 if (!eth->hwlro) { 945 ring = ð->rx_ring[0]; 946 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 947 } else { 948 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 949 ring = ð->rx_ring[i]; 950 if (ring->calc_idx_update) { 951 ring->calc_idx_update = false; 952 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 953 } 954 } 955 } 956 } 957 958 static int mtk_poll_rx(struct napi_struct *napi, int budget, 959 struct mtk_eth *eth) 960 { 961 struct mtk_rx_ring *ring; 962 int idx; 963 struct sk_buff *skb; 964 u8 *data, *new_data; 965 struct mtk_rx_dma *rxd, trxd; 966 int done = 0; 967 968 while (done < budget) { 969 struct net_device *netdev; 970 unsigned int pktlen; 971 dma_addr_t dma_addr; 972 int mac = 0; 973 974 ring = mtk_get_rx_ring(eth); 975 if (unlikely(!ring)) 976 goto rx_done; 977 978 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 979 rxd = &ring->dma[idx]; 980 data = ring->data[idx]; 981 982 mtk_rx_get_desc(&trxd, rxd); 983 if (!(trxd.rxd2 & RX_DMA_DONE)) 984 break; 985 986 /* find out which mac the packet come from. values start at 1 */ 987 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 988 RX_DMA_FPORT_MASK; 989 mac--; 990 991 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 992 !eth->netdev[mac])) 993 goto release_desc; 994 995 netdev = eth->netdev[mac]; 996 997 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 998 goto release_desc; 999 1000 /* alloc new buffer */ 1001 new_data = napi_alloc_frag(ring->frag_size); 1002 if (unlikely(!new_data)) { 1003 netdev->stats.rx_dropped++; 1004 goto release_desc; 1005 } 1006 dma_addr = dma_map_single(eth->dev, 1007 new_data + NET_SKB_PAD, 1008 ring->buf_size, 1009 DMA_FROM_DEVICE); 1010 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 1011 skb_free_frag(new_data); 1012 netdev->stats.rx_dropped++; 1013 goto release_desc; 1014 } 1015 1016 /* receive data */ 1017 skb = build_skb(data, ring->frag_size); 1018 if (unlikely(!skb)) { 1019 skb_free_frag(new_data); 1020 netdev->stats.rx_dropped++; 1021 goto release_desc; 1022 } 1023 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1024 1025 dma_unmap_single(eth->dev, trxd.rxd1, 1026 ring->buf_size, DMA_FROM_DEVICE); 1027 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1028 skb->dev = netdev; 1029 skb_put(skb, pktlen); 1030 if (trxd.rxd4 & RX_DMA_L4_VALID) 1031 skb->ip_summed = CHECKSUM_UNNECESSARY; 1032 else 1033 skb_checksum_none_assert(skb); 1034 skb->protocol = eth_type_trans(skb, netdev); 1035 1036 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1037 RX_DMA_VID(trxd.rxd3)) 1038 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1039 RX_DMA_VID(trxd.rxd3)); 1040 skb_record_rx_queue(skb, 0); 1041 napi_gro_receive(napi, skb); 1042 1043 ring->data[idx] = new_data; 1044 rxd->rxd1 = (unsigned int)dma_addr; 1045 1046 release_desc: 1047 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1048 1049 ring->calc_idx = idx; 1050 1051 done++; 1052 } 1053 1054 rx_done: 1055 if (done) { 1056 /* make sure that all changes to the dma ring are flushed before 1057 * we continue 1058 */ 1059 wmb(); 1060 mtk_update_rx_cpu_idx(eth); 1061 } 1062 1063 return done; 1064 } 1065 1066 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1067 { 1068 struct mtk_tx_ring *ring = ð->tx_ring; 1069 struct mtk_tx_dma *desc; 1070 struct sk_buff *skb; 1071 struct mtk_tx_buf *tx_buf; 1072 unsigned int done[MTK_MAX_DEVS]; 1073 unsigned int bytes[MTK_MAX_DEVS]; 1074 u32 cpu, dma; 1075 int total = 0, i; 1076 1077 memset(done, 0, sizeof(done)); 1078 memset(bytes, 0, sizeof(bytes)); 1079 1080 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1081 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1082 1083 desc = mtk_qdma_phys_to_virt(ring, cpu); 1084 1085 while ((cpu != dma) && budget) { 1086 u32 next_cpu = desc->txd2; 1087 int mac = 0; 1088 1089 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1090 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1091 break; 1092 1093 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1094 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1095 mac = 1; 1096 1097 skb = tx_buf->skb; 1098 if (!skb) 1099 break; 1100 1101 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1102 bytes[mac] += skb->len; 1103 done[mac]++; 1104 budget--; 1105 } 1106 mtk_tx_unmap(eth, tx_buf); 1107 1108 ring->last_free = desc; 1109 atomic_inc(&ring->free_count); 1110 1111 cpu = next_cpu; 1112 } 1113 1114 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1115 1116 for (i = 0; i < MTK_MAC_COUNT; i++) { 1117 if (!eth->netdev[i] || !done[i]) 1118 continue; 1119 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1120 total += done[i]; 1121 } 1122 1123 if (mtk_queue_stopped(eth) && 1124 (atomic_read(&ring->free_count) > ring->thresh)) 1125 mtk_wake_queue(eth); 1126 1127 return total; 1128 } 1129 1130 static void mtk_handle_status_irq(struct mtk_eth *eth) 1131 { 1132 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1133 1134 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1135 mtk_stats_update(eth); 1136 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1137 MTK_INT_STATUS2); 1138 } 1139 } 1140 1141 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1142 { 1143 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1144 u32 status, mask; 1145 int tx_done = 0; 1146 1147 mtk_handle_status_irq(eth); 1148 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 1149 tx_done = mtk_poll_tx(eth, budget); 1150 1151 if (unlikely(netif_msg_intr(eth))) { 1152 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1153 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 1154 dev_info(eth->dev, 1155 "done tx %d, intr 0x%08x/0x%x\n", 1156 tx_done, status, mask); 1157 } 1158 1159 if (tx_done == budget) 1160 return budget; 1161 1162 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1163 if (status & MTK_TX_DONE_INT) 1164 return budget; 1165 1166 napi_complete(napi); 1167 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1168 1169 return tx_done; 1170 } 1171 1172 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1173 { 1174 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1175 u32 status, mask; 1176 int rx_done = 0; 1177 int remain_budget = budget; 1178 1179 mtk_handle_status_irq(eth); 1180 1181 poll_again: 1182 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1183 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1184 1185 if (unlikely(netif_msg_intr(eth))) { 1186 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1187 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1188 dev_info(eth->dev, 1189 "done rx %d, intr 0x%08x/0x%x\n", 1190 rx_done, status, mask); 1191 } 1192 if (rx_done == remain_budget) 1193 return budget; 1194 1195 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1196 if (status & MTK_RX_DONE_INT) { 1197 remain_budget -= rx_done; 1198 goto poll_again; 1199 } 1200 napi_complete(napi); 1201 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1202 1203 return rx_done + budget - remain_budget; 1204 } 1205 1206 static int mtk_tx_alloc(struct mtk_eth *eth) 1207 { 1208 struct mtk_tx_ring *ring = ð->tx_ring; 1209 int i, sz = sizeof(*ring->dma); 1210 1211 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1212 GFP_KERNEL); 1213 if (!ring->buf) 1214 goto no_tx_mem; 1215 1216 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1217 &ring->phys, GFP_ATOMIC); 1218 if (!ring->dma) 1219 goto no_tx_mem; 1220 1221 for (i = 0; i < MTK_DMA_SIZE; i++) { 1222 int next = (i + 1) % MTK_DMA_SIZE; 1223 u32 next_ptr = ring->phys + next * sz; 1224 1225 ring->dma[i].txd2 = next_ptr; 1226 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1227 } 1228 1229 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1230 ring->next_free = &ring->dma[0]; 1231 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1232 ring->thresh = MAX_SKB_FRAGS; 1233 1234 /* make sure that all changes to the dma ring are flushed before we 1235 * continue 1236 */ 1237 wmb(); 1238 1239 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1240 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1241 mtk_w32(eth, 1242 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1243 MTK_QTX_CRX_PTR); 1244 mtk_w32(eth, 1245 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1246 MTK_QTX_DRX_PTR); 1247 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1248 1249 return 0; 1250 1251 no_tx_mem: 1252 return -ENOMEM; 1253 } 1254 1255 static void mtk_tx_clean(struct mtk_eth *eth) 1256 { 1257 struct mtk_tx_ring *ring = ð->tx_ring; 1258 int i; 1259 1260 if (ring->buf) { 1261 for (i = 0; i < MTK_DMA_SIZE; i++) 1262 mtk_tx_unmap(eth, &ring->buf[i]); 1263 kfree(ring->buf); 1264 ring->buf = NULL; 1265 } 1266 1267 if (ring->dma) { 1268 dma_free_coherent(eth->dev, 1269 MTK_DMA_SIZE * sizeof(*ring->dma), 1270 ring->dma, 1271 ring->phys); 1272 ring->dma = NULL; 1273 } 1274 } 1275 1276 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1277 { 1278 struct mtk_rx_ring *ring; 1279 int rx_data_len, rx_dma_size; 1280 int i; 1281 u32 offset = 0; 1282 1283 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1284 if (ring_no) 1285 return -EINVAL; 1286 ring = ð->rx_ring_qdma; 1287 offset = 0x1000; 1288 } else { 1289 ring = ð->rx_ring[ring_no]; 1290 } 1291 1292 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1293 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1294 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1295 } else { 1296 rx_data_len = ETH_DATA_LEN; 1297 rx_dma_size = MTK_DMA_SIZE; 1298 } 1299 1300 ring->frag_size = mtk_max_frag_size(rx_data_len); 1301 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1302 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1303 GFP_KERNEL); 1304 if (!ring->data) 1305 return -ENOMEM; 1306 1307 for (i = 0; i < rx_dma_size; i++) { 1308 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1309 if (!ring->data[i]) 1310 return -ENOMEM; 1311 } 1312 1313 ring->dma = dma_alloc_coherent(eth->dev, 1314 rx_dma_size * sizeof(*ring->dma), 1315 &ring->phys, GFP_ATOMIC); 1316 if (!ring->dma) 1317 return -ENOMEM; 1318 1319 for (i = 0; i < rx_dma_size; i++) { 1320 dma_addr_t dma_addr = dma_map_single(eth->dev, 1321 ring->data[i] + NET_SKB_PAD, 1322 ring->buf_size, 1323 DMA_FROM_DEVICE); 1324 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1325 return -ENOMEM; 1326 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1327 1328 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1329 } 1330 ring->dma_size = rx_dma_size; 1331 ring->calc_idx_update = false; 1332 ring->calc_idx = rx_dma_size - 1; 1333 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1334 /* make sure that all changes to the dma ring are flushed before we 1335 * continue 1336 */ 1337 wmb(); 1338 1339 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1340 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1341 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1342 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1343 1344 return 0; 1345 } 1346 1347 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1348 { 1349 int i; 1350 1351 if (ring->data && ring->dma) { 1352 for (i = 0; i < ring->dma_size; i++) { 1353 if (!ring->data[i]) 1354 continue; 1355 if (!ring->dma[i].rxd1) 1356 continue; 1357 dma_unmap_single(eth->dev, 1358 ring->dma[i].rxd1, 1359 ring->buf_size, 1360 DMA_FROM_DEVICE); 1361 skb_free_frag(ring->data[i]); 1362 } 1363 kfree(ring->data); 1364 ring->data = NULL; 1365 } 1366 1367 if (ring->dma) { 1368 dma_free_coherent(eth->dev, 1369 ring->dma_size * sizeof(*ring->dma), 1370 ring->dma, 1371 ring->phys); 1372 ring->dma = NULL; 1373 } 1374 } 1375 1376 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1377 { 1378 int i; 1379 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1380 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1381 1382 /* set LRO rings to auto-learn modes */ 1383 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1384 1385 /* validate LRO ring */ 1386 ring_ctrl_dw2 |= MTK_RING_VLD; 1387 1388 /* set AGE timer (unit: 20us) */ 1389 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1390 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1391 1392 /* set max AGG timer (unit: 20us) */ 1393 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1394 1395 /* set max LRO AGG count */ 1396 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1397 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1398 1399 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1400 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1401 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1402 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1403 } 1404 1405 /* IPv4 checksum update enable */ 1406 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1407 1408 /* switch priority comparison to packet count mode */ 1409 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1410 1411 /* bandwidth threshold setting */ 1412 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1413 1414 /* auto-learn score delta setting */ 1415 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1416 1417 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1418 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1419 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1420 1421 /* set HW LRO mode & the max aggregation count for rx packets */ 1422 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1423 1424 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1425 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1426 1427 /* enable HW LRO */ 1428 lro_ctrl_dw0 |= MTK_LRO_EN; 1429 1430 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1431 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1432 1433 return 0; 1434 } 1435 1436 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1437 { 1438 int i; 1439 u32 val; 1440 1441 /* relinquish lro rings, flush aggregated packets */ 1442 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1443 1444 /* wait for relinquishments done */ 1445 for (i = 0; i < 10; i++) { 1446 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1447 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1448 msleep(20); 1449 continue; 1450 } 1451 break; 1452 } 1453 1454 /* invalidate lro rings */ 1455 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1456 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1457 1458 /* disable HW LRO */ 1459 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1460 } 1461 1462 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1463 { 1464 u32 reg_val; 1465 1466 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1467 1468 /* invalidate the IP setting */ 1469 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1470 1471 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1472 1473 /* validate the IP setting */ 1474 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1475 } 1476 1477 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1478 { 1479 u32 reg_val; 1480 1481 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1482 1483 /* invalidate the IP setting */ 1484 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1485 1486 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1487 } 1488 1489 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1490 { 1491 int cnt = 0; 1492 int i; 1493 1494 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1495 if (mac->hwlro_ip[i]) 1496 cnt++; 1497 } 1498 1499 return cnt; 1500 } 1501 1502 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1503 struct ethtool_rxnfc *cmd) 1504 { 1505 struct ethtool_rx_flow_spec *fsp = 1506 (struct ethtool_rx_flow_spec *)&cmd->fs; 1507 struct mtk_mac *mac = netdev_priv(dev); 1508 struct mtk_eth *eth = mac->hw; 1509 int hwlro_idx; 1510 1511 if ((fsp->flow_type != TCP_V4_FLOW) || 1512 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1513 (fsp->location > 1)) 1514 return -EINVAL; 1515 1516 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1517 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1518 1519 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1520 1521 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1522 1523 return 0; 1524 } 1525 1526 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1527 struct ethtool_rxnfc *cmd) 1528 { 1529 struct ethtool_rx_flow_spec *fsp = 1530 (struct ethtool_rx_flow_spec *)&cmd->fs; 1531 struct mtk_mac *mac = netdev_priv(dev); 1532 struct mtk_eth *eth = mac->hw; 1533 int hwlro_idx; 1534 1535 if (fsp->location > 1) 1536 return -EINVAL; 1537 1538 mac->hwlro_ip[fsp->location] = 0; 1539 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1540 1541 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1542 1543 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1544 1545 return 0; 1546 } 1547 1548 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1549 { 1550 struct mtk_mac *mac = netdev_priv(dev); 1551 struct mtk_eth *eth = mac->hw; 1552 int i, hwlro_idx; 1553 1554 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1555 mac->hwlro_ip[i] = 0; 1556 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1557 1558 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1559 } 1560 1561 mac->hwlro_ip_cnt = 0; 1562 } 1563 1564 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1565 struct ethtool_rxnfc *cmd) 1566 { 1567 struct mtk_mac *mac = netdev_priv(dev); 1568 struct ethtool_rx_flow_spec *fsp = 1569 (struct ethtool_rx_flow_spec *)&cmd->fs; 1570 1571 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1572 fsp->flow_type = TCP_V4_FLOW; 1573 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1574 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1575 1576 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1577 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1578 fsp->h_u.tcp_ip4_spec.psrc = 0; 1579 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1580 fsp->h_u.tcp_ip4_spec.pdst = 0; 1581 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1582 fsp->h_u.tcp_ip4_spec.tos = 0; 1583 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1584 1585 return 0; 1586 } 1587 1588 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1589 struct ethtool_rxnfc *cmd, 1590 u32 *rule_locs) 1591 { 1592 struct mtk_mac *mac = netdev_priv(dev); 1593 int cnt = 0; 1594 int i; 1595 1596 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1597 if (mac->hwlro_ip[i]) { 1598 rule_locs[cnt] = i; 1599 cnt++; 1600 } 1601 } 1602 1603 cmd->rule_cnt = cnt; 1604 1605 return 0; 1606 } 1607 1608 static netdev_features_t mtk_fix_features(struct net_device *dev, 1609 netdev_features_t features) 1610 { 1611 if (!(features & NETIF_F_LRO)) { 1612 struct mtk_mac *mac = netdev_priv(dev); 1613 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1614 1615 if (ip_cnt) { 1616 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1617 1618 features |= NETIF_F_LRO; 1619 } 1620 } 1621 1622 return features; 1623 } 1624 1625 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1626 { 1627 int err = 0; 1628 1629 if (!((dev->features ^ features) & NETIF_F_LRO)) 1630 return 0; 1631 1632 if (!(features & NETIF_F_LRO)) 1633 mtk_hwlro_netdev_disable(dev); 1634 1635 return err; 1636 } 1637 1638 /* wait for DMA to finish whatever it is doing before we start using it again */ 1639 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1640 { 1641 unsigned long t_start = jiffies; 1642 1643 while (1) { 1644 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1645 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1646 return 0; 1647 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1648 break; 1649 } 1650 1651 dev_err(eth->dev, "DMA init timeout\n"); 1652 return -1; 1653 } 1654 1655 static int mtk_dma_init(struct mtk_eth *eth) 1656 { 1657 int err; 1658 u32 i; 1659 1660 if (mtk_dma_busy_wait(eth)) 1661 return -EBUSY; 1662 1663 /* QDMA needs scratch memory for internal reordering of the 1664 * descriptors 1665 */ 1666 err = mtk_init_fq_dma(eth); 1667 if (err) 1668 return err; 1669 1670 err = mtk_tx_alloc(eth); 1671 if (err) 1672 return err; 1673 1674 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 1675 if (err) 1676 return err; 1677 1678 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 1679 if (err) 1680 return err; 1681 1682 if (eth->hwlro) { 1683 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1684 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 1685 if (err) 1686 return err; 1687 } 1688 err = mtk_hwlro_rx_init(eth); 1689 if (err) 1690 return err; 1691 } 1692 1693 /* Enable random early drop and set drop threshold automatically */ 1694 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1695 MTK_QDMA_FC_THRES); 1696 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1697 1698 return 0; 1699 } 1700 1701 static void mtk_dma_free(struct mtk_eth *eth) 1702 { 1703 int i; 1704 1705 for (i = 0; i < MTK_MAC_COUNT; i++) 1706 if (eth->netdev[i]) 1707 netdev_reset_queue(eth->netdev[i]); 1708 if (eth->scratch_ring) { 1709 dma_free_coherent(eth->dev, 1710 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 1711 eth->scratch_ring, 1712 eth->phy_scratch_ring); 1713 eth->scratch_ring = NULL; 1714 eth->phy_scratch_ring = 0; 1715 } 1716 mtk_tx_clean(eth); 1717 mtk_rx_clean(eth, ð->rx_ring[0]); 1718 mtk_rx_clean(eth, ð->rx_ring_qdma); 1719 1720 if (eth->hwlro) { 1721 mtk_hwlro_rx_uninit(eth); 1722 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1723 mtk_rx_clean(eth, ð->rx_ring[i]); 1724 } 1725 1726 kfree(eth->scratch_head); 1727 } 1728 1729 static void mtk_tx_timeout(struct net_device *dev) 1730 { 1731 struct mtk_mac *mac = netdev_priv(dev); 1732 struct mtk_eth *eth = mac->hw; 1733 1734 eth->netdev[mac->id]->stats.tx_errors++; 1735 netif_err(eth, tx_err, dev, 1736 "transmit timed out\n"); 1737 schedule_work(ð->pending_work); 1738 } 1739 1740 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 1741 { 1742 struct mtk_eth *eth = _eth; 1743 1744 if (likely(napi_schedule_prep(ð->rx_napi))) { 1745 __napi_schedule(ð->rx_napi); 1746 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1747 } 1748 1749 return IRQ_HANDLED; 1750 } 1751 1752 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 1753 { 1754 struct mtk_eth *eth = _eth; 1755 1756 if (likely(napi_schedule_prep(ð->tx_napi))) { 1757 __napi_schedule(ð->tx_napi); 1758 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1759 } 1760 1761 return IRQ_HANDLED; 1762 } 1763 1764 #ifdef CONFIG_NET_POLL_CONTROLLER 1765 static void mtk_poll_controller(struct net_device *dev) 1766 { 1767 struct mtk_mac *mac = netdev_priv(dev); 1768 struct mtk_eth *eth = mac->hw; 1769 1770 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1771 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1772 mtk_handle_irq_rx(eth->irq[2], dev); 1773 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1774 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1775 } 1776 #endif 1777 1778 static int mtk_start_dma(struct mtk_eth *eth) 1779 { 1780 int err; 1781 1782 err = mtk_dma_init(eth); 1783 if (err) { 1784 mtk_dma_free(eth); 1785 return err; 1786 } 1787 1788 mtk_w32(eth, 1789 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 1790 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | 1791 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1792 MTK_RX_BT_32DWORDS, 1793 MTK_QDMA_GLO_CFG); 1794 1795 mtk_w32(eth, 1796 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1797 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 1798 MTK_PDMA_GLO_CFG); 1799 1800 return 0; 1801 } 1802 1803 static int mtk_open(struct net_device *dev) 1804 { 1805 struct mtk_mac *mac = netdev_priv(dev); 1806 struct mtk_eth *eth = mac->hw; 1807 1808 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1809 if (!refcount_read(ð->dma_refcnt)) { 1810 int err = mtk_start_dma(eth); 1811 1812 if (err) 1813 return err; 1814 1815 napi_enable(ð->tx_napi); 1816 napi_enable(ð->rx_napi); 1817 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1818 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1819 refcount_set(ð->dma_refcnt, 1); 1820 } 1821 else 1822 refcount_inc(ð->dma_refcnt); 1823 1824 phy_start(dev->phydev); 1825 netif_start_queue(dev); 1826 1827 return 0; 1828 } 1829 1830 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1831 { 1832 u32 val; 1833 int i; 1834 1835 /* stop the dma engine */ 1836 spin_lock_bh(ð->page_lock); 1837 val = mtk_r32(eth, glo_cfg); 1838 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1839 glo_cfg); 1840 spin_unlock_bh(ð->page_lock); 1841 1842 /* wait for dma stop */ 1843 for (i = 0; i < 10; i++) { 1844 val = mtk_r32(eth, glo_cfg); 1845 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1846 msleep(20); 1847 continue; 1848 } 1849 break; 1850 } 1851 } 1852 1853 static int mtk_stop(struct net_device *dev) 1854 { 1855 struct mtk_mac *mac = netdev_priv(dev); 1856 struct mtk_eth *eth = mac->hw; 1857 1858 netif_tx_disable(dev); 1859 phy_stop(dev->phydev); 1860 1861 /* only shutdown DMA if this is the last user */ 1862 if (!refcount_dec_and_test(ð->dma_refcnt)) 1863 return 0; 1864 1865 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1866 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1867 napi_disable(ð->tx_napi); 1868 napi_disable(ð->rx_napi); 1869 1870 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1871 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 1872 1873 mtk_dma_free(eth); 1874 1875 return 0; 1876 } 1877 1878 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 1879 { 1880 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1881 reset_bits, 1882 reset_bits); 1883 1884 usleep_range(1000, 1100); 1885 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1886 reset_bits, 1887 ~reset_bits); 1888 mdelay(10); 1889 } 1890 1891 static void mtk_clk_disable(struct mtk_eth *eth) 1892 { 1893 int clk; 1894 1895 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 1896 clk_disable_unprepare(eth->clks[clk]); 1897 } 1898 1899 static int mtk_clk_enable(struct mtk_eth *eth) 1900 { 1901 int clk, ret; 1902 1903 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 1904 ret = clk_prepare_enable(eth->clks[clk]); 1905 if (ret) 1906 goto err_disable_clks; 1907 } 1908 1909 return 0; 1910 1911 err_disable_clks: 1912 while (--clk >= 0) 1913 clk_disable_unprepare(eth->clks[clk]); 1914 1915 return ret; 1916 } 1917 1918 static int mtk_hw_init(struct mtk_eth *eth) 1919 { 1920 int i, val, ret; 1921 1922 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 1923 return 0; 1924 1925 pm_runtime_enable(eth->dev); 1926 pm_runtime_get_sync(eth->dev); 1927 1928 ret = mtk_clk_enable(eth); 1929 if (ret) 1930 goto err_disable_pm; 1931 1932 ethsys_reset(eth, RSTCTRL_FE); 1933 ethsys_reset(eth, RSTCTRL_PPE); 1934 1935 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 1936 for (i = 0; i < MTK_MAC_COUNT; i++) { 1937 if (!eth->mac[i]) 1938 continue; 1939 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id); 1940 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id); 1941 } 1942 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 1943 1944 if (eth->pctl) { 1945 /* Set GE2 driving and slew rate */ 1946 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1947 1948 /* set GE2 TDSEL */ 1949 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1950 1951 /* set GE2 TUNE */ 1952 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1953 } 1954 1955 /* Set linkdown as the default for each GMAC. Its own MCR would be set 1956 * up with the more appropriate value when mtk_phy_link_adjust call is 1957 * being invoked. 1958 */ 1959 for (i = 0; i < MTK_MAC_COUNT; i++) 1960 mtk_w32(eth, 0, MTK_MAC_MCR(i)); 1961 1962 /* Indicates CDM to parse the MTK special tag from CPU 1963 * which also is working out for untag packets. 1964 */ 1965 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 1966 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 1967 1968 /* Enable RX VLan Offloading */ 1969 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1970 1971 /* enable interrupt delay for RX */ 1972 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 1973 1974 /* disable delay and normal interrupt */ 1975 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1976 mtk_tx_irq_disable(eth, ~0); 1977 mtk_rx_irq_disable(eth, ~0); 1978 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1979 mtk_w32(eth, 0, MTK_RST_GL); 1980 1981 /* FE int grouping */ 1982 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 1983 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 1984 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 1985 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 1986 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 1987 1988 for (i = 0; i < 2; i++) { 1989 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1990 1991 /* setup the forward port to send frame to PDMA */ 1992 val &= ~0xffff; 1993 1994 /* Enable RX checksum */ 1995 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 1996 1997 /* setup the mac dma */ 1998 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 1999 } 2000 2001 return 0; 2002 2003 err_disable_pm: 2004 pm_runtime_put_sync(eth->dev); 2005 pm_runtime_disable(eth->dev); 2006 2007 return ret; 2008 } 2009 2010 static int mtk_hw_deinit(struct mtk_eth *eth) 2011 { 2012 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2013 return 0; 2014 2015 mtk_clk_disable(eth); 2016 2017 pm_runtime_put_sync(eth->dev); 2018 pm_runtime_disable(eth->dev); 2019 2020 return 0; 2021 } 2022 2023 static int __init mtk_init(struct net_device *dev) 2024 { 2025 struct mtk_mac *mac = netdev_priv(dev); 2026 struct mtk_eth *eth = mac->hw; 2027 const char *mac_addr; 2028 2029 mac_addr = of_get_mac_address(mac->of_node); 2030 if (mac_addr) 2031 ether_addr_copy(dev->dev_addr, mac_addr); 2032 2033 /* If the mac address is invalid, use random mac address */ 2034 if (!is_valid_ether_addr(dev->dev_addr)) { 2035 eth_hw_addr_random(dev); 2036 dev_err(eth->dev, "generated random MAC address %pM\n", 2037 dev->dev_addr); 2038 } 2039 2040 return mtk_phy_connect(dev); 2041 } 2042 2043 static void mtk_uninit(struct net_device *dev) 2044 { 2045 struct mtk_mac *mac = netdev_priv(dev); 2046 struct mtk_eth *eth = mac->hw; 2047 2048 phy_disconnect(dev->phydev); 2049 if (of_phy_is_fixed_link(mac->of_node)) 2050 of_phy_deregister_fixed_link(mac->of_node); 2051 mtk_tx_irq_disable(eth, ~0); 2052 mtk_rx_irq_disable(eth, ~0); 2053 } 2054 2055 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2056 { 2057 switch (cmd) { 2058 case SIOCGMIIPHY: 2059 case SIOCGMIIREG: 2060 case SIOCSMIIREG: 2061 return phy_mii_ioctl(dev->phydev, ifr, cmd); 2062 default: 2063 break; 2064 } 2065 2066 return -EOPNOTSUPP; 2067 } 2068 2069 static void mtk_pending_work(struct work_struct *work) 2070 { 2071 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2072 int err, i; 2073 unsigned long restart = 0; 2074 2075 rtnl_lock(); 2076 2077 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2078 2079 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2080 cpu_relax(); 2081 2082 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2083 /* stop all devices to make sure that dma is properly shut down */ 2084 for (i = 0; i < MTK_MAC_COUNT; i++) { 2085 if (!eth->netdev[i]) 2086 continue; 2087 mtk_stop(eth->netdev[i]); 2088 __set_bit(i, &restart); 2089 } 2090 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2091 2092 /* restart underlying hardware such as power, clock, pin mux 2093 * and the connected phy 2094 */ 2095 mtk_hw_deinit(eth); 2096 2097 if (eth->dev->pins) 2098 pinctrl_select_state(eth->dev->pins->p, 2099 eth->dev->pins->default_state); 2100 mtk_hw_init(eth); 2101 2102 for (i = 0; i < MTK_MAC_COUNT; i++) { 2103 if (!eth->mac[i] || 2104 of_phy_is_fixed_link(eth->mac[i]->of_node)) 2105 continue; 2106 err = phy_init_hw(eth->netdev[i]->phydev); 2107 if (err) 2108 dev_err(eth->dev, "%s: PHY init failed.\n", 2109 eth->netdev[i]->name); 2110 } 2111 2112 /* restart DMA and enable IRQs */ 2113 for (i = 0; i < MTK_MAC_COUNT; i++) { 2114 if (!test_bit(i, &restart)) 2115 continue; 2116 err = mtk_open(eth->netdev[i]); 2117 if (err) { 2118 netif_alert(eth, ifup, eth->netdev[i], 2119 "Driver up/down cycle failed, closing device.\n"); 2120 dev_close(eth->netdev[i]); 2121 } 2122 } 2123 2124 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2125 2126 clear_bit_unlock(MTK_RESETTING, ð->state); 2127 2128 rtnl_unlock(); 2129 } 2130 2131 static int mtk_free_dev(struct mtk_eth *eth) 2132 { 2133 int i; 2134 2135 for (i = 0; i < MTK_MAC_COUNT; i++) { 2136 if (!eth->netdev[i]) 2137 continue; 2138 free_netdev(eth->netdev[i]); 2139 } 2140 2141 return 0; 2142 } 2143 2144 static int mtk_unreg_dev(struct mtk_eth *eth) 2145 { 2146 int i; 2147 2148 for (i = 0; i < MTK_MAC_COUNT; i++) { 2149 if (!eth->netdev[i]) 2150 continue; 2151 unregister_netdev(eth->netdev[i]); 2152 } 2153 2154 return 0; 2155 } 2156 2157 static int mtk_cleanup(struct mtk_eth *eth) 2158 { 2159 mtk_unreg_dev(eth); 2160 mtk_free_dev(eth); 2161 cancel_work_sync(ð->pending_work); 2162 2163 return 0; 2164 } 2165 2166 static int mtk_get_link_ksettings(struct net_device *ndev, 2167 struct ethtool_link_ksettings *cmd) 2168 { 2169 struct mtk_mac *mac = netdev_priv(ndev); 2170 2171 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2172 return -EBUSY; 2173 2174 phy_ethtool_ksettings_get(ndev->phydev, cmd); 2175 2176 return 0; 2177 } 2178 2179 static int mtk_set_link_ksettings(struct net_device *ndev, 2180 const struct ethtool_link_ksettings *cmd) 2181 { 2182 struct mtk_mac *mac = netdev_priv(ndev); 2183 2184 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2185 return -EBUSY; 2186 2187 return phy_ethtool_ksettings_set(ndev->phydev, cmd); 2188 } 2189 2190 static void mtk_get_drvinfo(struct net_device *dev, 2191 struct ethtool_drvinfo *info) 2192 { 2193 struct mtk_mac *mac = netdev_priv(dev); 2194 2195 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2196 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2197 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2198 } 2199 2200 static u32 mtk_get_msglevel(struct net_device *dev) 2201 { 2202 struct mtk_mac *mac = netdev_priv(dev); 2203 2204 return mac->hw->msg_enable; 2205 } 2206 2207 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2208 { 2209 struct mtk_mac *mac = netdev_priv(dev); 2210 2211 mac->hw->msg_enable = value; 2212 } 2213 2214 static int mtk_nway_reset(struct net_device *dev) 2215 { 2216 struct mtk_mac *mac = netdev_priv(dev); 2217 2218 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2219 return -EBUSY; 2220 2221 return genphy_restart_aneg(dev->phydev); 2222 } 2223 2224 static u32 mtk_get_link(struct net_device *dev) 2225 { 2226 struct mtk_mac *mac = netdev_priv(dev); 2227 int err; 2228 2229 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2230 return -EBUSY; 2231 2232 err = genphy_update_link(dev->phydev); 2233 if (err) 2234 return ethtool_op_get_link(dev); 2235 2236 return dev->phydev->link; 2237 } 2238 2239 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2240 { 2241 int i; 2242 2243 switch (stringset) { 2244 case ETH_SS_STATS: 2245 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2246 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2247 data += ETH_GSTRING_LEN; 2248 } 2249 break; 2250 } 2251 } 2252 2253 static int mtk_get_sset_count(struct net_device *dev, int sset) 2254 { 2255 switch (sset) { 2256 case ETH_SS_STATS: 2257 return ARRAY_SIZE(mtk_ethtool_stats); 2258 default: 2259 return -EOPNOTSUPP; 2260 } 2261 } 2262 2263 static void mtk_get_ethtool_stats(struct net_device *dev, 2264 struct ethtool_stats *stats, u64 *data) 2265 { 2266 struct mtk_mac *mac = netdev_priv(dev); 2267 struct mtk_hw_stats *hwstats = mac->hw_stats; 2268 u64 *data_src, *data_dst; 2269 unsigned int start; 2270 int i; 2271 2272 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2273 return; 2274 2275 if (netif_running(dev) && netif_device_present(dev)) { 2276 if (spin_trylock_bh(&hwstats->stats_lock)) { 2277 mtk_stats_update_mac(mac); 2278 spin_unlock_bh(&hwstats->stats_lock); 2279 } 2280 } 2281 2282 data_src = (u64 *)hwstats; 2283 2284 do { 2285 data_dst = data; 2286 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2287 2288 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2289 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2290 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2291 } 2292 2293 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2294 u32 *rule_locs) 2295 { 2296 int ret = -EOPNOTSUPP; 2297 2298 switch (cmd->cmd) { 2299 case ETHTOOL_GRXRINGS: 2300 if (dev->features & NETIF_F_LRO) { 2301 cmd->data = MTK_MAX_RX_RING_NUM; 2302 ret = 0; 2303 } 2304 break; 2305 case ETHTOOL_GRXCLSRLCNT: 2306 if (dev->features & NETIF_F_LRO) { 2307 struct mtk_mac *mac = netdev_priv(dev); 2308 2309 cmd->rule_cnt = mac->hwlro_ip_cnt; 2310 ret = 0; 2311 } 2312 break; 2313 case ETHTOOL_GRXCLSRULE: 2314 if (dev->features & NETIF_F_LRO) 2315 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2316 break; 2317 case ETHTOOL_GRXCLSRLALL: 2318 if (dev->features & NETIF_F_LRO) 2319 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2320 rule_locs); 2321 break; 2322 default: 2323 break; 2324 } 2325 2326 return ret; 2327 } 2328 2329 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2330 { 2331 int ret = -EOPNOTSUPP; 2332 2333 switch (cmd->cmd) { 2334 case ETHTOOL_SRXCLSRLINS: 2335 if (dev->features & NETIF_F_LRO) 2336 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2337 break; 2338 case ETHTOOL_SRXCLSRLDEL: 2339 if (dev->features & NETIF_F_LRO) 2340 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2341 break; 2342 default: 2343 break; 2344 } 2345 2346 return ret; 2347 } 2348 2349 static const struct ethtool_ops mtk_ethtool_ops = { 2350 .get_link_ksettings = mtk_get_link_ksettings, 2351 .set_link_ksettings = mtk_set_link_ksettings, 2352 .get_drvinfo = mtk_get_drvinfo, 2353 .get_msglevel = mtk_get_msglevel, 2354 .set_msglevel = mtk_set_msglevel, 2355 .nway_reset = mtk_nway_reset, 2356 .get_link = mtk_get_link, 2357 .get_strings = mtk_get_strings, 2358 .get_sset_count = mtk_get_sset_count, 2359 .get_ethtool_stats = mtk_get_ethtool_stats, 2360 .get_rxnfc = mtk_get_rxnfc, 2361 .set_rxnfc = mtk_set_rxnfc, 2362 }; 2363 2364 static const struct net_device_ops mtk_netdev_ops = { 2365 .ndo_init = mtk_init, 2366 .ndo_uninit = mtk_uninit, 2367 .ndo_open = mtk_open, 2368 .ndo_stop = mtk_stop, 2369 .ndo_start_xmit = mtk_start_xmit, 2370 .ndo_set_mac_address = mtk_set_mac_address, 2371 .ndo_validate_addr = eth_validate_addr, 2372 .ndo_do_ioctl = mtk_do_ioctl, 2373 .ndo_tx_timeout = mtk_tx_timeout, 2374 .ndo_get_stats64 = mtk_get_stats64, 2375 .ndo_fix_features = mtk_fix_features, 2376 .ndo_set_features = mtk_set_features, 2377 #ifdef CONFIG_NET_POLL_CONTROLLER 2378 .ndo_poll_controller = mtk_poll_controller, 2379 #endif 2380 }; 2381 2382 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2383 { 2384 struct mtk_mac *mac; 2385 const __be32 *_id = of_get_property(np, "reg", NULL); 2386 int id, err; 2387 2388 if (!_id) { 2389 dev_err(eth->dev, "missing mac id\n"); 2390 return -EINVAL; 2391 } 2392 2393 id = be32_to_cpup(_id); 2394 if (id >= MTK_MAC_COUNT) { 2395 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2396 return -EINVAL; 2397 } 2398 2399 if (eth->netdev[id]) { 2400 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2401 return -EINVAL; 2402 } 2403 2404 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2405 if (!eth->netdev[id]) { 2406 dev_err(eth->dev, "alloc_etherdev failed\n"); 2407 return -ENOMEM; 2408 } 2409 mac = netdev_priv(eth->netdev[id]); 2410 eth->mac[id] = mac; 2411 mac->id = id; 2412 mac->hw = eth; 2413 mac->of_node = np; 2414 2415 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2416 mac->hwlro_ip_cnt = 0; 2417 2418 mac->hw_stats = devm_kzalloc(eth->dev, 2419 sizeof(*mac->hw_stats), 2420 GFP_KERNEL); 2421 if (!mac->hw_stats) { 2422 dev_err(eth->dev, "failed to allocate counter memory\n"); 2423 err = -ENOMEM; 2424 goto free_netdev; 2425 } 2426 spin_lock_init(&mac->hw_stats->stats_lock); 2427 u64_stats_init(&mac->hw_stats->syncp); 2428 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2429 2430 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2431 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2432 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2433 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2434 2435 eth->netdev[id]->hw_features = MTK_HW_FEATURES; 2436 if (eth->hwlro) 2437 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2438 2439 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 2440 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2441 eth->netdev[id]->features |= MTK_HW_FEATURES; 2442 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2443 2444 eth->netdev[id]->irq = eth->irq[0]; 2445 eth->netdev[id]->dev.of_node = np; 2446 2447 return 0; 2448 2449 free_netdev: 2450 free_netdev(eth->netdev[id]); 2451 return err; 2452 } 2453 2454 static int mtk_probe(struct platform_device *pdev) 2455 { 2456 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2457 struct device_node *mac_np; 2458 struct mtk_eth *eth; 2459 int err; 2460 int i; 2461 2462 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2463 if (!eth) 2464 return -ENOMEM; 2465 2466 eth->soc = of_device_get_match_data(&pdev->dev); 2467 2468 eth->dev = &pdev->dev; 2469 eth->base = devm_ioremap_resource(&pdev->dev, res); 2470 if (IS_ERR(eth->base)) 2471 return PTR_ERR(eth->base); 2472 2473 spin_lock_init(ð->page_lock); 2474 spin_lock_init(ð->tx_irq_lock); 2475 spin_lock_init(ð->rx_irq_lock); 2476 2477 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2478 "mediatek,ethsys"); 2479 if (IS_ERR(eth->ethsys)) { 2480 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2481 return PTR_ERR(eth->ethsys); 2482 } 2483 2484 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 2485 eth->sgmiisys = 2486 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2487 "mediatek,sgmiisys"); 2488 if (IS_ERR(eth->sgmiisys)) { 2489 dev_err(&pdev->dev, "no sgmiisys regmap found\n"); 2490 return PTR_ERR(eth->sgmiisys); 2491 } 2492 } 2493 2494 if (eth->soc->required_pctl) { 2495 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2496 "mediatek,pctl"); 2497 if (IS_ERR(eth->pctl)) { 2498 dev_err(&pdev->dev, "no pctl regmap found\n"); 2499 return PTR_ERR(eth->pctl); 2500 } 2501 } 2502 2503 for (i = 0; i < 3; i++) { 2504 eth->irq[i] = platform_get_irq(pdev, i); 2505 if (eth->irq[i] < 0) { 2506 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2507 return -ENXIO; 2508 } 2509 } 2510 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2511 eth->clks[i] = devm_clk_get(eth->dev, 2512 mtk_clks_source_name[i]); 2513 if (IS_ERR(eth->clks[i])) { 2514 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2515 return -EPROBE_DEFER; 2516 if (eth->soc->required_clks & BIT(i)) { 2517 dev_err(&pdev->dev, "clock %s not found\n", 2518 mtk_clks_source_name[i]); 2519 return -EINVAL; 2520 } 2521 eth->clks[i] = NULL; 2522 } 2523 } 2524 2525 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 2526 INIT_WORK(ð->pending_work, mtk_pending_work); 2527 2528 err = mtk_hw_init(eth); 2529 if (err) 2530 return err; 2531 2532 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 2533 2534 for_each_child_of_node(pdev->dev.of_node, mac_np) { 2535 if (!of_device_is_compatible(mac_np, 2536 "mediatek,eth-mac")) 2537 continue; 2538 2539 if (!of_device_is_available(mac_np)) 2540 continue; 2541 2542 err = mtk_add_mac(eth, mac_np); 2543 if (err) 2544 goto err_deinit_hw; 2545 } 2546 2547 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0, 2548 dev_name(eth->dev), eth); 2549 if (err) 2550 goto err_free_dev; 2551 2552 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0, 2553 dev_name(eth->dev), eth); 2554 if (err) 2555 goto err_free_dev; 2556 2557 err = mtk_mdio_init(eth); 2558 if (err) 2559 goto err_free_dev; 2560 2561 for (i = 0; i < MTK_MAX_DEVS; i++) { 2562 if (!eth->netdev[i]) 2563 continue; 2564 2565 err = register_netdev(eth->netdev[i]); 2566 if (err) { 2567 dev_err(eth->dev, "error bringing up device\n"); 2568 goto err_deinit_mdio; 2569 } else 2570 netif_info(eth, probe, eth->netdev[i], 2571 "mediatek frame engine at 0x%08lx, irq %d\n", 2572 eth->netdev[i]->base_addr, eth->irq[0]); 2573 } 2574 2575 /* we run 2 devices on the same DMA ring so we need a dummy device 2576 * for NAPI to work 2577 */ 2578 init_dummy_netdev(ð->dummy_dev); 2579 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 2580 MTK_NAPI_WEIGHT); 2581 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 2582 MTK_NAPI_WEIGHT); 2583 2584 platform_set_drvdata(pdev, eth); 2585 2586 return 0; 2587 2588 err_deinit_mdio: 2589 mtk_mdio_cleanup(eth); 2590 err_free_dev: 2591 mtk_free_dev(eth); 2592 err_deinit_hw: 2593 mtk_hw_deinit(eth); 2594 2595 return err; 2596 } 2597 2598 static int mtk_remove(struct platform_device *pdev) 2599 { 2600 struct mtk_eth *eth = platform_get_drvdata(pdev); 2601 int i; 2602 2603 /* stop all devices to make sure that dma is properly shut down */ 2604 for (i = 0; i < MTK_MAC_COUNT; i++) { 2605 if (!eth->netdev[i]) 2606 continue; 2607 mtk_stop(eth->netdev[i]); 2608 } 2609 2610 mtk_hw_deinit(eth); 2611 2612 netif_napi_del(ð->tx_napi); 2613 netif_napi_del(ð->rx_napi); 2614 mtk_cleanup(eth); 2615 mtk_mdio_cleanup(eth); 2616 2617 return 0; 2618 } 2619 2620 static const struct mtk_soc_data mt2701_data = { 2621 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO, 2622 .required_clks = MT7623_CLKS_BITMAP, 2623 .required_pctl = true, 2624 }; 2625 2626 static const struct mtk_soc_data mt7622_data = { 2627 .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW | MTK_HWLRO, 2628 .required_clks = MT7622_CLKS_BITMAP, 2629 .required_pctl = false, 2630 }; 2631 2632 static const struct mtk_soc_data mt7623_data = { 2633 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO, 2634 .required_clks = MT7623_CLKS_BITMAP, 2635 .required_pctl = true, 2636 }; 2637 2638 const struct of_device_id of_mtk_match[] = { 2639 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 2640 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 2641 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 2642 {}, 2643 }; 2644 MODULE_DEVICE_TABLE(of, of_mtk_match); 2645 2646 static struct platform_driver mtk_driver = { 2647 .probe = mtk_probe, 2648 .remove = mtk_remove, 2649 .driver = { 2650 .name = "mtk_soc_eth", 2651 .of_match_table = of_mtk_match, 2652 }, 2653 }; 2654 2655 module_platform_driver(mtk_driver); 2656 2657 MODULE_LICENSE("GPL"); 2658 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 2659 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 2660