1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/regmap.h> 14 #include <linux/clk.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/if_vlan.h> 17 #include <linux/reset.h> 18 #include <linux/tcp.h> 19 #include <linux/interrupt.h> 20 #include <linux/pinctrl/devinfo.h> 21 22 #include "mtk_eth_soc.h" 23 24 static int mtk_msg_level = -1; 25 module_param_named(msg_level, mtk_msg_level, int, 0); 26 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 27 28 #define MTK_ETHTOOL_STAT(x) { #x, \ 29 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 30 31 /* strings used by ethtool */ 32 static const struct mtk_ethtool_stats { 33 char str[ETH_GSTRING_LEN]; 34 u32 offset; 35 } mtk_ethtool_stats[] = { 36 MTK_ETHTOOL_STAT(tx_bytes), 37 MTK_ETHTOOL_STAT(tx_packets), 38 MTK_ETHTOOL_STAT(tx_skip), 39 MTK_ETHTOOL_STAT(tx_collisions), 40 MTK_ETHTOOL_STAT(rx_bytes), 41 MTK_ETHTOOL_STAT(rx_packets), 42 MTK_ETHTOOL_STAT(rx_overflow), 43 MTK_ETHTOOL_STAT(rx_fcs_errors), 44 MTK_ETHTOOL_STAT(rx_short_errors), 45 MTK_ETHTOOL_STAT(rx_long_errors), 46 MTK_ETHTOOL_STAT(rx_checksum_errors), 47 MTK_ETHTOOL_STAT(rx_flow_control_packets), 48 }; 49 50 static const char * const mtk_clks_source_name[] = { 51 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 52 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 53 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 54 "sgmii_ck", "eth2pll", 55 }; 56 57 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 58 { 59 __raw_writel(val, eth->base + reg); 60 } 61 62 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 63 { 64 return __raw_readl(eth->base + reg); 65 } 66 67 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 68 { 69 unsigned long t_start = jiffies; 70 71 while (1) { 72 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 73 return 0; 74 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 75 break; 76 usleep_range(10, 20); 77 } 78 79 dev_err(eth->dev, "mdio: MDIO timeout\n"); 80 return -1; 81 } 82 83 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 84 u32 phy_register, u32 write_data) 85 { 86 if (mtk_mdio_busy_wait(eth)) 87 return -1; 88 89 write_data &= 0xffff; 90 91 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 92 (phy_register << PHY_IAC_REG_SHIFT) | 93 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 94 MTK_PHY_IAC); 95 96 if (mtk_mdio_busy_wait(eth)) 97 return -1; 98 99 return 0; 100 } 101 102 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 103 { 104 u32 d; 105 106 if (mtk_mdio_busy_wait(eth)) 107 return 0xffff; 108 109 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 110 (phy_reg << PHY_IAC_REG_SHIFT) | 111 (phy_addr << PHY_IAC_ADDR_SHIFT), 112 MTK_PHY_IAC); 113 114 if (mtk_mdio_busy_wait(eth)) 115 return 0xffff; 116 117 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 118 119 return d; 120 } 121 122 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 123 int phy_reg, u16 val) 124 { 125 struct mtk_eth *eth = bus->priv; 126 127 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 128 } 129 130 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 131 { 132 struct mtk_eth *eth = bus->priv; 133 134 return _mtk_mdio_read(eth, phy_addr, phy_reg); 135 } 136 137 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 138 phy_interface_t interface) 139 { 140 u32 val; 141 142 /* Check DDR memory type. 143 * Currently TRGMII mode with DDR2 memory is not supported. 144 */ 145 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 146 if (interface == PHY_INTERFACE_MODE_TRGMII && 147 val & SYSCFG_DRAM_TYPE_DDR2) { 148 dev_err(eth->dev, 149 "TRGMII mode with DDR2 memory is not supported!\n"); 150 return -EOPNOTSUPP; 151 } 152 153 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 154 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 155 156 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 157 ETHSYS_TRGMII_MT7621_MASK, val); 158 159 return 0; 160 } 161 162 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 163 { 164 u32 val; 165 int ret; 166 167 val = (speed == SPEED_1000) ? 168 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 169 mtk_w32(eth, val, INTF_MODE); 170 171 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 172 ETHSYS_TRGMII_CLK_SEL362_5, 173 ETHSYS_TRGMII_CLK_SEL362_5); 174 175 val = (speed == SPEED_1000) ? 250000000 : 500000000; 176 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 177 if (ret) 178 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 179 180 val = (speed == SPEED_1000) ? 181 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 182 mtk_w32(eth, val, TRGMII_RCK_CTRL); 183 184 val = (speed == SPEED_1000) ? 185 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 186 mtk_w32(eth, val, TRGMII_TCK_CTRL); 187 } 188 189 static void mtk_phy_link_adjust(struct net_device *dev) 190 { 191 struct mtk_mac *mac = netdev_priv(dev); 192 u16 lcl_adv = 0, rmt_adv = 0; 193 u8 flowctrl; 194 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 195 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 196 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 197 MAC_MCR_BACKPR_EN; 198 199 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 200 return; 201 202 switch (dev->phydev->speed) { 203 case SPEED_1000: 204 mcr |= MAC_MCR_SPEED_1000; 205 break; 206 case SPEED_100: 207 mcr |= MAC_MCR_SPEED_100; 208 break; 209 } 210 211 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && !mac->id) { 212 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { 213 if (mt7621_gmac0_rgmii_adjust(mac->hw, 214 dev->phydev->interface)) 215 return; 216 } else { 217 if (!mac->trgmii) 218 mtk_gmac0_rgmii_adjust(mac->hw, 219 dev->phydev->speed); 220 } 221 } 222 223 if (dev->phydev->link) 224 mcr |= MAC_MCR_FORCE_LINK; 225 226 if (dev->phydev->duplex) { 227 mcr |= MAC_MCR_FORCE_DPX; 228 229 if (dev->phydev->pause) 230 rmt_adv = LPA_PAUSE_CAP; 231 if (dev->phydev->asym_pause) 232 rmt_adv |= LPA_PAUSE_ASYM; 233 234 lcl_adv = linkmode_adv_to_lcl_adv_t(dev->phydev->advertising); 235 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 236 237 if (flowctrl & FLOW_CTRL_TX) 238 mcr |= MAC_MCR_FORCE_TX_FC; 239 if (flowctrl & FLOW_CTRL_RX) 240 mcr |= MAC_MCR_FORCE_RX_FC; 241 242 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 243 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 244 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 245 } 246 247 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 248 249 if (!of_phy_is_fixed_link(mac->of_node)) 250 phy_print_status(dev->phydev); 251 } 252 253 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 254 struct device_node *phy_node) 255 { 256 struct phy_device *phydev; 257 int phy_mode; 258 259 phy_mode = of_get_phy_mode(phy_node); 260 if (phy_mode < 0) { 261 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 262 return -EINVAL; 263 } 264 265 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 266 mtk_phy_link_adjust, 0, phy_mode); 267 if (!phydev) { 268 dev_err(eth->dev, "could not connect to PHY\n"); 269 return -ENODEV; 270 } 271 272 dev_info(eth->dev, 273 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 274 mac->id, phydev_name(phydev), phydev->phy_id, 275 phydev->drv->name); 276 277 return 0; 278 } 279 280 static int mtk_phy_connect(struct net_device *dev) 281 { 282 struct mtk_mac *mac = netdev_priv(dev); 283 struct mtk_eth *eth; 284 struct device_node *np; 285 u32 val; 286 int err; 287 288 eth = mac->hw; 289 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 290 if (!np && of_phy_is_fixed_link(mac->of_node)) 291 if (!of_phy_register_fixed_link(mac->of_node)) 292 np = of_node_get(mac->of_node); 293 if (!np) 294 return -ENODEV; 295 296 err = mtk_setup_hw_path(eth, mac->id, of_get_phy_mode(np)); 297 if (err) 298 goto err_phy; 299 300 mac->ge_mode = 0; 301 switch (of_get_phy_mode(np)) { 302 case PHY_INTERFACE_MODE_TRGMII: 303 mac->trgmii = true; 304 case PHY_INTERFACE_MODE_RGMII_TXID: 305 case PHY_INTERFACE_MODE_RGMII_RXID: 306 case PHY_INTERFACE_MODE_RGMII_ID: 307 case PHY_INTERFACE_MODE_RGMII: 308 case PHY_INTERFACE_MODE_SGMII: 309 break; 310 case PHY_INTERFACE_MODE_MII: 311 case PHY_INTERFACE_MODE_GMII: 312 mac->ge_mode = 1; 313 break; 314 case PHY_INTERFACE_MODE_REVMII: 315 mac->ge_mode = 2; 316 break; 317 case PHY_INTERFACE_MODE_RMII: 318 if (!mac->id) 319 goto err_phy; 320 mac->ge_mode = 3; 321 break; 322 default: 323 goto err_phy; 324 } 325 326 /* put the gmac into the right mode */ 327 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 328 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 329 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id); 330 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 331 332 /* couple phydev to net_device */ 333 if (mtk_phy_connect_node(eth, mac, np)) 334 goto err_phy; 335 336 of_node_put(np); 337 338 return 0; 339 340 err_phy: 341 if (of_phy_is_fixed_link(mac->of_node)) 342 of_phy_deregister_fixed_link(mac->of_node); 343 of_node_put(np); 344 dev_err(eth->dev, "%s: invalid phy\n", __func__); 345 return -EINVAL; 346 } 347 348 static int mtk_mdio_init(struct mtk_eth *eth) 349 { 350 struct device_node *mii_np; 351 int ret; 352 353 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 354 if (!mii_np) { 355 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 356 return -ENODEV; 357 } 358 359 if (!of_device_is_available(mii_np)) { 360 ret = -ENODEV; 361 goto err_put_node; 362 } 363 364 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 365 if (!eth->mii_bus) { 366 ret = -ENOMEM; 367 goto err_put_node; 368 } 369 370 eth->mii_bus->name = "mdio"; 371 eth->mii_bus->read = mtk_mdio_read; 372 eth->mii_bus->write = mtk_mdio_write; 373 eth->mii_bus->priv = eth; 374 eth->mii_bus->parent = eth->dev; 375 376 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 377 ret = of_mdiobus_register(eth->mii_bus, mii_np); 378 379 err_put_node: 380 of_node_put(mii_np); 381 return ret; 382 } 383 384 static void mtk_mdio_cleanup(struct mtk_eth *eth) 385 { 386 if (!eth->mii_bus) 387 return; 388 389 mdiobus_unregister(eth->mii_bus); 390 } 391 392 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 393 { 394 unsigned long flags; 395 u32 val; 396 397 spin_lock_irqsave(ð->tx_irq_lock, flags); 398 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 399 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); 400 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 401 } 402 403 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 404 { 405 unsigned long flags; 406 u32 val; 407 408 spin_lock_irqsave(ð->tx_irq_lock, flags); 409 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 410 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); 411 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 412 } 413 414 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 415 { 416 unsigned long flags; 417 u32 val; 418 419 spin_lock_irqsave(ð->rx_irq_lock, flags); 420 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 421 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 422 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 423 } 424 425 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 426 { 427 unsigned long flags; 428 u32 val; 429 430 spin_lock_irqsave(ð->rx_irq_lock, flags); 431 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 432 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 433 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 434 } 435 436 static int mtk_set_mac_address(struct net_device *dev, void *p) 437 { 438 int ret = eth_mac_addr(dev, p); 439 struct mtk_mac *mac = netdev_priv(dev); 440 const char *macaddr = dev->dev_addr; 441 442 if (ret) 443 return ret; 444 445 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 446 return -EBUSY; 447 448 spin_lock_bh(&mac->hw->page_lock); 449 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 450 MTK_GDMA_MAC_ADRH(mac->id)); 451 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 452 (macaddr[4] << 8) | macaddr[5], 453 MTK_GDMA_MAC_ADRL(mac->id)); 454 spin_unlock_bh(&mac->hw->page_lock); 455 456 return 0; 457 } 458 459 void mtk_stats_update_mac(struct mtk_mac *mac) 460 { 461 struct mtk_hw_stats *hw_stats = mac->hw_stats; 462 unsigned int base = MTK_GDM1_TX_GBCNT; 463 u64 stats; 464 465 base += hw_stats->reg_offset; 466 467 u64_stats_update_begin(&hw_stats->syncp); 468 469 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 470 stats = mtk_r32(mac->hw, base + 0x04); 471 if (stats) 472 hw_stats->rx_bytes += (stats << 32); 473 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 474 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 475 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 476 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 477 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 478 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 479 hw_stats->rx_flow_control_packets += 480 mtk_r32(mac->hw, base + 0x24); 481 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 482 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 483 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 484 stats = mtk_r32(mac->hw, base + 0x34); 485 if (stats) 486 hw_stats->tx_bytes += (stats << 32); 487 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 488 u64_stats_update_end(&hw_stats->syncp); 489 } 490 491 static void mtk_stats_update(struct mtk_eth *eth) 492 { 493 int i; 494 495 for (i = 0; i < MTK_MAC_COUNT; i++) { 496 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 497 continue; 498 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 499 mtk_stats_update_mac(eth->mac[i]); 500 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 501 } 502 } 503 } 504 505 static void mtk_get_stats64(struct net_device *dev, 506 struct rtnl_link_stats64 *storage) 507 { 508 struct mtk_mac *mac = netdev_priv(dev); 509 struct mtk_hw_stats *hw_stats = mac->hw_stats; 510 unsigned int start; 511 512 if (netif_running(dev) && netif_device_present(dev)) { 513 if (spin_trylock_bh(&hw_stats->stats_lock)) { 514 mtk_stats_update_mac(mac); 515 spin_unlock_bh(&hw_stats->stats_lock); 516 } 517 } 518 519 do { 520 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 521 storage->rx_packets = hw_stats->rx_packets; 522 storage->tx_packets = hw_stats->tx_packets; 523 storage->rx_bytes = hw_stats->rx_bytes; 524 storage->tx_bytes = hw_stats->tx_bytes; 525 storage->collisions = hw_stats->tx_collisions; 526 storage->rx_length_errors = hw_stats->rx_short_errors + 527 hw_stats->rx_long_errors; 528 storage->rx_over_errors = hw_stats->rx_overflow; 529 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 530 storage->rx_errors = hw_stats->rx_checksum_errors; 531 storage->tx_aborted_errors = hw_stats->tx_skip; 532 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 533 534 storage->tx_errors = dev->stats.tx_errors; 535 storage->rx_dropped = dev->stats.rx_dropped; 536 storage->tx_dropped = dev->stats.tx_dropped; 537 } 538 539 static inline int mtk_max_frag_size(int mtu) 540 { 541 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 542 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 543 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 544 545 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 546 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 547 } 548 549 static inline int mtk_max_buf_size(int frag_size) 550 { 551 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 552 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 553 554 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 555 556 return buf_size; 557 } 558 559 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 560 struct mtk_rx_dma *dma_rxd) 561 { 562 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 563 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 564 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 565 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 566 } 567 568 /* the qdma core needs scratch memory to be setup */ 569 static int mtk_init_fq_dma(struct mtk_eth *eth) 570 { 571 dma_addr_t phy_ring_tail; 572 int cnt = MTK_DMA_SIZE; 573 dma_addr_t dma_addr; 574 int i; 575 576 eth->scratch_ring = dma_alloc_coherent(eth->dev, 577 cnt * sizeof(struct mtk_tx_dma), 578 ð->phy_scratch_ring, 579 GFP_ATOMIC); 580 if (unlikely(!eth->scratch_ring)) 581 return -ENOMEM; 582 583 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 584 GFP_KERNEL); 585 if (unlikely(!eth->scratch_head)) 586 return -ENOMEM; 587 588 dma_addr = dma_map_single(eth->dev, 589 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 590 DMA_FROM_DEVICE); 591 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 592 return -ENOMEM; 593 594 phy_ring_tail = eth->phy_scratch_ring + 595 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 596 597 for (i = 0; i < cnt; i++) { 598 eth->scratch_ring[i].txd1 = 599 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 600 if (i < cnt - 1) 601 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 602 ((i + 1) * sizeof(struct mtk_tx_dma))); 603 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 604 } 605 606 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 607 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 608 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 609 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 610 611 return 0; 612 } 613 614 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 615 { 616 void *ret = ring->dma; 617 618 return ret + (desc - ring->phys); 619 } 620 621 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 622 struct mtk_tx_dma *txd) 623 { 624 int idx = txd - ring->dma; 625 626 return &ring->buf[idx]; 627 } 628 629 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 630 { 631 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 632 dma_unmap_single(eth->dev, 633 dma_unmap_addr(tx_buf, dma_addr0), 634 dma_unmap_len(tx_buf, dma_len0), 635 DMA_TO_DEVICE); 636 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 637 dma_unmap_page(eth->dev, 638 dma_unmap_addr(tx_buf, dma_addr0), 639 dma_unmap_len(tx_buf, dma_len0), 640 DMA_TO_DEVICE); 641 } 642 tx_buf->flags = 0; 643 if (tx_buf->skb && 644 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 645 dev_kfree_skb_any(tx_buf->skb); 646 tx_buf->skb = NULL; 647 } 648 649 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 650 int tx_num, struct mtk_tx_ring *ring, bool gso) 651 { 652 struct mtk_mac *mac = netdev_priv(dev); 653 struct mtk_eth *eth = mac->hw; 654 struct mtk_tx_dma *itxd, *txd; 655 struct mtk_tx_buf *itx_buf, *tx_buf; 656 dma_addr_t mapped_addr; 657 unsigned int nr_frags; 658 int i, n_desc = 1; 659 u32 txd4 = 0, fport; 660 661 itxd = ring->next_free; 662 if (itxd == ring->last_free) 663 return -ENOMEM; 664 665 /* set the forward port */ 666 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 667 txd4 |= fport; 668 669 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 670 memset(itx_buf, 0, sizeof(*itx_buf)); 671 672 if (gso) 673 txd4 |= TX_DMA_TSO; 674 675 /* TX Checksum offload */ 676 if (skb->ip_summed == CHECKSUM_PARTIAL) 677 txd4 |= TX_DMA_CHKSUM; 678 679 /* VLAN header offload */ 680 if (skb_vlan_tag_present(skb)) 681 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 682 683 mapped_addr = dma_map_single(eth->dev, skb->data, 684 skb_headlen(skb), DMA_TO_DEVICE); 685 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 686 return -ENOMEM; 687 688 WRITE_ONCE(itxd->txd1, mapped_addr); 689 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 690 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 691 MTK_TX_FLAGS_FPORT1; 692 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr); 693 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb)); 694 695 /* TX SG offload */ 696 txd = itxd; 697 nr_frags = skb_shinfo(skb)->nr_frags; 698 for (i = 0; i < nr_frags; i++) { 699 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 700 unsigned int offset = 0; 701 int frag_size = skb_frag_size(frag); 702 703 while (frag_size) { 704 bool last_frag = false; 705 unsigned int frag_map_size; 706 707 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 708 if (txd == ring->last_free) 709 goto err_dma; 710 711 n_desc++; 712 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 713 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 714 frag_map_size, 715 DMA_TO_DEVICE); 716 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 717 goto err_dma; 718 719 if (i == nr_frags - 1 && 720 (frag_size - frag_map_size) == 0) 721 last_frag = true; 722 723 WRITE_ONCE(txd->txd1, mapped_addr); 724 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 725 TX_DMA_PLEN0(frag_map_size) | 726 last_frag * TX_DMA_LS0)); 727 WRITE_ONCE(txd->txd4, fport); 728 729 tx_buf = mtk_desc_to_tx_buf(ring, txd); 730 memset(tx_buf, 0, sizeof(*tx_buf)); 731 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 732 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 733 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 734 MTK_TX_FLAGS_FPORT1; 735 736 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 737 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 738 frag_size -= frag_map_size; 739 offset += frag_map_size; 740 } 741 } 742 743 /* store skb to cleanup */ 744 itx_buf->skb = skb; 745 746 WRITE_ONCE(itxd->txd4, txd4); 747 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 748 (!nr_frags * TX_DMA_LS0))); 749 750 netdev_sent_queue(dev, skb->len); 751 skb_tx_timestamp(skb); 752 753 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 754 atomic_sub(n_desc, &ring->free_count); 755 756 /* make sure that all changes to the dma ring are flushed before we 757 * continue 758 */ 759 wmb(); 760 761 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 762 !netdev_xmit_more()) 763 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 764 765 return 0; 766 767 err_dma: 768 do { 769 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 770 771 /* unmap dma */ 772 mtk_tx_unmap(eth, tx_buf); 773 774 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 775 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 776 } while (itxd != txd); 777 778 return -ENOMEM; 779 } 780 781 static inline int mtk_cal_txd_req(struct sk_buff *skb) 782 { 783 int i, nfrags; 784 skb_frag_t *frag; 785 786 nfrags = 1; 787 if (skb_is_gso(skb)) { 788 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 789 frag = &skb_shinfo(skb)->frags[i]; 790 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 791 MTK_TX_DMA_BUF_LEN); 792 } 793 } else { 794 nfrags += skb_shinfo(skb)->nr_frags; 795 } 796 797 return nfrags; 798 } 799 800 static int mtk_queue_stopped(struct mtk_eth *eth) 801 { 802 int i; 803 804 for (i = 0; i < MTK_MAC_COUNT; i++) { 805 if (!eth->netdev[i]) 806 continue; 807 if (netif_queue_stopped(eth->netdev[i])) 808 return 1; 809 } 810 811 return 0; 812 } 813 814 static void mtk_wake_queue(struct mtk_eth *eth) 815 { 816 int i; 817 818 for (i = 0; i < MTK_MAC_COUNT; i++) { 819 if (!eth->netdev[i]) 820 continue; 821 netif_wake_queue(eth->netdev[i]); 822 } 823 } 824 825 static void mtk_stop_queue(struct mtk_eth *eth) 826 { 827 int i; 828 829 for (i = 0; i < MTK_MAC_COUNT; i++) { 830 if (!eth->netdev[i]) 831 continue; 832 netif_stop_queue(eth->netdev[i]); 833 } 834 } 835 836 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 837 { 838 struct mtk_mac *mac = netdev_priv(dev); 839 struct mtk_eth *eth = mac->hw; 840 struct mtk_tx_ring *ring = ð->tx_ring; 841 struct net_device_stats *stats = &dev->stats; 842 bool gso = false; 843 int tx_num; 844 845 /* normally we can rely on the stack not calling this more than once, 846 * however we have 2 queues running on the same ring so we need to lock 847 * the ring access 848 */ 849 spin_lock(ð->page_lock); 850 851 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 852 goto drop; 853 854 tx_num = mtk_cal_txd_req(skb); 855 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 856 mtk_stop_queue(eth); 857 netif_err(eth, tx_queued, dev, 858 "Tx Ring full when queue awake!\n"); 859 spin_unlock(ð->page_lock); 860 return NETDEV_TX_BUSY; 861 } 862 863 /* TSO: fill MSS info in tcp checksum field */ 864 if (skb_is_gso(skb)) { 865 if (skb_cow_head(skb, 0)) { 866 netif_warn(eth, tx_err, dev, 867 "GSO expand head fail.\n"); 868 goto drop; 869 } 870 871 if (skb_shinfo(skb)->gso_type & 872 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 873 gso = true; 874 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 875 } 876 } 877 878 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 879 goto drop; 880 881 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 882 mtk_stop_queue(eth); 883 884 spin_unlock(ð->page_lock); 885 886 return NETDEV_TX_OK; 887 888 drop: 889 spin_unlock(ð->page_lock); 890 stats->tx_dropped++; 891 dev_kfree_skb_any(skb); 892 return NETDEV_TX_OK; 893 } 894 895 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 896 { 897 int i; 898 struct mtk_rx_ring *ring; 899 int idx; 900 901 if (!eth->hwlro) 902 return ð->rx_ring[0]; 903 904 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 905 ring = ð->rx_ring[i]; 906 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 907 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 908 ring->calc_idx_update = true; 909 return ring; 910 } 911 } 912 913 return NULL; 914 } 915 916 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 917 { 918 struct mtk_rx_ring *ring; 919 int i; 920 921 if (!eth->hwlro) { 922 ring = ð->rx_ring[0]; 923 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 924 } else { 925 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 926 ring = ð->rx_ring[i]; 927 if (ring->calc_idx_update) { 928 ring->calc_idx_update = false; 929 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 930 } 931 } 932 } 933 } 934 935 static int mtk_poll_rx(struct napi_struct *napi, int budget, 936 struct mtk_eth *eth) 937 { 938 struct mtk_rx_ring *ring; 939 int idx; 940 struct sk_buff *skb; 941 u8 *data, *new_data; 942 struct mtk_rx_dma *rxd, trxd; 943 int done = 0; 944 945 while (done < budget) { 946 struct net_device *netdev; 947 unsigned int pktlen; 948 dma_addr_t dma_addr; 949 int mac = 0; 950 951 ring = mtk_get_rx_ring(eth); 952 if (unlikely(!ring)) 953 goto rx_done; 954 955 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 956 rxd = &ring->dma[idx]; 957 data = ring->data[idx]; 958 959 mtk_rx_get_desc(&trxd, rxd); 960 if (!(trxd.rxd2 & RX_DMA_DONE)) 961 break; 962 963 /* find out which mac the packet come from. values start at 1 */ 964 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 965 RX_DMA_FPORT_MASK; 966 mac--; 967 968 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 969 !eth->netdev[mac])) 970 goto release_desc; 971 972 netdev = eth->netdev[mac]; 973 974 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 975 goto release_desc; 976 977 /* alloc new buffer */ 978 new_data = napi_alloc_frag(ring->frag_size); 979 if (unlikely(!new_data)) { 980 netdev->stats.rx_dropped++; 981 goto release_desc; 982 } 983 dma_addr = dma_map_single(eth->dev, 984 new_data + NET_SKB_PAD, 985 ring->buf_size, 986 DMA_FROM_DEVICE); 987 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 988 skb_free_frag(new_data); 989 netdev->stats.rx_dropped++; 990 goto release_desc; 991 } 992 993 /* receive data */ 994 skb = build_skb(data, ring->frag_size); 995 if (unlikely(!skb)) { 996 skb_free_frag(new_data); 997 netdev->stats.rx_dropped++; 998 goto release_desc; 999 } 1000 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1001 1002 dma_unmap_single(eth->dev, trxd.rxd1, 1003 ring->buf_size, DMA_FROM_DEVICE); 1004 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1005 skb->dev = netdev; 1006 skb_put(skb, pktlen); 1007 if (trxd.rxd4 & RX_DMA_L4_VALID) 1008 skb->ip_summed = CHECKSUM_UNNECESSARY; 1009 else 1010 skb_checksum_none_assert(skb); 1011 skb->protocol = eth_type_trans(skb, netdev); 1012 1013 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1014 RX_DMA_VID(trxd.rxd3)) 1015 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1016 RX_DMA_VID(trxd.rxd3)); 1017 skb_record_rx_queue(skb, 0); 1018 napi_gro_receive(napi, skb); 1019 1020 ring->data[idx] = new_data; 1021 rxd->rxd1 = (unsigned int)dma_addr; 1022 1023 release_desc: 1024 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1025 1026 ring->calc_idx = idx; 1027 1028 done++; 1029 } 1030 1031 rx_done: 1032 if (done) { 1033 /* make sure that all changes to the dma ring are flushed before 1034 * we continue 1035 */ 1036 wmb(); 1037 mtk_update_rx_cpu_idx(eth); 1038 } 1039 1040 return done; 1041 } 1042 1043 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1044 { 1045 struct mtk_tx_ring *ring = ð->tx_ring; 1046 struct mtk_tx_dma *desc; 1047 struct sk_buff *skb; 1048 struct mtk_tx_buf *tx_buf; 1049 unsigned int done[MTK_MAX_DEVS]; 1050 unsigned int bytes[MTK_MAX_DEVS]; 1051 u32 cpu, dma; 1052 int total = 0, i; 1053 1054 memset(done, 0, sizeof(done)); 1055 memset(bytes, 0, sizeof(bytes)); 1056 1057 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1058 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1059 1060 desc = mtk_qdma_phys_to_virt(ring, cpu); 1061 1062 while ((cpu != dma) && budget) { 1063 u32 next_cpu = desc->txd2; 1064 int mac = 0; 1065 1066 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1067 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1068 break; 1069 1070 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1071 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1072 mac = 1; 1073 1074 skb = tx_buf->skb; 1075 if (!skb) 1076 break; 1077 1078 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1079 bytes[mac] += skb->len; 1080 done[mac]++; 1081 budget--; 1082 } 1083 mtk_tx_unmap(eth, tx_buf); 1084 1085 ring->last_free = desc; 1086 atomic_inc(&ring->free_count); 1087 1088 cpu = next_cpu; 1089 } 1090 1091 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1092 1093 for (i = 0; i < MTK_MAC_COUNT; i++) { 1094 if (!eth->netdev[i] || !done[i]) 1095 continue; 1096 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1097 total += done[i]; 1098 } 1099 1100 if (mtk_queue_stopped(eth) && 1101 (atomic_read(&ring->free_count) > ring->thresh)) 1102 mtk_wake_queue(eth); 1103 1104 return total; 1105 } 1106 1107 static void mtk_handle_status_irq(struct mtk_eth *eth) 1108 { 1109 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1110 1111 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1112 mtk_stats_update(eth); 1113 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1114 MTK_INT_STATUS2); 1115 } 1116 } 1117 1118 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1119 { 1120 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1121 u32 status, mask; 1122 int tx_done = 0; 1123 1124 mtk_handle_status_irq(eth); 1125 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 1126 tx_done = mtk_poll_tx(eth, budget); 1127 1128 if (unlikely(netif_msg_intr(eth))) { 1129 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1130 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 1131 dev_info(eth->dev, 1132 "done tx %d, intr 0x%08x/0x%x\n", 1133 tx_done, status, mask); 1134 } 1135 1136 if (tx_done == budget) 1137 return budget; 1138 1139 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1140 if (status & MTK_TX_DONE_INT) 1141 return budget; 1142 1143 napi_complete(napi); 1144 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1145 1146 return tx_done; 1147 } 1148 1149 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1150 { 1151 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1152 u32 status, mask; 1153 int rx_done = 0; 1154 int remain_budget = budget; 1155 1156 mtk_handle_status_irq(eth); 1157 1158 poll_again: 1159 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1160 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1161 1162 if (unlikely(netif_msg_intr(eth))) { 1163 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1164 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1165 dev_info(eth->dev, 1166 "done rx %d, intr 0x%08x/0x%x\n", 1167 rx_done, status, mask); 1168 } 1169 if (rx_done == remain_budget) 1170 return budget; 1171 1172 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1173 if (status & MTK_RX_DONE_INT) { 1174 remain_budget -= rx_done; 1175 goto poll_again; 1176 } 1177 napi_complete(napi); 1178 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1179 1180 return rx_done + budget - remain_budget; 1181 } 1182 1183 static int mtk_tx_alloc(struct mtk_eth *eth) 1184 { 1185 struct mtk_tx_ring *ring = ð->tx_ring; 1186 int i, sz = sizeof(*ring->dma); 1187 1188 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1189 GFP_KERNEL); 1190 if (!ring->buf) 1191 goto no_tx_mem; 1192 1193 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1194 &ring->phys, GFP_ATOMIC); 1195 if (!ring->dma) 1196 goto no_tx_mem; 1197 1198 for (i = 0; i < MTK_DMA_SIZE; i++) { 1199 int next = (i + 1) % MTK_DMA_SIZE; 1200 u32 next_ptr = ring->phys + next * sz; 1201 1202 ring->dma[i].txd2 = next_ptr; 1203 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1204 } 1205 1206 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1207 ring->next_free = &ring->dma[0]; 1208 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1209 ring->thresh = MAX_SKB_FRAGS; 1210 1211 /* make sure that all changes to the dma ring are flushed before we 1212 * continue 1213 */ 1214 wmb(); 1215 1216 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1217 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1218 mtk_w32(eth, 1219 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1220 MTK_QTX_CRX_PTR); 1221 mtk_w32(eth, 1222 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1223 MTK_QTX_DRX_PTR); 1224 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1225 1226 return 0; 1227 1228 no_tx_mem: 1229 return -ENOMEM; 1230 } 1231 1232 static void mtk_tx_clean(struct mtk_eth *eth) 1233 { 1234 struct mtk_tx_ring *ring = ð->tx_ring; 1235 int i; 1236 1237 if (ring->buf) { 1238 for (i = 0; i < MTK_DMA_SIZE; i++) 1239 mtk_tx_unmap(eth, &ring->buf[i]); 1240 kfree(ring->buf); 1241 ring->buf = NULL; 1242 } 1243 1244 if (ring->dma) { 1245 dma_free_coherent(eth->dev, 1246 MTK_DMA_SIZE * sizeof(*ring->dma), 1247 ring->dma, 1248 ring->phys); 1249 ring->dma = NULL; 1250 } 1251 } 1252 1253 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1254 { 1255 struct mtk_rx_ring *ring; 1256 int rx_data_len, rx_dma_size; 1257 int i; 1258 u32 offset = 0; 1259 1260 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1261 if (ring_no) 1262 return -EINVAL; 1263 ring = ð->rx_ring_qdma; 1264 offset = 0x1000; 1265 } else { 1266 ring = ð->rx_ring[ring_no]; 1267 } 1268 1269 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1270 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1271 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1272 } else { 1273 rx_data_len = ETH_DATA_LEN; 1274 rx_dma_size = MTK_DMA_SIZE; 1275 } 1276 1277 ring->frag_size = mtk_max_frag_size(rx_data_len); 1278 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1279 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1280 GFP_KERNEL); 1281 if (!ring->data) 1282 return -ENOMEM; 1283 1284 for (i = 0; i < rx_dma_size; i++) { 1285 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1286 if (!ring->data[i]) 1287 return -ENOMEM; 1288 } 1289 1290 ring->dma = dma_alloc_coherent(eth->dev, 1291 rx_dma_size * sizeof(*ring->dma), 1292 &ring->phys, GFP_ATOMIC); 1293 if (!ring->dma) 1294 return -ENOMEM; 1295 1296 for (i = 0; i < rx_dma_size; i++) { 1297 dma_addr_t dma_addr = dma_map_single(eth->dev, 1298 ring->data[i] + NET_SKB_PAD, 1299 ring->buf_size, 1300 DMA_FROM_DEVICE); 1301 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1302 return -ENOMEM; 1303 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1304 1305 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1306 } 1307 ring->dma_size = rx_dma_size; 1308 ring->calc_idx_update = false; 1309 ring->calc_idx = rx_dma_size - 1; 1310 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1311 /* make sure that all changes to the dma ring are flushed before we 1312 * continue 1313 */ 1314 wmb(); 1315 1316 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1317 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1318 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1319 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1320 1321 return 0; 1322 } 1323 1324 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1325 { 1326 int i; 1327 1328 if (ring->data && ring->dma) { 1329 for (i = 0; i < ring->dma_size; i++) { 1330 if (!ring->data[i]) 1331 continue; 1332 if (!ring->dma[i].rxd1) 1333 continue; 1334 dma_unmap_single(eth->dev, 1335 ring->dma[i].rxd1, 1336 ring->buf_size, 1337 DMA_FROM_DEVICE); 1338 skb_free_frag(ring->data[i]); 1339 } 1340 kfree(ring->data); 1341 ring->data = NULL; 1342 } 1343 1344 if (ring->dma) { 1345 dma_free_coherent(eth->dev, 1346 ring->dma_size * sizeof(*ring->dma), 1347 ring->dma, 1348 ring->phys); 1349 ring->dma = NULL; 1350 } 1351 } 1352 1353 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1354 { 1355 int i; 1356 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1357 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1358 1359 /* set LRO rings to auto-learn modes */ 1360 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1361 1362 /* validate LRO ring */ 1363 ring_ctrl_dw2 |= MTK_RING_VLD; 1364 1365 /* set AGE timer (unit: 20us) */ 1366 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1367 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1368 1369 /* set max AGG timer (unit: 20us) */ 1370 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1371 1372 /* set max LRO AGG count */ 1373 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1374 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1375 1376 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1377 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1378 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1379 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1380 } 1381 1382 /* IPv4 checksum update enable */ 1383 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1384 1385 /* switch priority comparison to packet count mode */ 1386 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1387 1388 /* bandwidth threshold setting */ 1389 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1390 1391 /* auto-learn score delta setting */ 1392 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1393 1394 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1395 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1396 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1397 1398 /* set HW LRO mode & the max aggregation count for rx packets */ 1399 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1400 1401 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1402 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1403 1404 /* enable HW LRO */ 1405 lro_ctrl_dw0 |= MTK_LRO_EN; 1406 1407 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1408 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1409 1410 return 0; 1411 } 1412 1413 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1414 { 1415 int i; 1416 u32 val; 1417 1418 /* relinquish lro rings, flush aggregated packets */ 1419 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1420 1421 /* wait for relinquishments done */ 1422 for (i = 0; i < 10; i++) { 1423 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1424 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1425 msleep(20); 1426 continue; 1427 } 1428 break; 1429 } 1430 1431 /* invalidate lro rings */ 1432 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1433 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1434 1435 /* disable HW LRO */ 1436 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1437 } 1438 1439 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1440 { 1441 u32 reg_val; 1442 1443 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1444 1445 /* invalidate the IP setting */ 1446 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1447 1448 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1449 1450 /* validate the IP setting */ 1451 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1452 } 1453 1454 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1455 { 1456 u32 reg_val; 1457 1458 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1459 1460 /* invalidate the IP setting */ 1461 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1462 1463 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1464 } 1465 1466 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1467 { 1468 int cnt = 0; 1469 int i; 1470 1471 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1472 if (mac->hwlro_ip[i]) 1473 cnt++; 1474 } 1475 1476 return cnt; 1477 } 1478 1479 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1480 struct ethtool_rxnfc *cmd) 1481 { 1482 struct ethtool_rx_flow_spec *fsp = 1483 (struct ethtool_rx_flow_spec *)&cmd->fs; 1484 struct mtk_mac *mac = netdev_priv(dev); 1485 struct mtk_eth *eth = mac->hw; 1486 int hwlro_idx; 1487 1488 if ((fsp->flow_type != TCP_V4_FLOW) || 1489 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1490 (fsp->location > 1)) 1491 return -EINVAL; 1492 1493 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1494 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1495 1496 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1497 1498 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1499 1500 return 0; 1501 } 1502 1503 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1504 struct ethtool_rxnfc *cmd) 1505 { 1506 struct ethtool_rx_flow_spec *fsp = 1507 (struct ethtool_rx_flow_spec *)&cmd->fs; 1508 struct mtk_mac *mac = netdev_priv(dev); 1509 struct mtk_eth *eth = mac->hw; 1510 int hwlro_idx; 1511 1512 if (fsp->location > 1) 1513 return -EINVAL; 1514 1515 mac->hwlro_ip[fsp->location] = 0; 1516 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1517 1518 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1519 1520 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1521 1522 return 0; 1523 } 1524 1525 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1526 { 1527 struct mtk_mac *mac = netdev_priv(dev); 1528 struct mtk_eth *eth = mac->hw; 1529 int i, hwlro_idx; 1530 1531 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1532 mac->hwlro_ip[i] = 0; 1533 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1534 1535 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1536 } 1537 1538 mac->hwlro_ip_cnt = 0; 1539 } 1540 1541 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1542 struct ethtool_rxnfc *cmd) 1543 { 1544 struct mtk_mac *mac = netdev_priv(dev); 1545 struct ethtool_rx_flow_spec *fsp = 1546 (struct ethtool_rx_flow_spec *)&cmd->fs; 1547 1548 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1549 fsp->flow_type = TCP_V4_FLOW; 1550 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1551 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1552 1553 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1554 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1555 fsp->h_u.tcp_ip4_spec.psrc = 0; 1556 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1557 fsp->h_u.tcp_ip4_spec.pdst = 0; 1558 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1559 fsp->h_u.tcp_ip4_spec.tos = 0; 1560 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1561 1562 return 0; 1563 } 1564 1565 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1566 struct ethtool_rxnfc *cmd, 1567 u32 *rule_locs) 1568 { 1569 struct mtk_mac *mac = netdev_priv(dev); 1570 int cnt = 0; 1571 int i; 1572 1573 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1574 if (mac->hwlro_ip[i]) { 1575 rule_locs[cnt] = i; 1576 cnt++; 1577 } 1578 } 1579 1580 cmd->rule_cnt = cnt; 1581 1582 return 0; 1583 } 1584 1585 static netdev_features_t mtk_fix_features(struct net_device *dev, 1586 netdev_features_t features) 1587 { 1588 if (!(features & NETIF_F_LRO)) { 1589 struct mtk_mac *mac = netdev_priv(dev); 1590 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1591 1592 if (ip_cnt) { 1593 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1594 1595 features |= NETIF_F_LRO; 1596 } 1597 } 1598 1599 return features; 1600 } 1601 1602 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1603 { 1604 int err = 0; 1605 1606 if (!((dev->features ^ features) & NETIF_F_LRO)) 1607 return 0; 1608 1609 if (!(features & NETIF_F_LRO)) 1610 mtk_hwlro_netdev_disable(dev); 1611 1612 return err; 1613 } 1614 1615 /* wait for DMA to finish whatever it is doing before we start using it again */ 1616 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1617 { 1618 unsigned long t_start = jiffies; 1619 1620 while (1) { 1621 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1622 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1623 return 0; 1624 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1625 break; 1626 } 1627 1628 dev_err(eth->dev, "DMA init timeout\n"); 1629 return -1; 1630 } 1631 1632 static int mtk_dma_init(struct mtk_eth *eth) 1633 { 1634 int err; 1635 u32 i; 1636 1637 if (mtk_dma_busy_wait(eth)) 1638 return -EBUSY; 1639 1640 /* QDMA needs scratch memory for internal reordering of the 1641 * descriptors 1642 */ 1643 err = mtk_init_fq_dma(eth); 1644 if (err) 1645 return err; 1646 1647 err = mtk_tx_alloc(eth); 1648 if (err) 1649 return err; 1650 1651 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 1652 if (err) 1653 return err; 1654 1655 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 1656 if (err) 1657 return err; 1658 1659 if (eth->hwlro) { 1660 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1661 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 1662 if (err) 1663 return err; 1664 } 1665 err = mtk_hwlro_rx_init(eth); 1666 if (err) 1667 return err; 1668 } 1669 1670 /* Enable random early drop and set drop threshold automatically */ 1671 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1672 MTK_QDMA_FC_THRES); 1673 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1674 1675 return 0; 1676 } 1677 1678 static void mtk_dma_free(struct mtk_eth *eth) 1679 { 1680 int i; 1681 1682 for (i = 0; i < MTK_MAC_COUNT; i++) 1683 if (eth->netdev[i]) 1684 netdev_reset_queue(eth->netdev[i]); 1685 if (eth->scratch_ring) { 1686 dma_free_coherent(eth->dev, 1687 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 1688 eth->scratch_ring, 1689 eth->phy_scratch_ring); 1690 eth->scratch_ring = NULL; 1691 eth->phy_scratch_ring = 0; 1692 } 1693 mtk_tx_clean(eth); 1694 mtk_rx_clean(eth, ð->rx_ring[0]); 1695 mtk_rx_clean(eth, ð->rx_ring_qdma); 1696 1697 if (eth->hwlro) { 1698 mtk_hwlro_rx_uninit(eth); 1699 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1700 mtk_rx_clean(eth, ð->rx_ring[i]); 1701 } 1702 1703 kfree(eth->scratch_head); 1704 } 1705 1706 static void mtk_tx_timeout(struct net_device *dev) 1707 { 1708 struct mtk_mac *mac = netdev_priv(dev); 1709 struct mtk_eth *eth = mac->hw; 1710 1711 eth->netdev[mac->id]->stats.tx_errors++; 1712 netif_err(eth, tx_err, dev, 1713 "transmit timed out\n"); 1714 schedule_work(ð->pending_work); 1715 } 1716 1717 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 1718 { 1719 struct mtk_eth *eth = _eth; 1720 1721 if (likely(napi_schedule_prep(ð->rx_napi))) { 1722 __napi_schedule(ð->rx_napi); 1723 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1724 } 1725 1726 return IRQ_HANDLED; 1727 } 1728 1729 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 1730 { 1731 struct mtk_eth *eth = _eth; 1732 1733 if (likely(napi_schedule_prep(ð->tx_napi))) { 1734 __napi_schedule(ð->tx_napi); 1735 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1736 } 1737 1738 return IRQ_HANDLED; 1739 } 1740 1741 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 1742 { 1743 struct mtk_eth *eth = _eth; 1744 1745 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { 1746 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) 1747 mtk_handle_irq_rx(irq, _eth); 1748 } 1749 if (mtk_r32(eth, MTK_QDMA_INT_MASK) & MTK_TX_DONE_INT) { 1750 if (mtk_r32(eth, MTK_QMTK_INT_STATUS) & MTK_TX_DONE_INT) 1751 mtk_handle_irq_tx(irq, _eth); 1752 } 1753 1754 return IRQ_HANDLED; 1755 } 1756 1757 #ifdef CONFIG_NET_POLL_CONTROLLER 1758 static void mtk_poll_controller(struct net_device *dev) 1759 { 1760 struct mtk_mac *mac = netdev_priv(dev); 1761 struct mtk_eth *eth = mac->hw; 1762 1763 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1764 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1765 mtk_handle_irq_rx(eth->irq[2], dev); 1766 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1767 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1768 } 1769 #endif 1770 1771 static int mtk_start_dma(struct mtk_eth *eth) 1772 { 1773 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 1774 int err; 1775 1776 err = mtk_dma_init(eth); 1777 if (err) { 1778 mtk_dma_free(eth); 1779 return err; 1780 } 1781 1782 mtk_w32(eth, 1783 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 1784 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | 1785 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1786 MTK_RX_BT_32DWORDS, 1787 MTK_QDMA_GLO_CFG); 1788 1789 mtk_w32(eth, 1790 MTK_RX_DMA_EN | rx_2b_offset | 1791 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 1792 MTK_PDMA_GLO_CFG); 1793 1794 return 0; 1795 } 1796 1797 static int mtk_open(struct net_device *dev) 1798 { 1799 struct mtk_mac *mac = netdev_priv(dev); 1800 struct mtk_eth *eth = mac->hw; 1801 1802 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1803 if (!refcount_read(ð->dma_refcnt)) { 1804 int err = mtk_start_dma(eth); 1805 1806 if (err) 1807 return err; 1808 1809 napi_enable(ð->tx_napi); 1810 napi_enable(ð->rx_napi); 1811 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1812 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1813 refcount_set(ð->dma_refcnt, 1); 1814 } 1815 else 1816 refcount_inc(ð->dma_refcnt); 1817 1818 phy_start(dev->phydev); 1819 netif_start_queue(dev); 1820 1821 return 0; 1822 } 1823 1824 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1825 { 1826 u32 val; 1827 int i; 1828 1829 /* stop the dma engine */ 1830 spin_lock_bh(ð->page_lock); 1831 val = mtk_r32(eth, glo_cfg); 1832 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1833 glo_cfg); 1834 spin_unlock_bh(ð->page_lock); 1835 1836 /* wait for dma stop */ 1837 for (i = 0; i < 10; i++) { 1838 val = mtk_r32(eth, glo_cfg); 1839 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1840 msleep(20); 1841 continue; 1842 } 1843 break; 1844 } 1845 } 1846 1847 static int mtk_stop(struct net_device *dev) 1848 { 1849 struct mtk_mac *mac = netdev_priv(dev); 1850 struct mtk_eth *eth = mac->hw; 1851 1852 netif_tx_disable(dev); 1853 phy_stop(dev->phydev); 1854 1855 /* only shutdown DMA if this is the last user */ 1856 if (!refcount_dec_and_test(ð->dma_refcnt)) 1857 return 0; 1858 1859 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1860 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1861 napi_disable(ð->tx_napi); 1862 napi_disable(ð->rx_napi); 1863 1864 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1865 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 1866 1867 mtk_dma_free(eth); 1868 1869 return 0; 1870 } 1871 1872 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 1873 { 1874 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1875 reset_bits, 1876 reset_bits); 1877 1878 usleep_range(1000, 1100); 1879 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1880 reset_bits, 1881 ~reset_bits); 1882 mdelay(10); 1883 } 1884 1885 static void mtk_clk_disable(struct mtk_eth *eth) 1886 { 1887 int clk; 1888 1889 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 1890 clk_disable_unprepare(eth->clks[clk]); 1891 } 1892 1893 static int mtk_clk_enable(struct mtk_eth *eth) 1894 { 1895 int clk, ret; 1896 1897 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 1898 ret = clk_prepare_enable(eth->clks[clk]); 1899 if (ret) 1900 goto err_disable_clks; 1901 } 1902 1903 return 0; 1904 1905 err_disable_clks: 1906 while (--clk >= 0) 1907 clk_disable_unprepare(eth->clks[clk]); 1908 1909 return ret; 1910 } 1911 1912 static int mtk_hw_init(struct mtk_eth *eth) 1913 { 1914 int i, val, ret; 1915 1916 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 1917 return 0; 1918 1919 pm_runtime_enable(eth->dev); 1920 pm_runtime_get_sync(eth->dev); 1921 1922 ret = mtk_clk_enable(eth); 1923 if (ret) 1924 goto err_disable_pm; 1925 1926 ethsys_reset(eth, RSTCTRL_FE); 1927 ethsys_reset(eth, RSTCTRL_PPE); 1928 1929 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 1930 for (i = 0; i < MTK_MAC_COUNT; i++) { 1931 if (!eth->mac[i]) 1932 continue; 1933 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id); 1934 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id); 1935 } 1936 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 1937 1938 if (eth->pctl) { 1939 /* Set GE2 driving and slew rate */ 1940 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1941 1942 /* set GE2 TDSEL */ 1943 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1944 1945 /* set GE2 TUNE */ 1946 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1947 } 1948 1949 /* Set linkdown as the default for each GMAC. Its own MCR would be set 1950 * up with the more appropriate value when mtk_phy_link_adjust call is 1951 * being invoked. 1952 */ 1953 for (i = 0; i < MTK_MAC_COUNT; i++) 1954 mtk_w32(eth, 0, MTK_MAC_MCR(i)); 1955 1956 /* Indicates CDM to parse the MTK special tag from CPU 1957 * which also is working out for untag packets. 1958 */ 1959 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 1960 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 1961 1962 /* Enable RX VLan Offloading */ 1963 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1964 1965 /* enable interrupt delay for RX */ 1966 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 1967 1968 /* disable delay and normal interrupt */ 1969 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1970 mtk_tx_irq_disable(eth, ~0); 1971 mtk_rx_irq_disable(eth, ~0); 1972 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1973 mtk_w32(eth, 0, MTK_RST_GL); 1974 1975 /* FE int grouping */ 1976 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 1977 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 1978 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 1979 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 1980 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 1981 1982 for (i = 0; i < 2; i++) { 1983 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1984 1985 /* setup the forward port to send frame to PDMA */ 1986 val &= ~0xffff; 1987 1988 /* Enable RX checksum */ 1989 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 1990 1991 /* setup the mac dma */ 1992 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 1993 } 1994 1995 return 0; 1996 1997 err_disable_pm: 1998 pm_runtime_put_sync(eth->dev); 1999 pm_runtime_disable(eth->dev); 2000 2001 return ret; 2002 } 2003 2004 static int mtk_hw_deinit(struct mtk_eth *eth) 2005 { 2006 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2007 return 0; 2008 2009 mtk_clk_disable(eth); 2010 2011 pm_runtime_put_sync(eth->dev); 2012 pm_runtime_disable(eth->dev); 2013 2014 return 0; 2015 } 2016 2017 static int __init mtk_init(struct net_device *dev) 2018 { 2019 struct mtk_mac *mac = netdev_priv(dev); 2020 struct mtk_eth *eth = mac->hw; 2021 const char *mac_addr; 2022 2023 mac_addr = of_get_mac_address(mac->of_node); 2024 if (!IS_ERR(mac_addr)) 2025 ether_addr_copy(dev->dev_addr, mac_addr); 2026 2027 /* If the mac address is invalid, use random mac address */ 2028 if (!is_valid_ether_addr(dev->dev_addr)) { 2029 eth_hw_addr_random(dev); 2030 dev_err(eth->dev, "generated random MAC address %pM\n", 2031 dev->dev_addr); 2032 } 2033 2034 return mtk_phy_connect(dev); 2035 } 2036 2037 static void mtk_uninit(struct net_device *dev) 2038 { 2039 struct mtk_mac *mac = netdev_priv(dev); 2040 struct mtk_eth *eth = mac->hw; 2041 2042 phy_disconnect(dev->phydev); 2043 if (of_phy_is_fixed_link(mac->of_node)) 2044 of_phy_deregister_fixed_link(mac->of_node); 2045 mtk_tx_irq_disable(eth, ~0); 2046 mtk_rx_irq_disable(eth, ~0); 2047 } 2048 2049 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2050 { 2051 switch (cmd) { 2052 case SIOCGMIIPHY: 2053 case SIOCGMIIREG: 2054 case SIOCSMIIREG: 2055 return phy_mii_ioctl(dev->phydev, ifr, cmd); 2056 default: 2057 break; 2058 } 2059 2060 return -EOPNOTSUPP; 2061 } 2062 2063 static void mtk_pending_work(struct work_struct *work) 2064 { 2065 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2066 int err, i; 2067 unsigned long restart = 0; 2068 2069 rtnl_lock(); 2070 2071 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2072 2073 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2074 cpu_relax(); 2075 2076 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2077 /* stop all devices to make sure that dma is properly shut down */ 2078 for (i = 0; i < MTK_MAC_COUNT; i++) { 2079 if (!eth->netdev[i]) 2080 continue; 2081 mtk_stop(eth->netdev[i]); 2082 __set_bit(i, &restart); 2083 } 2084 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2085 2086 /* restart underlying hardware such as power, clock, pin mux 2087 * and the connected phy 2088 */ 2089 mtk_hw_deinit(eth); 2090 2091 if (eth->dev->pins) 2092 pinctrl_select_state(eth->dev->pins->p, 2093 eth->dev->pins->default_state); 2094 mtk_hw_init(eth); 2095 2096 for (i = 0; i < MTK_MAC_COUNT; i++) { 2097 if (!eth->mac[i] || 2098 of_phy_is_fixed_link(eth->mac[i]->of_node)) 2099 continue; 2100 err = phy_init_hw(eth->netdev[i]->phydev); 2101 if (err) 2102 dev_err(eth->dev, "%s: PHY init failed.\n", 2103 eth->netdev[i]->name); 2104 } 2105 2106 /* restart DMA and enable IRQs */ 2107 for (i = 0; i < MTK_MAC_COUNT; i++) { 2108 if (!test_bit(i, &restart)) 2109 continue; 2110 err = mtk_open(eth->netdev[i]); 2111 if (err) { 2112 netif_alert(eth, ifup, eth->netdev[i], 2113 "Driver up/down cycle failed, closing device.\n"); 2114 dev_close(eth->netdev[i]); 2115 } 2116 } 2117 2118 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2119 2120 clear_bit_unlock(MTK_RESETTING, ð->state); 2121 2122 rtnl_unlock(); 2123 } 2124 2125 static int mtk_free_dev(struct mtk_eth *eth) 2126 { 2127 int i; 2128 2129 for (i = 0; i < MTK_MAC_COUNT; i++) { 2130 if (!eth->netdev[i]) 2131 continue; 2132 free_netdev(eth->netdev[i]); 2133 } 2134 2135 return 0; 2136 } 2137 2138 static int mtk_unreg_dev(struct mtk_eth *eth) 2139 { 2140 int i; 2141 2142 for (i = 0; i < MTK_MAC_COUNT; i++) { 2143 if (!eth->netdev[i]) 2144 continue; 2145 unregister_netdev(eth->netdev[i]); 2146 } 2147 2148 return 0; 2149 } 2150 2151 static int mtk_cleanup(struct mtk_eth *eth) 2152 { 2153 mtk_unreg_dev(eth); 2154 mtk_free_dev(eth); 2155 cancel_work_sync(ð->pending_work); 2156 2157 return 0; 2158 } 2159 2160 static int mtk_get_link_ksettings(struct net_device *ndev, 2161 struct ethtool_link_ksettings *cmd) 2162 { 2163 struct mtk_mac *mac = netdev_priv(ndev); 2164 2165 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2166 return -EBUSY; 2167 2168 phy_ethtool_ksettings_get(ndev->phydev, cmd); 2169 2170 return 0; 2171 } 2172 2173 static int mtk_set_link_ksettings(struct net_device *ndev, 2174 const struct ethtool_link_ksettings *cmd) 2175 { 2176 struct mtk_mac *mac = netdev_priv(ndev); 2177 2178 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2179 return -EBUSY; 2180 2181 return phy_ethtool_ksettings_set(ndev->phydev, cmd); 2182 } 2183 2184 static void mtk_get_drvinfo(struct net_device *dev, 2185 struct ethtool_drvinfo *info) 2186 { 2187 struct mtk_mac *mac = netdev_priv(dev); 2188 2189 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2190 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2191 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2192 } 2193 2194 static u32 mtk_get_msglevel(struct net_device *dev) 2195 { 2196 struct mtk_mac *mac = netdev_priv(dev); 2197 2198 return mac->hw->msg_enable; 2199 } 2200 2201 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2202 { 2203 struct mtk_mac *mac = netdev_priv(dev); 2204 2205 mac->hw->msg_enable = value; 2206 } 2207 2208 static int mtk_nway_reset(struct net_device *dev) 2209 { 2210 struct mtk_mac *mac = netdev_priv(dev); 2211 2212 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2213 return -EBUSY; 2214 2215 return genphy_restart_aneg(dev->phydev); 2216 } 2217 2218 static u32 mtk_get_link(struct net_device *dev) 2219 { 2220 struct mtk_mac *mac = netdev_priv(dev); 2221 int err; 2222 2223 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2224 return -EBUSY; 2225 2226 err = genphy_update_link(dev->phydev); 2227 if (err) 2228 return ethtool_op_get_link(dev); 2229 2230 return dev->phydev->link; 2231 } 2232 2233 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2234 { 2235 int i; 2236 2237 switch (stringset) { 2238 case ETH_SS_STATS: 2239 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2240 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2241 data += ETH_GSTRING_LEN; 2242 } 2243 break; 2244 } 2245 } 2246 2247 static int mtk_get_sset_count(struct net_device *dev, int sset) 2248 { 2249 switch (sset) { 2250 case ETH_SS_STATS: 2251 return ARRAY_SIZE(mtk_ethtool_stats); 2252 default: 2253 return -EOPNOTSUPP; 2254 } 2255 } 2256 2257 static void mtk_get_ethtool_stats(struct net_device *dev, 2258 struct ethtool_stats *stats, u64 *data) 2259 { 2260 struct mtk_mac *mac = netdev_priv(dev); 2261 struct mtk_hw_stats *hwstats = mac->hw_stats; 2262 u64 *data_src, *data_dst; 2263 unsigned int start; 2264 int i; 2265 2266 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2267 return; 2268 2269 if (netif_running(dev) && netif_device_present(dev)) { 2270 if (spin_trylock_bh(&hwstats->stats_lock)) { 2271 mtk_stats_update_mac(mac); 2272 spin_unlock_bh(&hwstats->stats_lock); 2273 } 2274 } 2275 2276 data_src = (u64 *)hwstats; 2277 2278 do { 2279 data_dst = data; 2280 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2281 2282 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2283 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2284 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2285 } 2286 2287 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2288 u32 *rule_locs) 2289 { 2290 int ret = -EOPNOTSUPP; 2291 2292 switch (cmd->cmd) { 2293 case ETHTOOL_GRXRINGS: 2294 if (dev->hw_features & NETIF_F_LRO) { 2295 cmd->data = MTK_MAX_RX_RING_NUM; 2296 ret = 0; 2297 } 2298 break; 2299 case ETHTOOL_GRXCLSRLCNT: 2300 if (dev->hw_features & NETIF_F_LRO) { 2301 struct mtk_mac *mac = netdev_priv(dev); 2302 2303 cmd->rule_cnt = mac->hwlro_ip_cnt; 2304 ret = 0; 2305 } 2306 break; 2307 case ETHTOOL_GRXCLSRULE: 2308 if (dev->hw_features & NETIF_F_LRO) 2309 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2310 break; 2311 case ETHTOOL_GRXCLSRLALL: 2312 if (dev->hw_features & NETIF_F_LRO) 2313 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2314 rule_locs); 2315 break; 2316 default: 2317 break; 2318 } 2319 2320 return ret; 2321 } 2322 2323 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2324 { 2325 int ret = -EOPNOTSUPP; 2326 2327 switch (cmd->cmd) { 2328 case ETHTOOL_SRXCLSRLINS: 2329 if (dev->hw_features & NETIF_F_LRO) 2330 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2331 break; 2332 case ETHTOOL_SRXCLSRLDEL: 2333 if (dev->hw_features & NETIF_F_LRO) 2334 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2335 break; 2336 default: 2337 break; 2338 } 2339 2340 return ret; 2341 } 2342 2343 static const struct ethtool_ops mtk_ethtool_ops = { 2344 .get_link_ksettings = mtk_get_link_ksettings, 2345 .set_link_ksettings = mtk_set_link_ksettings, 2346 .get_drvinfo = mtk_get_drvinfo, 2347 .get_msglevel = mtk_get_msglevel, 2348 .set_msglevel = mtk_set_msglevel, 2349 .nway_reset = mtk_nway_reset, 2350 .get_link = mtk_get_link, 2351 .get_strings = mtk_get_strings, 2352 .get_sset_count = mtk_get_sset_count, 2353 .get_ethtool_stats = mtk_get_ethtool_stats, 2354 .get_rxnfc = mtk_get_rxnfc, 2355 .set_rxnfc = mtk_set_rxnfc, 2356 }; 2357 2358 static const struct net_device_ops mtk_netdev_ops = { 2359 .ndo_init = mtk_init, 2360 .ndo_uninit = mtk_uninit, 2361 .ndo_open = mtk_open, 2362 .ndo_stop = mtk_stop, 2363 .ndo_start_xmit = mtk_start_xmit, 2364 .ndo_set_mac_address = mtk_set_mac_address, 2365 .ndo_validate_addr = eth_validate_addr, 2366 .ndo_do_ioctl = mtk_do_ioctl, 2367 .ndo_tx_timeout = mtk_tx_timeout, 2368 .ndo_get_stats64 = mtk_get_stats64, 2369 .ndo_fix_features = mtk_fix_features, 2370 .ndo_set_features = mtk_set_features, 2371 #ifdef CONFIG_NET_POLL_CONTROLLER 2372 .ndo_poll_controller = mtk_poll_controller, 2373 #endif 2374 }; 2375 2376 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2377 { 2378 struct mtk_mac *mac; 2379 const __be32 *_id = of_get_property(np, "reg", NULL); 2380 int id, err; 2381 2382 if (!_id) { 2383 dev_err(eth->dev, "missing mac id\n"); 2384 return -EINVAL; 2385 } 2386 2387 id = be32_to_cpup(_id); 2388 if (id >= MTK_MAC_COUNT) { 2389 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2390 return -EINVAL; 2391 } 2392 2393 if (eth->netdev[id]) { 2394 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2395 return -EINVAL; 2396 } 2397 2398 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2399 if (!eth->netdev[id]) { 2400 dev_err(eth->dev, "alloc_etherdev failed\n"); 2401 return -ENOMEM; 2402 } 2403 mac = netdev_priv(eth->netdev[id]); 2404 eth->mac[id] = mac; 2405 mac->id = id; 2406 mac->hw = eth; 2407 mac->of_node = np; 2408 2409 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2410 mac->hwlro_ip_cnt = 0; 2411 2412 mac->hw_stats = devm_kzalloc(eth->dev, 2413 sizeof(*mac->hw_stats), 2414 GFP_KERNEL); 2415 if (!mac->hw_stats) { 2416 dev_err(eth->dev, "failed to allocate counter memory\n"); 2417 err = -ENOMEM; 2418 goto free_netdev; 2419 } 2420 spin_lock_init(&mac->hw_stats->stats_lock); 2421 u64_stats_init(&mac->hw_stats->syncp); 2422 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2423 2424 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2425 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2426 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2427 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2428 2429 eth->netdev[id]->hw_features = MTK_HW_FEATURES; 2430 if (eth->hwlro) 2431 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2432 2433 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 2434 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2435 eth->netdev[id]->features |= MTK_HW_FEATURES; 2436 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2437 2438 eth->netdev[id]->irq = eth->irq[0]; 2439 eth->netdev[id]->dev.of_node = np; 2440 2441 return 0; 2442 2443 free_netdev: 2444 free_netdev(eth->netdev[id]); 2445 return err; 2446 } 2447 2448 static int mtk_probe(struct platform_device *pdev) 2449 { 2450 struct device_node *mac_np; 2451 struct mtk_eth *eth; 2452 int err; 2453 int i; 2454 2455 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2456 if (!eth) 2457 return -ENOMEM; 2458 2459 eth->soc = of_device_get_match_data(&pdev->dev); 2460 2461 eth->dev = &pdev->dev; 2462 eth->base = devm_platform_ioremap_resource(pdev, 0); 2463 if (IS_ERR(eth->base)) 2464 return PTR_ERR(eth->base); 2465 2466 spin_lock_init(ð->page_lock); 2467 spin_lock_init(ð->tx_irq_lock); 2468 spin_lock_init(ð->rx_irq_lock); 2469 2470 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2471 "mediatek,ethsys"); 2472 if (IS_ERR(eth->ethsys)) { 2473 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2474 return PTR_ERR(eth->ethsys); 2475 } 2476 2477 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 2478 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2479 "mediatek,infracfg"); 2480 if (IS_ERR(eth->infra)) { 2481 dev_err(&pdev->dev, "no infracfg regmap found\n"); 2482 return PTR_ERR(eth->infra); 2483 } 2484 } 2485 2486 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 2487 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 2488 GFP_KERNEL); 2489 if (!eth->sgmii) 2490 return -ENOMEM; 2491 2492 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 2493 eth->soc->ana_rgc3); 2494 2495 if (err) 2496 return err; 2497 } 2498 2499 if (eth->soc->required_pctl) { 2500 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2501 "mediatek,pctl"); 2502 if (IS_ERR(eth->pctl)) { 2503 dev_err(&pdev->dev, "no pctl regmap found\n"); 2504 return PTR_ERR(eth->pctl); 2505 } 2506 } 2507 2508 for (i = 0; i < 3; i++) { 2509 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 2510 eth->irq[i] = eth->irq[0]; 2511 else 2512 eth->irq[i] = platform_get_irq(pdev, i); 2513 if (eth->irq[i] < 0) { 2514 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2515 return -ENXIO; 2516 } 2517 } 2518 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2519 eth->clks[i] = devm_clk_get(eth->dev, 2520 mtk_clks_source_name[i]); 2521 if (IS_ERR(eth->clks[i])) { 2522 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2523 return -EPROBE_DEFER; 2524 if (eth->soc->required_clks & BIT(i)) { 2525 dev_err(&pdev->dev, "clock %s not found\n", 2526 mtk_clks_source_name[i]); 2527 return -EINVAL; 2528 } 2529 eth->clks[i] = NULL; 2530 } 2531 } 2532 2533 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 2534 INIT_WORK(ð->pending_work, mtk_pending_work); 2535 2536 err = mtk_hw_init(eth); 2537 if (err) 2538 return err; 2539 2540 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 2541 2542 for_each_child_of_node(pdev->dev.of_node, mac_np) { 2543 if (!of_device_is_compatible(mac_np, 2544 "mediatek,eth-mac")) 2545 continue; 2546 2547 if (!of_device_is_available(mac_np)) 2548 continue; 2549 2550 err = mtk_add_mac(eth, mac_np); 2551 if (err) { 2552 of_node_put(mac_np); 2553 goto err_deinit_hw; 2554 } 2555 } 2556 2557 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 2558 err = devm_request_irq(eth->dev, eth->irq[0], 2559 mtk_handle_irq, 0, 2560 dev_name(eth->dev), eth); 2561 } else { 2562 err = devm_request_irq(eth->dev, eth->irq[1], 2563 mtk_handle_irq_tx, 0, 2564 dev_name(eth->dev), eth); 2565 if (err) 2566 goto err_free_dev; 2567 2568 err = devm_request_irq(eth->dev, eth->irq[2], 2569 mtk_handle_irq_rx, 0, 2570 dev_name(eth->dev), eth); 2571 } 2572 if (err) 2573 goto err_free_dev; 2574 2575 err = mtk_mdio_init(eth); 2576 if (err) 2577 goto err_free_dev; 2578 2579 for (i = 0; i < MTK_MAX_DEVS; i++) { 2580 if (!eth->netdev[i]) 2581 continue; 2582 2583 err = register_netdev(eth->netdev[i]); 2584 if (err) { 2585 dev_err(eth->dev, "error bringing up device\n"); 2586 goto err_deinit_mdio; 2587 } else 2588 netif_info(eth, probe, eth->netdev[i], 2589 "mediatek frame engine at 0x%08lx, irq %d\n", 2590 eth->netdev[i]->base_addr, eth->irq[0]); 2591 } 2592 2593 /* we run 2 devices on the same DMA ring so we need a dummy device 2594 * for NAPI to work 2595 */ 2596 init_dummy_netdev(ð->dummy_dev); 2597 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 2598 MTK_NAPI_WEIGHT); 2599 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 2600 MTK_NAPI_WEIGHT); 2601 2602 platform_set_drvdata(pdev, eth); 2603 2604 return 0; 2605 2606 err_deinit_mdio: 2607 mtk_mdio_cleanup(eth); 2608 err_free_dev: 2609 mtk_free_dev(eth); 2610 err_deinit_hw: 2611 mtk_hw_deinit(eth); 2612 2613 return err; 2614 } 2615 2616 static int mtk_remove(struct platform_device *pdev) 2617 { 2618 struct mtk_eth *eth = platform_get_drvdata(pdev); 2619 int i; 2620 2621 /* stop all devices to make sure that dma is properly shut down */ 2622 for (i = 0; i < MTK_MAC_COUNT; i++) { 2623 if (!eth->netdev[i]) 2624 continue; 2625 mtk_stop(eth->netdev[i]); 2626 } 2627 2628 mtk_hw_deinit(eth); 2629 2630 netif_napi_del(ð->tx_napi); 2631 netif_napi_del(ð->rx_napi); 2632 mtk_cleanup(eth); 2633 mtk_mdio_cleanup(eth); 2634 2635 return 0; 2636 } 2637 2638 static const struct mtk_soc_data mt2701_data = { 2639 .caps = MT7623_CAPS | MTK_HWLRO, 2640 .required_clks = MT7623_CLKS_BITMAP, 2641 .required_pctl = true, 2642 }; 2643 2644 static const struct mtk_soc_data mt7621_data = { 2645 .caps = MT7621_CAPS, 2646 .required_clks = MT7621_CLKS_BITMAP, 2647 .required_pctl = false, 2648 }; 2649 2650 static const struct mtk_soc_data mt7622_data = { 2651 .ana_rgc3 = 0x2028, 2652 .caps = MT7622_CAPS | MTK_HWLRO, 2653 .required_clks = MT7622_CLKS_BITMAP, 2654 .required_pctl = false, 2655 }; 2656 2657 static const struct mtk_soc_data mt7623_data = { 2658 .caps = MT7623_CAPS | MTK_HWLRO, 2659 .required_clks = MT7623_CLKS_BITMAP, 2660 .required_pctl = true, 2661 }; 2662 2663 static const struct mtk_soc_data mt7629_data = { 2664 .ana_rgc3 = 0x128, 2665 .caps = MT7629_CAPS | MTK_HWLRO, 2666 .required_clks = MT7629_CLKS_BITMAP, 2667 .required_pctl = false, 2668 }; 2669 2670 const struct of_device_id of_mtk_match[] = { 2671 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 2672 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 2673 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 2674 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 2675 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 2676 {}, 2677 }; 2678 MODULE_DEVICE_TABLE(of, of_mtk_match); 2679 2680 static struct platform_driver mtk_driver = { 2681 .probe = mtk_probe, 2682 .remove = mtk_remove, 2683 .driver = { 2684 .name = "mtk_soc_eth", 2685 .of_match_table = of_mtk_match, 2686 }, 2687 }; 2688 2689 module_platform_driver(mtk_driver); 2690 2691 MODULE_LICENSE("GPL"); 2692 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 2693 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 2694