1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/regmap.h> 14 #include <linux/clk.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/if_vlan.h> 17 #include <linux/reset.h> 18 #include <linux/tcp.h> 19 #include <linux/interrupt.h> 20 #include <linux/pinctrl/devinfo.h> 21 #include <linux/phylink.h> 22 #include <net/dsa.h> 23 24 #include "mtk_eth_soc.h" 25 26 static int mtk_msg_level = -1; 27 module_param_named(msg_level, mtk_msg_level, int, 0); 28 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 29 30 #define MTK_ETHTOOL_STAT(x) { #x, \ 31 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 32 33 /* strings used by ethtool */ 34 static const struct mtk_ethtool_stats { 35 char str[ETH_GSTRING_LEN]; 36 u32 offset; 37 } mtk_ethtool_stats[] = { 38 MTK_ETHTOOL_STAT(tx_bytes), 39 MTK_ETHTOOL_STAT(tx_packets), 40 MTK_ETHTOOL_STAT(tx_skip), 41 MTK_ETHTOOL_STAT(tx_collisions), 42 MTK_ETHTOOL_STAT(rx_bytes), 43 MTK_ETHTOOL_STAT(rx_packets), 44 MTK_ETHTOOL_STAT(rx_overflow), 45 MTK_ETHTOOL_STAT(rx_fcs_errors), 46 MTK_ETHTOOL_STAT(rx_short_errors), 47 MTK_ETHTOOL_STAT(rx_long_errors), 48 MTK_ETHTOOL_STAT(rx_checksum_errors), 49 MTK_ETHTOOL_STAT(rx_flow_control_packets), 50 }; 51 52 static const char * const mtk_clks_source_name[] = { 53 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 54 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 55 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 56 "sgmii_ck", "eth2pll", 57 }; 58 59 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 60 { 61 __raw_writel(val, eth->base + reg); 62 } 63 64 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 65 { 66 return __raw_readl(eth->base + reg); 67 } 68 69 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 70 { 71 u32 val; 72 73 val = mtk_r32(eth, reg); 74 val &= ~mask; 75 val |= set; 76 mtk_w32(eth, val, reg); 77 return reg; 78 } 79 80 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 81 { 82 unsigned long t_start = jiffies; 83 84 while (1) { 85 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 86 return 0; 87 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 88 break; 89 usleep_range(10, 20); 90 } 91 92 dev_err(eth->dev, "mdio: MDIO timeout\n"); 93 return -1; 94 } 95 96 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 97 u32 phy_register, u32 write_data) 98 { 99 if (mtk_mdio_busy_wait(eth)) 100 return -1; 101 102 write_data &= 0xffff; 103 104 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 105 (phy_register << PHY_IAC_REG_SHIFT) | 106 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 107 MTK_PHY_IAC); 108 109 if (mtk_mdio_busy_wait(eth)) 110 return -1; 111 112 return 0; 113 } 114 115 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 116 { 117 u32 d; 118 119 if (mtk_mdio_busy_wait(eth)) 120 return 0xffff; 121 122 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 123 (phy_reg << PHY_IAC_REG_SHIFT) | 124 (phy_addr << PHY_IAC_ADDR_SHIFT), 125 MTK_PHY_IAC); 126 127 if (mtk_mdio_busy_wait(eth)) 128 return 0xffff; 129 130 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 131 132 return d; 133 } 134 135 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 136 int phy_reg, u16 val) 137 { 138 struct mtk_eth *eth = bus->priv; 139 140 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 141 } 142 143 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 144 { 145 struct mtk_eth *eth = bus->priv; 146 147 return _mtk_mdio_read(eth, phy_addr, phy_reg); 148 } 149 150 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 151 phy_interface_t interface) 152 { 153 u32 val; 154 155 /* Check DDR memory type. 156 * Currently TRGMII mode with DDR2 memory is not supported. 157 */ 158 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 159 if (interface == PHY_INTERFACE_MODE_TRGMII && 160 val & SYSCFG_DRAM_TYPE_DDR2) { 161 dev_err(eth->dev, 162 "TRGMII mode with DDR2 memory is not supported!\n"); 163 return -EOPNOTSUPP; 164 } 165 166 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 167 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 168 169 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 170 ETHSYS_TRGMII_MT7621_MASK, val); 171 172 return 0; 173 } 174 175 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 176 phy_interface_t interface, int speed) 177 { 178 u32 val; 179 int ret; 180 181 if (interface == PHY_INTERFACE_MODE_TRGMII) { 182 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 183 val = 500000000; 184 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 185 if (ret) 186 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 187 return; 188 } 189 190 val = (speed == SPEED_1000) ? 191 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 192 mtk_w32(eth, val, INTF_MODE); 193 194 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 195 ETHSYS_TRGMII_CLK_SEL362_5, 196 ETHSYS_TRGMII_CLK_SEL362_5); 197 198 val = (speed == SPEED_1000) ? 250000000 : 500000000; 199 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 200 if (ret) 201 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 202 203 val = (speed == SPEED_1000) ? 204 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 205 mtk_w32(eth, val, TRGMII_RCK_CTRL); 206 207 val = (speed == SPEED_1000) ? 208 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 209 mtk_w32(eth, val, TRGMII_TCK_CTRL); 210 } 211 212 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 213 const struct phylink_link_state *state) 214 { 215 struct mtk_mac *mac = container_of(config, struct mtk_mac, 216 phylink_config); 217 struct mtk_eth *eth = mac->hw; 218 u32 mcr_cur, mcr_new, sid, i; 219 int val, ge_mode, err; 220 221 /* MT76x8 has no hardware settings between for the MAC */ 222 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 223 mac->interface != state->interface) { 224 /* Setup soc pin functions */ 225 switch (state->interface) { 226 case PHY_INTERFACE_MODE_TRGMII: 227 if (mac->id) 228 goto err_phy; 229 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 230 MTK_GMAC1_TRGMII)) 231 goto err_phy; 232 fallthrough; 233 case PHY_INTERFACE_MODE_RGMII_TXID: 234 case PHY_INTERFACE_MODE_RGMII_RXID: 235 case PHY_INTERFACE_MODE_RGMII_ID: 236 case PHY_INTERFACE_MODE_RGMII: 237 case PHY_INTERFACE_MODE_MII: 238 case PHY_INTERFACE_MODE_REVMII: 239 case PHY_INTERFACE_MODE_RMII: 240 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 241 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 242 if (err) 243 goto init_err; 244 } 245 break; 246 case PHY_INTERFACE_MODE_1000BASEX: 247 case PHY_INTERFACE_MODE_2500BASEX: 248 case PHY_INTERFACE_MODE_SGMII: 249 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 250 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 251 if (err) 252 goto init_err; 253 } 254 break; 255 case PHY_INTERFACE_MODE_GMII: 256 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 257 err = mtk_gmac_gephy_path_setup(eth, mac->id); 258 if (err) 259 goto init_err; 260 } 261 break; 262 default: 263 goto err_phy; 264 } 265 266 /* Setup clock for 1st gmac */ 267 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 268 !phy_interface_mode_is_8023z(state->interface) && 269 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 270 if (MTK_HAS_CAPS(mac->hw->soc->caps, 271 MTK_TRGMII_MT7621_CLK)) { 272 if (mt7621_gmac0_rgmii_adjust(mac->hw, 273 state->interface)) 274 goto err_phy; 275 } else { 276 mtk_gmac0_rgmii_adjust(mac->hw, 277 state->interface, 278 state->speed); 279 280 /* mt7623_pad_clk_setup */ 281 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 282 mtk_w32(mac->hw, 283 TD_DM_DRVP(8) | TD_DM_DRVN(8), 284 TRGMII_TD_ODT(i)); 285 286 /* Assert/release MT7623 RXC reset */ 287 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 288 TRGMII_RCK_CTRL); 289 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 290 } 291 } 292 293 ge_mode = 0; 294 switch (state->interface) { 295 case PHY_INTERFACE_MODE_MII: 296 case PHY_INTERFACE_MODE_GMII: 297 ge_mode = 1; 298 break; 299 case PHY_INTERFACE_MODE_REVMII: 300 ge_mode = 2; 301 break; 302 case PHY_INTERFACE_MODE_RMII: 303 if (mac->id) 304 goto err_phy; 305 ge_mode = 3; 306 break; 307 default: 308 break; 309 } 310 311 /* put the gmac into the right mode */ 312 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 313 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 314 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 315 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 316 317 mac->interface = state->interface; 318 } 319 320 /* SGMII */ 321 if (state->interface == PHY_INTERFACE_MODE_SGMII || 322 phy_interface_mode_is_8023z(state->interface)) { 323 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 324 * being setup done. 325 */ 326 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 327 328 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 329 SYSCFG0_SGMII_MASK, 330 ~(u32)SYSCFG0_SGMII_MASK); 331 332 /* Decide how GMAC and SGMIISYS be mapped */ 333 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 334 0 : mac->id; 335 336 /* Setup SGMIISYS with the determined property */ 337 if (state->interface != PHY_INTERFACE_MODE_SGMII) 338 err = mtk_sgmii_setup_mode_force(eth->sgmii, sid, 339 state); 340 else if (phylink_autoneg_inband(mode)) 341 err = mtk_sgmii_setup_mode_an(eth->sgmii, sid); 342 343 if (err) 344 goto init_err; 345 346 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 347 SYSCFG0_SGMII_MASK, val); 348 } else if (phylink_autoneg_inband(mode)) { 349 dev_err(eth->dev, 350 "In-band mode not supported in non SGMII mode!\n"); 351 return; 352 } 353 354 /* Setup gmac */ 355 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 356 mcr_new = mcr_cur; 357 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 358 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; 359 360 /* Only update control register when needed! */ 361 if (mcr_new != mcr_cur) 362 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 363 364 return; 365 366 err_phy: 367 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 368 mac->id, phy_modes(state->interface)); 369 return; 370 371 init_err: 372 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 373 mac->id, phy_modes(state->interface), err); 374 } 375 376 static void mtk_mac_pcs_get_state(struct phylink_config *config, 377 struct phylink_link_state *state) 378 { 379 struct mtk_mac *mac = container_of(config, struct mtk_mac, 380 phylink_config); 381 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 382 383 state->link = (pmsr & MAC_MSR_LINK); 384 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 385 386 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 387 case 0: 388 state->speed = SPEED_10; 389 break; 390 case MAC_MSR_SPEED_100: 391 state->speed = SPEED_100; 392 break; 393 case MAC_MSR_SPEED_1000: 394 state->speed = SPEED_1000; 395 break; 396 default: 397 state->speed = SPEED_UNKNOWN; 398 break; 399 } 400 401 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 402 if (pmsr & MAC_MSR_RX_FC) 403 state->pause |= MLO_PAUSE_RX; 404 if (pmsr & MAC_MSR_TX_FC) 405 state->pause |= MLO_PAUSE_TX; 406 } 407 408 static void mtk_mac_an_restart(struct phylink_config *config) 409 { 410 struct mtk_mac *mac = container_of(config, struct mtk_mac, 411 phylink_config); 412 413 mtk_sgmii_restart_an(mac->hw, mac->id); 414 } 415 416 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 417 phy_interface_t interface) 418 { 419 struct mtk_mac *mac = container_of(config, struct mtk_mac, 420 phylink_config); 421 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 422 423 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 424 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 425 } 426 427 static void mtk_mac_link_up(struct phylink_config *config, 428 struct phy_device *phy, 429 unsigned int mode, phy_interface_t interface, 430 int speed, int duplex, bool tx_pause, bool rx_pause) 431 { 432 struct mtk_mac *mac = container_of(config, struct mtk_mac, 433 phylink_config); 434 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 435 436 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 437 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 438 MAC_MCR_FORCE_RX_FC); 439 440 /* Configure speed */ 441 switch (speed) { 442 case SPEED_2500: 443 case SPEED_1000: 444 mcr |= MAC_MCR_SPEED_1000; 445 break; 446 case SPEED_100: 447 mcr |= MAC_MCR_SPEED_100; 448 break; 449 } 450 451 /* Configure duplex */ 452 if (duplex == DUPLEX_FULL) 453 mcr |= MAC_MCR_FORCE_DPX; 454 455 /* Configure pause modes - phylink will avoid these for half duplex */ 456 if (tx_pause) 457 mcr |= MAC_MCR_FORCE_TX_FC; 458 if (rx_pause) 459 mcr |= MAC_MCR_FORCE_RX_FC; 460 461 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 462 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 463 } 464 465 static void mtk_validate(struct phylink_config *config, 466 unsigned long *supported, 467 struct phylink_link_state *state) 468 { 469 struct mtk_mac *mac = container_of(config, struct mtk_mac, 470 phylink_config); 471 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 472 473 if (state->interface != PHY_INTERFACE_MODE_NA && 474 state->interface != PHY_INTERFACE_MODE_MII && 475 state->interface != PHY_INTERFACE_MODE_GMII && 476 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) && 477 phy_interface_mode_is_rgmii(state->interface)) && 478 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && 479 !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) && 480 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) && 481 (state->interface == PHY_INTERFACE_MODE_SGMII || 482 phy_interface_mode_is_8023z(state->interface)))) { 483 linkmode_zero(supported); 484 return; 485 } 486 487 phylink_set_port_modes(mask); 488 phylink_set(mask, Autoneg); 489 490 switch (state->interface) { 491 case PHY_INTERFACE_MODE_TRGMII: 492 phylink_set(mask, 1000baseT_Full); 493 break; 494 case PHY_INTERFACE_MODE_1000BASEX: 495 case PHY_INTERFACE_MODE_2500BASEX: 496 phylink_set(mask, 1000baseX_Full); 497 phylink_set(mask, 2500baseX_Full); 498 break; 499 case PHY_INTERFACE_MODE_GMII: 500 case PHY_INTERFACE_MODE_RGMII: 501 case PHY_INTERFACE_MODE_RGMII_ID: 502 case PHY_INTERFACE_MODE_RGMII_RXID: 503 case PHY_INTERFACE_MODE_RGMII_TXID: 504 phylink_set(mask, 1000baseT_Half); 505 fallthrough; 506 case PHY_INTERFACE_MODE_SGMII: 507 phylink_set(mask, 1000baseT_Full); 508 phylink_set(mask, 1000baseX_Full); 509 fallthrough; 510 case PHY_INTERFACE_MODE_MII: 511 case PHY_INTERFACE_MODE_RMII: 512 case PHY_INTERFACE_MODE_REVMII: 513 case PHY_INTERFACE_MODE_NA: 514 default: 515 phylink_set(mask, 10baseT_Half); 516 phylink_set(mask, 10baseT_Full); 517 phylink_set(mask, 100baseT_Half); 518 phylink_set(mask, 100baseT_Full); 519 break; 520 } 521 522 if (state->interface == PHY_INTERFACE_MODE_NA) { 523 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 524 phylink_set(mask, 1000baseT_Full); 525 phylink_set(mask, 1000baseX_Full); 526 phylink_set(mask, 2500baseX_Full); 527 } 528 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) { 529 phylink_set(mask, 1000baseT_Full); 530 phylink_set(mask, 1000baseT_Half); 531 phylink_set(mask, 1000baseX_Full); 532 } 533 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) { 534 phylink_set(mask, 1000baseT_Full); 535 phylink_set(mask, 1000baseT_Half); 536 } 537 } 538 539 phylink_set(mask, Pause); 540 phylink_set(mask, Asym_Pause); 541 542 linkmode_and(supported, supported, mask); 543 linkmode_and(state->advertising, state->advertising, mask); 544 545 /* We can only operate at 2500BaseX or 1000BaseX. If requested 546 * to advertise both, only report advertising at 2500BaseX. 547 */ 548 phylink_helper_basex_speed(state); 549 } 550 551 static const struct phylink_mac_ops mtk_phylink_ops = { 552 .validate = mtk_validate, 553 .mac_pcs_get_state = mtk_mac_pcs_get_state, 554 .mac_an_restart = mtk_mac_an_restart, 555 .mac_config = mtk_mac_config, 556 .mac_link_down = mtk_mac_link_down, 557 .mac_link_up = mtk_mac_link_up, 558 }; 559 560 static int mtk_mdio_init(struct mtk_eth *eth) 561 { 562 struct device_node *mii_np; 563 int ret; 564 565 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 566 if (!mii_np) { 567 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 568 return -ENODEV; 569 } 570 571 if (!of_device_is_available(mii_np)) { 572 ret = -ENODEV; 573 goto err_put_node; 574 } 575 576 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 577 if (!eth->mii_bus) { 578 ret = -ENOMEM; 579 goto err_put_node; 580 } 581 582 eth->mii_bus->name = "mdio"; 583 eth->mii_bus->read = mtk_mdio_read; 584 eth->mii_bus->write = mtk_mdio_write; 585 eth->mii_bus->priv = eth; 586 eth->mii_bus->parent = eth->dev; 587 588 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 589 ret = of_mdiobus_register(eth->mii_bus, mii_np); 590 591 err_put_node: 592 of_node_put(mii_np); 593 return ret; 594 } 595 596 static void mtk_mdio_cleanup(struct mtk_eth *eth) 597 { 598 if (!eth->mii_bus) 599 return; 600 601 mdiobus_unregister(eth->mii_bus); 602 } 603 604 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 605 { 606 unsigned long flags; 607 u32 val; 608 609 spin_lock_irqsave(ð->tx_irq_lock, flags); 610 val = mtk_r32(eth, eth->tx_int_mask_reg); 611 mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg); 612 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 613 } 614 615 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 616 { 617 unsigned long flags; 618 u32 val; 619 620 spin_lock_irqsave(ð->tx_irq_lock, flags); 621 val = mtk_r32(eth, eth->tx_int_mask_reg); 622 mtk_w32(eth, val | mask, eth->tx_int_mask_reg); 623 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 624 } 625 626 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 627 { 628 unsigned long flags; 629 u32 val; 630 631 spin_lock_irqsave(ð->rx_irq_lock, flags); 632 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 633 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 634 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 635 } 636 637 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 638 { 639 unsigned long flags; 640 u32 val; 641 642 spin_lock_irqsave(ð->rx_irq_lock, flags); 643 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 644 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 645 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 646 } 647 648 static int mtk_set_mac_address(struct net_device *dev, void *p) 649 { 650 int ret = eth_mac_addr(dev, p); 651 struct mtk_mac *mac = netdev_priv(dev); 652 struct mtk_eth *eth = mac->hw; 653 const char *macaddr = dev->dev_addr; 654 655 if (ret) 656 return ret; 657 658 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 659 return -EBUSY; 660 661 spin_lock_bh(&mac->hw->page_lock); 662 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 663 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 664 MT7628_SDM_MAC_ADRH); 665 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 666 (macaddr[4] << 8) | macaddr[5], 667 MT7628_SDM_MAC_ADRL); 668 } else { 669 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 670 MTK_GDMA_MAC_ADRH(mac->id)); 671 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 672 (macaddr[4] << 8) | macaddr[5], 673 MTK_GDMA_MAC_ADRL(mac->id)); 674 } 675 spin_unlock_bh(&mac->hw->page_lock); 676 677 return 0; 678 } 679 680 void mtk_stats_update_mac(struct mtk_mac *mac) 681 { 682 struct mtk_hw_stats *hw_stats = mac->hw_stats; 683 unsigned int base = MTK_GDM1_TX_GBCNT; 684 u64 stats; 685 686 base += hw_stats->reg_offset; 687 688 u64_stats_update_begin(&hw_stats->syncp); 689 690 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 691 stats = mtk_r32(mac->hw, base + 0x04); 692 if (stats) 693 hw_stats->rx_bytes += (stats << 32); 694 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 695 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 696 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 697 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 698 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 699 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 700 hw_stats->rx_flow_control_packets += 701 mtk_r32(mac->hw, base + 0x24); 702 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 703 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 704 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 705 stats = mtk_r32(mac->hw, base + 0x34); 706 if (stats) 707 hw_stats->tx_bytes += (stats << 32); 708 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 709 u64_stats_update_end(&hw_stats->syncp); 710 } 711 712 static void mtk_stats_update(struct mtk_eth *eth) 713 { 714 int i; 715 716 for (i = 0; i < MTK_MAC_COUNT; i++) { 717 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 718 continue; 719 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 720 mtk_stats_update_mac(eth->mac[i]); 721 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 722 } 723 } 724 } 725 726 static void mtk_get_stats64(struct net_device *dev, 727 struct rtnl_link_stats64 *storage) 728 { 729 struct mtk_mac *mac = netdev_priv(dev); 730 struct mtk_hw_stats *hw_stats = mac->hw_stats; 731 unsigned int start; 732 733 if (netif_running(dev) && netif_device_present(dev)) { 734 if (spin_trylock_bh(&hw_stats->stats_lock)) { 735 mtk_stats_update_mac(mac); 736 spin_unlock_bh(&hw_stats->stats_lock); 737 } 738 } 739 740 do { 741 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 742 storage->rx_packets = hw_stats->rx_packets; 743 storage->tx_packets = hw_stats->tx_packets; 744 storage->rx_bytes = hw_stats->rx_bytes; 745 storage->tx_bytes = hw_stats->tx_bytes; 746 storage->collisions = hw_stats->tx_collisions; 747 storage->rx_length_errors = hw_stats->rx_short_errors + 748 hw_stats->rx_long_errors; 749 storage->rx_over_errors = hw_stats->rx_overflow; 750 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 751 storage->rx_errors = hw_stats->rx_checksum_errors; 752 storage->tx_aborted_errors = hw_stats->tx_skip; 753 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 754 755 storage->tx_errors = dev->stats.tx_errors; 756 storage->rx_dropped = dev->stats.rx_dropped; 757 storage->tx_dropped = dev->stats.tx_dropped; 758 } 759 760 static inline int mtk_max_frag_size(int mtu) 761 { 762 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 763 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 764 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 765 766 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 767 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 768 } 769 770 static inline int mtk_max_buf_size(int frag_size) 771 { 772 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 773 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 774 775 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 776 777 return buf_size; 778 } 779 780 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 781 struct mtk_rx_dma *dma_rxd) 782 { 783 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 784 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 785 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 786 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 787 } 788 789 /* the qdma core needs scratch memory to be setup */ 790 static int mtk_init_fq_dma(struct mtk_eth *eth) 791 { 792 dma_addr_t phy_ring_tail; 793 int cnt = MTK_DMA_SIZE; 794 dma_addr_t dma_addr; 795 int i; 796 797 eth->scratch_ring = dma_alloc_coherent(eth->dev, 798 cnt * sizeof(struct mtk_tx_dma), 799 ð->phy_scratch_ring, 800 GFP_ATOMIC); 801 if (unlikely(!eth->scratch_ring)) 802 return -ENOMEM; 803 804 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 805 GFP_KERNEL); 806 if (unlikely(!eth->scratch_head)) 807 return -ENOMEM; 808 809 dma_addr = dma_map_single(eth->dev, 810 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 811 DMA_FROM_DEVICE); 812 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 813 return -ENOMEM; 814 815 phy_ring_tail = eth->phy_scratch_ring + 816 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 817 818 for (i = 0; i < cnt; i++) { 819 eth->scratch_ring[i].txd1 = 820 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 821 if (i < cnt - 1) 822 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 823 ((i + 1) * sizeof(struct mtk_tx_dma))); 824 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 825 } 826 827 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 828 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 829 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 830 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 831 832 return 0; 833 } 834 835 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 836 { 837 void *ret = ring->dma; 838 839 return ret + (desc - ring->phys); 840 } 841 842 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 843 struct mtk_tx_dma *txd) 844 { 845 int idx = txd - ring->dma; 846 847 return &ring->buf[idx]; 848 } 849 850 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 851 struct mtk_tx_dma *dma) 852 { 853 return ring->dma_pdma - ring->dma + dma; 854 } 855 856 static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma) 857 { 858 return ((void *)dma - (void *)ring->dma) / sizeof(*dma); 859 } 860 861 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 862 { 863 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 864 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 865 dma_unmap_single(eth->dev, 866 dma_unmap_addr(tx_buf, dma_addr0), 867 dma_unmap_len(tx_buf, dma_len0), 868 DMA_TO_DEVICE); 869 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 870 dma_unmap_page(eth->dev, 871 dma_unmap_addr(tx_buf, dma_addr0), 872 dma_unmap_len(tx_buf, dma_len0), 873 DMA_TO_DEVICE); 874 } 875 } else { 876 if (dma_unmap_len(tx_buf, dma_len0)) { 877 dma_unmap_page(eth->dev, 878 dma_unmap_addr(tx_buf, dma_addr0), 879 dma_unmap_len(tx_buf, dma_len0), 880 DMA_TO_DEVICE); 881 } 882 883 if (dma_unmap_len(tx_buf, dma_len1)) { 884 dma_unmap_page(eth->dev, 885 dma_unmap_addr(tx_buf, dma_addr1), 886 dma_unmap_len(tx_buf, dma_len1), 887 DMA_TO_DEVICE); 888 } 889 } 890 891 tx_buf->flags = 0; 892 if (tx_buf->skb && 893 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 894 dev_kfree_skb_any(tx_buf->skb); 895 tx_buf->skb = NULL; 896 } 897 898 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 899 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 900 size_t size, int idx) 901 { 902 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 903 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 904 dma_unmap_len_set(tx_buf, dma_len0, size); 905 } else { 906 if (idx & 1) { 907 txd->txd3 = mapped_addr; 908 txd->txd2 |= TX_DMA_PLEN1(size); 909 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 910 dma_unmap_len_set(tx_buf, dma_len1, size); 911 } else { 912 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 913 txd->txd1 = mapped_addr; 914 txd->txd2 = TX_DMA_PLEN0(size); 915 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 916 dma_unmap_len_set(tx_buf, dma_len0, size); 917 } 918 } 919 } 920 921 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 922 int tx_num, struct mtk_tx_ring *ring, bool gso) 923 { 924 struct mtk_mac *mac = netdev_priv(dev); 925 struct mtk_eth *eth = mac->hw; 926 struct mtk_tx_dma *itxd, *txd; 927 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 928 struct mtk_tx_buf *itx_buf, *tx_buf; 929 dma_addr_t mapped_addr; 930 unsigned int nr_frags; 931 int i, n_desc = 1; 932 u32 txd4 = 0, fport; 933 int k = 0; 934 935 itxd = ring->next_free; 936 itxd_pdma = qdma_to_pdma(ring, itxd); 937 if (itxd == ring->last_free) 938 return -ENOMEM; 939 940 /* set the forward port */ 941 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 942 txd4 |= fport; 943 944 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 945 memset(itx_buf, 0, sizeof(*itx_buf)); 946 947 if (gso) 948 txd4 |= TX_DMA_TSO; 949 950 /* TX Checksum offload */ 951 if (skb->ip_summed == CHECKSUM_PARTIAL) 952 txd4 |= TX_DMA_CHKSUM; 953 954 /* VLAN header offload */ 955 if (skb_vlan_tag_present(skb)) 956 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 957 958 mapped_addr = dma_map_single(eth->dev, skb->data, 959 skb_headlen(skb), DMA_TO_DEVICE); 960 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 961 return -ENOMEM; 962 963 WRITE_ONCE(itxd->txd1, mapped_addr); 964 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 965 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 966 MTK_TX_FLAGS_FPORT1; 967 setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb), 968 k++); 969 970 /* TX SG offload */ 971 txd = itxd; 972 txd_pdma = qdma_to_pdma(ring, txd); 973 nr_frags = skb_shinfo(skb)->nr_frags; 974 975 for (i = 0; i < nr_frags; i++) { 976 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 977 unsigned int offset = 0; 978 int frag_size = skb_frag_size(frag); 979 980 while (frag_size) { 981 bool last_frag = false; 982 unsigned int frag_map_size; 983 bool new_desc = true; 984 985 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) || 986 (i & 0x1)) { 987 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 988 txd_pdma = qdma_to_pdma(ring, txd); 989 if (txd == ring->last_free) 990 goto err_dma; 991 992 n_desc++; 993 } else { 994 new_desc = false; 995 } 996 997 998 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 999 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 1000 frag_map_size, 1001 DMA_TO_DEVICE); 1002 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 1003 goto err_dma; 1004 1005 if (i == nr_frags - 1 && 1006 (frag_size - frag_map_size) == 0) 1007 last_frag = true; 1008 1009 WRITE_ONCE(txd->txd1, mapped_addr); 1010 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 1011 TX_DMA_PLEN0(frag_map_size) | 1012 last_frag * TX_DMA_LS0)); 1013 WRITE_ONCE(txd->txd4, fport); 1014 1015 tx_buf = mtk_desc_to_tx_buf(ring, txd); 1016 if (new_desc) 1017 memset(tx_buf, 0, sizeof(*tx_buf)); 1018 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 1019 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1020 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1021 MTK_TX_FLAGS_FPORT1; 1022 1023 setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr, 1024 frag_map_size, k++); 1025 1026 frag_size -= frag_map_size; 1027 offset += frag_map_size; 1028 } 1029 } 1030 1031 /* store skb to cleanup */ 1032 itx_buf->skb = skb; 1033 1034 WRITE_ONCE(itxd->txd4, txd4); 1035 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 1036 (!nr_frags * TX_DMA_LS0))); 1037 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1038 if (k & 0x1) 1039 txd_pdma->txd2 |= TX_DMA_LS0; 1040 else 1041 txd_pdma->txd2 |= TX_DMA_LS1; 1042 } 1043 1044 netdev_sent_queue(dev, skb->len); 1045 skb_tx_timestamp(skb); 1046 1047 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1048 atomic_sub(n_desc, &ring->free_count); 1049 1050 /* make sure that all changes to the dma ring are flushed before we 1051 * continue 1052 */ 1053 wmb(); 1054 1055 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1056 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 1057 !netdev_xmit_more()) 1058 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 1059 } else { 1060 int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd), 1061 ring->dma_size); 1062 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1063 } 1064 1065 return 0; 1066 1067 err_dma: 1068 do { 1069 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 1070 1071 /* unmap dma */ 1072 mtk_tx_unmap(eth, tx_buf); 1073 1074 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1075 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1076 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1077 1078 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1079 itxd_pdma = qdma_to_pdma(ring, itxd); 1080 } while (itxd != txd); 1081 1082 return -ENOMEM; 1083 } 1084 1085 static inline int mtk_cal_txd_req(struct sk_buff *skb) 1086 { 1087 int i, nfrags; 1088 skb_frag_t *frag; 1089 1090 nfrags = 1; 1091 if (skb_is_gso(skb)) { 1092 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1093 frag = &skb_shinfo(skb)->frags[i]; 1094 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1095 MTK_TX_DMA_BUF_LEN); 1096 } 1097 } else { 1098 nfrags += skb_shinfo(skb)->nr_frags; 1099 } 1100 1101 return nfrags; 1102 } 1103 1104 static int mtk_queue_stopped(struct mtk_eth *eth) 1105 { 1106 int i; 1107 1108 for (i = 0; i < MTK_MAC_COUNT; i++) { 1109 if (!eth->netdev[i]) 1110 continue; 1111 if (netif_queue_stopped(eth->netdev[i])) 1112 return 1; 1113 } 1114 1115 return 0; 1116 } 1117 1118 static void mtk_wake_queue(struct mtk_eth *eth) 1119 { 1120 int i; 1121 1122 for (i = 0; i < MTK_MAC_COUNT; i++) { 1123 if (!eth->netdev[i]) 1124 continue; 1125 netif_wake_queue(eth->netdev[i]); 1126 } 1127 } 1128 1129 static void mtk_stop_queue(struct mtk_eth *eth) 1130 { 1131 int i; 1132 1133 for (i = 0; i < MTK_MAC_COUNT; i++) { 1134 if (!eth->netdev[i]) 1135 continue; 1136 netif_stop_queue(eth->netdev[i]); 1137 } 1138 } 1139 1140 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1141 { 1142 struct mtk_mac *mac = netdev_priv(dev); 1143 struct mtk_eth *eth = mac->hw; 1144 struct mtk_tx_ring *ring = ð->tx_ring; 1145 struct net_device_stats *stats = &dev->stats; 1146 bool gso = false; 1147 int tx_num; 1148 1149 /* normally we can rely on the stack not calling this more than once, 1150 * however we have 2 queues running on the same ring so we need to lock 1151 * the ring access 1152 */ 1153 spin_lock(ð->page_lock); 1154 1155 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1156 goto drop; 1157 1158 tx_num = mtk_cal_txd_req(skb); 1159 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1160 mtk_stop_queue(eth); 1161 netif_err(eth, tx_queued, dev, 1162 "Tx Ring full when queue awake!\n"); 1163 spin_unlock(ð->page_lock); 1164 return NETDEV_TX_BUSY; 1165 } 1166 1167 /* TSO: fill MSS info in tcp checksum field */ 1168 if (skb_is_gso(skb)) { 1169 if (skb_cow_head(skb, 0)) { 1170 netif_warn(eth, tx_err, dev, 1171 "GSO expand head fail.\n"); 1172 goto drop; 1173 } 1174 1175 if (skb_shinfo(skb)->gso_type & 1176 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1177 gso = true; 1178 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1179 } 1180 } 1181 1182 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1183 goto drop; 1184 1185 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1186 mtk_stop_queue(eth); 1187 1188 spin_unlock(ð->page_lock); 1189 1190 return NETDEV_TX_OK; 1191 1192 drop: 1193 spin_unlock(ð->page_lock); 1194 stats->tx_dropped++; 1195 dev_kfree_skb_any(skb); 1196 return NETDEV_TX_OK; 1197 } 1198 1199 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1200 { 1201 int i; 1202 struct mtk_rx_ring *ring; 1203 int idx; 1204 1205 if (!eth->hwlro) 1206 return ð->rx_ring[0]; 1207 1208 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1209 ring = ð->rx_ring[i]; 1210 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1211 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 1212 ring->calc_idx_update = true; 1213 return ring; 1214 } 1215 } 1216 1217 return NULL; 1218 } 1219 1220 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1221 { 1222 struct mtk_rx_ring *ring; 1223 int i; 1224 1225 if (!eth->hwlro) { 1226 ring = ð->rx_ring[0]; 1227 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1228 } else { 1229 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1230 ring = ð->rx_ring[i]; 1231 if (ring->calc_idx_update) { 1232 ring->calc_idx_update = false; 1233 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1234 } 1235 } 1236 } 1237 } 1238 1239 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1240 struct mtk_eth *eth) 1241 { 1242 struct mtk_rx_ring *ring; 1243 int idx; 1244 struct sk_buff *skb; 1245 u8 *data, *new_data; 1246 struct mtk_rx_dma *rxd, trxd; 1247 int done = 0; 1248 1249 while (done < budget) { 1250 struct net_device *netdev; 1251 unsigned int pktlen; 1252 dma_addr_t dma_addr; 1253 int mac; 1254 1255 ring = mtk_get_rx_ring(eth); 1256 if (unlikely(!ring)) 1257 goto rx_done; 1258 1259 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1260 rxd = &ring->dma[idx]; 1261 data = ring->data[idx]; 1262 1263 mtk_rx_get_desc(&trxd, rxd); 1264 if (!(trxd.rxd2 & RX_DMA_DONE)) 1265 break; 1266 1267 /* find out which mac the packet come from. values start at 1 */ 1268 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) || 1269 (trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 1270 mac = 0; 1271 else 1272 mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 1273 RX_DMA_FPORT_MASK) - 1; 1274 1275 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1276 !eth->netdev[mac])) 1277 goto release_desc; 1278 1279 netdev = eth->netdev[mac]; 1280 1281 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1282 goto release_desc; 1283 1284 /* alloc new buffer */ 1285 new_data = napi_alloc_frag(ring->frag_size); 1286 if (unlikely(!new_data)) { 1287 netdev->stats.rx_dropped++; 1288 goto release_desc; 1289 } 1290 dma_addr = dma_map_single(eth->dev, 1291 new_data + NET_SKB_PAD + 1292 eth->ip_align, 1293 ring->buf_size, 1294 DMA_FROM_DEVICE); 1295 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 1296 skb_free_frag(new_data); 1297 netdev->stats.rx_dropped++; 1298 goto release_desc; 1299 } 1300 1301 /* receive data */ 1302 skb = build_skb(data, ring->frag_size); 1303 if (unlikely(!skb)) { 1304 skb_free_frag(new_data); 1305 netdev->stats.rx_dropped++; 1306 goto release_desc; 1307 } 1308 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1309 1310 dma_unmap_single(eth->dev, trxd.rxd1, 1311 ring->buf_size, DMA_FROM_DEVICE); 1312 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1313 skb->dev = netdev; 1314 skb_put(skb, pktlen); 1315 if (trxd.rxd4 & eth->rx_dma_l4_valid) 1316 skb->ip_summed = CHECKSUM_UNNECESSARY; 1317 else 1318 skb_checksum_none_assert(skb); 1319 skb->protocol = eth_type_trans(skb, netdev); 1320 1321 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1322 RX_DMA_VID(trxd.rxd3)) 1323 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1324 RX_DMA_VID(trxd.rxd3)); 1325 skb_record_rx_queue(skb, 0); 1326 napi_gro_receive(napi, skb); 1327 1328 ring->data[idx] = new_data; 1329 rxd->rxd1 = (unsigned int)dma_addr; 1330 1331 release_desc: 1332 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1333 rxd->rxd2 = RX_DMA_LSO; 1334 else 1335 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1336 1337 ring->calc_idx = idx; 1338 1339 done++; 1340 } 1341 1342 rx_done: 1343 if (done) { 1344 /* make sure that all changes to the dma ring are flushed before 1345 * we continue 1346 */ 1347 wmb(); 1348 mtk_update_rx_cpu_idx(eth); 1349 } 1350 1351 return done; 1352 } 1353 1354 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 1355 unsigned int *done, unsigned int *bytes) 1356 { 1357 struct mtk_tx_ring *ring = ð->tx_ring; 1358 struct mtk_tx_dma *desc; 1359 struct sk_buff *skb; 1360 struct mtk_tx_buf *tx_buf; 1361 u32 cpu, dma; 1362 1363 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1364 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1365 1366 desc = mtk_qdma_phys_to_virt(ring, cpu); 1367 1368 while ((cpu != dma) && budget) { 1369 u32 next_cpu = desc->txd2; 1370 int mac = 0; 1371 1372 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1373 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1374 break; 1375 1376 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1377 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1378 mac = 1; 1379 1380 skb = tx_buf->skb; 1381 if (!skb) 1382 break; 1383 1384 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1385 bytes[mac] += skb->len; 1386 done[mac]++; 1387 budget--; 1388 } 1389 mtk_tx_unmap(eth, tx_buf); 1390 1391 ring->last_free = desc; 1392 atomic_inc(&ring->free_count); 1393 1394 cpu = next_cpu; 1395 } 1396 1397 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1398 1399 return budget; 1400 } 1401 1402 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 1403 unsigned int *done, unsigned int *bytes) 1404 { 1405 struct mtk_tx_ring *ring = ð->tx_ring; 1406 struct mtk_tx_dma *desc; 1407 struct sk_buff *skb; 1408 struct mtk_tx_buf *tx_buf; 1409 u32 cpu, dma; 1410 1411 cpu = ring->cpu_idx; 1412 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 1413 1414 while ((cpu != dma) && budget) { 1415 tx_buf = &ring->buf[cpu]; 1416 skb = tx_buf->skb; 1417 if (!skb) 1418 break; 1419 1420 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1421 bytes[0] += skb->len; 1422 done[0]++; 1423 budget--; 1424 } 1425 1426 mtk_tx_unmap(eth, tx_buf); 1427 1428 desc = &ring->dma[cpu]; 1429 ring->last_free = desc; 1430 atomic_inc(&ring->free_count); 1431 1432 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 1433 } 1434 1435 ring->cpu_idx = cpu; 1436 1437 return budget; 1438 } 1439 1440 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1441 { 1442 struct mtk_tx_ring *ring = ð->tx_ring; 1443 unsigned int done[MTK_MAX_DEVS]; 1444 unsigned int bytes[MTK_MAX_DEVS]; 1445 int total = 0, i; 1446 1447 memset(done, 0, sizeof(done)); 1448 memset(bytes, 0, sizeof(bytes)); 1449 1450 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1451 budget = mtk_poll_tx_qdma(eth, budget, done, bytes); 1452 else 1453 budget = mtk_poll_tx_pdma(eth, budget, done, bytes); 1454 1455 for (i = 0; i < MTK_MAC_COUNT; i++) { 1456 if (!eth->netdev[i] || !done[i]) 1457 continue; 1458 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1459 total += done[i]; 1460 } 1461 1462 if (mtk_queue_stopped(eth) && 1463 (atomic_read(&ring->free_count) > ring->thresh)) 1464 mtk_wake_queue(eth); 1465 1466 return total; 1467 } 1468 1469 static void mtk_handle_status_irq(struct mtk_eth *eth) 1470 { 1471 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1472 1473 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1474 mtk_stats_update(eth); 1475 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1476 MTK_INT_STATUS2); 1477 } 1478 } 1479 1480 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1481 { 1482 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1483 u32 status, mask; 1484 int tx_done = 0; 1485 1486 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1487 mtk_handle_status_irq(eth); 1488 mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg); 1489 tx_done = mtk_poll_tx(eth, budget); 1490 1491 if (unlikely(netif_msg_intr(eth))) { 1492 status = mtk_r32(eth, eth->tx_int_status_reg); 1493 mask = mtk_r32(eth, eth->tx_int_mask_reg); 1494 dev_info(eth->dev, 1495 "done tx %d, intr 0x%08x/0x%x\n", 1496 tx_done, status, mask); 1497 } 1498 1499 if (tx_done == budget) 1500 return budget; 1501 1502 status = mtk_r32(eth, eth->tx_int_status_reg); 1503 if (status & MTK_TX_DONE_INT) 1504 return budget; 1505 1506 napi_complete(napi); 1507 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1508 1509 return tx_done; 1510 } 1511 1512 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1513 { 1514 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1515 u32 status, mask; 1516 int rx_done = 0; 1517 int remain_budget = budget; 1518 1519 mtk_handle_status_irq(eth); 1520 1521 poll_again: 1522 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1523 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1524 1525 if (unlikely(netif_msg_intr(eth))) { 1526 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1527 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1528 dev_info(eth->dev, 1529 "done rx %d, intr 0x%08x/0x%x\n", 1530 rx_done, status, mask); 1531 } 1532 if (rx_done == remain_budget) 1533 return budget; 1534 1535 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1536 if (status & MTK_RX_DONE_INT) { 1537 remain_budget -= rx_done; 1538 goto poll_again; 1539 } 1540 napi_complete(napi); 1541 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1542 1543 return rx_done + budget - remain_budget; 1544 } 1545 1546 static int mtk_tx_alloc(struct mtk_eth *eth) 1547 { 1548 struct mtk_tx_ring *ring = ð->tx_ring; 1549 int i, sz = sizeof(*ring->dma); 1550 1551 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1552 GFP_KERNEL); 1553 if (!ring->buf) 1554 goto no_tx_mem; 1555 1556 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1557 &ring->phys, GFP_ATOMIC); 1558 if (!ring->dma) 1559 goto no_tx_mem; 1560 1561 for (i = 0; i < MTK_DMA_SIZE; i++) { 1562 int next = (i + 1) % MTK_DMA_SIZE; 1563 u32 next_ptr = ring->phys + next * sz; 1564 1565 ring->dma[i].txd2 = next_ptr; 1566 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1567 } 1568 1569 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 1570 * only as the framework. The real HW descriptors are the PDMA 1571 * descriptors in ring->dma_pdma. 1572 */ 1573 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1574 ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1575 &ring->phys_pdma, 1576 GFP_ATOMIC); 1577 if (!ring->dma_pdma) 1578 goto no_tx_mem; 1579 1580 for (i = 0; i < MTK_DMA_SIZE; i++) { 1581 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 1582 ring->dma_pdma[i].txd4 = 0; 1583 } 1584 } 1585 1586 ring->dma_size = MTK_DMA_SIZE; 1587 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1588 ring->next_free = &ring->dma[0]; 1589 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1590 ring->thresh = MAX_SKB_FRAGS; 1591 1592 /* make sure that all changes to the dma ring are flushed before we 1593 * continue 1594 */ 1595 wmb(); 1596 1597 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1598 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1599 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1600 mtk_w32(eth, 1601 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1602 MTK_QTX_CRX_PTR); 1603 mtk_w32(eth, 1604 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1605 MTK_QTX_DRX_PTR); 1606 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, 1607 MTK_QTX_CFG(0)); 1608 } else { 1609 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 1610 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); 1611 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 1612 mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX); 1613 } 1614 1615 return 0; 1616 1617 no_tx_mem: 1618 return -ENOMEM; 1619 } 1620 1621 static void mtk_tx_clean(struct mtk_eth *eth) 1622 { 1623 struct mtk_tx_ring *ring = ð->tx_ring; 1624 int i; 1625 1626 if (ring->buf) { 1627 for (i = 0; i < MTK_DMA_SIZE; i++) 1628 mtk_tx_unmap(eth, &ring->buf[i]); 1629 kfree(ring->buf); 1630 ring->buf = NULL; 1631 } 1632 1633 if (ring->dma) { 1634 dma_free_coherent(eth->dev, 1635 MTK_DMA_SIZE * sizeof(*ring->dma), 1636 ring->dma, 1637 ring->phys); 1638 ring->dma = NULL; 1639 } 1640 1641 if (ring->dma_pdma) { 1642 dma_free_coherent(eth->dev, 1643 MTK_DMA_SIZE * sizeof(*ring->dma_pdma), 1644 ring->dma_pdma, 1645 ring->phys_pdma); 1646 ring->dma_pdma = NULL; 1647 } 1648 } 1649 1650 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1651 { 1652 struct mtk_rx_ring *ring; 1653 int rx_data_len, rx_dma_size; 1654 int i; 1655 u32 offset = 0; 1656 1657 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1658 if (ring_no) 1659 return -EINVAL; 1660 ring = ð->rx_ring_qdma; 1661 offset = 0x1000; 1662 } else { 1663 ring = ð->rx_ring[ring_no]; 1664 } 1665 1666 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1667 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1668 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1669 } else { 1670 rx_data_len = ETH_DATA_LEN; 1671 rx_dma_size = MTK_DMA_SIZE; 1672 } 1673 1674 ring->frag_size = mtk_max_frag_size(rx_data_len); 1675 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1676 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1677 GFP_KERNEL); 1678 if (!ring->data) 1679 return -ENOMEM; 1680 1681 for (i = 0; i < rx_dma_size; i++) { 1682 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1683 if (!ring->data[i]) 1684 return -ENOMEM; 1685 } 1686 1687 ring->dma = dma_alloc_coherent(eth->dev, 1688 rx_dma_size * sizeof(*ring->dma), 1689 &ring->phys, GFP_ATOMIC); 1690 if (!ring->dma) 1691 return -ENOMEM; 1692 1693 for (i = 0; i < rx_dma_size; i++) { 1694 dma_addr_t dma_addr = dma_map_single(eth->dev, 1695 ring->data[i] + NET_SKB_PAD + eth->ip_align, 1696 ring->buf_size, 1697 DMA_FROM_DEVICE); 1698 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1699 return -ENOMEM; 1700 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1701 1702 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1703 ring->dma[i].rxd2 = RX_DMA_LSO; 1704 else 1705 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1706 } 1707 ring->dma_size = rx_dma_size; 1708 ring->calc_idx_update = false; 1709 ring->calc_idx = rx_dma_size - 1; 1710 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1711 /* make sure that all changes to the dma ring are flushed before we 1712 * continue 1713 */ 1714 wmb(); 1715 1716 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1717 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1718 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1719 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1720 1721 return 0; 1722 } 1723 1724 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1725 { 1726 int i; 1727 1728 if (ring->data && ring->dma) { 1729 for (i = 0; i < ring->dma_size; i++) { 1730 if (!ring->data[i]) 1731 continue; 1732 if (!ring->dma[i].rxd1) 1733 continue; 1734 dma_unmap_single(eth->dev, 1735 ring->dma[i].rxd1, 1736 ring->buf_size, 1737 DMA_FROM_DEVICE); 1738 skb_free_frag(ring->data[i]); 1739 } 1740 kfree(ring->data); 1741 ring->data = NULL; 1742 } 1743 1744 if (ring->dma) { 1745 dma_free_coherent(eth->dev, 1746 ring->dma_size * sizeof(*ring->dma), 1747 ring->dma, 1748 ring->phys); 1749 ring->dma = NULL; 1750 } 1751 } 1752 1753 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1754 { 1755 int i; 1756 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1757 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1758 1759 /* set LRO rings to auto-learn modes */ 1760 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1761 1762 /* validate LRO ring */ 1763 ring_ctrl_dw2 |= MTK_RING_VLD; 1764 1765 /* set AGE timer (unit: 20us) */ 1766 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1767 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1768 1769 /* set max AGG timer (unit: 20us) */ 1770 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1771 1772 /* set max LRO AGG count */ 1773 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1774 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1775 1776 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1777 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1778 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1779 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1780 } 1781 1782 /* IPv4 checksum update enable */ 1783 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1784 1785 /* switch priority comparison to packet count mode */ 1786 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1787 1788 /* bandwidth threshold setting */ 1789 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1790 1791 /* auto-learn score delta setting */ 1792 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1793 1794 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1795 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1796 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1797 1798 /* set HW LRO mode & the max aggregation count for rx packets */ 1799 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1800 1801 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1802 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1803 1804 /* enable HW LRO */ 1805 lro_ctrl_dw0 |= MTK_LRO_EN; 1806 1807 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1808 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1809 1810 return 0; 1811 } 1812 1813 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1814 { 1815 int i; 1816 u32 val; 1817 1818 /* relinquish lro rings, flush aggregated packets */ 1819 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1820 1821 /* wait for relinquishments done */ 1822 for (i = 0; i < 10; i++) { 1823 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1824 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1825 msleep(20); 1826 continue; 1827 } 1828 break; 1829 } 1830 1831 /* invalidate lro rings */ 1832 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1833 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1834 1835 /* disable HW LRO */ 1836 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1837 } 1838 1839 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1840 { 1841 u32 reg_val; 1842 1843 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1844 1845 /* invalidate the IP setting */ 1846 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1847 1848 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1849 1850 /* validate the IP setting */ 1851 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1852 } 1853 1854 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1855 { 1856 u32 reg_val; 1857 1858 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1859 1860 /* invalidate the IP setting */ 1861 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1862 1863 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1864 } 1865 1866 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1867 { 1868 int cnt = 0; 1869 int i; 1870 1871 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1872 if (mac->hwlro_ip[i]) 1873 cnt++; 1874 } 1875 1876 return cnt; 1877 } 1878 1879 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1880 struct ethtool_rxnfc *cmd) 1881 { 1882 struct ethtool_rx_flow_spec *fsp = 1883 (struct ethtool_rx_flow_spec *)&cmd->fs; 1884 struct mtk_mac *mac = netdev_priv(dev); 1885 struct mtk_eth *eth = mac->hw; 1886 int hwlro_idx; 1887 1888 if ((fsp->flow_type != TCP_V4_FLOW) || 1889 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1890 (fsp->location > 1)) 1891 return -EINVAL; 1892 1893 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1894 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1895 1896 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1897 1898 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1899 1900 return 0; 1901 } 1902 1903 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1904 struct ethtool_rxnfc *cmd) 1905 { 1906 struct ethtool_rx_flow_spec *fsp = 1907 (struct ethtool_rx_flow_spec *)&cmd->fs; 1908 struct mtk_mac *mac = netdev_priv(dev); 1909 struct mtk_eth *eth = mac->hw; 1910 int hwlro_idx; 1911 1912 if (fsp->location > 1) 1913 return -EINVAL; 1914 1915 mac->hwlro_ip[fsp->location] = 0; 1916 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1917 1918 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1919 1920 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1921 1922 return 0; 1923 } 1924 1925 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1926 { 1927 struct mtk_mac *mac = netdev_priv(dev); 1928 struct mtk_eth *eth = mac->hw; 1929 int i, hwlro_idx; 1930 1931 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1932 mac->hwlro_ip[i] = 0; 1933 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1934 1935 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1936 } 1937 1938 mac->hwlro_ip_cnt = 0; 1939 } 1940 1941 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1942 struct ethtool_rxnfc *cmd) 1943 { 1944 struct mtk_mac *mac = netdev_priv(dev); 1945 struct ethtool_rx_flow_spec *fsp = 1946 (struct ethtool_rx_flow_spec *)&cmd->fs; 1947 1948 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1949 fsp->flow_type = TCP_V4_FLOW; 1950 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1951 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1952 1953 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1954 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1955 fsp->h_u.tcp_ip4_spec.psrc = 0; 1956 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1957 fsp->h_u.tcp_ip4_spec.pdst = 0; 1958 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1959 fsp->h_u.tcp_ip4_spec.tos = 0; 1960 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1961 1962 return 0; 1963 } 1964 1965 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1966 struct ethtool_rxnfc *cmd, 1967 u32 *rule_locs) 1968 { 1969 struct mtk_mac *mac = netdev_priv(dev); 1970 int cnt = 0; 1971 int i; 1972 1973 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1974 if (mac->hwlro_ip[i]) { 1975 rule_locs[cnt] = i; 1976 cnt++; 1977 } 1978 } 1979 1980 cmd->rule_cnt = cnt; 1981 1982 return 0; 1983 } 1984 1985 static netdev_features_t mtk_fix_features(struct net_device *dev, 1986 netdev_features_t features) 1987 { 1988 if (!(features & NETIF_F_LRO)) { 1989 struct mtk_mac *mac = netdev_priv(dev); 1990 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1991 1992 if (ip_cnt) { 1993 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1994 1995 features |= NETIF_F_LRO; 1996 } 1997 } 1998 1999 return features; 2000 } 2001 2002 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2003 { 2004 int err = 0; 2005 2006 if (!((dev->features ^ features) & NETIF_F_LRO)) 2007 return 0; 2008 2009 if (!(features & NETIF_F_LRO)) 2010 mtk_hwlro_netdev_disable(dev); 2011 2012 return err; 2013 } 2014 2015 /* wait for DMA to finish whatever it is doing before we start using it again */ 2016 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2017 { 2018 unsigned long t_start = jiffies; 2019 2020 while (1) { 2021 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2022 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 2023 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 2024 return 0; 2025 } else { 2026 if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) & 2027 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 2028 return 0; 2029 } 2030 2031 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 2032 break; 2033 } 2034 2035 dev_err(eth->dev, "DMA init timeout\n"); 2036 return -1; 2037 } 2038 2039 static int mtk_dma_init(struct mtk_eth *eth) 2040 { 2041 int err; 2042 u32 i; 2043 2044 if (mtk_dma_busy_wait(eth)) 2045 return -EBUSY; 2046 2047 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2048 /* QDMA needs scratch memory for internal reordering of the 2049 * descriptors 2050 */ 2051 err = mtk_init_fq_dma(eth); 2052 if (err) 2053 return err; 2054 } 2055 2056 err = mtk_tx_alloc(eth); 2057 if (err) 2058 return err; 2059 2060 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2061 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2062 if (err) 2063 return err; 2064 } 2065 2066 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2067 if (err) 2068 return err; 2069 2070 if (eth->hwlro) { 2071 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2072 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2073 if (err) 2074 return err; 2075 } 2076 err = mtk_hwlro_rx_init(eth); 2077 if (err) 2078 return err; 2079 } 2080 2081 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2082 /* Enable random early drop and set drop threshold 2083 * automatically 2084 */ 2085 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2086 FC_THRES_MIN, MTK_QDMA_FC_THRES); 2087 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 2088 } 2089 2090 return 0; 2091 } 2092 2093 static void mtk_dma_free(struct mtk_eth *eth) 2094 { 2095 int i; 2096 2097 for (i = 0; i < MTK_MAC_COUNT; i++) 2098 if (eth->netdev[i]) 2099 netdev_reset_queue(eth->netdev[i]); 2100 if (eth->scratch_ring) { 2101 dma_free_coherent(eth->dev, 2102 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 2103 eth->scratch_ring, 2104 eth->phy_scratch_ring); 2105 eth->scratch_ring = NULL; 2106 eth->phy_scratch_ring = 0; 2107 } 2108 mtk_tx_clean(eth); 2109 mtk_rx_clean(eth, ð->rx_ring[0]); 2110 mtk_rx_clean(eth, ð->rx_ring_qdma); 2111 2112 if (eth->hwlro) { 2113 mtk_hwlro_rx_uninit(eth); 2114 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2115 mtk_rx_clean(eth, ð->rx_ring[i]); 2116 } 2117 2118 kfree(eth->scratch_head); 2119 } 2120 2121 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 2122 { 2123 struct mtk_mac *mac = netdev_priv(dev); 2124 struct mtk_eth *eth = mac->hw; 2125 2126 eth->netdev[mac->id]->stats.tx_errors++; 2127 netif_err(eth, tx_err, dev, 2128 "transmit timed out\n"); 2129 schedule_work(ð->pending_work); 2130 } 2131 2132 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 2133 { 2134 struct mtk_eth *eth = _eth; 2135 2136 if (likely(napi_schedule_prep(ð->rx_napi))) { 2137 __napi_schedule(ð->rx_napi); 2138 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2139 } 2140 2141 return IRQ_HANDLED; 2142 } 2143 2144 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 2145 { 2146 struct mtk_eth *eth = _eth; 2147 2148 if (likely(napi_schedule_prep(ð->tx_napi))) { 2149 __napi_schedule(ð->tx_napi); 2150 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2151 } 2152 2153 return IRQ_HANDLED; 2154 } 2155 2156 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 2157 { 2158 struct mtk_eth *eth = _eth; 2159 2160 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { 2161 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) 2162 mtk_handle_irq_rx(irq, _eth); 2163 } 2164 if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) { 2165 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) 2166 mtk_handle_irq_tx(irq, _eth); 2167 } 2168 2169 return IRQ_HANDLED; 2170 } 2171 2172 #ifdef CONFIG_NET_POLL_CONTROLLER 2173 static void mtk_poll_controller(struct net_device *dev) 2174 { 2175 struct mtk_mac *mac = netdev_priv(dev); 2176 struct mtk_eth *eth = mac->hw; 2177 2178 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2179 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2180 mtk_handle_irq_rx(eth->irq[2], dev); 2181 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2182 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2183 } 2184 #endif 2185 2186 static int mtk_start_dma(struct mtk_eth *eth) 2187 { 2188 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 2189 int err; 2190 2191 err = mtk_dma_init(eth); 2192 if (err) { 2193 mtk_dma_free(eth); 2194 return err; 2195 } 2196 2197 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2198 mtk_w32(eth, 2199 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 2200 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | 2201 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 2202 MTK_RX_BT_32DWORDS, 2203 MTK_QDMA_GLO_CFG); 2204 2205 mtk_w32(eth, 2206 MTK_RX_DMA_EN | rx_2b_offset | 2207 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 2208 MTK_PDMA_GLO_CFG); 2209 } else { 2210 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2211 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 2212 MTK_PDMA_GLO_CFG); 2213 } 2214 2215 return 0; 2216 } 2217 2218 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 2219 { 2220 int i; 2221 2222 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2223 return; 2224 2225 for (i = 0; i < MTK_MAC_COUNT; i++) { 2226 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 2227 2228 /* default setup the forward port to send frame to PDMA */ 2229 val &= ~0xffff; 2230 2231 /* Enable RX checksum */ 2232 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2233 2234 val |= config; 2235 2236 if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0])) 2237 val |= MTK_GDMA_SPECIAL_TAG; 2238 2239 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2240 } 2241 /* Reset and enable PSE */ 2242 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 2243 mtk_w32(eth, 0, MTK_RST_GL); 2244 } 2245 2246 static int mtk_open(struct net_device *dev) 2247 { 2248 struct mtk_mac *mac = netdev_priv(dev); 2249 struct mtk_eth *eth = mac->hw; 2250 int err; 2251 2252 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 2253 if (err) { 2254 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 2255 err); 2256 return err; 2257 } 2258 2259 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 2260 if (!refcount_read(ð->dma_refcnt)) { 2261 u32 gdm_config = MTK_GDMA_TO_PDMA; 2262 int err; 2263 2264 err = mtk_start_dma(eth); 2265 if (err) 2266 return err; 2267 2268 if (eth->soc->offload_version && mtk_ppe_start(ð->ppe) == 0) 2269 gdm_config = MTK_GDMA_TO_PPE; 2270 2271 mtk_gdm_config(eth, gdm_config); 2272 2273 napi_enable(ð->tx_napi); 2274 napi_enable(ð->rx_napi); 2275 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2276 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2277 refcount_set(ð->dma_refcnt, 1); 2278 } 2279 else 2280 refcount_inc(ð->dma_refcnt); 2281 2282 phylink_start(mac->phylink); 2283 netif_start_queue(dev); 2284 return 0; 2285 } 2286 2287 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 2288 { 2289 u32 val; 2290 int i; 2291 2292 /* stop the dma engine */ 2293 spin_lock_bh(ð->page_lock); 2294 val = mtk_r32(eth, glo_cfg); 2295 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 2296 glo_cfg); 2297 spin_unlock_bh(ð->page_lock); 2298 2299 /* wait for dma stop */ 2300 for (i = 0; i < 10; i++) { 2301 val = mtk_r32(eth, glo_cfg); 2302 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 2303 msleep(20); 2304 continue; 2305 } 2306 break; 2307 } 2308 } 2309 2310 static int mtk_stop(struct net_device *dev) 2311 { 2312 struct mtk_mac *mac = netdev_priv(dev); 2313 struct mtk_eth *eth = mac->hw; 2314 2315 phylink_stop(mac->phylink); 2316 2317 netif_tx_disable(dev); 2318 2319 phylink_disconnect_phy(mac->phylink); 2320 2321 /* only shutdown DMA if this is the last user */ 2322 if (!refcount_dec_and_test(ð->dma_refcnt)) 2323 return 0; 2324 2325 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 2326 2327 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2328 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2329 napi_disable(ð->tx_napi); 2330 napi_disable(ð->rx_napi); 2331 2332 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2333 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 2334 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 2335 2336 mtk_dma_free(eth); 2337 2338 if (eth->soc->offload_version) 2339 mtk_ppe_stop(ð->ppe); 2340 2341 return 0; 2342 } 2343 2344 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 2345 { 2346 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2347 reset_bits, 2348 reset_bits); 2349 2350 usleep_range(1000, 1100); 2351 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2352 reset_bits, 2353 ~reset_bits); 2354 mdelay(10); 2355 } 2356 2357 static void mtk_clk_disable(struct mtk_eth *eth) 2358 { 2359 int clk; 2360 2361 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 2362 clk_disable_unprepare(eth->clks[clk]); 2363 } 2364 2365 static int mtk_clk_enable(struct mtk_eth *eth) 2366 { 2367 int clk, ret; 2368 2369 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 2370 ret = clk_prepare_enable(eth->clks[clk]); 2371 if (ret) 2372 goto err_disable_clks; 2373 } 2374 2375 return 0; 2376 2377 err_disable_clks: 2378 while (--clk >= 0) 2379 clk_disable_unprepare(eth->clks[clk]); 2380 2381 return ret; 2382 } 2383 2384 static int mtk_hw_init(struct mtk_eth *eth) 2385 { 2386 int i, val, ret; 2387 2388 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 2389 return 0; 2390 2391 pm_runtime_enable(eth->dev); 2392 pm_runtime_get_sync(eth->dev); 2393 2394 ret = mtk_clk_enable(eth); 2395 if (ret) 2396 goto err_disable_pm; 2397 2398 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2399 ret = device_reset(eth->dev); 2400 if (ret) { 2401 dev_err(eth->dev, "MAC reset failed!\n"); 2402 goto err_disable_pm; 2403 } 2404 2405 /* enable interrupt delay for RX */ 2406 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 2407 2408 /* disable delay and normal interrupt */ 2409 mtk_tx_irq_disable(eth, ~0); 2410 mtk_rx_irq_disable(eth, ~0); 2411 2412 return 0; 2413 } 2414 2415 /* Non-MT7628 handling... */ 2416 ethsys_reset(eth, RSTCTRL_FE); 2417 ethsys_reset(eth, RSTCTRL_PPE); 2418 2419 if (eth->pctl) { 2420 /* Set GE2 driving and slew rate */ 2421 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 2422 2423 /* set GE2 TDSEL */ 2424 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 2425 2426 /* set GE2 TUNE */ 2427 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 2428 } 2429 2430 /* Set linkdown as the default for each GMAC. Its own MCR would be set 2431 * up with the more appropriate value when mtk_mac_config call is being 2432 * invoked. 2433 */ 2434 for (i = 0; i < MTK_MAC_COUNT; i++) 2435 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 2436 2437 /* Indicates CDM to parse the MTK special tag from CPU 2438 * which also is working out for untag packets. 2439 */ 2440 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 2441 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 2442 2443 /* Enable RX VLan Offloading */ 2444 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 2445 2446 /* enable interrupt delay for RX */ 2447 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 2448 2449 /* disable delay and normal interrupt */ 2450 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 2451 mtk_tx_irq_disable(eth, ~0); 2452 mtk_rx_irq_disable(eth, ~0); 2453 2454 /* FE int grouping */ 2455 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 2456 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 2457 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 2458 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 2459 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 2460 2461 return 0; 2462 2463 err_disable_pm: 2464 pm_runtime_put_sync(eth->dev); 2465 pm_runtime_disable(eth->dev); 2466 2467 return ret; 2468 } 2469 2470 static int mtk_hw_deinit(struct mtk_eth *eth) 2471 { 2472 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2473 return 0; 2474 2475 mtk_clk_disable(eth); 2476 2477 pm_runtime_put_sync(eth->dev); 2478 pm_runtime_disable(eth->dev); 2479 2480 return 0; 2481 } 2482 2483 static int __init mtk_init(struct net_device *dev) 2484 { 2485 struct mtk_mac *mac = netdev_priv(dev); 2486 struct mtk_eth *eth = mac->hw; 2487 const char *mac_addr; 2488 2489 mac_addr = of_get_mac_address(mac->of_node); 2490 if (!IS_ERR(mac_addr)) 2491 ether_addr_copy(dev->dev_addr, mac_addr); 2492 2493 /* If the mac address is invalid, use random mac address */ 2494 if (!is_valid_ether_addr(dev->dev_addr)) { 2495 eth_hw_addr_random(dev); 2496 dev_err(eth->dev, "generated random MAC address %pM\n", 2497 dev->dev_addr); 2498 } 2499 2500 return 0; 2501 } 2502 2503 static void mtk_uninit(struct net_device *dev) 2504 { 2505 struct mtk_mac *mac = netdev_priv(dev); 2506 struct mtk_eth *eth = mac->hw; 2507 2508 phylink_disconnect_phy(mac->phylink); 2509 mtk_tx_irq_disable(eth, ~0); 2510 mtk_rx_irq_disable(eth, ~0); 2511 } 2512 2513 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 2514 { 2515 int length = new_mtu + MTK_RX_ETH_HLEN; 2516 struct mtk_mac *mac = netdev_priv(dev); 2517 struct mtk_eth *eth = mac->hw; 2518 u32 mcr_cur, mcr_new; 2519 2520 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2521 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 2522 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 2523 2524 if (length <= 1518) 2525 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 2526 else if (length <= 1536) 2527 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 2528 else if (length <= 1552) 2529 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 2530 else 2531 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 2532 2533 if (mcr_new != mcr_cur) 2534 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 2535 } 2536 2537 dev->mtu = new_mtu; 2538 2539 return 0; 2540 } 2541 2542 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2543 { 2544 struct mtk_mac *mac = netdev_priv(dev); 2545 2546 switch (cmd) { 2547 case SIOCGMIIPHY: 2548 case SIOCGMIIREG: 2549 case SIOCSMIIREG: 2550 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 2551 default: 2552 break; 2553 } 2554 2555 return -EOPNOTSUPP; 2556 } 2557 2558 static void mtk_pending_work(struct work_struct *work) 2559 { 2560 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2561 int err, i; 2562 unsigned long restart = 0; 2563 2564 rtnl_lock(); 2565 2566 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2567 2568 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2569 cpu_relax(); 2570 2571 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2572 /* stop all devices to make sure that dma is properly shut down */ 2573 for (i = 0; i < MTK_MAC_COUNT; i++) { 2574 if (!eth->netdev[i]) 2575 continue; 2576 mtk_stop(eth->netdev[i]); 2577 __set_bit(i, &restart); 2578 } 2579 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2580 2581 /* restart underlying hardware such as power, clock, pin mux 2582 * and the connected phy 2583 */ 2584 mtk_hw_deinit(eth); 2585 2586 if (eth->dev->pins) 2587 pinctrl_select_state(eth->dev->pins->p, 2588 eth->dev->pins->default_state); 2589 mtk_hw_init(eth); 2590 2591 /* restart DMA and enable IRQs */ 2592 for (i = 0; i < MTK_MAC_COUNT; i++) { 2593 if (!test_bit(i, &restart)) 2594 continue; 2595 err = mtk_open(eth->netdev[i]); 2596 if (err) { 2597 netif_alert(eth, ifup, eth->netdev[i], 2598 "Driver up/down cycle failed, closing device.\n"); 2599 dev_close(eth->netdev[i]); 2600 } 2601 } 2602 2603 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2604 2605 clear_bit_unlock(MTK_RESETTING, ð->state); 2606 2607 rtnl_unlock(); 2608 } 2609 2610 static int mtk_free_dev(struct mtk_eth *eth) 2611 { 2612 int i; 2613 2614 for (i = 0; i < MTK_MAC_COUNT; i++) { 2615 if (!eth->netdev[i]) 2616 continue; 2617 free_netdev(eth->netdev[i]); 2618 } 2619 2620 return 0; 2621 } 2622 2623 static int mtk_unreg_dev(struct mtk_eth *eth) 2624 { 2625 int i; 2626 2627 for (i = 0; i < MTK_MAC_COUNT; i++) { 2628 if (!eth->netdev[i]) 2629 continue; 2630 unregister_netdev(eth->netdev[i]); 2631 } 2632 2633 return 0; 2634 } 2635 2636 static int mtk_cleanup(struct mtk_eth *eth) 2637 { 2638 mtk_unreg_dev(eth); 2639 mtk_free_dev(eth); 2640 cancel_work_sync(ð->pending_work); 2641 2642 return 0; 2643 } 2644 2645 static int mtk_get_link_ksettings(struct net_device *ndev, 2646 struct ethtool_link_ksettings *cmd) 2647 { 2648 struct mtk_mac *mac = netdev_priv(ndev); 2649 2650 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2651 return -EBUSY; 2652 2653 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 2654 } 2655 2656 static int mtk_set_link_ksettings(struct net_device *ndev, 2657 const struct ethtool_link_ksettings *cmd) 2658 { 2659 struct mtk_mac *mac = netdev_priv(ndev); 2660 2661 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2662 return -EBUSY; 2663 2664 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 2665 } 2666 2667 static void mtk_get_drvinfo(struct net_device *dev, 2668 struct ethtool_drvinfo *info) 2669 { 2670 struct mtk_mac *mac = netdev_priv(dev); 2671 2672 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2673 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2674 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2675 } 2676 2677 static u32 mtk_get_msglevel(struct net_device *dev) 2678 { 2679 struct mtk_mac *mac = netdev_priv(dev); 2680 2681 return mac->hw->msg_enable; 2682 } 2683 2684 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2685 { 2686 struct mtk_mac *mac = netdev_priv(dev); 2687 2688 mac->hw->msg_enable = value; 2689 } 2690 2691 static int mtk_nway_reset(struct net_device *dev) 2692 { 2693 struct mtk_mac *mac = netdev_priv(dev); 2694 2695 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2696 return -EBUSY; 2697 2698 if (!mac->phylink) 2699 return -ENOTSUPP; 2700 2701 return phylink_ethtool_nway_reset(mac->phylink); 2702 } 2703 2704 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2705 { 2706 int i; 2707 2708 switch (stringset) { 2709 case ETH_SS_STATS: 2710 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2711 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2712 data += ETH_GSTRING_LEN; 2713 } 2714 break; 2715 } 2716 } 2717 2718 static int mtk_get_sset_count(struct net_device *dev, int sset) 2719 { 2720 switch (sset) { 2721 case ETH_SS_STATS: 2722 return ARRAY_SIZE(mtk_ethtool_stats); 2723 default: 2724 return -EOPNOTSUPP; 2725 } 2726 } 2727 2728 static void mtk_get_ethtool_stats(struct net_device *dev, 2729 struct ethtool_stats *stats, u64 *data) 2730 { 2731 struct mtk_mac *mac = netdev_priv(dev); 2732 struct mtk_hw_stats *hwstats = mac->hw_stats; 2733 u64 *data_src, *data_dst; 2734 unsigned int start; 2735 int i; 2736 2737 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2738 return; 2739 2740 if (netif_running(dev) && netif_device_present(dev)) { 2741 if (spin_trylock_bh(&hwstats->stats_lock)) { 2742 mtk_stats_update_mac(mac); 2743 spin_unlock_bh(&hwstats->stats_lock); 2744 } 2745 } 2746 2747 data_src = (u64 *)hwstats; 2748 2749 do { 2750 data_dst = data; 2751 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2752 2753 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2754 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2755 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2756 } 2757 2758 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2759 u32 *rule_locs) 2760 { 2761 int ret = -EOPNOTSUPP; 2762 2763 switch (cmd->cmd) { 2764 case ETHTOOL_GRXRINGS: 2765 if (dev->hw_features & NETIF_F_LRO) { 2766 cmd->data = MTK_MAX_RX_RING_NUM; 2767 ret = 0; 2768 } 2769 break; 2770 case ETHTOOL_GRXCLSRLCNT: 2771 if (dev->hw_features & NETIF_F_LRO) { 2772 struct mtk_mac *mac = netdev_priv(dev); 2773 2774 cmd->rule_cnt = mac->hwlro_ip_cnt; 2775 ret = 0; 2776 } 2777 break; 2778 case ETHTOOL_GRXCLSRULE: 2779 if (dev->hw_features & NETIF_F_LRO) 2780 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2781 break; 2782 case ETHTOOL_GRXCLSRLALL: 2783 if (dev->hw_features & NETIF_F_LRO) 2784 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2785 rule_locs); 2786 break; 2787 default: 2788 break; 2789 } 2790 2791 return ret; 2792 } 2793 2794 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2795 { 2796 int ret = -EOPNOTSUPP; 2797 2798 switch (cmd->cmd) { 2799 case ETHTOOL_SRXCLSRLINS: 2800 if (dev->hw_features & NETIF_F_LRO) 2801 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2802 break; 2803 case ETHTOOL_SRXCLSRLDEL: 2804 if (dev->hw_features & NETIF_F_LRO) 2805 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2806 break; 2807 default: 2808 break; 2809 } 2810 2811 return ret; 2812 } 2813 2814 static const struct ethtool_ops mtk_ethtool_ops = { 2815 .get_link_ksettings = mtk_get_link_ksettings, 2816 .set_link_ksettings = mtk_set_link_ksettings, 2817 .get_drvinfo = mtk_get_drvinfo, 2818 .get_msglevel = mtk_get_msglevel, 2819 .set_msglevel = mtk_set_msglevel, 2820 .nway_reset = mtk_nway_reset, 2821 .get_link = ethtool_op_get_link, 2822 .get_strings = mtk_get_strings, 2823 .get_sset_count = mtk_get_sset_count, 2824 .get_ethtool_stats = mtk_get_ethtool_stats, 2825 .get_rxnfc = mtk_get_rxnfc, 2826 .set_rxnfc = mtk_set_rxnfc, 2827 }; 2828 2829 static const struct net_device_ops mtk_netdev_ops = { 2830 .ndo_init = mtk_init, 2831 .ndo_uninit = mtk_uninit, 2832 .ndo_open = mtk_open, 2833 .ndo_stop = mtk_stop, 2834 .ndo_start_xmit = mtk_start_xmit, 2835 .ndo_set_mac_address = mtk_set_mac_address, 2836 .ndo_validate_addr = eth_validate_addr, 2837 .ndo_do_ioctl = mtk_do_ioctl, 2838 .ndo_change_mtu = mtk_change_mtu, 2839 .ndo_tx_timeout = mtk_tx_timeout, 2840 .ndo_get_stats64 = mtk_get_stats64, 2841 .ndo_fix_features = mtk_fix_features, 2842 .ndo_set_features = mtk_set_features, 2843 #ifdef CONFIG_NET_POLL_CONTROLLER 2844 .ndo_poll_controller = mtk_poll_controller, 2845 #endif 2846 .ndo_setup_tc = mtk_eth_setup_tc, 2847 }; 2848 2849 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2850 { 2851 const __be32 *_id = of_get_property(np, "reg", NULL); 2852 phy_interface_t phy_mode; 2853 struct phylink *phylink; 2854 struct mtk_mac *mac; 2855 int id, err; 2856 2857 if (!_id) { 2858 dev_err(eth->dev, "missing mac id\n"); 2859 return -EINVAL; 2860 } 2861 2862 id = be32_to_cpup(_id); 2863 if (id >= MTK_MAC_COUNT) { 2864 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2865 return -EINVAL; 2866 } 2867 2868 if (eth->netdev[id]) { 2869 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2870 return -EINVAL; 2871 } 2872 2873 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2874 if (!eth->netdev[id]) { 2875 dev_err(eth->dev, "alloc_etherdev failed\n"); 2876 return -ENOMEM; 2877 } 2878 mac = netdev_priv(eth->netdev[id]); 2879 eth->mac[id] = mac; 2880 mac->id = id; 2881 mac->hw = eth; 2882 mac->of_node = np; 2883 2884 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2885 mac->hwlro_ip_cnt = 0; 2886 2887 mac->hw_stats = devm_kzalloc(eth->dev, 2888 sizeof(*mac->hw_stats), 2889 GFP_KERNEL); 2890 if (!mac->hw_stats) { 2891 dev_err(eth->dev, "failed to allocate counter memory\n"); 2892 err = -ENOMEM; 2893 goto free_netdev; 2894 } 2895 spin_lock_init(&mac->hw_stats->stats_lock); 2896 u64_stats_init(&mac->hw_stats->syncp); 2897 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2898 2899 /* phylink create */ 2900 err = of_get_phy_mode(np, &phy_mode); 2901 if (err) { 2902 dev_err(eth->dev, "incorrect phy-mode\n"); 2903 goto free_netdev; 2904 } 2905 2906 /* mac config is not set */ 2907 mac->interface = PHY_INTERFACE_MODE_NA; 2908 mac->mode = MLO_AN_PHY; 2909 mac->speed = SPEED_UNKNOWN; 2910 2911 mac->phylink_config.dev = ð->netdev[id]->dev; 2912 mac->phylink_config.type = PHYLINK_NETDEV; 2913 2914 phylink = phylink_create(&mac->phylink_config, 2915 of_fwnode_handle(mac->of_node), 2916 phy_mode, &mtk_phylink_ops); 2917 if (IS_ERR(phylink)) { 2918 err = PTR_ERR(phylink); 2919 goto free_netdev; 2920 } 2921 2922 mac->phylink = phylink; 2923 2924 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2925 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2926 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2927 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2928 2929 eth->netdev[id]->hw_features = eth->soc->hw_features; 2930 if (eth->hwlro) 2931 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2932 2933 eth->netdev[id]->vlan_features = eth->soc->hw_features & 2934 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2935 eth->netdev[id]->features |= eth->soc->hw_features; 2936 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2937 2938 eth->netdev[id]->irq = eth->irq[0]; 2939 eth->netdev[id]->dev.of_node = np; 2940 2941 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2942 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 2943 else 2944 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 2945 2946 return 0; 2947 2948 free_netdev: 2949 free_netdev(eth->netdev[id]); 2950 return err; 2951 } 2952 2953 static int mtk_probe(struct platform_device *pdev) 2954 { 2955 struct device_node *mac_np; 2956 struct mtk_eth *eth; 2957 int err, i; 2958 2959 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2960 if (!eth) 2961 return -ENOMEM; 2962 2963 eth->soc = of_device_get_match_data(&pdev->dev); 2964 2965 eth->dev = &pdev->dev; 2966 eth->base = devm_platform_ioremap_resource(pdev, 0); 2967 if (IS_ERR(eth->base)) 2968 return PTR_ERR(eth->base); 2969 2970 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2971 eth->tx_int_mask_reg = MTK_QDMA_INT_MASK; 2972 eth->tx_int_status_reg = MTK_QDMA_INT_STATUS; 2973 } else { 2974 eth->tx_int_mask_reg = MTK_PDMA_INT_MASK; 2975 eth->tx_int_status_reg = MTK_PDMA_INT_STATUS; 2976 } 2977 2978 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2979 eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA; 2980 eth->ip_align = NET_IP_ALIGN; 2981 } else { 2982 eth->rx_dma_l4_valid = RX_DMA_L4_VALID; 2983 } 2984 2985 spin_lock_init(ð->page_lock); 2986 spin_lock_init(ð->tx_irq_lock); 2987 spin_lock_init(ð->rx_irq_lock); 2988 2989 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2990 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2991 "mediatek,ethsys"); 2992 if (IS_ERR(eth->ethsys)) { 2993 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2994 return PTR_ERR(eth->ethsys); 2995 } 2996 } 2997 2998 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 2999 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3000 "mediatek,infracfg"); 3001 if (IS_ERR(eth->infra)) { 3002 dev_err(&pdev->dev, "no infracfg regmap found\n"); 3003 return PTR_ERR(eth->infra); 3004 } 3005 } 3006 3007 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 3008 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 3009 GFP_KERNEL); 3010 if (!eth->sgmii) 3011 return -ENOMEM; 3012 3013 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 3014 eth->soc->ana_rgc3); 3015 3016 if (err) 3017 return err; 3018 } 3019 3020 if (eth->soc->required_pctl) { 3021 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3022 "mediatek,pctl"); 3023 if (IS_ERR(eth->pctl)) { 3024 dev_err(&pdev->dev, "no pctl regmap found\n"); 3025 return PTR_ERR(eth->pctl); 3026 } 3027 } 3028 3029 for (i = 0; i < 3; i++) { 3030 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 3031 eth->irq[i] = eth->irq[0]; 3032 else 3033 eth->irq[i] = platform_get_irq(pdev, i); 3034 if (eth->irq[i] < 0) { 3035 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 3036 return -ENXIO; 3037 } 3038 } 3039 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 3040 eth->clks[i] = devm_clk_get(eth->dev, 3041 mtk_clks_source_name[i]); 3042 if (IS_ERR(eth->clks[i])) { 3043 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 3044 return -EPROBE_DEFER; 3045 if (eth->soc->required_clks & BIT(i)) { 3046 dev_err(&pdev->dev, "clock %s not found\n", 3047 mtk_clks_source_name[i]); 3048 return -EINVAL; 3049 } 3050 eth->clks[i] = NULL; 3051 } 3052 } 3053 3054 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 3055 INIT_WORK(ð->pending_work, mtk_pending_work); 3056 3057 err = mtk_hw_init(eth); 3058 if (err) 3059 return err; 3060 3061 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 3062 3063 for_each_child_of_node(pdev->dev.of_node, mac_np) { 3064 if (!of_device_is_compatible(mac_np, 3065 "mediatek,eth-mac")) 3066 continue; 3067 3068 if (!of_device_is_available(mac_np)) 3069 continue; 3070 3071 err = mtk_add_mac(eth, mac_np); 3072 if (err) { 3073 of_node_put(mac_np); 3074 goto err_deinit_hw; 3075 } 3076 } 3077 3078 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 3079 err = devm_request_irq(eth->dev, eth->irq[0], 3080 mtk_handle_irq, 0, 3081 dev_name(eth->dev), eth); 3082 } else { 3083 err = devm_request_irq(eth->dev, eth->irq[1], 3084 mtk_handle_irq_tx, 0, 3085 dev_name(eth->dev), eth); 3086 if (err) 3087 goto err_free_dev; 3088 3089 err = devm_request_irq(eth->dev, eth->irq[2], 3090 mtk_handle_irq_rx, 0, 3091 dev_name(eth->dev), eth); 3092 } 3093 if (err) 3094 goto err_free_dev; 3095 3096 /* No MT7628/88 support yet */ 3097 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3098 err = mtk_mdio_init(eth); 3099 if (err) 3100 goto err_free_dev; 3101 } 3102 3103 if (eth->soc->offload_version) { 3104 err = mtk_ppe_init(ð->ppe, eth->dev, 3105 eth->base + MTK_ETH_PPE_BASE, 2); 3106 if (err) 3107 goto err_free_dev; 3108 3109 err = mtk_eth_offload_init(eth); 3110 if (err) 3111 goto err_free_dev; 3112 } 3113 3114 for (i = 0; i < MTK_MAX_DEVS; i++) { 3115 if (!eth->netdev[i]) 3116 continue; 3117 3118 err = register_netdev(eth->netdev[i]); 3119 if (err) { 3120 dev_err(eth->dev, "error bringing up device\n"); 3121 goto err_deinit_mdio; 3122 } else 3123 netif_info(eth, probe, eth->netdev[i], 3124 "mediatek frame engine at 0x%08lx, irq %d\n", 3125 eth->netdev[i]->base_addr, eth->irq[0]); 3126 } 3127 3128 /* we run 2 devices on the same DMA ring so we need a dummy device 3129 * for NAPI to work 3130 */ 3131 init_dummy_netdev(ð->dummy_dev); 3132 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 3133 MTK_NAPI_WEIGHT); 3134 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 3135 MTK_NAPI_WEIGHT); 3136 3137 platform_set_drvdata(pdev, eth); 3138 3139 return 0; 3140 3141 err_deinit_mdio: 3142 mtk_mdio_cleanup(eth); 3143 err_free_dev: 3144 mtk_free_dev(eth); 3145 err_deinit_hw: 3146 mtk_hw_deinit(eth); 3147 3148 return err; 3149 } 3150 3151 static int mtk_remove(struct platform_device *pdev) 3152 { 3153 struct mtk_eth *eth = platform_get_drvdata(pdev); 3154 struct mtk_mac *mac; 3155 int i; 3156 3157 /* stop all devices to make sure that dma is properly shut down */ 3158 for (i = 0; i < MTK_MAC_COUNT; i++) { 3159 if (!eth->netdev[i]) 3160 continue; 3161 mtk_stop(eth->netdev[i]); 3162 mac = netdev_priv(eth->netdev[i]); 3163 phylink_disconnect_phy(mac->phylink); 3164 } 3165 3166 mtk_hw_deinit(eth); 3167 3168 netif_napi_del(ð->tx_napi); 3169 netif_napi_del(ð->rx_napi); 3170 mtk_cleanup(eth); 3171 mtk_mdio_cleanup(eth); 3172 3173 return 0; 3174 } 3175 3176 static const struct mtk_soc_data mt2701_data = { 3177 .caps = MT7623_CAPS | MTK_HWLRO, 3178 .hw_features = MTK_HW_FEATURES, 3179 .required_clks = MT7623_CLKS_BITMAP, 3180 .required_pctl = true, 3181 }; 3182 3183 static const struct mtk_soc_data mt7621_data = { 3184 .caps = MT7621_CAPS, 3185 .hw_features = MTK_HW_FEATURES, 3186 .required_clks = MT7621_CLKS_BITMAP, 3187 .required_pctl = false, 3188 .offload_version = 2, 3189 }; 3190 3191 static const struct mtk_soc_data mt7622_data = { 3192 .ana_rgc3 = 0x2028, 3193 .caps = MT7622_CAPS | MTK_HWLRO, 3194 .hw_features = MTK_HW_FEATURES, 3195 .required_clks = MT7622_CLKS_BITMAP, 3196 .required_pctl = false, 3197 .offload_version = 2, 3198 }; 3199 3200 static const struct mtk_soc_data mt7623_data = { 3201 .caps = MT7623_CAPS | MTK_HWLRO, 3202 .hw_features = MTK_HW_FEATURES, 3203 .required_clks = MT7623_CLKS_BITMAP, 3204 .required_pctl = true, 3205 }; 3206 3207 static const struct mtk_soc_data mt7629_data = { 3208 .ana_rgc3 = 0x128, 3209 .caps = MT7629_CAPS | MTK_HWLRO, 3210 .hw_features = MTK_HW_FEATURES, 3211 .required_clks = MT7629_CLKS_BITMAP, 3212 .required_pctl = false, 3213 }; 3214 3215 static const struct mtk_soc_data rt5350_data = { 3216 .caps = MT7628_CAPS, 3217 .hw_features = MTK_HW_FEATURES_MT7628, 3218 .required_clks = MT7628_CLKS_BITMAP, 3219 .required_pctl = false, 3220 }; 3221 3222 const struct of_device_id of_mtk_match[] = { 3223 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 3224 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 3225 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 3226 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 3227 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 3228 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 3229 {}, 3230 }; 3231 MODULE_DEVICE_TABLE(of, of_mtk_match); 3232 3233 static struct platform_driver mtk_driver = { 3234 .probe = mtk_probe, 3235 .remove = mtk_remove, 3236 .driver = { 3237 .name = "mtk_soc_eth", 3238 .of_match_table = of_mtk_match, 3239 }, 3240 }; 3241 3242 module_platform_driver(mtk_driver); 3243 3244 MODULE_LICENSE("GPL"); 3245 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 3246 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 3247