1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #include <linux/of_device.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/regmap.h> 20 #include <linux/clk.h> 21 #include <linux/if_vlan.h> 22 #include <linux/reset.h> 23 #include <linux/tcp.h> 24 25 #include "mtk_eth_soc.h" 26 27 static int mtk_msg_level = -1; 28 module_param_named(msg_level, mtk_msg_level, int, 0); 29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 30 31 #define MTK_ETHTOOL_STAT(x) { #x, \ 32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 33 34 /* strings used by ethtool */ 35 static const struct mtk_ethtool_stats { 36 char str[ETH_GSTRING_LEN]; 37 u32 offset; 38 } mtk_ethtool_stats[] = { 39 MTK_ETHTOOL_STAT(tx_bytes), 40 MTK_ETHTOOL_STAT(tx_packets), 41 MTK_ETHTOOL_STAT(tx_skip), 42 MTK_ETHTOOL_STAT(tx_collisions), 43 MTK_ETHTOOL_STAT(rx_bytes), 44 MTK_ETHTOOL_STAT(rx_packets), 45 MTK_ETHTOOL_STAT(rx_overflow), 46 MTK_ETHTOOL_STAT(rx_fcs_errors), 47 MTK_ETHTOOL_STAT(rx_short_errors), 48 MTK_ETHTOOL_STAT(rx_long_errors), 49 MTK_ETHTOOL_STAT(rx_checksum_errors), 50 MTK_ETHTOOL_STAT(rx_flow_control_packets), 51 }; 52 53 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 54 { 55 __raw_writel(val, eth->base + reg); 56 } 57 58 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 59 { 60 return __raw_readl(eth->base + reg); 61 } 62 63 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 64 { 65 unsigned long t_start = jiffies; 66 67 while (1) { 68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 69 return 0; 70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 71 break; 72 usleep_range(10, 20); 73 } 74 75 dev_err(eth->dev, "mdio: MDIO timeout\n"); 76 return -1; 77 } 78 79 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 80 u32 phy_register, u32 write_data) 81 { 82 if (mtk_mdio_busy_wait(eth)) 83 return -1; 84 85 write_data &= 0xffff; 86 87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 88 (phy_register << PHY_IAC_REG_SHIFT) | 89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 90 MTK_PHY_IAC); 91 92 if (mtk_mdio_busy_wait(eth)) 93 return -1; 94 95 return 0; 96 } 97 98 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 99 { 100 u32 d; 101 102 if (mtk_mdio_busy_wait(eth)) 103 return 0xffff; 104 105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 106 (phy_reg << PHY_IAC_REG_SHIFT) | 107 (phy_addr << PHY_IAC_ADDR_SHIFT), 108 MTK_PHY_IAC); 109 110 if (mtk_mdio_busy_wait(eth)) 111 return 0xffff; 112 113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 114 115 return d; 116 } 117 118 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 119 int phy_reg, u16 val) 120 { 121 struct mtk_eth *eth = bus->priv; 122 123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 124 } 125 126 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 127 { 128 struct mtk_eth *eth = bus->priv; 129 130 return _mtk_mdio_read(eth, phy_addr, phy_reg); 131 } 132 133 static void mtk_phy_link_adjust(struct net_device *dev) 134 { 135 struct mtk_mac *mac = netdev_priv(dev); 136 u16 lcl_adv = 0, rmt_adv = 0; 137 u8 flowctrl; 138 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 139 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 140 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 141 MAC_MCR_BACKPR_EN; 142 143 switch (mac->phy_dev->speed) { 144 case SPEED_1000: 145 mcr |= MAC_MCR_SPEED_1000; 146 break; 147 case SPEED_100: 148 mcr |= MAC_MCR_SPEED_100; 149 break; 150 }; 151 152 if (mac->phy_dev->link) 153 mcr |= MAC_MCR_FORCE_LINK; 154 155 if (mac->phy_dev->duplex) { 156 mcr |= MAC_MCR_FORCE_DPX; 157 158 if (mac->phy_dev->pause) 159 rmt_adv = LPA_PAUSE_CAP; 160 if (mac->phy_dev->asym_pause) 161 rmt_adv |= LPA_PAUSE_ASYM; 162 163 if (mac->phy_dev->advertising & ADVERTISED_Pause) 164 lcl_adv |= ADVERTISE_PAUSE_CAP; 165 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause) 166 lcl_adv |= ADVERTISE_PAUSE_ASYM; 167 168 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 169 170 if (flowctrl & FLOW_CTRL_TX) 171 mcr |= MAC_MCR_FORCE_TX_FC; 172 if (flowctrl & FLOW_CTRL_RX) 173 mcr |= MAC_MCR_FORCE_RX_FC; 174 175 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 176 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 177 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 178 } 179 180 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 181 182 if (mac->phy_dev->link) 183 netif_carrier_on(dev); 184 else 185 netif_carrier_off(dev); 186 } 187 188 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 189 struct device_node *phy_node) 190 { 191 const __be32 *_addr = NULL; 192 struct phy_device *phydev; 193 int phy_mode, addr; 194 195 _addr = of_get_property(phy_node, "reg", NULL); 196 197 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) { 198 pr_err("%s: invalid phy address\n", phy_node->name); 199 return -EINVAL; 200 } 201 addr = be32_to_cpu(*_addr); 202 phy_mode = of_get_phy_mode(phy_node); 203 if (phy_mode < 0) { 204 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 205 return -EINVAL; 206 } 207 208 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 209 mtk_phy_link_adjust, 0, phy_mode); 210 if (!phydev) { 211 dev_err(eth->dev, "could not connect to PHY\n"); 212 return -ENODEV; 213 } 214 215 dev_info(eth->dev, 216 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 217 mac->id, phydev_name(phydev), phydev->phy_id, 218 phydev->drv->name); 219 220 mac->phy_dev = phydev; 221 222 return 0; 223 } 224 225 static int mtk_phy_connect(struct mtk_mac *mac) 226 { 227 struct mtk_eth *eth = mac->hw; 228 struct device_node *np; 229 u32 val, ge_mode; 230 231 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 232 if (!np && of_phy_is_fixed_link(mac->of_node)) 233 if (!of_phy_register_fixed_link(mac->of_node)) 234 np = of_node_get(mac->of_node); 235 if (!np) 236 return -ENODEV; 237 238 switch (of_get_phy_mode(np)) { 239 case PHY_INTERFACE_MODE_RGMII_TXID: 240 case PHY_INTERFACE_MODE_RGMII_RXID: 241 case PHY_INTERFACE_MODE_RGMII_ID: 242 case PHY_INTERFACE_MODE_RGMII: 243 ge_mode = 0; 244 break; 245 case PHY_INTERFACE_MODE_MII: 246 ge_mode = 1; 247 break; 248 case PHY_INTERFACE_MODE_RMII: 249 ge_mode = 2; 250 break; 251 default: 252 dev_err(eth->dev, "invalid phy_mode\n"); 253 return -1; 254 } 255 256 /* put the gmac into the right mode */ 257 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 258 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 259 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 260 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 261 262 mtk_phy_connect_node(eth, mac, np); 263 mac->phy_dev->autoneg = AUTONEG_ENABLE; 264 mac->phy_dev->speed = 0; 265 mac->phy_dev->duplex = 0; 266 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause | 267 SUPPORTED_Asym_Pause; 268 mac->phy_dev->advertising = mac->phy_dev->supported | 269 ADVERTISED_Autoneg; 270 phy_start_aneg(mac->phy_dev); 271 272 return 0; 273 } 274 275 static int mtk_mdio_init(struct mtk_eth *eth) 276 { 277 struct device_node *mii_np; 278 int err; 279 280 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 281 if (!mii_np) { 282 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 283 return -ENODEV; 284 } 285 286 if (!of_device_is_available(mii_np)) { 287 err = 0; 288 goto err_put_node; 289 } 290 291 eth->mii_bus = mdiobus_alloc(); 292 if (!eth->mii_bus) { 293 err = -ENOMEM; 294 goto err_put_node; 295 } 296 297 eth->mii_bus->name = "mdio"; 298 eth->mii_bus->read = mtk_mdio_read; 299 eth->mii_bus->write = mtk_mdio_write; 300 eth->mii_bus->priv = eth; 301 eth->mii_bus->parent = eth->dev; 302 303 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name); 304 err = of_mdiobus_register(eth->mii_bus, mii_np); 305 if (err) 306 goto err_free_bus; 307 308 return 0; 309 310 err_free_bus: 311 mdiobus_free(eth->mii_bus); 312 313 err_put_node: 314 of_node_put(mii_np); 315 eth->mii_bus = NULL; 316 return err; 317 } 318 319 static void mtk_mdio_cleanup(struct mtk_eth *eth) 320 { 321 if (!eth->mii_bus) 322 return; 323 324 mdiobus_unregister(eth->mii_bus); 325 of_node_put(eth->mii_bus->dev.of_node); 326 mdiobus_free(eth->mii_bus); 327 } 328 329 static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask) 330 { 331 unsigned long flags; 332 u32 val; 333 334 spin_lock_irqsave(ð->irq_lock, flags); 335 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 336 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); 337 spin_unlock_irqrestore(ð->irq_lock, flags); 338 } 339 340 static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask) 341 { 342 unsigned long flags; 343 u32 val; 344 345 spin_lock_irqsave(ð->irq_lock, flags); 346 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 347 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); 348 spin_unlock_irqrestore(ð->irq_lock, flags); 349 } 350 351 static int mtk_set_mac_address(struct net_device *dev, void *p) 352 { 353 int ret = eth_mac_addr(dev, p); 354 struct mtk_mac *mac = netdev_priv(dev); 355 const char *macaddr = dev->dev_addr; 356 unsigned long flags; 357 358 if (ret) 359 return ret; 360 361 spin_lock_irqsave(&mac->hw->page_lock, flags); 362 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 363 MTK_GDMA_MAC_ADRH(mac->id)); 364 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 365 (macaddr[4] << 8) | macaddr[5], 366 MTK_GDMA_MAC_ADRL(mac->id)); 367 spin_unlock_irqrestore(&mac->hw->page_lock, flags); 368 369 return 0; 370 } 371 372 void mtk_stats_update_mac(struct mtk_mac *mac) 373 { 374 struct mtk_hw_stats *hw_stats = mac->hw_stats; 375 unsigned int base = MTK_GDM1_TX_GBCNT; 376 u64 stats; 377 378 base += hw_stats->reg_offset; 379 380 u64_stats_update_begin(&hw_stats->syncp); 381 382 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 383 stats = mtk_r32(mac->hw, base + 0x04); 384 if (stats) 385 hw_stats->rx_bytes += (stats << 32); 386 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 387 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 388 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 389 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 390 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 391 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 392 hw_stats->rx_flow_control_packets += 393 mtk_r32(mac->hw, base + 0x24); 394 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 395 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 396 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 397 stats = mtk_r32(mac->hw, base + 0x34); 398 if (stats) 399 hw_stats->tx_bytes += (stats << 32); 400 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 401 u64_stats_update_end(&hw_stats->syncp); 402 } 403 404 static void mtk_stats_update(struct mtk_eth *eth) 405 { 406 int i; 407 408 for (i = 0; i < MTK_MAC_COUNT; i++) { 409 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 410 continue; 411 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 412 mtk_stats_update_mac(eth->mac[i]); 413 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 414 } 415 } 416 } 417 418 static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev, 419 struct rtnl_link_stats64 *storage) 420 { 421 struct mtk_mac *mac = netdev_priv(dev); 422 struct mtk_hw_stats *hw_stats = mac->hw_stats; 423 unsigned int start; 424 425 if (netif_running(dev) && netif_device_present(dev)) { 426 if (spin_trylock(&hw_stats->stats_lock)) { 427 mtk_stats_update_mac(mac); 428 spin_unlock(&hw_stats->stats_lock); 429 } 430 } 431 432 do { 433 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 434 storage->rx_packets = hw_stats->rx_packets; 435 storage->tx_packets = hw_stats->tx_packets; 436 storage->rx_bytes = hw_stats->rx_bytes; 437 storage->tx_bytes = hw_stats->tx_bytes; 438 storage->collisions = hw_stats->tx_collisions; 439 storage->rx_length_errors = hw_stats->rx_short_errors + 440 hw_stats->rx_long_errors; 441 storage->rx_over_errors = hw_stats->rx_overflow; 442 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 443 storage->rx_errors = hw_stats->rx_checksum_errors; 444 storage->tx_aborted_errors = hw_stats->tx_skip; 445 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 446 447 storage->tx_errors = dev->stats.tx_errors; 448 storage->rx_dropped = dev->stats.rx_dropped; 449 storage->tx_dropped = dev->stats.tx_dropped; 450 451 return storage; 452 } 453 454 static inline int mtk_max_frag_size(int mtu) 455 { 456 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 457 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 458 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 459 460 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 461 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 462 } 463 464 static inline int mtk_max_buf_size(int frag_size) 465 { 466 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 467 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 468 469 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 470 471 return buf_size; 472 } 473 474 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 475 struct mtk_rx_dma *dma_rxd) 476 { 477 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 478 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 479 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 480 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 481 } 482 483 /* the qdma core needs scratch memory to be setup */ 484 static int mtk_init_fq_dma(struct mtk_eth *eth) 485 { 486 dma_addr_t phy_ring_tail; 487 int cnt = MTK_DMA_SIZE; 488 dma_addr_t dma_addr; 489 int i; 490 491 eth->scratch_ring = dma_alloc_coherent(eth->dev, 492 cnt * sizeof(struct mtk_tx_dma), 493 ð->phy_scratch_ring, 494 GFP_ATOMIC | __GFP_ZERO); 495 if (unlikely(!eth->scratch_ring)) 496 return -ENOMEM; 497 498 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 499 GFP_KERNEL); 500 if (unlikely(!eth->scratch_head)) 501 return -ENOMEM; 502 503 dma_addr = dma_map_single(eth->dev, 504 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 505 DMA_FROM_DEVICE); 506 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 507 return -ENOMEM; 508 509 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt); 510 phy_ring_tail = eth->phy_scratch_ring + 511 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 512 513 for (i = 0; i < cnt; i++) { 514 eth->scratch_ring[i].txd1 = 515 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 516 if (i < cnt - 1) 517 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 518 ((i + 1) * sizeof(struct mtk_tx_dma))); 519 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 520 } 521 522 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 523 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 524 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 525 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 526 527 return 0; 528 } 529 530 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 531 { 532 void *ret = ring->dma; 533 534 return ret + (desc - ring->phys); 535 } 536 537 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 538 struct mtk_tx_dma *txd) 539 { 540 int idx = txd - ring->dma; 541 542 return &ring->buf[idx]; 543 } 544 545 static void mtk_tx_unmap(struct device *dev, struct mtk_tx_buf *tx_buf) 546 { 547 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 548 dma_unmap_single(dev, 549 dma_unmap_addr(tx_buf, dma_addr0), 550 dma_unmap_len(tx_buf, dma_len0), 551 DMA_TO_DEVICE); 552 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 553 dma_unmap_page(dev, 554 dma_unmap_addr(tx_buf, dma_addr0), 555 dma_unmap_len(tx_buf, dma_len0), 556 DMA_TO_DEVICE); 557 } 558 tx_buf->flags = 0; 559 if (tx_buf->skb && 560 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 561 dev_kfree_skb_any(tx_buf->skb); 562 tx_buf->skb = NULL; 563 } 564 565 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 566 int tx_num, struct mtk_tx_ring *ring, bool gso) 567 { 568 struct mtk_mac *mac = netdev_priv(dev); 569 struct mtk_eth *eth = mac->hw; 570 struct mtk_tx_dma *itxd, *txd; 571 struct mtk_tx_buf *tx_buf; 572 dma_addr_t mapped_addr; 573 unsigned int nr_frags; 574 int i, n_desc = 1; 575 u32 txd4 = 0; 576 577 itxd = ring->next_free; 578 if (itxd == ring->last_free) 579 return -ENOMEM; 580 581 /* set the forward port */ 582 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT; 583 584 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 585 memset(tx_buf, 0, sizeof(*tx_buf)); 586 587 if (gso) 588 txd4 |= TX_DMA_TSO; 589 590 /* TX Checksum offload */ 591 if (skb->ip_summed == CHECKSUM_PARTIAL) 592 txd4 |= TX_DMA_CHKSUM; 593 594 /* VLAN header offload */ 595 if (skb_vlan_tag_present(skb)) 596 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 597 598 mapped_addr = dma_map_single(&dev->dev, skb->data, 599 skb_headlen(skb), DMA_TO_DEVICE); 600 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr))) 601 return -ENOMEM; 602 603 WRITE_ONCE(itxd->txd1, mapped_addr); 604 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 605 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 606 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb)); 607 608 /* TX SG offload */ 609 txd = itxd; 610 nr_frags = skb_shinfo(skb)->nr_frags; 611 for (i = 0; i < nr_frags; i++) { 612 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 613 unsigned int offset = 0; 614 int frag_size = skb_frag_size(frag); 615 616 while (frag_size) { 617 bool last_frag = false; 618 unsigned int frag_map_size; 619 620 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 621 if (txd == ring->last_free) 622 goto err_dma; 623 624 n_desc++; 625 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 626 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset, 627 frag_map_size, 628 DMA_TO_DEVICE); 629 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr))) 630 goto err_dma; 631 632 if (i == nr_frags - 1 && 633 (frag_size - frag_map_size) == 0) 634 last_frag = true; 635 636 WRITE_ONCE(txd->txd1, mapped_addr); 637 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 638 TX_DMA_PLEN0(frag_map_size) | 639 last_frag * TX_DMA_LS0)); 640 WRITE_ONCE(txd->txd4, 0); 641 642 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 643 tx_buf = mtk_desc_to_tx_buf(ring, txd); 644 memset(tx_buf, 0, sizeof(*tx_buf)); 645 646 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 647 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 648 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 649 frag_size -= frag_map_size; 650 offset += frag_map_size; 651 } 652 } 653 654 /* store skb to cleanup */ 655 tx_buf->skb = skb; 656 657 WRITE_ONCE(itxd->txd4, txd4); 658 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 659 (!nr_frags * TX_DMA_LS0))); 660 661 netdev_sent_queue(dev, skb->len); 662 skb_tx_timestamp(skb); 663 664 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 665 atomic_sub(n_desc, &ring->free_count); 666 667 /* make sure that all changes to the dma ring are flushed before we 668 * continue 669 */ 670 wmb(); 671 672 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more) 673 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 674 675 return 0; 676 677 err_dma: 678 do { 679 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 680 681 /* unmap dma */ 682 mtk_tx_unmap(&dev->dev, tx_buf); 683 684 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 685 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 686 } while (itxd != txd); 687 688 return -ENOMEM; 689 } 690 691 static inline int mtk_cal_txd_req(struct sk_buff *skb) 692 { 693 int i, nfrags; 694 struct skb_frag_struct *frag; 695 696 nfrags = 1; 697 if (skb_is_gso(skb)) { 698 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 699 frag = &skb_shinfo(skb)->frags[i]; 700 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); 701 } 702 } else { 703 nfrags += skb_shinfo(skb)->nr_frags; 704 } 705 706 return nfrags; 707 } 708 709 static int mtk_queue_stopped(struct mtk_eth *eth) 710 { 711 int i; 712 713 for (i = 0; i < MTK_MAC_COUNT; i++) { 714 if (!eth->netdev[i]) 715 continue; 716 if (netif_queue_stopped(eth->netdev[i])) 717 return 1; 718 } 719 720 return 0; 721 } 722 723 static void mtk_wake_queue(struct mtk_eth *eth) 724 { 725 int i; 726 727 for (i = 0; i < MTK_MAC_COUNT; i++) { 728 if (!eth->netdev[i]) 729 continue; 730 netif_wake_queue(eth->netdev[i]); 731 } 732 } 733 734 static void mtk_stop_queue(struct mtk_eth *eth) 735 { 736 int i; 737 738 for (i = 0; i < MTK_MAC_COUNT; i++) { 739 if (!eth->netdev[i]) 740 continue; 741 netif_stop_queue(eth->netdev[i]); 742 } 743 } 744 745 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 746 { 747 struct mtk_mac *mac = netdev_priv(dev); 748 struct mtk_eth *eth = mac->hw; 749 struct mtk_tx_ring *ring = ð->tx_ring; 750 struct net_device_stats *stats = &dev->stats; 751 unsigned long flags; 752 bool gso = false; 753 int tx_num; 754 755 /* normally we can rely on the stack not calling this more than once, 756 * however we have 2 queues running on the same ring so we need to lock 757 * the ring access 758 */ 759 spin_lock_irqsave(ð->page_lock, flags); 760 761 tx_num = mtk_cal_txd_req(skb); 762 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 763 mtk_stop_queue(eth); 764 netif_err(eth, tx_queued, dev, 765 "Tx Ring full when queue awake!\n"); 766 spin_unlock_irqrestore(ð->page_lock, flags); 767 return NETDEV_TX_BUSY; 768 } 769 770 /* TSO: fill MSS info in tcp checksum field */ 771 if (skb_is_gso(skb)) { 772 if (skb_cow_head(skb, 0)) { 773 netif_warn(eth, tx_err, dev, 774 "GSO expand head fail.\n"); 775 goto drop; 776 } 777 778 if (skb_shinfo(skb)->gso_type & 779 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 780 gso = true; 781 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 782 } 783 } 784 785 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 786 goto drop; 787 788 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 789 mtk_stop_queue(eth); 790 791 spin_unlock_irqrestore(ð->page_lock, flags); 792 793 return NETDEV_TX_OK; 794 795 drop: 796 spin_unlock_irqrestore(ð->page_lock, flags); 797 stats->tx_dropped++; 798 dev_kfree_skb(skb); 799 return NETDEV_TX_OK; 800 } 801 802 static int mtk_poll_rx(struct napi_struct *napi, int budget, 803 struct mtk_eth *eth) 804 { 805 struct mtk_rx_ring *ring = ð->rx_ring; 806 int idx = ring->calc_idx; 807 struct sk_buff *skb; 808 u8 *data, *new_data; 809 struct mtk_rx_dma *rxd, trxd; 810 int done = 0; 811 812 while (done < budget) { 813 struct net_device *netdev; 814 unsigned int pktlen; 815 dma_addr_t dma_addr; 816 int mac = 0; 817 818 idx = NEXT_RX_DESP_IDX(idx); 819 rxd = &ring->dma[idx]; 820 data = ring->data[idx]; 821 822 mtk_rx_get_desc(&trxd, rxd); 823 if (!(trxd.rxd2 & RX_DMA_DONE)) 824 break; 825 826 /* find out which mac the packet come from. values start at 1 */ 827 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 828 RX_DMA_FPORT_MASK; 829 mac--; 830 831 netdev = eth->netdev[mac]; 832 833 /* alloc new buffer */ 834 new_data = napi_alloc_frag(ring->frag_size); 835 if (unlikely(!new_data)) { 836 netdev->stats.rx_dropped++; 837 goto release_desc; 838 } 839 dma_addr = dma_map_single(ð->netdev[mac]->dev, 840 new_data + NET_SKB_PAD, 841 ring->buf_size, 842 DMA_FROM_DEVICE); 843 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) { 844 skb_free_frag(new_data); 845 netdev->stats.rx_dropped++; 846 goto release_desc; 847 } 848 849 /* receive data */ 850 skb = build_skb(data, ring->frag_size); 851 if (unlikely(!skb)) { 852 put_page(virt_to_head_page(new_data)); 853 netdev->stats.rx_dropped++; 854 goto release_desc; 855 } 856 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 857 858 dma_unmap_single(&netdev->dev, trxd.rxd1, 859 ring->buf_size, DMA_FROM_DEVICE); 860 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 861 skb->dev = netdev; 862 skb_put(skb, pktlen); 863 if (trxd.rxd4 & RX_DMA_L4_VALID) 864 skb->ip_summed = CHECKSUM_UNNECESSARY; 865 else 866 skb_checksum_none_assert(skb); 867 skb->protocol = eth_type_trans(skb, netdev); 868 869 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 870 RX_DMA_VID(trxd.rxd3)) 871 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 872 RX_DMA_VID(trxd.rxd3)); 873 napi_gro_receive(napi, skb); 874 875 ring->data[idx] = new_data; 876 rxd->rxd1 = (unsigned int)dma_addr; 877 878 release_desc: 879 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 880 881 ring->calc_idx = idx; 882 /* make sure that all changes to the dma ring are flushed before 883 * we continue 884 */ 885 wmb(); 886 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0); 887 done++; 888 } 889 890 if (done < budget) 891 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS); 892 893 return done; 894 } 895 896 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 897 { 898 struct mtk_tx_ring *ring = ð->tx_ring; 899 struct mtk_tx_dma *desc; 900 struct sk_buff *skb; 901 struct mtk_tx_buf *tx_buf; 902 unsigned int done[MTK_MAX_DEVS]; 903 unsigned int bytes[MTK_MAX_DEVS]; 904 u32 cpu, dma; 905 static int condition; 906 int total = 0, i; 907 908 memset(done, 0, sizeof(done)); 909 memset(bytes, 0, sizeof(bytes)); 910 911 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 912 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 913 914 desc = mtk_qdma_phys_to_virt(ring, cpu); 915 916 while ((cpu != dma) && budget) { 917 u32 next_cpu = desc->txd2; 918 int mac; 919 920 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 921 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 922 break; 923 924 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) & 925 TX_DMA_FPORT_MASK; 926 mac--; 927 928 tx_buf = mtk_desc_to_tx_buf(ring, desc); 929 skb = tx_buf->skb; 930 if (!skb) { 931 condition = 1; 932 break; 933 } 934 935 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 936 bytes[mac] += skb->len; 937 done[mac]++; 938 budget--; 939 } 940 mtk_tx_unmap(eth->dev, tx_buf); 941 942 ring->last_free = desc; 943 atomic_inc(&ring->free_count); 944 945 cpu = next_cpu; 946 } 947 948 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 949 950 for (i = 0; i < MTK_MAC_COUNT; i++) { 951 if (!eth->netdev[i] || !done[i]) 952 continue; 953 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 954 total += done[i]; 955 } 956 957 if (mtk_queue_stopped(eth) && 958 (atomic_read(&ring->free_count) > ring->thresh)) 959 mtk_wake_queue(eth); 960 961 return total; 962 } 963 964 static void mtk_handle_status_irq(struct mtk_eth *eth) 965 { 966 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 967 968 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 969 mtk_stats_update(eth); 970 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 971 MTK_INT_STATUS2); 972 } 973 } 974 975 static int mtk_napi_tx(struct napi_struct *napi, int budget) 976 { 977 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 978 u32 status, mask; 979 int tx_done = 0; 980 981 mtk_handle_status_irq(eth); 982 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 983 tx_done = mtk_poll_tx(eth, budget); 984 985 if (unlikely(netif_msg_intr(eth))) { 986 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 987 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 988 dev_info(eth->dev, 989 "done tx %d, intr 0x%08x/0x%x\n", 990 tx_done, status, mask); 991 } 992 993 if (tx_done == budget) 994 return budget; 995 996 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 997 if (status & MTK_TX_DONE_INT) 998 return budget; 999 1000 napi_complete(napi); 1001 mtk_irq_enable(eth, MTK_TX_DONE_INT); 1002 1003 return tx_done; 1004 } 1005 1006 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1007 { 1008 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1009 u32 status, mask; 1010 int rx_done = 0; 1011 1012 mtk_handle_status_irq(eth); 1013 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS); 1014 rx_done = mtk_poll_rx(napi, budget, eth); 1015 1016 if (unlikely(netif_msg_intr(eth))) { 1017 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1018 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 1019 dev_info(eth->dev, 1020 "done rx %d, intr 0x%08x/0x%x\n", 1021 rx_done, status, mask); 1022 } 1023 1024 if (rx_done == budget) 1025 return budget; 1026 1027 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1028 if (status & MTK_RX_DONE_INT) 1029 return budget; 1030 1031 napi_complete(napi); 1032 mtk_irq_enable(eth, MTK_RX_DONE_INT); 1033 1034 return rx_done; 1035 } 1036 1037 static int mtk_tx_alloc(struct mtk_eth *eth) 1038 { 1039 struct mtk_tx_ring *ring = ð->tx_ring; 1040 int i, sz = sizeof(*ring->dma); 1041 1042 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1043 GFP_KERNEL); 1044 if (!ring->buf) 1045 goto no_tx_mem; 1046 1047 ring->dma = dma_alloc_coherent(eth->dev, 1048 MTK_DMA_SIZE * sz, 1049 &ring->phys, 1050 GFP_ATOMIC | __GFP_ZERO); 1051 if (!ring->dma) 1052 goto no_tx_mem; 1053 1054 memset(ring->dma, 0, MTK_DMA_SIZE * sz); 1055 for (i = 0; i < MTK_DMA_SIZE; i++) { 1056 int next = (i + 1) % MTK_DMA_SIZE; 1057 u32 next_ptr = ring->phys + next * sz; 1058 1059 ring->dma[i].txd2 = next_ptr; 1060 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1061 } 1062 1063 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1064 ring->next_free = &ring->dma[0]; 1065 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1066 ring->thresh = MAX_SKB_FRAGS; 1067 1068 /* make sure that all changes to the dma ring are flushed before we 1069 * continue 1070 */ 1071 wmb(); 1072 1073 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1074 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1075 mtk_w32(eth, 1076 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1077 MTK_QTX_CRX_PTR); 1078 mtk_w32(eth, 1079 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1080 MTK_QTX_DRX_PTR); 1081 1082 return 0; 1083 1084 no_tx_mem: 1085 return -ENOMEM; 1086 } 1087 1088 static void mtk_tx_clean(struct mtk_eth *eth) 1089 { 1090 struct mtk_tx_ring *ring = ð->tx_ring; 1091 int i; 1092 1093 if (ring->buf) { 1094 for (i = 0; i < MTK_DMA_SIZE; i++) 1095 mtk_tx_unmap(eth->dev, &ring->buf[i]); 1096 kfree(ring->buf); 1097 ring->buf = NULL; 1098 } 1099 1100 if (ring->dma) { 1101 dma_free_coherent(eth->dev, 1102 MTK_DMA_SIZE * sizeof(*ring->dma), 1103 ring->dma, 1104 ring->phys); 1105 ring->dma = NULL; 1106 } 1107 } 1108 1109 static int mtk_rx_alloc(struct mtk_eth *eth) 1110 { 1111 struct mtk_rx_ring *ring = ð->rx_ring; 1112 int i; 1113 1114 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN); 1115 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1116 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data), 1117 GFP_KERNEL); 1118 if (!ring->data) 1119 return -ENOMEM; 1120 1121 for (i = 0; i < MTK_DMA_SIZE; i++) { 1122 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1123 if (!ring->data[i]) 1124 return -ENOMEM; 1125 } 1126 1127 ring->dma = dma_alloc_coherent(eth->dev, 1128 MTK_DMA_SIZE * sizeof(*ring->dma), 1129 &ring->phys, 1130 GFP_ATOMIC | __GFP_ZERO); 1131 if (!ring->dma) 1132 return -ENOMEM; 1133 1134 for (i = 0; i < MTK_DMA_SIZE; i++) { 1135 dma_addr_t dma_addr = dma_map_single(eth->dev, 1136 ring->data[i] + NET_SKB_PAD, 1137 ring->buf_size, 1138 DMA_FROM_DEVICE); 1139 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1140 return -ENOMEM; 1141 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1142 1143 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1144 } 1145 ring->calc_idx = MTK_DMA_SIZE - 1; 1146 /* make sure that all changes to the dma ring are flushed before we 1147 * continue 1148 */ 1149 wmb(); 1150 1151 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0); 1152 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0); 1153 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0); 1154 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX); 1155 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1156 1157 return 0; 1158 } 1159 1160 static void mtk_rx_clean(struct mtk_eth *eth) 1161 { 1162 struct mtk_rx_ring *ring = ð->rx_ring; 1163 int i; 1164 1165 if (ring->data && ring->dma) { 1166 for (i = 0; i < MTK_DMA_SIZE; i++) { 1167 if (!ring->data[i]) 1168 continue; 1169 if (!ring->dma[i].rxd1) 1170 continue; 1171 dma_unmap_single(eth->dev, 1172 ring->dma[i].rxd1, 1173 ring->buf_size, 1174 DMA_FROM_DEVICE); 1175 skb_free_frag(ring->data[i]); 1176 } 1177 kfree(ring->data); 1178 ring->data = NULL; 1179 } 1180 1181 if (ring->dma) { 1182 dma_free_coherent(eth->dev, 1183 MTK_DMA_SIZE * sizeof(*ring->dma), 1184 ring->dma, 1185 ring->phys); 1186 ring->dma = NULL; 1187 } 1188 } 1189 1190 /* wait for DMA to finish whatever it is doing before we start using it again */ 1191 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1192 { 1193 unsigned long t_start = jiffies; 1194 1195 while (1) { 1196 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1197 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1198 return 0; 1199 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1200 break; 1201 } 1202 1203 dev_err(eth->dev, "DMA init timeout\n"); 1204 return -1; 1205 } 1206 1207 static int mtk_dma_init(struct mtk_eth *eth) 1208 { 1209 int err; 1210 1211 if (mtk_dma_busy_wait(eth)) 1212 return -EBUSY; 1213 1214 /* QDMA needs scratch memory for internal reordering of the 1215 * descriptors 1216 */ 1217 err = mtk_init_fq_dma(eth); 1218 if (err) 1219 return err; 1220 1221 err = mtk_tx_alloc(eth); 1222 if (err) 1223 return err; 1224 1225 err = mtk_rx_alloc(eth); 1226 if (err) 1227 return err; 1228 1229 /* Enable random early drop and set drop threshold automatically */ 1230 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1231 MTK_QDMA_FC_THRES); 1232 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1233 1234 return 0; 1235 } 1236 1237 static void mtk_dma_free(struct mtk_eth *eth) 1238 { 1239 int i; 1240 1241 for (i = 0; i < MTK_MAC_COUNT; i++) 1242 if (eth->netdev[i]) 1243 netdev_reset_queue(eth->netdev[i]); 1244 if (eth->scratch_ring) { 1245 dma_free_coherent(eth->dev, 1246 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 1247 eth->scratch_ring, 1248 eth->phy_scratch_ring); 1249 eth->scratch_ring = NULL; 1250 eth->phy_scratch_ring = 0; 1251 } 1252 mtk_tx_clean(eth); 1253 mtk_rx_clean(eth); 1254 kfree(eth->scratch_head); 1255 } 1256 1257 static void mtk_tx_timeout(struct net_device *dev) 1258 { 1259 struct mtk_mac *mac = netdev_priv(dev); 1260 struct mtk_eth *eth = mac->hw; 1261 1262 eth->netdev[mac->id]->stats.tx_errors++; 1263 netif_err(eth, tx_err, dev, 1264 "transmit timed out\n"); 1265 schedule_work(ð->pending_work); 1266 } 1267 1268 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 1269 { 1270 struct mtk_eth *eth = _eth; 1271 1272 if (likely(napi_schedule_prep(ð->rx_napi))) { 1273 __napi_schedule(ð->rx_napi); 1274 mtk_irq_disable(eth, MTK_RX_DONE_INT); 1275 } 1276 1277 return IRQ_HANDLED; 1278 } 1279 1280 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 1281 { 1282 struct mtk_eth *eth = _eth; 1283 1284 if (likely(napi_schedule_prep(ð->tx_napi))) { 1285 __napi_schedule(ð->tx_napi); 1286 mtk_irq_disable(eth, MTK_TX_DONE_INT); 1287 } 1288 1289 return IRQ_HANDLED; 1290 } 1291 1292 #ifdef CONFIG_NET_POLL_CONTROLLER 1293 static void mtk_poll_controller(struct net_device *dev) 1294 { 1295 struct mtk_mac *mac = netdev_priv(dev); 1296 struct mtk_eth *eth = mac->hw; 1297 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT; 1298 1299 mtk_irq_disable(eth, int_mask); 1300 mtk_handle_irq_rx(eth->irq[2], dev); 1301 mtk_irq_enable(eth, int_mask); 1302 } 1303 #endif 1304 1305 static int mtk_start_dma(struct mtk_eth *eth) 1306 { 1307 int err; 1308 1309 err = mtk_dma_init(eth); 1310 if (err) { 1311 mtk_dma_free(eth); 1312 return err; 1313 } 1314 1315 mtk_w32(eth, 1316 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN | 1317 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS | 1318 MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO, 1319 MTK_QDMA_GLO_CFG); 1320 1321 return 0; 1322 } 1323 1324 static int mtk_open(struct net_device *dev) 1325 { 1326 struct mtk_mac *mac = netdev_priv(dev); 1327 struct mtk_eth *eth = mac->hw; 1328 1329 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1330 if (!atomic_read(ð->dma_refcnt)) { 1331 int err = mtk_start_dma(eth); 1332 1333 if (err) 1334 return err; 1335 1336 napi_enable(ð->tx_napi); 1337 napi_enable(ð->rx_napi); 1338 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT); 1339 } 1340 atomic_inc(ð->dma_refcnt); 1341 1342 phy_start(mac->phy_dev); 1343 netif_start_queue(dev); 1344 1345 return 0; 1346 } 1347 1348 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1349 { 1350 unsigned long flags; 1351 u32 val; 1352 int i; 1353 1354 /* stop the dma engine */ 1355 spin_lock_irqsave(ð->page_lock, flags); 1356 val = mtk_r32(eth, glo_cfg); 1357 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1358 glo_cfg); 1359 spin_unlock_irqrestore(ð->page_lock, flags); 1360 1361 /* wait for dma stop */ 1362 for (i = 0; i < 10; i++) { 1363 val = mtk_r32(eth, glo_cfg); 1364 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1365 msleep(20); 1366 continue; 1367 } 1368 break; 1369 } 1370 } 1371 1372 static int mtk_stop(struct net_device *dev) 1373 { 1374 struct mtk_mac *mac = netdev_priv(dev); 1375 struct mtk_eth *eth = mac->hw; 1376 1377 netif_tx_disable(dev); 1378 phy_stop(mac->phy_dev); 1379 1380 /* only shutdown DMA if this is the last user */ 1381 if (!atomic_dec_and_test(ð->dma_refcnt)) 1382 return 0; 1383 1384 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT); 1385 napi_disable(ð->tx_napi); 1386 napi_disable(ð->rx_napi); 1387 1388 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1389 1390 mtk_dma_free(eth); 1391 1392 return 0; 1393 } 1394 1395 static int __init mtk_hw_init(struct mtk_eth *eth) 1396 { 1397 int err, i; 1398 1399 /* reset the frame engine */ 1400 reset_control_assert(eth->rstc); 1401 usleep_range(10, 20); 1402 reset_control_deassert(eth->rstc); 1403 usleep_range(10, 20); 1404 1405 /* Set GE2 driving and slew rate */ 1406 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1407 1408 /* set GE2 TDSEL */ 1409 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1410 1411 /* set GE2 TUNE */ 1412 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1413 1414 /* GE1, Force 1000M/FD, FC ON */ 1415 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0)); 1416 1417 /* GE2, Force 1000M/FD, FC ON */ 1418 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1)); 1419 1420 /* Enable RX VLan Offloading */ 1421 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1422 1423 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0, 1424 dev_name(eth->dev), eth); 1425 if (err) 1426 return err; 1427 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0, 1428 dev_name(eth->dev), eth); 1429 if (err) 1430 return err; 1431 1432 err = mtk_mdio_init(eth); 1433 if (err) 1434 return err; 1435 1436 /* disable delay and normal interrupt */ 1437 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1438 mtk_irq_disable(eth, ~0); 1439 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1440 mtk_w32(eth, 0, MTK_RST_GL); 1441 1442 /* FE int grouping */ 1443 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 1444 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 1445 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 1446 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 1447 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 1448 1449 for (i = 0; i < 2; i++) { 1450 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1451 1452 /* setup the forward port to send frame to QDMA */ 1453 val &= ~0xffff; 1454 val |= 0x5555; 1455 1456 /* Enable RX checksum */ 1457 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 1458 1459 /* setup the mac dma */ 1460 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 1461 } 1462 1463 return 0; 1464 } 1465 1466 static int __init mtk_init(struct net_device *dev) 1467 { 1468 struct mtk_mac *mac = netdev_priv(dev); 1469 struct mtk_eth *eth = mac->hw; 1470 const char *mac_addr; 1471 1472 mac_addr = of_get_mac_address(mac->of_node); 1473 if (mac_addr) 1474 ether_addr_copy(dev->dev_addr, mac_addr); 1475 1476 /* If the mac address is invalid, use random mac address */ 1477 if (!is_valid_ether_addr(dev->dev_addr)) { 1478 random_ether_addr(dev->dev_addr); 1479 dev_err(eth->dev, "generated random MAC address %pM\n", 1480 dev->dev_addr); 1481 dev->addr_assign_type = NET_ADDR_RANDOM; 1482 } 1483 1484 return mtk_phy_connect(mac); 1485 } 1486 1487 static void mtk_uninit(struct net_device *dev) 1488 { 1489 struct mtk_mac *mac = netdev_priv(dev); 1490 struct mtk_eth *eth = mac->hw; 1491 1492 phy_disconnect(mac->phy_dev); 1493 mtk_mdio_cleanup(eth); 1494 mtk_irq_disable(eth, ~0); 1495 free_irq(eth->irq[1], dev); 1496 free_irq(eth->irq[2], dev); 1497 } 1498 1499 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1500 { 1501 struct mtk_mac *mac = netdev_priv(dev); 1502 1503 switch (cmd) { 1504 case SIOCGMIIPHY: 1505 case SIOCGMIIREG: 1506 case SIOCSMIIREG: 1507 return phy_mii_ioctl(mac->phy_dev, ifr, cmd); 1508 default: 1509 break; 1510 } 1511 1512 return -EOPNOTSUPP; 1513 } 1514 1515 static void mtk_pending_work(struct work_struct *work) 1516 { 1517 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 1518 int err, i; 1519 unsigned long restart = 0; 1520 1521 rtnl_lock(); 1522 1523 /* stop all devices to make sure that dma is properly shut down */ 1524 for (i = 0; i < MTK_MAC_COUNT; i++) { 1525 if (!eth->netdev[i]) 1526 continue; 1527 mtk_stop(eth->netdev[i]); 1528 __set_bit(i, &restart); 1529 } 1530 1531 /* restart DMA and enable IRQs */ 1532 for (i = 0; i < MTK_MAC_COUNT; i++) { 1533 if (!test_bit(i, &restart)) 1534 continue; 1535 err = mtk_open(eth->netdev[i]); 1536 if (err) { 1537 netif_alert(eth, ifup, eth->netdev[i], 1538 "Driver up/down cycle failed, closing device.\n"); 1539 dev_close(eth->netdev[i]); 1540 } 1541 } 1542 rtnl_unlock(); 1543 } 1544 1545 static int mtk_cleanup(struct mtk_eth *eth) 1546 { 1547 int i; 1548 1549 for (i = 0; i < MTK_MAC_COUNT; i++) { 1550 if (!eth->netdev[i]) 1551 continue; 1552 1553 unregister_netdev(eth->netdev[i]); 1554 free_netdev(eth->netdev[i]); 1555 } 1556 cancel_work_sync(ð->pending_work); 1557 1558 return 0; 1559 } 1560 1561 static int mtk_get_settings(struct net_device *dev, 1562 struct ethtool_cmd *cmd) 1563 { 1564 struct mtk_mac *mac = netdev_priv(dev); 1565 int err; 1566 1567 err = phy_read_status(mac->phy_dev); 1568 if (err) 1569 return -ENODEV; 1570 1571 return phy_ethtool_gset(mac->phy_dev, cmd); 1572 } 1573 1574 static int mtk_set_settings(struct net_device *dev, 1575 struct ethtool_cmd *cmd) 1576 { 1577 struct mtk_mac *mac = netdev_priv(dev); 1578 1579 if (cmd->phy_address != mac->phy_dev->mdio.addr) { 1580 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus, 1581 cmd->phy_address); 1582 if (!mac->phy_dev) 1583 return -ENODEV; 1584 } 1585 1586 return phy_ethtool_sset(mac->phy_dev, cmd); 1587 } 1588 1589 static void mtk_get_drvinfo(struct net_device *dev, 1590 struct ethtool_drvinfo *info) 1591 { 1592 struct mtk_mac *mac = netdev_priv(dev); 1593 1594 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 1595 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 1596 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 1597 } 1598 1599 static u32 mtk_get_msglevel(struct net_device *dev) 1600 { 1601 struct mtk_mac *mac = netdev_priv(dev); 1602 1603 return mac->hw->msg_enable; 1604 } 1605 1606 static void mtk_set_msglevel(struct net_device *dev, u32 value) 1607 { 1608 struct mtk_mac *mac = netdev_priv(dev); 1609 1610 mac->hw->msg_enable = value; 1611 } 1612 1613 static int mtk_nway_reset(struct net_device *dev) 1614 { 1615 struct mtk_mac *mac = netdev_priv(dev); 1616 1617 return genphy_restart_aneg(mac->phy_dev); 1618 } 1619 1620 static u32 mtk_get_link(struct net_device *dev) 1621 { 1622 struct mtk_mac *mac = netdev_priv(dev); 1623 int err; 1624 1625 err = genphy_update_link(mac->phy_dev); 1626 if (err) 1627 return ethtool_op_get_link(dev); 1628 1629 return mac->phy_dev->link; 1630 } 1631 1632 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1633 { 1634 int i; 1635 1636 switch (stringset) { 1637 case ETH_SS_STATS: 1638 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 1639 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 1640 data += ETH_GSTRING_LEN; 1641 } 1642 break; 1643 } 1644 } 1645 1646 static int mtk_get_sset_count(struct net_device *dev, int sset) 1647 { 1648 switch (sset) { 1649 case ETH_SS_STATS: 1650 return ARRAY_SIZE(mtk_ethtool_stats); 1651 default: 1652 return -EOPNOTSUPP; 1653 } 1654 } 1655 1656 static void mtk_get_ethtool_stats(struct net_device *dev, 1657 struct ethtool_stats *stats, u64 *data) 1658 { 1659 struct mtk_mac *mac = netdev_priv(dev); 1660 struct mtk_hw_stats *hwstats = mac->hw_stats; 1661 u64 *data_src, *data_dst; 1662 unsigned int start; 1663 int i; 1664 1665 if (netif_running(dev) && netif_device_present(dev)) { 1666 if (spin_trylock(&hwstats->stats_lock)) { 1667 mtk_stats_update_mac(mac); 1668 spin_unlock(&hwstats->stats_lock); 1669 } 1670 } 1671 1672 do { 1673 data_src = (u64*)hwstats; 1674 data_dst = data; 1675 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 1676 1677 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 1678 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 1679 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 1680 } 1681 1682 static struct ethtool_ops mtk_ethtool_ops = { 1683 .get_settings = mtk_get_settings, 1684 .set_settings = mtk_set_settings, 1685 .get_drvinfo = mtk_get_drvinfo, 1686 .get_msglevel = mtk_get_msglevel, 1687 .set_msglevel = mtk_set_msglevel, 1688 .nway_reset = mtk_nway_reset, 1689 .get_link = mtk_get_link, 1690 .get_strings = mtk_get_strings, 1691 .get_sset_count = mtk_get_sset_count, 1692 .get_ethtool_stats = mtk_get_ethtool_stats, 1693 }; 1694 1695 static const struct net_device_ops mtk_netdev_ops = { 1696 .ndo_init = mtk_init, 1697 .ndo_uninit = mtk_uninit, 1698 .ndo_open = mtk_open, 1699 .ndo_stop = mtk_stop, 1700 .ndo_start_xmit = mtk_start_xmit, 1701 .ndo_set_mac_address = mtk_set_mac_address, 1702 .ndo_validate_addr = eth_validate_addr, 1703 .ndo_do_ioctl = mtk_do_ioctl, 1704 .ndo_change_mtu = eth_change_mtu, 1705 .ndo_tx_timeout = mtk_tx_timeout, 1706 .ndo_get_stats64 = mtk_get_stats64, 1707 #ifdef CONFIG_NET_POLL_CONTROLLER 1708 .ndo_poll_controller = mtk_poll_controller, 1709 #endif 1710 }; 1711 1712 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 1713 { 1714 struct mtk_mac *mac; 1715 const __be32 *_id = of_get_property(np, "reg", NULL); 1716 int id, err; 1717 1718 if (!_id) { 1719 dev_err(eth->dev, "missing mac id\n"); 1720 return -EINVAL; 1721 } 1722 1723 id = be32_to_cpup(_id); 1724 if (id >= MTK_MAC_COUNT) { 1725 dev_err(eth->dev, "%d is not a valid mac id\n", id); 1726 return -EINVAL; 1727 } 1728 1729 if (eth->netdev[id]) { 1730 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 1731 return -EINVAL; 1732 } 1733 1734 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 1735 if (!eth->netdev[id]) { 1736 dev_err(eth->dev, "alloc_etherdev failed\n"); 1737 return -ENOMEM; 1738 } 1739 mac = netdev_priv(eth->netdev[id]); 1740 eth->mac[id] = mac; 1741 mac->id = id; 1742 mac->hw = eth; 1743 mac->of_node = np; 1744 1745 mac->hw_stats = devm_kzalloc(eth->dev, 1746 sizeof(*mac->hw_stats), 1747 GFP_KERNEL); 1748 if (!mac->hw_stats) { 1749 dev_err(eth->dev, "failed to allocate counter memory\n"); 1750 err = -ENOMEM; 1751 goto free_netdev; 1752 } 1753 spin_lock_init(&mac->hw_stats->stats_lock); 1754 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 1755 1756 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 1757 eth->netdev[id]->watchdog_timeo = 5 * HZ; 1758 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 1759 eth->netdev[id]->base_addr = (unsigned long)eth->base; 1760 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 1761 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 1762 eth->netdev[id]->features |= MTK_HW_FEATURES; 1763 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 1764 1765 err = register_netdev(eth->netdev[id]); 1766 if (err) { 1767 dev_err(eth->dev, "error bringing up device\n"); 1768 goto free_netdev; 1769 } 1770 eth->netdev[id]->irq = eth->irq[0]; 1771 netif_info(eth, probe, eth->netdev[id], 1772 "mediatek frame engine at 0x%08lx, irq %d\n", 1773 eth->netdev[id]->base_addr, eth->irq[0]); 1774 1775 return 0; 1776 1777 free_netdev: 1778 free_netdev(eth->netdev[id]); 1779 return err; 1780 } 1781 1782 static int mtk_probe(struct platform_device *pdev) 1783 { 1784 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1785 struct device_node *mac_np; 1786 const struct of_device_id *match; 1787 struct mtk_soc_data *soc; 1788 struct mtk_eth *eth; 1789 int err; 1790 int i; 1791 1792 match = of_match_device(of_mtk_match, &pdev->dev); 1793 soc = (struct mtk_soc_data *)match->data; 1794 1795 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 1796 if (!eth) 1797 return -ENOMEM; 1798 1799 eth->base = devm_ioremap_resource(&pdev->dev, res); 1800 if (IS_ERR(eth->base)) 1801 return PTR_ERR(eth->base); 1802 1803 spin_lock_init(ð->page_lock); 1804 spin_lock_init(ð->irq_lock); 1805 1806 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1807 "mediatek,ethsys"); 1808 if (IS_ERR(eth->ethsys)) { 1809 dev_err(&pdev->dev, "no ethsys regmap found\n"); 1810 return PTR_ERR(eth->ethsys); 1811 } 1812 1813 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1814 "mediatek,pctl"); 1815 if (IS_ERR(eth->pctl)) { 1816 dev_err(&pdev->dev, "no pctl regmap found\n"); 1817 return PTR_ERR(eth->pctl); 1818 } 1819 1820 eth->rstc = devm_reset_control_get(&pdev->dev, "eth"); 1821 if (IS_ERR(eth->rstc)) { 1822 dev_err(&pdev->dev, "no eth reset found\n"); 1823 return PTR_ERR(eth->rstc); 1824 } 1825 1826 for (i = 0; i < 3; i++) { 1827 eth->irq[i] = platform_get_irq(pdev, i); 1828 if (eth->irq[i] < 0) { 1829 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 1830 return -ENXIO; 1831 } 1832 } 1833 1834 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif"); 1835 eth->clk_esw = devm_clk_get(&pdev->dev, "esw"); 1836 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1"); 1837 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2"); 1838 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) || 1839 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif)) 1840 return -ENODEV; 1841 1842 clk_prepare_enable(eth->clk_ethif); 1843 clk_prepare_enable(eth->clk_esw); 1844 clk_prepare_enable(eth->clk_gp1); 1845 clk_prepare_enable(eth->clk_gp2); 1846 1847 eth->dev = &pdev->dev; 1848 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 1849 INIT_WORK(ð->pending_work, mtk_pending_work); 1850 1851 err = mtk_hw_init(eth); 1852 if (err) 1853 return err; 1854 1855 for_each_child_of_node(pdev->dev.of_node, mac_np) { 1856 if (!of_device_is_compatible(mac_np, 1857 "mediatek,eth-mac")) 1858 continue; 1859 1860 if (!of_device_is_available(mac_np)) 1861 continue; 1862 1863 err = mtk_add_mac(eth, mac_np); 1864 if (err) 1865 goto err_free_dev; 1866 } 1867 1868 /* we run 2 devices on the same DMA ring so we need a dummy device 1869 * for NAPI to work 1870 */ 1871 init_dummy_netdev(ð->dummy_dev); 1872 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 1873 MTK_NAPI_WEIGHT); 1874 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 1875 MTK_NAPI_WEIGHT); 1876 1877 platform_set_drvdata(pdev, eth); 1878 1879 return 0; 1880 1881 err_free_dev: 1882 mtk_cleanup(eth); 1883 return err; 1884 } 1885 1886 static int mtk_remove(struct platform_device *pdev) 1887 { 1888 struct mtk_eth *eth = platform_get_drvdata(pdev); 1889 1890 clk_disable_unprepare(eth->clk_ethif); 1891 clk_disable_unprepare(eth->clk_esw); 1892 clk_disable_unprepare(eth->clk_gp1); 1893 clk_disable_unprepare(eth->clk_gp2); 1894 1895 netif_napi_del(ð->tx_napi); 1896 netif_napi_del(ð->rx_napi); 1897 mtk_cleanup(eth); 1898 platform_set_drvdata(pdev, NULL); 1899 1900 return 0; 1901 } 1902 1903 const struct of_device_id of_mtk_match[] = { 1904 { .compatible = "mediatek,mt7623-eth" }, 1905 {}, 1906 }; 1907 1908 static struct platform_driver mtk_driver = { 1909 .probe = mtk_probe, 1910 .remove = mtk_remove, 1911 .driver = { 1912 .name = "mtk_soc_eth", 1913 .of_match_table = of_mtk_match, 1914 }, 1915 }; 1916 1917 module_platform_driver(mtk_driver); 1918 1919 MODULE_LICENSE("GPL"); 1920 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 1921 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 1922