1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/clk.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/if_vlan.h> 19 #include <linux/reset.h> 20 #include <linux/tcp.h> 21 #include <linux/interrupt.h> 22 #include <linux/pinctrl/devinfo.h> 23 #include <linux/phylink.h> 24 #include <linux/pcs/pcs-mtk-lynxi.h> 25 #include <linux/jhash.h> 26 #include <linux/bitfield.h> 27 #include <net/dsa.h> 28 #include <net/dst_metadata.h> 29 30 #include "mtk_eth_soc.h" 31 #include "mtk_wed.h" 32 33 static int mtk_msg_level = -1; 34 module_param_named(msg_level, mtk_msg_level, int, 0); 35 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 36 37 #define MTK_ETHTOOL_STAT(x) { #x, \ 38 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 39 40 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 41 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 42 sizeof(u64) } 43 44 static const struct mtk_reg_map mtk_reg_map = { 45 .tx_irq_mask = 0x1a1c, 46 .tx_irq_status = 0x1a18, 47 .pdma = { 48 .rx_ptr = 0x0900, 49 .rx_cnt_cfg = 0x0904, 50 .pcrx_ptr = 0x0908, 51 .glo_cfg = 0x0a04, 52 .rst_idx = 0x0a08, 53 .delay_irq = 0x0a0c, 54 .irq_status = 0x0a20, 55 .irq_mask = 0x0a28, 56 .adma_rx_dbg0 = 0x0a38, 57 .int_grp = 0x0a50, 58 }, 59 .qdma = { 60 .qtx_cfg = 0x1800, 61 .qtx_sch = 0x1804, 62 .rx_ptr = 0x1900, 63 .rx_cnt_cfg = 0x1904, 64 .qcrx_ptr = 0x1908, 65 .glo_cfg = 0x1a04, 66 .rst_idx = 0x1a08, 67 .delay_irq = 0x1a0c, 68 .fc_th = 0x1a10, 69 .tx_sch_rate = 0x1a14, 70 .int_grp = 0x1a20, 71 .hred = 0x1a44, 72 .ctx_ptr = 0x1b00, 73 .dtx_ptr = 0x1b04, 74 .crx_ptr = 0x1b10, 75 .drx_ptr = 0x1b14, 76 .fq_head = 0x1b20, 77 .fq_tail = 0x1b24, 78 .fq_count = 0x1b28, 79 .fq_blen = 0x1b2c, 80 }, 81 .gdm1_cnt = 0x2400, 82 .gdma_to_ppe = 0x4444, 83 .ppe_base = 0x0c00, 84 .wdma_base = { 85 [0] = 0x2800, 86 [1] = 0x2c00, 87 }, 88 .pse_iq_sta = 0x0110, 89 .pse_oq_sta = 0x0118, 90 }; 91 92 static const struct mtk_reg_map mt7628_reg_map = { 93 .tx_irq_mask = 0x0a28, 94 .tx_irq_status = 0x0a20, 95 .pdma = { 96 .rx_ptr = 0x0900, 97 .rx_cnt_cfg = 0x0904, 98 .pcrx_ptr = 0x0908, 99 .glo_cfg = 0x0a04, 100 .rst_idx = 0x0a08, 101 .delay_irq = 0x0a0c, 102 .irq_status = 0x0a20, 103 .irq_mask = 0x0a28, 104 .int_grp = 0x0a50, 105 }, 106 }; 107 108 static const struct mtk_reg_map mt7986_reg_map = { 109 .tx_irq_mask = 0x461c, 110 .tx_irq_status = 0x4618, 111 .pdma = { 112 .rx_ptr = 0x6100, 113 .rx_cnt_cfg = 0x6104, 114 .pcrx_ptr = 0x6108, 115 .glo_cfg = 0x6204, 116 .rst_idx = 0x6208, 117 .delay_irq = 0x620c, 118 .irq_status = 0x6220, 119 .irq_mask = 0x6228, 120 .adma_rx_dbg0 = 0x6238, 121 .int_grp = 0x6250, 122 }, 123 .qdma = { 124 .qtx_cfg = 0x4400, 125 .qtx_sch = 0x4404, 126 .rx_ptr = 0x4500, 127 .rx_cnt_cfg = 0x4504, 128 .qcrx_ptr = 0x4508, 129 .glo_cfg = 0x4604, 130 .rst_idx = 0x4608, 131 .delay_irq = 0x460c, 132 .fc_th = 0x4610, 133 .int_grp = 0x4620, 134 .hred = 0x4644, 135 .ctx_ptr = 0x4700, 136 .dtx_ptr = 0x4704, 137 .crx_ptr = 0x4710, 138 .drx_ptr = 0x4714, 139 .fq_head = 0x4720, 140 .fq_tail = 0x4724, 141 .fq_count = 0x4728, 142 .fq_blen = 0x472c, 143 .tx_sch_rate = 0x4798, 144 }, 145 .gdm1_cnt = 0x1c00, 146 .gdma_to_ppe = 0x3333, 147 .ppe_base = 0x2000, 148 .wdma_base = { 149 [0] = 0x4800, 150 [1] = 0x4c00, 151 }, 152 .pse_iq_sta = 0x0180, 153 .pse_oq_sta = 0x01a0, 154 }; 155 156 static const struct mtk_reg_map mt7988_reg_map = { 157 .tx_irq_mask = 0x461c, 158 .tx_irq_status = 0x4618, 159 .pdma = { 160 .rx_ptr = 0x6900, 161 .rx_cnt_cfg = 0x6904, 162 .pcrx_ptr = 0x6908, 163 .glo_cfg = 0x6a04, 164 .rst_idx = 0x6a08, 165 .delay_irq = 0x6a0c, 166 .irq_status = 0x6a20, 167 .irq_mask = 0x6a28, 168 .adma_rx_dbg0 = 0x6a38, 169 .int_grp = 0x6a50, 170 }, 171 .qdma = { 172 .qtx_cfg = 0x4400, 173 .qtx_sch = 0x4404, 174 .rx_ptr = 0x4500, 175 .rx_cnt_cfg = 0x4504, 176 .qcrx_ptr = 0x4508, 177 .glo_cfg = 0x4604, 178 .rst_idx = 0x4608, 179 .delay_irq = 0x460c, 180 .fc_th = 0x4610, 181 .int_grp = 0x4620, 182 .hred = 0x4644, 183 .ctx_ptr = 0x4700, 184 .dtx_ptr = 0x4704, 185 .crx_ptr = 0x4710, 186 .drx_ptr = 0x4714, 187 .fq_head = 0x4720, 188 .fq_tail = 0x4724, 189 .fq_count = 0x4728, 190 .fq_blen = 0x472c, 191 .tx_sch_rate = 0x4798, 192 }, 193 .gdm1_cnt = 0x1c00, 194 .gdma_to_ppe = 0x3333, 195 .ppe_base = 0x2000, 196 .wdma_base = { 197 [0] = 0x4800, 198 [1] = 0x4c00, 199 }, 200 .pse_iq_sta = 0x0180, 201 .pse_oq_sta = 0x01a0, 202 }; 203 204 /* strings used by ethtool */ 205 static const struct mtk_ethtool_stats { 206 char str[ETH_GSTRING_LEN]; 207 u32 offset; 208 } mtk_ethtool_stats[] = { 209 MTK_ETHTOOL_STAT(tx_bytes), 210 MTK_ETHTOOL_STAT(tx_packets), 211 MTK_ETHTOOL_STAT(tx_skip), 212 MTK_ETHTOOL_STAT(tx_collisions), 213 MTK_ETHTOOL_STAT(rx_bytes), 214 MTK_ETHTOOL_STAT(rx_packets), 215 MTK_ETHTOOL_STAT(rx_overflow), 216 MTK_ETHTOOL_STAT(rx_fcs_errors), 217 MTK_ETHTOOL_STAT(rx_short_errors), 218 MTK_ETHTOOL_STAT(rx_long_errors), 219 MTK_ETHTOOL_STAT(rx_checksum_errors), 220 MTK_ETHTOOL_STAT(rx_flow_control_packets), 221 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 222 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 223 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 224 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 225 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 226 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 227 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 228 }; 229 230 static const char * const mtk_clks_source_name[] = { 231 "ethif", 232 "sgmiitop", 233 "esw", 234 "gp0", 235 "gp1", 236 "gp2", 237 "gp3", 238 "xgp1", 239 "xgp2", 240 "xgp3", 241 "crypto", 242 "fe", 243 "trgpll", 244 "sgmii_tx250m", 245 "sgmii_rx250m", 246 "sgmii_cdr_ref", 247 "sgmii_cdr_fb", 248 "sgmii2_tx250m", 249 "sgmii2_rx250m", 250 "sgmii2_cdr_ref", 251 "sgmii2_cdr_fb", 252 "sgmii_ck", 253 "eth2pll", 254 "wocpu0", 255 "wocpu1", 256 "netsys0", 257 "netsys1", 258 "ethwarp_wocpu2", 259 "ethwarp_wocpu1", 260 "ethwarp_wocpu0", 261 "top_usxgmii0_sel", 262 "top_usxgmii1_sel", 263 "top_sgm0_sel", 264 "top_sgm1_sel", 265 "top_xfi_phy0_xtal_sel", 266 "top_xfi_phy1_xtal_sel", 267 "top_eth_gmii_sel", 268 "top_eth_refck_50m_sel", 269 "top_eth_sys_200m_sel", 270 "top_eth_sys_sel", 271 "top_eth_xgmii_sel", 272 "top_eth_mii_sel", 273 "top_netsys_sel", 274 "top_netsys_500m_sel", 275 "top_netsys_pao_2x_sel", 276 "top_netsys_sync_250m_sel", 277 "top_netsys_ppefb_250m_sel", 278 "top_netsys_warp_sel", 279 }; 280 281 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 282 { 283 __raw_writel(val, eth->base + reg); 284 } 285 286 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 287 { 288 return __raw_readl(eth->base + reg); 289 } 290 291 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg) 292 { 293 u32 val; 294 295 val = mtk_r32(eth, reg); 296 val &= ~mask; 297 val |= set; 298 mtk_w32(eth, val, reg); 299 return reg; 300 } 301 302 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 303 { 304 unsigned long t_start = jiffies; 305 306 while (1) { 307 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 308 return 0; 309 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 310 break; 311 cond_resched(); 312 } 313 314 dev_err(eth->dev, "mdio: MDIO timeout\n"); 315 return -ETIMEDOUT; 316 } 317 318 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 319 u32 write_data) 320 { 321 int ret; 322 323 ret = mtk_mdio_busy_wait(eth); 324 if (ret < 0) 325 return ret; 326 327 mtk_w32(eth, PHY_IAC_ACCESS | 328 PHY_IAC_START_C22 | 329 PHY_IAC_CMD_WRITE | 330 PHY_IAC_REG(phy_reg) | 331 PHY_IAC_ADDR(phy_addr) | 332 PHY_IAC_DATA(write_data), 333 MTK_PHY_IAC); 334 335 ret = mtk_mdio_busy_wait(eth); 336 if (ret < 0) 337 return ret; 338 339 return 0; 340 } 341 342 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 343 u32 devad, u32 phy_reg, u32 write_data) 344 { 345 int ret; 346 347 ret = mtk_mdio_busy_wait(eth); 348 if (ret < 0) 349 return ret; 350 351 mtk_w32(eth, PHY_IAC_ACCESS | 352 PHY_IAC_START_C45 | 353 PHY_IAC_CMD_C45_ADDR | 354 PHY_IAC_REG(devad) | 355 PHY_IAC_ADDR(phy_addr) | 356 PHY_IAC_DATA(phy_reg), 357 MTK_PHY_IAC); 358 359 ret = mtk_mdio_busy_wait(eth); 360 if (ret < 0) 361 return ret; 362 363 mtk_w32(eth, PHY_IAC_ACCESS | 364 PHY_IAC_START_C45 | 365 PHY_IAC_CMD_WRITE | 366 PHY_IAC_REG(devad) | 367 PHY_IAC_ADDR(phy_addr) | 368 PHY_IAC_DATA(write_data), 369 MTK_PHY_IAC); 370 371 ret = mtk_mdio_busy_wait(eth); 372 if (ret < 0) 373 return ret; 374 375 return 0; 376 } 377 378 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 379 { 380 int ret; 381 382 ret = mtk_mdio_busy_wait(eth); 383 if (ret < 0) 384 return ret; 385 386 mtk_w32(eth, PHY_IAC_ACCESS | 387 PHY_IAC_START_C22 | 388 PHY_IAC_CMD_C22_READ | 389 PHY_IAC_REG(phy_reg) | 390 PHY_IAC_ADDR(phy_addr), 391 MTK_PHY_IAC); 392 393 ret = mtk_mdio_busy_wait(eth); 394 if (ret < 0) 395 return ret; 396 397 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 398 } 399 400 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 401 u32 devad, u32 phy_reg) 402 { 403 int ret; 404 405 ret = mtk_mdio_busy_wait(eth); 406 if (ret < 0) 407 return ret; 408 409 mtk_w32(eth, PHY_IAC_ACCESS | 410 PHY_IAC_START_C45 | 411 PHY_IAC_CMD_C45_ADDR | 412 PHY_IAC_REG(devad) | 413 PHY_IAC_ADDR(phy_addr) | 414 PHY_IAC_DATA(phy_reg), 415 MTK_PHY_IAC); 416 417 ret = mtk_mdio_busy_wait(eth); 418 if (ret < 0) 419 return ret; 420 421 mtk_w32(eth, PHY_IAC_ACCESS | 422 PHY_IAC_START_C45 | 423 PHY_IAC_CMD_C45_READ | 424 PHY_IAC_REG(devad) | 425 PHY_IAC_ADDR(phy_addr), 426 MTK_PHY_IAC); 427 428 ret = mtk_mdio_busy_wait(eth); 429 if (ret < 0) 430 return ret; 431 432 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 433 } 434 435 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 436 int phy_reg, u16 val) 437 { 438 struct mtk_eth *eth = bus->priv; 439 440 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 441 } 442 443 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 444 int devad, int phy_reg, u16 val) 445 { 446 struct mtk_eth *eth = bus->priv; 447 448 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 449 } 450 451 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 452 { 453 struct mtk_eth *eth = bus->priv; 454 455 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 456 } 457 458 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 459 int phy_reg) 460 { 461 struct mtk_eth *eth = bus->priv; 462 463 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 464 } 465 466 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 467 phy_interface_t interface) 468 { 469 u32 val; 470 471 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 472 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 473 474 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 475 ETHSYS_TRGMII_MT7621_MASK, val); 476 477 return 0; 478 } 479 480 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 481 phy_interface_t interface) 482 { 483 int ret; 484 485 if (interface == PHY_INTERFACE_MODE_TRGMII) { 486 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 487 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000); 488 if (ret) 489 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 490 return; 491 } 492 493 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); 494 } 495 496 static void mtk_setup_bridge_switch(struct mtk_eth *eth) 497 { 498 /* Force Port1 XGMAC Link Up */ 499 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), 500 MTK_XGMAC_STS(MTK_GMAC1_ID)); 501 502 /* Adjust GSW bridge IPG to 11 */ 503 mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, 504 (GSW_IPG_11 << GSWTX_IPG_SHIFT) | 505 (GSW_IPG_11 << GSWRX_IPG_SHIFT), 506 MTK_GSW_CFG); 507 } 508 509 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 510 phy_interface_t interface) 511 { 512 struct mtk_mac *mac = container_of(config, struct mtk_mac, 513 phylink_config); 514 struct mtk_eth *eth = mac->hw; 515 unsigned int sid; 516 517 if (interface == PHY_INTERFACE_MODE_SGMII || 518 phy_interface_mode_is_8023z(interface)) { 519 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 520 0 : mac->id; 521 522 return eth->sgmii_pcs[sid]; 523 } 524 525 return NULL; 526 } 527 528 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 529 const struct phylink_link_state *state) 530 { 531 struct mtk_mac *mac = container_of(config, struct mtk_mac, 532 phylink_config); 533 struct mtk_eth *eth = mac->hw; 534 int val, ge_mode, err = 0; 535 u32 i; 536 537 /* MT76x8 has no hardware settings between for the MAC */ 538 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 539 mac->interface != state->interface) { 540 /* Setup soc pin functions */ 541 switch (state->interface) { 542 case PHY_INTERFACE_MODE_TRGMII: 543 case PHY_INTERFACE_MODE_RGMII_TXID: 544 case PHY_INTERFACE_MODE_RGMII_RXID: 545 case PHY_INTERFACE_MODE_RGMII_ID: 546 case PHY_INTERFACE_MODE_RGMII: 547 case PHY_INTERFACE_MODE_MII: 548 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 549 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 550 if (err) 551 goto init_err; 552 } 553 break; 554 case PHY_INTERFACE_MODE_1000BASEX: 555 case PHY_INTERFACE_MODE_2500BASEX: 556 case PHY_INTERFACE_MODE_SGMII: 557 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 558 if (err) 559 goto init_err; 560 break; 561 case PHY_INTERFACE_MODE_GMII: 562 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 563 err = mtk_gmac_gephy_path_setup(eth, mac->id); 564 if (err) 565 goto init_err; 566 } 567 break; 568 case PHY_INTERFACE_MODE_INTERNAL: 569 break; 570 default: 571 goto err_phy; 572 } 573 574 /* Setup clock for 1st gmac */ 575 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 576 !phy_interface_mode_is_8023z(state->interface) && 577 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 578 if (MTK_HAS_CAPS(mac->hw->soc->caps, 579 MTK_TRGMII_MT7621_CLK)) { 580 if (mt7621_gmac0_rgmii_adjust(mac->hw, 581 state->interface)) 582 goto err_phy; 583 } else { 584 mtk_gmac0_rgmii_adjust(mac->hw, 585 state->interface); 586 587 /* mt7623_pad_clk_setup */ 588 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 589 mtk_w32(mac->hw, 590 TD_DM_DRVP(8) | TD_DM_DRVN(8), 591 TRGMII_TD_ODT(i)); 592 593 /* Assert/release MT7623 RXC reset */ 594 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 595 TRGMII_RCK_CTRL); 596 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 597 } 598 } 599 600 switch (state->interface) { 601 case PHY_INTERFACE_MODE_MII: 602 case PHY_INTERFACE_MODE_GMII: 603 ge_mode = 1; 604 break; 605 default: 606 ge_mode = 0; 607 break; 608 } 609 610 /* put the gmac into the right mode */ 611 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 612 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 613 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 614 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 615 616 mac->interface = state->interface; 617 } 618 619 /* SGMII */ 620 if (state->interface == PHY_INTERFACE_MODE_SGMII || 621 phy_interface_mode_is_8023z(state->interface)) { 622 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 623 * being setup done. 624 */ 625 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 626 627 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 628 SYSCFG0_SGMII_MASK, 629 ~(u32)SYSCFG0_SGMII_MASK); 630 631 /* Save the syscfg0 value for mac_finish */ 632 mac->syscfg0 = val; 633 } else if (phylink_autoneg_inband(mode)) { 634 dev_err(eth->dev, 635 "In-band mode not supported in non SGMII mode!\n"); 636 return; 637 } 638 639 /* Setup gmac */ 640 if (mtk_is_netsys_v3_or_greater(eth) && 641 mac->interface == PHY_INTERFACE_MODE_INTERNAL) { 642 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); 643 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); 644 645 mtk_setup_bridge_switch(eth); 646 } 647 648 return; 649 650 err_phy: 651 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 652 mac->id, phy_modes(state->interface)); 653 return; 654 655 init_err: 656 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 657 mac->id, phy_modes(state->interface), err); 658 } 659 660 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 661 phy_interface_t interface) 662 { 663 struct mtk_mac *mac = container_of(config, struct mtk_mac, 664 phylink_config); 665 struct mtk_eth *eth = mac->hw; 666 u32 mcr_cur, mcr_new; 667 668 /* Enable SGMII */ 669 if (interface == PHY_INTERFACE_MODE_SGMII || 670 phy_interface_mode_is_8023z(interface)) 671 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 672 SYSCFG0_SGMII_MASK, mac->syscfg0); 673 674 /* Setup gmac */ 675 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 676 mcr_new = mcr_cur; 677 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 678 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK | 679 MAC_MCR_RX_FIFO_CLR_DIS; 680 681 /* Only update control register when needed! */ 682 if (mcr_new != mcr_cur) 683 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 684 685 return 0; 686 } 687 688 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 689 phy_interface_t interface) 690 { 691 struct mtk_mac *mac = container_of(config, struct mtk_mac, 692 phylink_config); 693 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 694 695 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 696 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 697 } 698 699 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 700 int speed) 701 { 702 const struct mtk_soc_data *soc = eth->soc; 703 u32 ofs, val; 704 705 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 706 return; 707 708 val = MTK_QTX_SCH_MIN_RATE_EN | 709 /* minimum: 10 Mbps */ 710 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 711 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 712 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 713 if (mtk_is_netsys_v1(eth)) 714 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 715 716 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 717 switch (speed) { 718 case SPEED_10: 719 val |= MTK_QTX_SCH_MAX_RATE_EN | 720 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 721 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 722 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 723 break; 724 case SPEED_100: 725 val |= MTK_QTX_SCH_MAX_RATE_EN | 726 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 727 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3); 728 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 729 break; 730 case SPEED_1000: 731 val |= MTK_QTX_SCH_MAX_RATE_EN | 732 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 733 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 734 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 735 break; 736 default: 737 break; 738 } 739 } else { 740 switch (speed) { 741 case SPEED_10: 742 val |= MTK_QTX_SCH_MAX_RATE_EN | 743 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 744 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 745 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 746 break; 747 case SPEED_100: 748 val |= MTK_QTX_SCH_MAX_RATE_EN | 749 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 750 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5); 751 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 752 break; 753 case SPEED_1000: 754 val |= MTK_QTX_SCH_MAX_RATE_EN | 755 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) | 756 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 757 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 758 break; 759 default: 760 break; 761 } 762 } 763 764 ofs = MTK_QTX_OFFSET * idx; 765 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 766 } 767 768 static void mtk_mac_link_up(struct phylink_config *config, 769 struct phy_device *phy, 770 unsigned int mode, phy_interface_t interface, 771 int speed, int duplex, bool tx_pause, bool rx_pause) 772 { 773 struct mtk_mac *mac = container_of(config, struct mtk_mac, 774 phylink_config); 775 u32 mcr; 776 777 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 778 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 779 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 780 MAC_MCR_FORCE_RX_FC); 781 782 /* Configure speed */ 783 mac->speed = speed; 784 switch (speed) { 785 case SPEED_2500: 786 case SPEED_1000: 787 mcr |= MAC_MCR_SPEED_1000; 788 break; 789 case SPEED_100: 790 mcr |= MAC_MCR_SPEED_100; 791 break; 792 } 793 794 /* Configure duplex */ 795 if (duplex == DUPLEX_FULL) 796 mcr |= MAC_MCR_FORCE_DPX; 797 798 /* Configure pause modes - phylink will avoid these for half duplex */ 799 if (tx_pause) 800 mcr |= MAC_MCR_FORCE_TX_FC; 801 if (rx_pause) 802 mcr |= MAC_MCR_FORCE_RX_FC; 803 804 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 805 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 806 } 807 808 static const struct phylink_mac_ops mtk_phylink_ops = { 809 .mac_select_pcs = mtk_mac_select_pcs, 810 .mac_config = mtk_mac_config, 811 .mac_finish = mtk_mac_finish, 812 .mac_link_down = mtk_mac_link_down, 813 .mac_link_up = mtk_mac_link_up, 814 }; 815 816 static int mtk_mdio_init(struct mtk_eth *eth) 817 { 818 unsigned int max_clk = 2500000, divider; 819 struct device_node *mii_np; 820 int ret; 821 u32 val; 822 823 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 824 if (!mii_np) { 825 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 826 return -ENODEV; 827 } 828 829 if (!of_device_is_available(mii_np)) { 830 ret = -ENODEV; 831 goto err_put_node; 832 } 833 834 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 835 if (!eth->mii_bus) { 836 ret = -ENOMEM; 837 goto err_put_node; 838 } 839 840 eth->mii_bus->name = "mdio"; 841 eth->mii_bus->read = mtk_mdio_read_c22; 842 eth->mii_bus->write = mtk_mdio_write_c22; 843 eth->mii_bus->read_c45 = mtk_mdio_read_c45; 844 eth->mii_bus->write_c45 = mtk_mdio_write_c45; 845 eth->mii_bus->priv = eth; 846 eth->mii_bus->parent = eth->dev; 847 848 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 849 850 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { 851 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { 852 dev_err(eth->dev, "MDIO clock frequency out of range"); 853 ret = -EINVAL; 854 goto err_put_node; 855 } 856 max_clk = val; 857 } 858 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); 859 860 /* Configure MDC Turbo Mode */ 861 if (mtk_is_netsys_v3_or_greater(eth)) 862 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); 863 864 /* Configure MDC Divider */ 865 val = FIELD_PREP(PPSC_MDC_CFG, divider); 866 if (!mtk_is_netsys_v3_or_greater(eth)) 867 val |= PPSC_MDC_TURBO; 868 mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC); 869 870 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); 871 872 ret = of_mdiobus_register(eth->mii_bus, mii_np); 873 874 err_put_node: 875 of_node_put(mii_np); 876 return ret; 877 } 878 879 static void mtk_mdio_cleanup(struct mtk_eth *eth) 880 { 881 if (!eth->mii_bus) 882 return; 883 884 mdiobus_unregister(eth->mii_bus); 885 } 886 887 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 888 { 889 unsigned long flags; 890 u32 val; 891 892 spin_lock_irqsave(ð->tx_irq_lock, flags); 893 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 894 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 895 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 896 } 897 898 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 899 { 900 unsigned long flags; 901 u32 val; 902 903 spin_lock_irqsave(ð->tx_irq_lock, flags); 904 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 905 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 906 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 907 } 908 909 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 910 { 911 unsigned long flags; 912 u32 val; 913 914 spin_lock_irqsave(ð->rx_irq_lock, flags); 915 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 916 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 917 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 918 } 919 920 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 921 { 922 unsigned long flags; 923 u32 val; 924 925 spin_lock_irqsave(ð->rx_irq_lock, flags); 926 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 927 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 928 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 929 } 930 931 static int mtk_set_mac_address(struct net_device *dev, void *p) 932 { 933 int ret = eth_mac_addr(dev, p); 934 struct mtk_mac *mac = netdev_priv(dev); 935 struct mtk_eth *eth = mac->hw; 936 const char *macaddr = dev->dev_addr; 937 938 if (ret) 939 return ret; 940 941 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 942 return -EBUSY; 943 944 spin_lock_bh(&mac->hw->page_lock); 945 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 946 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 947 MT7628_SDM_MAC_ADRH); 948 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 949 (macaddr[4] << 8) | macaddr[5], 950 MT7628_SDM_MAC_ADRL); 951 } else { 952 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 953 MTK_GDMA_MAC_ADRH(mac->id)); 954 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 955 (macaddr[4] << 8) | macaddr[5], 956 MTK_GDMA_MAC_ADRL(mac->id)); 957 } 958 spin_unlock_bh(&mac->hw->page_lock); 959 960 return 0; 961 } 962 963 void mtk_stats_update_mac(struct mtk_mac *mac) 964 { 965 struct mtk_hw_stats *hw_stats = mac->hw_stats; 966 struct mtk_eth *eth = mac->hw; 967 968 u64_stats_update_begin(&hw_stats->syncp); 969 970 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 971 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 972 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 973 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 974 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 975 hw_stats->rx_checksum_errors += 976 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 977 } else { 978 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 979 unsigned int offs = hw_stats->reg_offset; 980 u64 stats; 981 982 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 983 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 984 if (stats) 985 hw_stats->rx_bytes += (stats << 32); 986 hw_stats->rx_packets += 987 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 988 hw_stats->rx_overflow += 989 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 990 hw_stats->rx_fcs_errors += 991 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 992 hw_stats->rx_short_errors += 993 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 994 hw_stats->rx_long_errors += 995 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 996 hw_stats->rx_checksum_errors += 997 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 998 hw_stats->rx_flow_control_packets += 999 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 1000 1001 if (mtk_is_netsys_v3_or_greater(eth)) { 1002 hw_stats->tx_skip += 1003 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); 1004 hw_stats->tx_collisions += 1005 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); 1006 hw_stats->tx_bytes += 1007 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); 1008 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); 1009 if (stats) 1010 hw_stats->tx_bytes += (stats << 32); 1011 hw_stats->tx_packets += 1012 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); 1013 } else { 1014 hw_stats->tx_skip += 1015 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 1016 hw_stats->tx_collisions += 1017 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 1018 hw_stats->tx_bytes += 1019 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 1020 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 1021 if (stats) 1022 hw_stats->tx_bytes += (stats << 32); 1023 hw_stats->tx_packets += 1024 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 1025 } 1026 } 1027 1028 u64_stats_update_end(&hw_stats->syncp); 1029 } 1030 1031 static void mtk_stats_update(struct mtk_eth *eth) 1032 { 1033 int i; 1034 1035 for (i = 0; i < MTK_MAX_DEVS; i++) { 1036 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 1037 continue; 1038 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 1039 mtk_stats_update_mac(eth->mac[i]); 1040 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 1041 } 1042 } 1043 } 1044 1045 static void mtk_get_stats64(struct net_device *dev, 1046 struct rtnl_link_stats64 *storage) 1047 { 1048 struct mtk_mac *mac = netdev_priv(dev); 1049 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1050 unsigned int start; 1051 1052 if (netif_running(dev) && netif_device_present(dev)) { 1053 if (spin_trylock_bh(&hw_stats->stats_lock)) { 1054 mtk_stats_update_mac(mac); 1055 spin_unlock_bh(&hw_stats->stats_lock); 1056 } 1057 } 1058 1059 do { 1060 start = u64_stats_fetch_begin(&hw_stats->syncp); 1061 storage->rx_packets = hw_stats->rx_packets; 1062 storage->tx_packets = hw_stats->tx_packets; 1063 storage->rx_bytes = hw_stats->rx_bytes; 1064 storage->tx_bytes = hw_stats->tx_bytes; 1065 storage->collisions = hw_stats->tx_collisions; 1066 storage->rx_length_errors = hw_stats->rx_short_errors + 1067 hw_stats->rx_long_errors; 1068 storage->rx_over_errors = hw_stats->rx_overflow; 1069 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 1070 storage->rx_errors = hw_stats->rx_checksum_errors; 1071 storage->tx_aborted_errors = hw_stats->tx_skip; 1072 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 1073 1074 storage->tx_errors = dev->stats.tx_errors; 1075 storage->rx_dropped = dev->stats.rx_dropped; 1076 storage->tx_dropped = dev->stats.tx_dropped; 1077 } 1078 1079 static inline int mtk_max_frag_size(int mtu) 1080 { 1081 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 1082 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 1083 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 1084 1085 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 1086 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1087 } 1088 1089 static inline int mtk_max_buf_size(int frag_size) 1090 { 1091 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 1092 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1093 1094 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 1095 1096 return buf_size; 1097 } 1098 1099 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 1100 struct mtk_rx_dma_v2 *dma_rxd) 1101 { 1102 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 1103 if (!(rxd->rxd2 & RX_DMA_DONE)) 1104 return false; 1105 1106 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 1107 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 1108 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 1109 if (mtk_is_netsys_v2_or_greater(eth)) { 1110 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 1111 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 1112 } 1113 1114 return true; 1115 } 1116 1117 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 1118 { 1119 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 1120 unsigned long data; 1121 1122 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 1123 get_order(size)); 1124 1125 return (void *)data; 1126 } 1127 1128 /* the qdma core needs scratch memory to be setup */ 1129 static int mtk_init_fq_dma(struct mtk_eth *eth) 1130 { 1131 const struct mtk_soc_data *soc = eth->soc; 1132 dma_addr_t phy_ring_tail; 1133 int cnt = MTK_QDMA_RING_SIZE; 1134 dma_addr_t dma_addr; 1135 int i; 1136 1137 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 1138 cnt * soc->txrx.txd_size, 1139 ð->phy_scratch_ring, 1140 GFP_KERNEL); 1141 if (unlikely(!eth->scratch_ring)) 1142 return -ENOMEM; 1143 1144 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1145 if (unlikely(!eth->scratch_head)) 1146 return -ENOMEM; 1147 1148 dma_addr = dma_map_single(eth->dma_dev, 1149 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 1150 DMA_FROM_DEVICE); 1151 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1152 return -ENOMEM; 1153 1154 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); 1155 1156 for (i = 0; i < cnt; i++) { 1157 struct mtk_tx_dma_v2 *txd; 1158 1159 txd = eth->scratch_ring + i * soc->txrx.txd_size; 1160 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1161 if (i < cnt - 1) 1162 txd->txd2 = eth->phy_scratch_ring + 1163 (i + 1) * soc->txrx.txd_size; 1164 1165 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1166 txd->txd4 = 0; 1167 if (mtk_is_netsys_v2_or_greater(eth)) { 1168 txd->txd5 = 0; 1169 txd->txd6 = 0; 1170 txd->txd7 = 0; 1171 txd->txd8 = 0; 1172 } 1173 } 1174 1175 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1176 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1177 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1178 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1179 1180 return 0; 1181 } 1182 1183 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1184 { 1185 return ring->dma + (desc - ring->phys); 1186 } 1187 1188 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1189 void *txd, u32 txd_size) 1190 { 1191 int idx = (txd - ring->dma) / txd_size; 1192 1193 return &ring->buf[idx]; 1194 } 1195 1196 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1197 struct mtk_tx_dma *dma) 1198 { 1199 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1200 } 1201 1202 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1203 { 1204 return (dma - ring->dma) / txd_size; 1205 } 1206 1207 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1208 struct xdp_frame_bulk *bq, bool napi) 1209 { 1210 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1211 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1212 dma_unmap_single(eth->dma_dev, 1213 dma_unmap_addr(tx_buf, dma_addr0), 1214 dma_unmap_len(tx_buf, dma_len0), 1215 DMA_TO_DEVICE); 1216 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1217 dma_unmap_page(eth->dma_dev, 1218 dma_unmap_addr(tx_buf, dma_addr0), 1219 dma_unmap_len(tx_buf, dma_len0), 1220 DMA_TO_DEVICE); 1221 } 1222 } else { 1223 if (dma_unmap_len(tx_buf, dma_len0)) { 1224 dma_unmap_page(eth->dma_dev, 1225 dma_unmap_addr(tx_buf, dma_addr0), 1226 dma_unmap_len(tx_buf, dma_len0), 1227 DMA_TO_DEVICE); 1228 } 1229 1230 if (dma_unmap_len(tx_buf, dma_len1)) { 1231 dma_unmap_page(eth->dma_dev, 1232 dma_unmap_addr(tx_buf, dma_addr1), 1233 dma_unmap_len(tx_buf, dma_len1), 1234 DMA_TO_DEVICE); 1235 } 1236 } 1237 1238 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1239 if (tx_buf->type == MTK_TYPE_SKB) { 1240 struct sk_buff *skb = tx_buf->data; 1241 1242 if (napi) 1243 napi_consume_skb(skb, napi); 1244 else 1245 dev_kfree_skb_any(skb); 1246 } else { 1247 struct xdp_frame *xdpf = tx_buf->data; 1248 1249 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1250 xdp_return_frame_rx_napi(xdpf); 1251 else if (bq) 1252 xdp_return_frame_bulk(xdpf, bq); 1253 else 1254 xdp_return_frame(xdpf); 1255 } 1256 } 1257 tx_buf->flags = 0; 1258 tx_buf->data = NULL; 1259 } 1260 1261 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1262 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1263 size_t size, int idx) 1264 { 1265 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1266 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1267 dma_unmap_len_set(tx_buf, dma_len0, size); 1268 } else { 1269 if (idx & 1) { 1270 txd->txd3 = mapped_addr; 1271 txd->txd2 |= TX_DMA_PLEN1(size); 1272 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1273 dma_unmap_len_set(tx_buf, dma_len1, size); 1274 } else { 1275 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1276 txd->txd1 = mapped_addr; 1277 txd->txd2 = TX_DMA_PLEN0(size); 1278 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1279 dma_unmap_len_set(tx_buf, dma_len0, size); 1280 } 1281 } 1282 } 1283 1284 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1285 struct mtk_tx_dma_desc_info *info) 1286 { 1287 struct mtk_mac *mac = netdev_priv(dev); 1288 struct mtk_eth *eth = mac->hw; 1289 struct mtk_tx_dma *desc = txd; 1290 u32 data; 1291 1292 WRITE_ONCE(desc->txd1, info->addr); 1293 1294 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1295 FIELD_PREP(TX_DMA_PQID, info->qid); 1296 if (info->last) 1297 data |= TX_DMA_LS0; 1298 WRITE_ONCE(desc->txd3, data); 1299 1300 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1301 if (info->first) { 1302 if (info->gso) 1303 data |= TX_DMA_TSO; 1304 /* tx checksum offload */ 1305 if (info->csum) 1306 data |= TX_DMA_CHKSUM; 1307 /* vlan header offload */ 1308 if (info->vlan) 1309 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1310 } 1311 WRITE_ONCE(desc->txd4, data); 1312 } 1313 1314 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1315 struct mtk_tx_dma_desc_info *info) 1316 { 1317 struct mtk_mac *mac = netdev_priv(dev); 1318 struct mtk_tx_dma_v2 *desc = txd; 1319 struct mtk_eth *eth = mac->hw; 1320 u32 data; 1321 1322 WRITE_ONCE(desc->txd1, info->addr); 1323 1324 data = TX_DMA_PLEN0(info->size); 1325 if (info->last) 1326 data |= TX_DMA_LS0; 1327 WRITE_ONCE(desc->txd3, data); 1328 1329 /* set forward port */ 1330 switch (mac->id) { 1331 case MTK_GMAC1_ID: 1332 data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; 1333 break; 1334 case MTK_GMAC2_ID: 1335 data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; 1336 break; 1337 case MTK_GMAC3_ID: 1338 data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; 1339 break; 1340 } 1341 1342 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1343 WRITE_ONCE(desc->txd4, data); 1344 1345 data = 0; 1346 if (info->first) { 1347 if (info->gso) 1348 data |= TX_DMA_TSO_V2; 1349 /* tx checksum offload */ 1350 if (info->csum) 1351 data |= TX_DMA_CHKSUM_V2; 1352 if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev)) 1353 data |= TX_DMA_SPTAG_V3; 1354 } 1355 WRITE_ONCE(desc->txd5, data); 1356 1357 data = 0; 1358 if (info->first && info->vlan) 1359 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1360 WRITE_ONCE(desc->txd6, data); 1361 1362 WRITE_ONCE(desc->txd7, 0); 1363 WRITE_ONCE(desc->txd8, 0); 1364 } 1365 1366 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1367 struct mtk_tx_dma_desc_info *info) 1368 { 1369 struct mtk_mac *mac = netdev_priv(dev); 1370 struct mtk_eth *eth = mac->hw; 1371 1372 if (mtk_is_netsys_v2_or_greater(eth)) 1373 mtk_tx_set_dma_desc_v2(dev, txd, info); 1374 else 1375 mtk_tx_set_dma_desc_v1(dev, txd, info); 1376 } 1377 1378 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1379 int tx_num, struct mtk_tx_ring *ring, bool gso) 1380 { 1381 struct mtk_tx_dma_desc_info txd_info = { 1382 .size = skb_headlen(skb), 1383 .gso = gso, 1384 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1385 .vlan = skb_vlan_tag_present(skb), 1386 .qid = skb_get_queue_mapping(skb), 1387 .vlan_tci = skb_vlan_tag_get(skb), 1388 .first = true, 1389 .last = !skb_is_nonlinear(skb), 1390 }; 1391 struct netdev_queue *txq; 1392 struct mtk_mac *mac = netdev_priv(dev); 1393 struct mtk_eth *eth = mac->hw; 1394 const struct mtk_soc_data *soc = eth->soc; 1395 struct mtk_tx_dma *itxd, *txd; 1396 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1397 struct mtk_tx_buf *itx_buf, *tx_buf; 1398 int i, n_desc = 1; 1399 int queue = skb_get_queue_mapping(skb); 1400 int k = 0; 1401 1402 txq = netdev_get_tx_queue(dev, queue); 1403 itxd = ring->next_free; 1404 itxd_pdma = qdma_to_pdma(ring, itxd); 1405 if (itxd == ring->last_free) 1406 return -ENOMEM; 1407 1408 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1409 memset(itx_buf, 0, sizeof(*itx_buf)); 1410 1411 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1412 DMA_TO_DEVICE); 1413 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1414 return -ENOMEM; 1415 1416 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1417 1418 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1419 itx_buf->mac_id = mac->id; 1420 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1421 k++); 1422 1423 /* TX SG offload */ 1424 txd = itxd; 1425 txd_pdma = qdma_to_pdma(ring, txd); 1426 1427 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1428 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1429 unsigned int offset = 0; 1430 int frag_size = skb_frag_size(frag); 1431 1432 while (frag_size) { 1433 bool new_desc = true; 1434 1435 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1436 (i & 0x1)) { 1437 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1438 txd_pdma = qdma_to_pdma(ring, txd); 1439 if (txd == ring->last_free) 1440 goto err_dma; 1441 1442 n_desc++; 1443 } else { 1444 new_desc = false; 1445 } 1446 1447 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1448 txd_info.size = min_t(unsigned int, frag_size, 1449 soc->txrx.dma_max_len); 1450 txd_info.qid = queue; 1451 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1452 !(frag_size - txd_info.size); 1453 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1454 offset, txd_info.size, 1455 DMA_TO_DEVICE); 1456 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1457 goto err_dma; 1458 1459 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1460 1461 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1462 soc->txrx.txd_size); 1463 if (new_desc) 1464 memset(tx_buf, 0, sizeof(*tx_buf)); 1465 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1466 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1467 tx_buf->mac_id = mac->id; 1468 1469 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1470 txd_info.size, k++); 1471 1472 frag_size -= txd_info.size; 1473 offset += txd_info.size; 1474 } 1475 } 1476 1477 /* store skb to cleanup */ 1478 itx_buf->type = MTK_TYPE_SKB; 1479 itx_buf->data = skb; 1480 1481 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1482 if (k & 0x1) 1483 txd_pdma->txd2 |= TX_DMA_LS0; 1484 else 1485 txd_pdma->txd2 |= TX_DMA_LS1; 1486 } 1487 1488 netdev_tx_sent_queue(txq, skb->len); 1489 skb_tx_timestamp(skb); 1490 1491 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1492 atomic_sub(n_desc, &ring->free_count); 1493 1494 /* make sure that all changes to the dma ring are flushed before we 1495 * continue 1496 */ 1497 wmb(); 1498 1499 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1500 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1501 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1502 } else { 1503 int next_idx; 1504 1505 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), 1506 ring->dma_size); 1507 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1508 } 1509 1510 return 0; 1511 1512 err_dma: 1513 do { 1514 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1515 1516 /* unmap dma */ 1517 mtk_tx_unmap(eth, tx_buf, NULL, false); 1518 1519 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1520 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1521 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1522 1523 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1524 itxd_pdma = qdma_to_pdma(ring, itxd); 1525 } while (itxd != txd); 1526 1527 return -ENOMEM; 1528 } 1529 1530 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1531 { 1532 int i, nfrags = 1; 1533 skb_frag_t *frag; 1534 1535 if (skb_is_gso(skb)) { 1536 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1537 frag = &skb_shinfo(skb)->frags[i]; 1538 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1539 eth->soc->txrx.dma_max_len); 1540 } 1541 } else { 1542 nfrags += skb_shinfo(skb)->nr_frags; 1543 } 1544 1545 return nfrags; 1546 } 1547 1548 static int mtk_queue_stopped(struct mtk_eth *eth) 1549 { 1550 int i; 1551 1552 for (i = 0; i < MTK_MAX_DEVS; i++) { 1553 if (!eth->netdev[i]) 1554 continue; 1555 if (netif_queue_stopped(eth->netdev[i])) 1556 return 1; 1557 } 1558 1559 return 0; 1560 } 1561 1562 static void mtk_wake_queue(struct mtk_eth *eth) 1563 { 1564 int i; 1565 1566 for (i = 0; i < MTK_MAX_DEVS; i++) { 1567 if (!eth->netdev[i]) 1568 continue; 1569 netif_tx_wake_all_queues(eth->netdev[i]); 1570 } 1571 } 1572 1573 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1574 { 1575 struct mtk_mac *mac = netdev_priv(dev); 1576 struct mtk_eth *eth = mac->hw; 1577 struct mtk_tx_ring *ring = ð->tx_ring; 1578 struct net_device_stats *stats = &dev->stats; 1579 bool gso = false; 1580 int tx_num; 1581 1582 /* normally we can rely on the stack not calling this more than once, 1583 * however we have 2 queues running on the same ring so we need to lock 1584 * the ring access 1585 */ 1586 spin_lock(ð->page_lock); 1587 1588 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1589 goto drop; 1590 1591 tx_num = mtk_cal_txd_req(eth, skb); 1592 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1593 netif_tx_stop_all_queues(dev); 1594 netif_err(eth, tx_queued, dev, 1595 "Tx Ring full when queue awake!\n"); 1596 spin_unlock(ð->page_lock); 1597 return NETDEV_TX_BUSY; 1598 } 1599 1600 /* TSO: fill MSS info in tcp checksum field */ 1601 if (skb_is_gso(skb)) { 1602 if (skb_cow_head(skb, 0)) { 1603 netif_warn(eth, tx_err, dev, 1604 "GSO expand head fail.\n"); 1605 goto drop; 1606 } 1607 1608 if (skb_shinfo(skb)->gso_type & 1609 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1610 gso = true; 1611 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1612 } 1613 } 1614 1615 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1616 goto drop; 1617 1618 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1619 netif_tx_stop_all_queues(dev); 1620 1621 spin_unlock(ð->page_lock); 1622 1623 return NETDEV_TX_OK; 1624 1625 drop: 1626 spin_unlock(ð->page_lock); 1627 stats->tx_dropped++; 1628 dev_kfree_skb_any(skb); 1629 return NETDEV_TX_OK; 1630 } 1631 1632 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1633 { 1634 int i; 1635 struct mtk_rx_ring *ring; 1636 int idx; 1637 1638 if (!eth->hwlro) 1639 return ð->rx_ring[0]; 1640 1641 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1642 struct mtk_rx_dma *rxd; 1643 1644 ring = ð->rx_ring[i]; 1645 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1646 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1647 if (rxd->rxd2 & RX_DMA_DONE) { 1648 ring->calc_idx_update = true; 1649 return ring; 1650 } 1651 } 1652 1653 return NULL; 1654 } 1655 1656 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1657 { 1658 struct mtk_rx_ring *ring; 1659 int i; 1660 1661 if (!eth->hwlro) { 1662 ring = ð->rx_ring[0]; 1663 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1664 } else { 1665 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1666 ring = ð->rx_ring[i]; 1667 if (ring->calc_idx_update) { 1668 ring->calc_idx_update = false; 1669 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1670 } 1671 } 1672 } 1673 } 1674 1675 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1676 { 1677 return mtk_is_netsys_v2_or_greater(eth); 1678 } 1679 1680 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1681 struct xdp_rxq_info *xdp_q, 1682 int id, int size) 1683 { 1684 struct page_pool_params pp_params = { 1685 .order = 0, 1686 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1687 .pool_size = size, 1688 .nid = NUMA_NO_NODE, 1689 .dev = eth->dma_dev, 1690 .offset = MTK_PP_HEADROOM, 1691 .max_len = MTK_PP_MAX_BUF_SIZE, 1692 }; 1693 struct page_pool *pp; 1694 int err; 1695 1696 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1697 : DMA_FROM_DEVICE; 1698 pp = page_pool_create(&pp_params); 1699 if (IS_ERR(pp)) 1700 return pp; 1701 1702 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, id, 1703 eth->rx_napi.napi_id, PAGE_SIZE); 1704 if (err < 0) 1705 goto err_free_pp; 1706 1707 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1708 if (err) 1709 goto err_unregister_rxq; 1710 1711 return pp; 1712 1713 err_unregister_rxq: 1714 xdp_rxq_info_unreg(xdp_q); 1715 err_free_pp: 1716 page_pool_destroy(pp); 1717 1718 return ERR_PTR(err); 1719 } 1720 1721 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1722 gfp_t gfp_mask) 1723 { 1724 struct page *page; 1725 1726 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1727 if (!page) 1728 return NULL; 1729 1730 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1731 return page_address(page); 1732 } 1733 1734 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1735 { 1736 if (ring->page_pool) 1737 page_pool_put_full_page(ring->page_pool, 1738 virt_to_head_page(data), napi); 1739 else 1740 skb_free_frag(data); 1741 } 1742 1743 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1744 struct mtk_tx_dma_desc_info *txd_info, 1745 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1746 void *data, u16 headroom, int index, bool dma_map) 1747 { 1748 struct mtk_tx_ring *ring = ð->tx_ring; 1749 struct mtk_mac *mac = netdev_priv(dev); 1750 struct mtk_tx_dma *txd_pdma; 1751 1752 if (dma_map) { /* ndo_xdp_xmit */ 1753 txd_info->addr = dma_map_single(eth->dma_dev, data, 1754 txd_info->size, DMA_TO_DEVICE); 1755 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1756 return -ENOMEM; 1757 1758 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1759 } else { 1760 struct page *page = virt_to_head_page(data); 1761 1762 txd_info->addr = page_pool_get_dma_addr(page) + 1763 sizeof(struct xdp_frame) + headroom; 1764 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1765 txd_info->size, DMA_BIDIRECTIONAL); 1766 } 1767 mtk_tx_set_dma_desc(dev, txd, txd_info); 1768 1769 tx_buf->mac_id = mac->id; 1770 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1771 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1772 1773 txd_pdma = qdma_to_pdma(ring, txd); 1774 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1775 index); 1776 1777 return 0; 1778 } 1779 1780 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1781 struct net_device *dev, bool dma_map) 1782 { 1783 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1784 const struct mtk_soc_data *soc = eth->soc; 1785 struct mtk_tx_ring *ring = ð->tx_ring; 1786 struct mtk_mac *mac = netdev_priv(dev); 1787 struct mtk_tx_dma_desc_info txd_info = { 1788 .size = xdpf->len, 1789 .first = true, 1790 .last = !xdp_frame_has_frags(xdpf), 1791 .qid = mac->id, 1792 }; 1793 int err, index = 0, n_desc = 1, nr_frags; 1794 struct mtk_tx_buf *htx_buf, *tx_buf; 1795 struct mtk_tx_dma *htxd, *txd; 1796 void *data = xdpf->data; 1797 1798 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1799 return -EBUSY; 1800 1801 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1802 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1803 return -EBUSY; 1804 1805 spin_lock(ð->page_lock); 1806 1807 txd = ring->next_free; 1808 if (txd == ring->last_free) { 1809 spin_unlock(ð->page_lock); 1810 return -ENOMEM; 1811 } 1812 htxd = txd; 1813 1814 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); 1815 memset(tx_buf, 0, sizeof(*tx_buf)); 1816 htx_buf = tx_buf; 1817 1818 for (;;) { 1819 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1820 data, xdpf->headroom, index, dma_map); 1821 if (err < 0) 1822 goto unmap; 1823 1824 if (txd_info.last) 1825 break; 1826 1827 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1828 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1829 if (txd == ring->last_free) 1830 goto unmap; 1831 1832 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1833 soc->txrx.txd_size); 1834 memset(tx_buf, 0, sizeof(*tx_buf)); 1835 n_desc++; 1836 } 1837 1838 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1839 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1840 txd_info.last = index + 1 == nr_frags; 1841 txd_info.qid = mac->id; 1842 data = skb_frag_address(&sinfo->frags[index]); 1843 1844 index++; 1845 } 1846 /* store xdpf for cleanup */ 1847 htx_buf->data = xdpf; 1848 1849 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1850 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1851 1852 if (index & 1) 1853 txd_pdma->txd2 |= TX_DMA_LS0; 1854 else 1855 txd_pdma->txd2 |= TX_DMA_LS1; 1856 } 1857 1858 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1859 atomic_sub(n_desc, &ring->free_count); 1860 1861 /* make sure that all changes to the dma ring are flushed before we 1862 * continue 1863 */ 1864 wmb(); 1865 1866 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1867 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1868 } else { 1869 int idx; 1870 1871 idx = txd_to_idx(ring, txd, soc->txrx.txd_size); 1872 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1873 MT7628_TX_CTX_IDX0); 1874 } 1875 1876 spin_unlock(ð->page_lock); 1877 1878 return 0; 1879 1880 unmap: 1881 while (htxd != txd) { 1882 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); 1883 mtk_tx_unmap(eth, tx_buf, NULL, false); 1884 1885 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1886 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1887 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1888 1889 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1890 } 1891 1892 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1893 } 1894 1895 spin_unlock(ð->page_lock); 1896 1897 return err; 1898 } 1899 1900 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1901 struct xdp_frame **frames, u32 flags) 1902 { 1903 struct mtk_mac *mac = netdev_priv(dev); 1904 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1905 struct mtk_eth *eth = mac->hw; 1906 int i, nxmit = 0; 1907 1908 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1909 return -EINVAL; 1910 1911 for (i = 0; i < num_frame; i++) { 1912 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1913 break; 1914 nxmit++; 1915 } 1916 1917 u64_stats_update_begin(&hw_stats->syncp); 1918 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1919 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1920 u64_stats_update_end(&hw_stats->syncp); 1921 1922 return nxmit; 1923 } 1924 1925 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1926 struct xdp_buff *xdp, struct net_device *dev) 1927 { 1928 struct mtk_mac *mac = netdev_priv(dev); 1929 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1930 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 1931 struct bpf_prog *prog; 1932 u32 act = XDP_PASS; 1933 1934 rcu_read_lock(); 1935 1936 prog = rcu_dereference(eth->prog); 1937 if (!prog) 1938 goto out; 1939 1940 act = bpf_prog_run_xdp(prog, xdp); 1941 switch (act) { 1942 case XDP_PASS: 1943 count = &hw_stats->xdp_stats.rx_xdp_pass; 1944 goto update_stats; 1945 case XDP_REDIRECT: 1946 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 1947 act = XDP_DROP; 1948 break; 1949 } 1950 1951 count = &hw_stats->xdp_stats.rx_xdp_redirect; 1952 goto update_stats; 1953 case XDP_TX: { 1954 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 1955 1956 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 1957 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 1958 act = XDP_DROP; 1959 break; 1960 } 1961 1962 count = &hw_stats->xdp_stats.rx_xdp_tx; 1963 goto update_stats; 1964 } 1965 default: 1966 bpf_warn_invalid_xdp_action(dev, prog, act); 1967 fallthrough; 1968 case XDP_ABORTED: 1969 trace_xdp_exception(dev, prog, act); 1970 fallthrough; 1971 case XDP_DROP: 1972 break; 1973 } 1974 1975 page_pool_put_full_page(ring->page_pool, 1976 virt_to_head_page(xdp->data), true); 1977 1978 update_stats: 1979 u64_stats_update_begin(&hw_stats->syncp); 1980 *count = *count + 1; 1981 u64_stats_update_end(&hw_stats->syncp); 1982 out: 1983 rcu_read_unlock(); 1984 1985 return act; 1986 } 1987 1988 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1989 struct mtk_eth *eth) 1990 { 1991 struct dim_sample dim_sample = {}; 1992 struct mtk_rx_ring *ring; 1993 bool xdp_flush = false; 1994 int idx; 1995 struct sk_buff *skb; 1996 u8 *data, *new_data; 1997 struct mtk_rx_dma_v2 *rxd, trxd; 1998 int done = 0, bytes = 0; 1999 2000 while (done < budget) { 2001 unsigned int pktlen, *rxdcsum; 2002 struct net_device *netdev; 2003 dma_addr_t dma_addr; 2004 u32 hash, reason; 2005 int mac = 0; 2006 2007 ring = mtk_get_rx_ring(eth); 2008 if (unlikely(!ring)) 2009 goto rx_done; 2010 2011 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 2012 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 2013 data = ring->data[idx]; 2014 2015 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 2016 break; 2017 2018 /* find out which mac the packet come from. values start at 1 */ 2019 if (mtk_is_netsys_v2_or_greater(eth)) { 2020 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); 2021 2022 switch (val) { 2023 case PSE_GDM1_PORT: 2024 case PSE_GDM2_PORT: 2025 mac = val - 1; 2026 break; 2027 case PSE_GDM3_PORT: 2028 mac = MTK_GMAC3_ID; 2029 break; 2030 default: 2031 break; 2032 } 2033 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 2034 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { 2035 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 2036 } 2037 2038 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || 2039 !eth->netdev[mac])) 2040 goto release_desc; 2041 2042 netdev = eth->netdev[mac]; 2043 2044 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 2045 goto release_desc; 2046 2047 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 2048 2049 /* alloc new buffer */ 2050 if (ring->page_pool) { 2051 struct page *page = virt_to_head_page(data); 2052 struct xdp_buff xdp; 2053 u32 ret; 2054 2055 new_data = mtk_page_pool_get_buff(ring->page_pool, 2056 &dma_addr, 2057 GFP_ATOMIC); 2058 if (unlikely(!new_data)) { 2059 netdev->stats.rx_dropped++; 2060 goto release_desc; 2061 } 2062 2063 dma_sync_single_for_cpu(eth->dma_dev, 2064 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 2065 pktlen, page_pool_get_dma_dir(ring->page_pool)); 2066 2067 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 2068 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 2069 false); 2070 xdp_buff_clear_frags_flag(&xdp); 2071 2072 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 2073 if (ret == XDP_REDIRECT) 2074 xdp_flush = true; 2075 2076 if (ret != XDP_PASS) 2077 goto skip_rx; 2078 2079 skb = build_skb(data, PAGE_SIZE); 2080 if (unlikely(!skb)) { 2081 page_pool_put_full_page(ring->page_pool, 2082 page, true); 2083 netdev->stats.rx_dropped++; 2084 goto skip_rx; 2085 } 2086 2087 skb_reserve(skb, xdp.data - xdp.data_hard_start); 2088 skb_put(skb, xdp.data_end - xdp.data); 2089 skb_mark_for_recycle(skb); 2090 } else { 2091 if (ring->frag_size <= PAGE_SIZE) 2092 new_data = napi_alloc_frag(ring->frag_size); 2093 else 2094 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 2095 2096 if (unlikely(!new_data)) { 2097 netdev->stats.rx_dropped++; 2098 goto release_desc; 2099 } 2100 2101 dma_addr = dma_map_single(eth->dma_dev, 2102 new_data + NET_SKB_PAD + eth->ip_align, 2103 ring->buf_size, DMA_FROM_DEVICE); 2104 if (unlikely(dma_mapping_error(eth->dma_dev, 2105 dma_addr))) { 2106 skb_free_frag(new_data); 2107 netdev->stats.rx_dropped++; 2108 goto release_desc; 2109 } 2110 2111 dma_unmap_single(eth->dma_dev, trxd.rxd1, 2112 ring->buf_size, DMA_FROM_DEVICE); 2113 2114 skb = build_skb(data, ring->frag_size); 2115 if (unlikely(!skb)) { 2116 netdev->stats.rx_dropped++; 2117 skb_free_frag(data); 2118 goto skip_rx; 2119 } 2120 2121 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 2122 skb_put(skb, pktlen); 2123 } 2124 2125 skb->dev = netdev; 2126 bytes += skb->len; 2127 2128 if (mtk_is_netsys_v2_or_greater(eth)) { 2129 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 2130 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 2131 if (hash != MTK_RXD5_FOE_ENTRY) 2132 skb_set_hash(skb, jhash_1word(hash, 0), 2133 PKT_HASH_TYPE_L4); 2134 rxdcsum = &trxd.rxd3; 2135 } else { 2136 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 2137 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 2138 if (hash != MTK_RXD4_FOE_ENTRY) 2139 skb_set_hash(skb, jhash_1word(hash, 0), 2140 PKT_HASH_TYPE_L4); 2141 rxdcsum = &trxd.rxd4; 2142 } 2143 2144 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) 2145 skb->ip_summed = CHECKSUM_UNNECESSARY; 2146 else 2147 skb_checksum_none_assert(skb); 2148 skb->protocol = eth_type_trans(skb, netdev); 2149 2150 /* When using VLAN untagging in combination with DSA, the 2151 * hardware treats the MTK special tag as a VLAN and untags it. 2152 */ 2153 if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) && 2154 netdev_uses_dsa(netdev)) { 2155 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); 2156 2157 if (port < ARRAY_SIZE(eth->dsa_meta) && 2158 eth->dsa_meta[port]) 2159 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 2160 } 2161 2162 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2163 mtk_ppe_check_skb(eth->ppe[0], skb, hash); 2164 2165 skb_record_rx_queue(skb, 0); 2166 napi_gro_receive(napi, skb); 2167 2168 skip_rx: 2169 ring->data[idx] = new_data; 2170 rxd->rxd1 = (unsigned int)dma_addr; 2171 release_desc: 2172 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2173 rxd->rxd2 = RX_DMA_LSO; 2174 else 2175 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2176 2177 ring->calc_idx = idx; 2178 done++; 2179 } 2180 2181 rx_done: 2182 if (done) { 2183 /* make sure that all changes to the dma ring are flushed before 2184 * we continue 2185 */ 2186 wmb(); 2187 mtk_update_rx_cpu_idx(eth); 2188 } 2189 2190 eth->rx_packets += done; 2191 eth->rx_bytes += bytes; 2192 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2193 &dim_sample); 2194 net_dim(ð->rx_dim, dim_sample); 2195 2196 if (xdp_flush) 2197 xdp_do_flush_map(); 2198 2199 return done; 2200 } 2201 2202 struct mtk_poll_state { 2203 struct netdev_queue *txq; 2204 unsigned int total; 2205 unsigned int done; 2206 unsigned int bytes; 2207 }; 2208 2209 static void 2210 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2211 struct sk_buff *skb) 2212 { 2213 struct netdev_queue *txq; 2214 struct net_device *dev; 2215 unsigned int bytes = skb->len; 2216 2217 state->total++; 2218 eth->tx_packets++; 2219 eth->tx_bytes += bytes; 2220 2221 dev = eth->netdev[mac]; 2222 if (!dev) 2223 return; 2224 2225 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2226 if (state->txq == txq) { 2227 state->done++; 2228 state->bytes += bytes; 2229 return; 2230 } 2231 2232 if (state->txq) 2233 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2234 2235 state->txq = txq; 2236 state->done = 1; 2237 state->bytes = bytes; 2238 } 2239 2240 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2241 struct mtk_poll_state *state) 2242 { 2243 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2244 struct mtk_tx_ring *ring = ð->tx_ring; 2245 struct mtk_tx_buf *tx_buf; 2246 struct xdp_frame_bulk bq; 2247 struct mtk_tx_dma *desc; 2248 u32 cpu, dma; 2249 2250 cpu = ring->last_free_ptr; 2251 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2252 2253 desc = mtk_qdma_phys_to_virt(ring, cpu); 2254 xdp_frame_bulk_init(&bq); 2255 2256 while ((cpu != dma) && budget) { 2257 u32 next_cpu = desc->txd2; 2258 2259 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2260 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2261 break; 2262 2263 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2264 eth->soc->txrx.txd_size); 2265 if (!tx_buf->data) 2266 break; 2267 2268 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2269 if (tx_buf->type == MTK_TYPE_SKB) 2270 mtk_poll_tx_done(eth, state, tx_buf->mac_id, 2271 tx_buf->data); 2272 2273 budget--; 2274 } 2275 mtk_tx_unmap(eth, tx_buf, &bq, true); 2276 2277 ring->last_free = desc; 2278 atomic_inc(&ring->free_count); 2279 2280 cpu = next_cpu; 2281 } 2282 xdp_flush_frame_bulk(&bq); 2283 2284 ring->last_free_ptr = cpu; 2285 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2286 2287 return budget; 2288 } 2289 2290 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2291 struct mtk_poll_state *state) 2292 { 2293 struct mtk_tx_ring *ring = ð->tx_ring; 2294 struct mtk_tx_buf *tx_buf; 2295 struct xdp_frame_bulk bq; 2296 struct mtk_tx_dma *desc; 2297 u32 cpu, dma; 2298 2299 cpu = ring->cpu_idx; 2300 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2301 xdp_frame_bulk_init(&bq); 2302 2303 while ((cpu != dma) && budget) { 2304 tx_buf = &ring->buf[cpu]; 2305 if (!tx_buf->data) 2306 break; 2307 2308 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2309 if (tx_buf->type == MTK_TYPE_SKB) 2310 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2311 budget--; 2312 } 2313 mtk_tx_unmap(eth, tx_buf, &bq, true); 2314 2315 desc = ring->dma + cpu * eth->soc->txrx.txd_size; 2316 ring->last_free = desc; 2317 atomic_inc(&ring->free_count); 2318 2319 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2320 } 2321 xdp_flush_frame_bulk(&bq); 2322 2323 ring->cpu_idx = cpu; 2324 2325 return budget; 2326 } 2327 2328 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2329 { 2330 struct mtk_tx_ring *ring = ð->tx_ring; 2331 struct dim_sample dim_sample = {}; 2332 struct mtk_poll_state state = {}; 2333 2334 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2335 budget = mtk_poll_tx_qdma(eth, budget, &state); 2336 else 2337 budget = mtk_poll_tx_pdma(eth, budget, &state); 2338 2339 if (state.txq) 2340 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2341 2342 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2343 &dim_sample); 2344 net_dim(ð->tx_dim, dim_sample); 2345 2346 if (mtk_queue_stopped(eth) && 2347 (atomic_read(&ring->free_count) > ring->thresh)) 2348 mtk_wake_queue(eth); 2349 2350 return state.total; 2351 } 2352 2353 static void mtk_handle_status_irq(struct mtk_eth *eth) 2354 { 2355 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2356 2357 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2358 mtk_stats_update(eth); 2359 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2360 MTK_INT_STATUS2); 2361 } 2362 } 2363 2364 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2365 { 2366 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2367 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2368 int tx_done = 0; 2369 2370 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2371 mtk_handle_status_irq(eth); 2372 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2373 tx_done = mtk_poll_tx(eth, budget); 2374 2375 if (unlikely(netif_msg_intr(eth))) { 2376 dev_info(eth->dev, 2377 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2378 mtk_r32(eth, reg_map->tx_irq_status), 2379 mtk_r32(eth, reg_map->tx_irq_mask)); 2380 } 2381 2382 if (tx_done == budget) 2383 return budget; 2384 2385 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2386 return budget; 2387 2388 if (napi_complete_done(napi, tx_done)) 2389 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2390 2391 return tx_done; 2392 } 2393 2394 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2395 { 2396 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2397 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2398 int rx_done_total = 0; 2399 2400 mtk_handle_status_irq(eth); 2401 2402 do { 2403 int rx_done; 2404 2405 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, 2406 reg_map->pdma.irq_status); 2407 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2408 rx_done_total += rx_done; 2409 2410 if (unlikely(netif_msg_intr(eth))) { 2411 dev_info(eth->dev, 2412 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2413 mtk_r32(eth, reg_map->pdma.irq_status), 2414 mtk_r32(eth, reg_map->pdma.irq_mask)); 2415 } 2416 2417 if (rx_done_total == budget) 2418 return budget; 2419 2420 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2421 eth->soc->txrx.rx_irq_done_mask); 2422 2423 if (napi_complete_done(napi, rx_done_total)) 2424 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2425 2426 return rx_done_total; 2427 } 2428 2429 static int mtk_tx_alloc(struct mtk_eth *eth) 2430 { 2431 const struct mtk_soc_data *soc = eth->soc; 2432 struct mtk_tx_ring *ring = ð->tx_ring; 2433 int i, sz = soc->txrx.txd_size; 2434 struct mtk_tx_dma_v2 *txd; 2435 int ring_size; 2436 u32 ofs, val; 2437 2438 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2439 ring_size = MTK_QDMA_RING_SIZE; 2440 else 2441 ring_size = MTK_DMA_SIZE; 2442 2443 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), 2444 GFP_KERNEL); 2445 if (!ring->buf) 2446 goto no_tx_mem; 2447 2448 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2449 &ring->phys, GFP_KERNEL); 2450 if (!ring->dma) 2451 goto no_tx_mem; 2452 2453 for (i = 0; i < ring_size; i++) { 2454 int next = (i + 1) % ring_size; 2455 u32 next_ptr = ring->phys + next * sz; 2456 2457 txd = ring->dma + i * sz; 2458 txd->txd2 = next_ptr; 2459 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2460 txd->txd4 = 0; 2461 if (mtk_is_netsys_v2_or_greater(eth)) { 2462 txd->txd5 = 0; 2463 txd->txd6 = 0; 2464 txd->txd7 = 0; 2465 txd->txd8 = 0; 2466 } 2467 } 2468 2469 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2470 * only as the framework. The real HW descriptors are the PDMA 2471 * descriptors in ring->dma_pdma. 2472 */ 2473 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2474 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2475 &ring->phys_pdma, GFP_KERNEL); 2476 if (!ring->dma_pdma) 2477 goto no_tx_mem; 2478 2479 for (i = 0; i < ring_size; i++) { 2480 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2481 ring->dma_pdma[i].txd4 = 0; 2482 } 2483 } 2484 2485 ring->dma_size = ring_size; 2486 atomic_set(&ring->free_count, ring_size - 2); 2487 ring->next_free = ring->dma; 2488 ring->last_free = (void *)txd; 2489 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2490 ring->thresh = MAX_SKB_FRAGS; 2491 2492 /* make sure that all changes to the dma ring are flushed before we 2493 * continue 2494 */ 2495 wmb(); 2496 2497 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2498 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2499 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2500 mtk_w32(eth, 2501 ring->phys + ((ring_size - 1) * sz), 2502 soc->reg_map->qdma.crx_ptr); 2503 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2504 2505 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2506 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2507 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2508 2509 val = MTK_QTX_SCH_MIN_RATE_EN | 2510 /* minimum: 10 Mbps */ 2511 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2512 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2513 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2514 if (mtk_is_netsys_v1(eth)) 2515 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2516 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2517 ofs += MTK_QTX_OFFSET; 2518 } 2519 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2520 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2521 if (mtk_is_netsys_v2_or_greater(eth)) 2522 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2523 } else { 2524 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2525 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2526 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2527 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2528 } 2529 2530 return 0; 2531 2532 no_tx_mem: 2533 return -ENOMEM; 2534 } 2535 2536 static void mtk_tx_clean(struct mtk_eth *eth) 2537 { 2538 const struct mtk_soc_data *soc = eth->soc; 2539 struct mtk_tx_ring *ring = ð->tx_ring; 2540 int i; 2541 2542 if (ring->buf) { 2543 for (i = 0; i < ring->dma_size; i++) 2544 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2545 kfree(ring->buf); 2546 ring->buf = NULL; 2547 } 2548 2549 if (ring->dma) { 2550 dma_free_coherent(eth->dma_dev, 2551 ring->dma_size * soc->txrx.txd_size, 2552 ring->dma, ring->phys); 2553 ring->dma = NULL; 2554 } 2555 2556 if (ring->dma_pdma) { 2557 dma_free_coherent(eth->dma_dev, 2558 ring->dma_size * soc->txrx.txd_size, 2559 ring->dma_pdma, ring->phys_pdma); 2560 ring->dma_pdma = NULL; 2561 } 2562 } 2563 2564 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2565 { 2566 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2567 struct mtk_rx_ring *ring; 2568 int rx_data_len, rx_dma_size; 2569 int i; 2570 2571 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2572 if (ring_no) 2573 return -EINVAL; 2574 ring = ð->rx_ring_qdma; 2575 } else { 2576 ring = ð->rx_ring[ring_no]; 2577 } 2578 2579 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2580 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2581 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2582 } else { 2583 rx_data_len = ETH_DATA_LEN; 2584 rx_dma_size = MTK_DMA_SIZE; 2585 } 2586 2587 ring->frag_size = mtk_max_frag_size(rx_data_len); 2588 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2589 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2590 GFP_KERNEL); 2591 if (!ring->data) 2592 return -ENOMEM; 2593 2594 if (mtk_page_pool_enabled(eth)) { 2595 struct page_pool *pp; 2596 2597 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2598 rx_dma_size); 2599 if (IS_ERR(pp)) 2600 return PTR_ERR(pp); 2601 2602 ring->page_pool = pp; 2603 } 2604 2605 ring->dma = dma_alloc_coherent(eth->dma_dev, 2606 rx_dma_size * eth->soc->txrx.rxd_size, 2607 &ring->phys, GFP_KERNEL); 2608 if (!ring->dma) 2609 return -ENOMEM; 2610 2611 for (i = 0; i < rx_dma_size; i++) { 2612 struct mtk_rx_dma_v2 *rxd; 2613 dma_addr_t dma_addr; 2614 void *data; 2615 2616 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2617 if (ring->page_pool) { 2618 data = mtk_page_pool_get_buff(ring->page_pool, 2619 &dma_addr, GFP_KERNEL); 2620 if (!data) 2621 return -ENOMEM; 2622 } else { 2623 if (ring->frag_size <= PAGE_SIZE) 2624 data = netdev_alloc_frag(ring->frag_size); 2625 else 2626 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2627 2628 if (!data) 2629 return -ENOMEM; 2630 2631 dma_addr = dma_map_single(eth->dma_dev, 2632 data + NET_SKB_PAD + eth->ip_align, 2633 ring->buf_size, DMA_FROM_DEVICE); 2634 if (unlikely(dma_mapping_error(eth->dma_dev, 2635 dma_addr))) { 2636 skb_free_frag(data); 2637 return -ENOMEM; 2638 } 2639 } 2640 rxd->rxd1 = (unsigned int)dma_addr; 2641 ring->data[i] = data; 2642 2643 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2644 rxd->rxd2 = RX_DMA_LSO; 2645 else 2646 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2647 2648 rxd->rxd3 = 0; 2649 rxd->rxd4 = 0; 2650 if (mtk_is_netsys_v2_or_greater(eth)) { 2651 rxd->rxd5 = 0; 2652 rxd->rxd6 = 0; 2653 rxd->rxd7 = 0; 2654 rxd->rxd8 = 0; 2655 } 2656 } 2657 2658 ring->dma_size = rx_dma_size; 2659 ring->calc_idx_update = false; 2660 ring->calc_idx = rx_dma_size - 1; 2661 if (rx_flag == MTK_RX_FLAGS_QDMA) 2662 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2663 ring_no * MTK_QRX_OFFSET; 2664 else 2665 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2666 ring_no * MTK_QRX_OFFSET; 2667 /* make sure that all changes to the dma ring are flushed before we 2668 * continue 2669 */ 2670 wmb(); 2671 2672 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2673 mtk_w32(eth, ring->phys, 2674 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2675 mtk_w32(eth, rx_dma_size, 2676 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2677 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2678 reg_map->qdma.rst_idx); 2679 } else { 2680 mtk_w32(eth, ring->phys, 2681 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2682 mtk_w32(eth, rx_dma_size, 2683 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2684 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2685 reg_map->pdma.rst_idx); 2686 } 2687 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2688 2689 return 0; 2690 } 2691 2692 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 2693 { 2694 int i; 2695 2696 if (ring->data && ring->dma) { 2697 for (i = 0; i < ring->dma_size; i++) { 2698 struct mtk_rx_dma *rxd; 2699 2700 if (!ring->data[i]) 2701 continue; 2702 2703 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2704 if (!rxd->rxd1) 2705 continue; 2706 2707 dma_unmap_single(eth->dma_dev, rxd->rxd1, 2708 ring->buf_size, DMA_FROM_DEVICE); 2709 mtk_rx_put_buff(ring, ring->data[i], false); 2710 } 2711 kfree(ring->data); 2712 ring->data = NULL; 2713 } 2714 2715 if (ring->dma) { 2716 dma_free_coherent(eth->dma_dev, 2717 ring->dma_size * eth->soc->txrx.rxd_size, 2718 ring->dma, ring->phys); 2719 ring->dma = NULL; 2720 } 2721 2722 if (ring->page_pool) { 2723 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2724 xdp_rxq_info_unreg(&ring->xdp_q); 2725 page_pool_destroy(ring->page_pool); 2726 ring->page_pool = NULL; 2727 } 2728 } 2729 2730 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2731 { 2732 int i; 2733 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2734 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2735 2736 /* set LRO rings to auto-learn modes */ 2737 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2738 2739 /* validate LRO ring */ 2740 ring_ctrl_dw2 |= MTK_RING_VLD; 2741 2742 /* set AGE timer (unit: 20us) */ 2743 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2744 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2745 2746 /* set max AGG timer (unit: 20us) */ 2747 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2748 2749 /* set max LRO AGG count */ 2750 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2751 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2752 2753 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2754 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2755 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2756 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2757 } 2758 2759 /* IPv4 checksum update enable */ 2760 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2761 2762 /* switch priority comparison to packet count mode */ 2763 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2764 2765 /* bandwidth threshold setting */ 2766 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2767 2768 /* auto-learn score delta setting */ 2769 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2770 2771 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2772 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2773 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2774 2775 /* set HW LRO mode & the max aggregation count for rx packets */ 2776 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2777 2778 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2779 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2780 2781 /* enable HW LRO */ 2782 lro_ctrl_dw0 |= MTK_LRO_EN; 2783 2784 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2785 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2786 2787 return 0; 2788 } 2789 2790 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2791 { 2792 int i; 2793 u32 val; 2794 2795 /* relinquish lro rings, flush aggregated packets */ 2796 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2797 2798 /* wait for relinquishments done */ 2799 for (i = 0; i < 10; i++) { 2800 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2801 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2802 msleep(20); 2803 continue; 2804 } 2805 break; 2806 } 2807 2808 /* invalidate lro rings */ 2809 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2810 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2811 2812 /* disable HW LRO */ 2813 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2814 } 2815 2816 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2817 { 2818 u32 reg_val; 2819 2820 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2821 2822 /* invalidate the IP setting */ 2823 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2824 2825 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2826 2827 /* validate the IP setting */ 2828 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2829 } 2830 2831 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2832 { 2833 u32 reg_val; 2834 2835 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2836 2837 /* invalidate the IP setting */ 2838 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2839 2840 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2841 } 2842 2843 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2844 { 2845 int cnt = 0; 2846 int i; 2847 2848 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2849 if (mac->hwlro_ip[i]) 2850 cnt++; 2851 } 2852 2853 return cnt; 2854 } 2855 2856 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2857 struct ethtool_rxnfc *cmd) 2858 { 2859 struct ethtool_rx_flow_spec *fsp = 2860 (struct ethtool_rx_flow_spec *)&cmd->fs; 2861 struct mtk_mac *mac = netdev_priv(dev); 2862 struct mtk_eth *eth = mac->hw; 2863 int hwlro_idx; 2864 2865 if ((fsp->flow_type != TCP_V4_FLOW) || 2866 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2867 (fsp->location > 1)) 2868 return -EINVAL; 2869 2870 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2871 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2872 2873 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2874 2875 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2876 2877 return 0; 2878 } 2879 2880 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2881 struct ethtool_rxnfc *cmd) 2882 { 2883 struct ethtool_rx_flow_spec *fsp = 2884 (struct ethtool_rx_flow_spec *)&cmd->fs; 2885 struct mtk_mac *mac = netdev_priv(dev); 2886 struct mtk_eth *eth = mac->hw; 2887 int hwlro_idx; 2888 2889 if (fsp->location > 1) 2890 return -EINVAL; 2891 2892 mac->hwlro_ip[fsp->location] = 0; 2893 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2894 2895 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2896 2897 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2898 2899 return 0; 2900 } 2901 2902 static void mtk_hwlro_netdev_disable(struct net_device *dev) 2903 { 2904 struct mtk_mac *mac = netdev_priv(dev); 2905 struct mtk_eth *eth = mac->hw; 2906 int i, hwlro_idx; 2907 2908 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2909 mac->hwlro_ip[i] = 0; 2910 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 2911 2912 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2913 } 2914 2915 mac->hwlro_ip_cnt = 0; 2916 } 2917 2918 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 2919 struct ethtool_rxnfc *cmd) 2920 { 2921 struct mtk_mac *mac = netdev_priv(dev); 2922 struct ethtool_rx_flow_spec *fsp = 2923 (struct ethtool_rx_flow_spec *)&cmd->fs; 2924 2925 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 2926 return -EINVAL; 2927 2928 /* only tcp dst ipv4 is meaningful, others are meaningless */ 2929 fsp->flow_type = TCP_V4_FLOW; 2930 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 2931 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 2932 2933 fsp->h_u.tcp_ip4_spec.ip4src = 0; 2934 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 2935 fsp->h_u.tcp_ip4_spec.psrc = 0; 2936 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 2937 fsp->h_u.tcp_ip4_spec.pdst = 0; 2938 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 2939 fsp->h_u.tcp_ip4_spec.tos = 0; 2940 fsp->m_u.tcp_ip4_spec.tos = 0xff; 2941 2942 return 0; 2943 } 2944 2945 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 2946 struct ethtool_rxnfc *cmd, 2947 u32 *rule_locs) 2948 { 2949 struct mtk_mac *mac = netdev_priv(dev); 2950 int cnt = 0; 2951 int i; 2952 2953 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2954 if (mac->hwlro_ip[i]) { 2955 rule_locs[cnt] = i; 2956 cnt++; 2957 } 2958 } 2959 2960 cmd->rule_cnt = cnt; 2961 2962 return 0; 2963 } 2964 2965 static netdev_features_t mtk_fix_features(struct net_device *dev, 2966 netdev_features_t features) 2967 { 2968 if (!(features & NETIF_F_LRO)) { 2969 struct mtk_mac *mac = netdev_priv(dev); 2970 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2971 2972 if (ip_cnt) { 2973 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 2974 2975 features |= NETIF_F_LRO; 2976 } 2977 } 2978 2979 return features; 2980 } 2981 2982 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2983 { 2984 netdev_features_t diff = dev->features ^ features; 2985 2986 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 2987 mtk_hwlro_netdev_disable(dev); 2988 2989 return 0; 2990 } 2991 2992 /* wait for DMA to finish whatever it is doing before we start using it again */ 2993 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2994 { 2995 unsigned int reg; 2996 int ret; 2997 u32 val; 2998 2999 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3000 reg = eth->soc->reg_map->qdma.glo_cfg; 3001 else 3002 reg = eth->soc->reg_map->pdma.glo_cfg; 3003 3004 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 3005 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 3006 5, MTK_DMA_BUSY_TIMEOUT_US); 3007 if (ret) 3008 dev_err(eth->dev, "DMA init timeout\n"); 3009 3010 return ret; 3011 } 3012 3013 static int mtk_dma_init(struct mtk_eth *eth) 3014 { 3015 int err; 3016 u32 i; 3017 3018 if (mtk_dma_busy_wait(eth)) 3019 return -EBUSY; 3020 3021 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3022 /* QDMA needs scratch memory for internal reordering of the 3023 * descriptors 3024 */ 3025 err = mtk_init_fq_dma(eth); 3026 if (err) 3027 return err; 3028 } 3029 3030 err = mtk_tx_alloc(eth); 3031 if (err) 3032 return err; 3033 3034 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3035 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 3036 if (err) 3037 return err; 3038 } 3039 3040 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 3041 if (err) 3042 return err; 3043 3044 if (eth->hwlro) { 3045 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 3046 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 3047 if (err) 3048 return err; 3049 } 3050 err = mtk_hwlro_rx_init(eth); 3051 if (err) 3052 return err; 3053 } 3054 3055 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3056 /* Enable random early drop and set drop threshold 3057 * automatically 3058 */ 3059 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 3060 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 3061 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 3062 } 3063 3064 return 0; 3065 } 3066 3067 static void mtk_dma_free(struct mtk_eth *eth) 3068 { 3069 const struct mtk_soc_data *soc = eth->soc; 3070 int i; 3071 3072 for (i = 0; i < MTK_MAX_DEVS; i++) 3073 if (eth->netdev[i]) 3074 netdev_reset_queue(eth->netdev[i]); 3075 if (eth->scratch_ring) { 3076 dma_free_coherent(eth->dma_dev, 3077 MTK_QDMA_RING_SIZE * soc->txrx.txd_size, 3078 eth->scratch_ring, eth->phy_scratch_ring); 3079 eth->scratch_ring = NULL; 3080 eth->phy_scratch_ring = 0; 3081 } 3082 mtk_tx_clean(eth); 3083 mtk_rx_clean(eth, ð->rx_ring[0]); 3084 mtk_rx_clean(eth, ð->rx_ring_qdma); 3085 3086 if (eth->hwlro) { 3087 mtk_hwlro_rx_uninit(eth); 3088 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 3089 mtk_rx_clean(eth, ð->rx_ring[i]); 3090 } 3091 3092 kfree(eth->scratch_head); 3093 } 3094 3095 static bool mtk_hw_reset_check(struct mtk_eth *eth) 3096 { 3097 u32 val = mtk_r32(eth, MTK_INT_STATUS2); 3098 3099 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || 3100 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || 3101 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); 3102 } 3103 3104 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 3105 { 3106 struct mtk_mac *mac = netdev_priv(dev); 3107 struct mtk_eth *eth = mac->hw; 3108 3109 if (test_bit(MTK_RESETTING, ð->state)) 3110 return; 3111 3112 if (!mtk_hw_reset_check(eth)) 3113 return; 3114 3115 eth->netdev[mac->id]->stats.tx_errors++; 3116 netif_err(eth, tx_err, dev, "transmit timed out\n"); 3117 3118 schedule_work(ð->pending_work); 3119 } 3120 3121 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 3122 { 3123 struct mtk_eth *eth = _eth; 3124 3125 eth->rx_events++; 3126 if (likely(napi_schedule_prep(ð->rx_napi))) { 3127 __napi_schedule(ð->rx_napi); 3128 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3129 } 3130 3131 return IRQ_HANDLED; 3132 } 3133 3134 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 3135 { 3136 struct mtk_eth *eth = _eth; 3137 3138 eth->tx_events++; 3139 if (likely(napi_schedule_prep(ð->tx_napi))) { 3140 __napi_schedule(ð->tx_napi); 3141 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3142 } 3143 3144 return IRQ_HANDLED; 3145 } 3146 3147 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 3148 { 3149 struct mtk_eth *eth = _eth; 3150 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3151 3152 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 3153 eth->soc->txrx.rx_irq_done_mask) { 3154 if (mtk_r32(eth, reg_map->pdma.irq_status) & 3155 eth->soc->txrx.rx_irq_done_mask) 3156 mtk_handle_irq_rx(irq, _eth); 3157 } 3158 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3159 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3160 mtk_handle_irq_tx(irq, _eth); 3161 } 3162 3163 return IRQ_HANDLED; 3164 } 3165 3166 #ifdef CONFIG_NET_POLL_CONTROLLER 3167 static void mtk_poll_controller(struct net_device *dev) 3168 { 3169 struct mtk_mac *mac = netdev_priv(dev); 3170 struct mtk_eth *eth = mac->hw; 3171 3172 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3173 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3174 mtk_handle_irq_rx(eth->irq[2], dev); 3175 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3176 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 3177 } 3178 #endif 3179 3180 static int mtk_start_dma(struct mtk_eth *eth) 3181 { 3182 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3183 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3184 int err; 3185 3186 err = mtk_dma_init(eth); 3187 if (err) { 3188 mtk_dma_free(eth); 3189 return err; 3190 } 3191 3192 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3193 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3194 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3195 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3196 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3197 3198 if (mtk_is_netsys_v2_or_greater(eth)) 3199 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3200 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3201 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; 3202 else 3203 val |= MTK_RX_BT_32DWORDS; 3204 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3205 3206 mtk_w32(eth, 3207 MTK_RX_DMA_EN | rx_2b_offset | 3208 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3209 reg_map->pdma.glo_cfg); 3210 } else { 3211 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3212 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3213 reg_map->pdma.glo_cfg); 3214 } 3215 3216 return 0; 3217 } 3218 3219 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 3220 { 3221 int i; 3222 3223 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3224 return; 3225 3226 for (i = 0; i < MTK_MAX_DEVS; i++) { 3227 u32 val; 3228 3229 if (!eth->netdev[i]) 3230 continue; 3231 3232 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 3233 3234 /* default setup the forward port to send frame to PDMA */ 3235 val &= ~0xffff; 3236 3237 /* Enable RX checksum */ 3238 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3239 3240 val |= config; 3241 3242 if (netdev_uses_dsa(eth->netdev[i])) 3243 val |= MTK_GDMA_SPECIAL_TAG; 3244 3245 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 3246 } 3247 /* Reset and enable PSE */ 3248 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 3249 mtk_w32(eth, 0, MTK_RST_GL); 3250 } 3251 3252 3253 static bool mtk_uses_dsa(struct net_device *dev) 3254 { 3255 #if IS_ENABLED(CONFIG_NET_DSA) 3256 return netdev_uses_dsa(dev) && 3257 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3258 #else 3259 return false; 3260 #endif 3261 } 3262 3263 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3264 { 3265 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3266 struct mtk_eth *eth = mac->hw; 3267 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3268 struct ethtool_link_ksettings s; 3269 struct net_device *ldev; 3270 struct list_head *iter; 3271 struct dsa_port *dp; 3272 3273 if (event != NETDEV_CHANGE) 3274 return NOTIFY_DONE; 3275 3276 netdev_for_each_lower_dev(dev, ldev, iter) { 3277 if (netdev_priv(ldev) == mac) 3278 goto found; 3279 } 3280 3281 return NOTIFY_DONE; 3282 3283 found: 3284 if (!dsa_slave_dev_check(dev)) 3285 return NOTIFY_DONE; 3286 3287 if (__ethtool_get_link_ksettings(dev, &s)) 3288 return NOTIFY_DONE; 3289 3290 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3291 return NOTIFY_DONE; 3292 3293 dp = dsa_port_from_netdev(dev); 3294 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3295 return NOTIFY_DONE; 3296 3297 if (mac->speed > 0 && mac->speed <= s.base.speed) 3298 s.base.speed = 0; 3299 3300 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3301 3302 return NOTIFY_DONE; 3303 } 3304 3305 static int mtk_open(struct net_device *dev) 3306 { 3307 struct mtk_mac *mac = netdev_priv(dev); 3308 struct mtk_eth *eth = mac->hw; 3309 int i, err; 3310 3311 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3312 if (err) { 3313 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3314 err); 3315 return err; 3316 } 3317 3318 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3319 if (!refcount_read(ð->dma_refcnt)) { 3320 const struct mtk_soc_data *soc = eth->soc; 3321 u32 gdm_config; 3322 int i; 3323 3324 err = mtk_start_dma(eth); 3325 if (err) { 3326 phylink_disconnect_phy(mac->phylink); 3327 return err; 3328 } 3329 3330 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3331 mtk_ppe_start(eth->ppe[i]); 3332 3333 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe 3334 : MTK_GDMA_TO_PDMA; 3335 mtk_gdm_config(eth, gdm_config); 3336 3337 napi_enable(ð->tx_napi); 3338 napi_enable(ð->rx_napi); 3339 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3340 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); 3341 refcount_set(ð->dma_refcnt, 1); 3342 } 3343 else 3344 refcount_inc(ð->dma_refcnt); 3345 3346 phylink_start(mac->phylink); 3347 netif_tx_start_all_queues(dev); 3348 3349 if (mtk_is_netsys_v2_or_greater(eth)) 3350 return 0; 3351 3352 if (mtk_uses_dsa(dev) && !eth->prog) { 3353 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3354 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3355 3356 if (md_dst) 3357 continue; 3358 3359 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3360 GFP_KERNEL); 3361 if (!md_dst) 3362 return -ENOMEM; 3363 3364 md_dst->u.port_info.port_id = i; 3365 eth->dsa_meta[i] = md_dst; 3366 } 3367 } else { 3368 /* Hardware DSA untagging and VLAN RX offloading need to be 3369 * disabled if at least one MAC does not use DSA. 3370 */ 3371 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3372 3373 val &= ~MTK_CDMP_STAG_EN; 3374 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3375 3376 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); 3377 } 3378 3379 return 0; 3380 } 3381 3382 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3383 { 3384 u32 val; 3385 int i; 3386 3387 /* stop the dma engine */ 3388 spin_lock_bh(ð->page_lock); 3389 val = mtk_r32(eth, glo_cfg); 3390 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3391 glo_cfg); 3392 spin_unlock_bh(ð->page_lock); 3393 3394 /* wait for dma stop */ 3395 for (i = 0; i < 10; i++) { 3396 val = mtk_r32(eth, glo_cfg); 3397 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3398 msleep(20); 3399 continue; 3400 } 3401 break; 3402 } 3403 } 3404 3405 static int mtk_stop(struct net_device *dev) 3406 { 3407 struct mtk_mac *mac = netdev_priv(dev); 3408 struct mtk_eth *eth = mac->hw; 3409 int i; 3410 3411 phylink_stop(mac->phylink); 3412 3413 netif_tx_disable(dev); 3414 3415 phylink_disconnect_phy(mac->phylink); 3416 3417 /* only shutdown DMA if this is the last user */ 3418 if (!refcount_dec_and_test(ð->dma_refcnt)) 3419 return 0; 3420 3421 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 3422 3423 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3424 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3425 napi_disable(ð->tx_napi); 3426 napi_disable(ð->rx_napi); 3427 3428 cancel_work_sync(ð->rx_dim.work); 3429 cancel_work_sync(ð->tx_dim.work); 3430 3431 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3432 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3433 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3434 3435 mtk_dma_free(eth); 3436 3437 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3438 mtk_ppe_stop(eth->ppe[i]); 3439 3440 return 0; 3441 } 3442 3443 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3444 struct netlink_ext_ack *extack) 3445 { 3446 struct mtk_mac *mac = netdev_priv(dev); 3447 struct mtk_eth *eth = mac->hw; 3448 struct bpf_prog *old_prog; 3449 bool need_update; 3450 3451 if (eth->hwlro) { 3452 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3453 return -EOPNOTSUPP; 3454 } 3455 3456 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3457 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3458 return -EOPNOTSUPP; 3459 } 3460 3461 need_update = !!eth->prog != !!prog; 3462 if (netif_running(dev) && need_update) 3463 mtk_stop(dev); 3464 3465 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3466 if (old_prog) 3467 bpf_prog_put(old_prog); 3468 3469 if (netif_running(dev) && need_update) 3470 return mtk_open(dev); 3471 3472 return 0; 3473 } 3474 3475 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3476 { 3477 switch (xdp->command) { 3478 case XDP_SETUP_PROG: 3479 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3480 default: 3481 return -EINVAL; 3482 } 3483 } 3484 3485 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3486 { 3487 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3488 reset_bits, 3489 reset_bits); 3490 3491 usleep_range(1000, 1100); 3492 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3493 reset_bits, 3494 ~reset_bits); 3495 mdelay(10); 3496 } 3497 3498 static void mtk_clk_disable(struct mtk_eth *eth) 3499 { 3500 int clk; 3501 3502 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3503 clk_disable_unprepare(eth->clks[clk]); 3504 } 3505 3506 static int mtk_clk_enable(struct mtk_eth *eth) 3507 { 3508 int clk, ret; 3509 3510 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3511 ret = clk_prepare_enable(eth->clks[clk]); 3512 if (ret) 3513 goto err_disable_clks; 3514 } 3515 3516 return 0; 3517 3518 err_disable_clks: 3519 while (--clk >= 0) 3520 clk_disable_unprepare(eth->clks[clk]); 3521 3522 return ret; 3523 } 3524 3525 static void mtk_dim_rx(struct work_struct *work) 3526 { 3527 struct dim *dim = container_of(work, struct dim, work); 3528 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3529 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3530 struct dim_cq_moder cur_profile; 3531 u32 val, cur; 3532 3533 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3534 dim->profile_ix); 3535 spin_lock_bh(ð->dim_lock); 3536 3537 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3538 val &= MTK_PDMA_DELAY_TX_MASK; 3539 val |= MTK_PDMA_DELAY_RX_EN; 3540 3541 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3542 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3543 3544 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3545 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3546 3547 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3548 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3549 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3550 3551 spin_unlock_bh(ð->dim_lock); 3552 3553 dim->state = DIM_START_MEASURE; 3554 } 3555 3556 static void mtk_dim_tx(struct work_struct *work) 3557 { 3558 struct dim *dim = container_of(work, struct dim, work); 3559 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3560 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3561 struct dim_cq_moder cur_profile; 3562 u32 val, cur; 3563 3564 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3565 dim->profile_ix); 3566 spin_lock_bh(ð->dim_lock); 3567 3568 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3569 val &= MTK_PDMA_DELAY_RX_MASK; 3570 val |= MTK_PDMA_DELAY_TX_EN; 3571 3572 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3573 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3574 3575 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3576 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3577 3578 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3579 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3580 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3581 3582 spin_unlock_bh(ð->dim_lock); 3583 3584 dim->state = DIM_START_MEASURE; 3585 } 3586 3587 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3588 { 3589 struct mtk_eth *eth = mac->hw; 3590 u32 mcr_cur, mcr_new; 3591 3592 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3593 return; 3594 3595 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3596 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3597 3598 if (val <= 1518) 3599 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3600 else if (val <= 1536) 3601 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3602 else if (val <= 1552) 3603 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3604 else 3605 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3606 3607 if (mcr_new != mcr_cur) 3608 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3609 } 3610 3611 static void mtk_hw_reset(struct mtk_eth *eth) 3612 { 3613 u32 val; 3614 3615 if (mtk_is_netsys_v2_or_greater(eth)) { 3616 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3617 val = RSTCTRL_PPE0_V2; 3618 } else { 3619 val = RSTCTRL_PPE0; 3620 } 3621 3622 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3623 val |= RSTCTRL_PPE1; 3624 3625 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3626 3627 if (mtk_is_netsys_v2_or_greater(eth)) 3628 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3629 0x3ffffff); 3630 } 3631 3632 static u32 mtk_hw_reset_read(struct mtk_eth *eth) 3633 { 3634 u32 val; 3635 3636 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); 3637 return val; 3638 } 3639 3640 static void mtk_hw_warm_reset(struct mtk_eth *eth) 3641 { 3642 u32 rst_mask, val; 3643 3644 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, 3645 RSTCTRL_FE); 3646 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, 3647 val & RSTCTRL_FE, 1, 1000)) { 3648 dev_err(eth->dev, "warm reset failed\n"); 3649 mtk_hw_reset(eth); 3650 return; 3651 } 3652 3653 if (mtk_is_netsys_v2_or_greater(eth)) 3654 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 3655 else 3656 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; 3657 3658 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3659 rst_mask |= RSTCTRL_PPE1; 3660 3661 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); 3662 3663 udelay(1); 3664 val = mtk_hw_reset_read(eth); 3665 if (!(val & rst_mask)) 3666 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", 3667 val, rst_mask); 3668 3669 rst_mask |= RSTCTRL_FE; 3670 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); 3671 3672 udelay(1); 3673 val = mtk_hw_reset_read(eth); 3674 if (val & rst_mask) 3675 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", 3676 val, rst_mask); 3677 } 3678 3679 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) 3680 { 3681 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3682 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; 3683 bool oq_hang, cdm1_busy, adma_busy; 3684 bool wtx_busy, cdm_full, oq_free; 3685 u32 wdidx, val, gdm1_fc, gdm2_fc; 3686 bool qfsm_hang, qfwd_hang; 3687 bool ret = false; 3688 3689 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3690 return false; 3691 3692 /* WDMA sanity checks */ 3693 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); 3694 3695 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); 3696 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); 3697 3698 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); 3699 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); 3700 3701 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && 3702 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && 3703 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); 3704 3705 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { 3706 if (++eth->reset.wdma_hang_count > 2) { 3707 eth->reset.wdma_hang_count = 0; 3708 ret = true; 3709 } 3710 goto out; 3711 } 3712 3713 /* QDMA sanity checks */ 3714 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); 3715 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); 3716 3717 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; 3718 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; 3719 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; 3720 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; 3721 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); 3722 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); 3723 3724 if (qfsm_hang && qfwd_hang && 3725 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || 3726 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { 3727 if (++eth->reset.qdma_hang_count > 2) { 3728 eth->reset.qdma_hang_count = 0; 3729 ret = true; 3730 } 3731 goto out; 3732 } 3733 3734 /* ADMA sanity checks */ 3735 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); 3736 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); 3737 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && 3738 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); 3739 3740 if (oq_hang && cdm1_busy && adma_busy) { 3741 if (++eth->reset.adma_hang_count > 2) { 3742 eth->reset.adma_hang_count = 0; 3743 ret = true; 3744 } 3745 goto out; 3746 } 3747 3748 eth->reset.wdma_hang_count = 0; 3749 eth->reset.qdma_hang_count = 0; 3750 eth->reset.adma_hang_count = 0; 3751 out: 3752 eth->reset.wdidx = wdidx; 3753 3754 return ret; 3755 } 3756 3757 static void mtk_hw_reset_monitor_work(struct work_struct *work) 3758 { 3759 struct delayed_work *del_work = to_delayed_work(work); 3760 struct mtk_eth *eth = container_of(del_work, struct mtk_eth, 3761 reset.monitor_work); 3762 3763 if (test_bit(MTK_RESETTING, ð->state)) 3764 goto out; 3765 3766 /* DMA stuck checks */ 3767 if (mtk_hw_check_dma_hang(eth)) 3768 schedule_work(ð->pending_work); 3769 3770 out: 3771 schedule_delayed_work(ð->reset.monitor_work, 3772 MTK_DMA_MONITOR_TIMEOUT); 3773 } 3774 3775 static int mtk_hw_init(struct mtk_eth *eth, bool reset) 3776 { 3777 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3778 ETHSYS_DMA_AG_MAP_PPE; 3779 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3780 int i, val, ret; 3781 3782 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) 3783 return 0; 3784 3785 if (!reset) { 3786 pm_runtime_enable(eth->dev); 3787 pm_runtime_get_sync(eth->dev); 3788 3789 ret = mtk_clk_enable(eth); 3790 if (ret) 3791 goto err_disable_pm; 3792 } 3793 3794 if (eth->ethsys) 3795 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3796 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3797 3798 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3799 ret = device_reset(eth->dev); 3800 if (ret) { 3801 dev_err(eth->dev, "MAC reset failed!\n"); 3802 goto err_disable_pm; 3803 } 3804 3805 /* set interrupt delays based on current Net DIM sample */ 3806 mtk_dim_rx(ð->rx_dim.work); 3807 mtk_dim_tx(ð->tx_dim.work); 3808 3809 /* disable delay and normal interrupt */ 3810 mtk_tx_irq_disable(eth, ~0); 3811 mtk_rx_irq_disable(eth, ~0); 3812 3813 return 0; 3814 } 3815 3816 msleep(100); 3817 3818 if (reset) 3819 mtk_hw_warm_reset(eth); 3820 else 3821 mtk_hw_reset(eth); 3822 3823 if (mtk_is_netsys_v2_or_greater(eth)) { 3824 /* Set FE to PDMAv2 if necessary */ 3825 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3826 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3827 } 3828 3829 if (eth->pctl) { 3830 /* Set GE2 driving and slew rate */ 3831 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3832 3833 /* set GE2 TDSEL */ 3834 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3835 3836 /* set GE2 TUNE */ 3837 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3838 } 3839 3840 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3841 * up with the more appropriate value when mtk_mac_config call is being 3842 * invoked. 3843 */ 3844 for (i = 0; i < MTK_MAX_DEVS; i++) { 3845 struct net_device *dev = eth->netdev[i]; 3846 3847 if (!dev) 3848 continue; 3849 3850 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3851 mtk_set_mcr_max_rx(netdev_priv(dev), 3852 dev->mtu + MTK_RX_ETH_HLEN); 3853 } 3854 3855 /* Indicates CDM to parse the MTK special tag from CPU 3856 * which also is working out for untag packets. 3857 */ 3858 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3859 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 3860 if (mtk_is_netsys_v1(eth)) { 3861 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3862 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 3863 3864 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 3865 } 3866 3867 /* set interrupt delays based on current Net DIM sample */ 3868 mtk_dim_rx(ð->rx_dim.work); 3869 mtk_dim_tx(ð->tx_dim.work); 3870 3871 /* disable delay and normal interrupt */ 3872 mtk_tx_irq_disable(eth, ~0); 3873 mtk_rx_irq_disable(eth, ~0); 3874 3875 /* FE int grouping */ 3876 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 3877 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); 3878 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 3879 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 3880 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 3881 3882 if (mtk_is_netsys_v3_or_greater(eth)) { 3883 /* PSE should not drop port1, port8 and port9 packets */ 3884 mtk_w32(eth, 0x00000302, PSE_DROP_CFG); 3885 3886 /* GDM and CDM Threshold */ 3887 mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); 3888 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); 3889 3890 /* Disable GDM1 RX CRC stripping */ 3891 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); 3892 3893 /* PSE GDM3 MIB counter has incorrect hw default values, 3894 * so the driver ought to read clear the values beforehand 3895 * in case ethtool retrieve wrong mib values. 3896 */ 3897 for (i = 0; i < 0x80; i += 0x4) 3898 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); 3899 } else if (!mtk_is_netsys_v1(eth)) { 3900 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 3901 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 3902 3903 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 3904 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); 3905 3906 /* PSE Free Queue Flow Control */ 3907 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 3908 3909 /* PSE config input queue threshold */ 3910 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 3911 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 3912 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 3913 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 3914 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 3915 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 3916 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 3917 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 3918 3919 /* PSE config output queue threshold */ 3920 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 3921 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 3922 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 3923 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 3924 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 3925 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 3926 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 3927 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 3928 3929 /* GDM and CDM Threshold */ 3930 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 3931 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 3932 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 3933 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 3934 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 3935 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 3936 } 3937 3938 return 0; 3939 3940 err_disable_pm: 3941 if (!reset) { 3942 pm_runtime_put_sync(eth->dev); 3943 pm_runtime_disable(eth->dev); 3944 } 3945 3946 return ret; 3947 } 3948 3949 static int mtk_hw_deinit(struct mtk_eth *eth) 3950 { 3951 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 3952 return 0; 3953 3954 mtk_clk_disable(eth); 3955 3956 pm_runtime_put_sync(eth->dev); 3957 pm_runtime_disable(eth->dev); 3958 3959 return 0; 3960 } 3961 3962 static void mtk_uninit(struct net_device *dev) 3963 { 3964 struct mtk_mac *mac = netdev_priv(dev); 3965 struct mtk_eth *eth = mac->hw; 3966 3967 phylink_disconnect_phy(mac->phylink); 3968 mtk_tx_irq_disable(eth, ~0); 3969 mtk_rx_irq_disable(eth, ~0); 3970 } 3971 3972 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 3973 { 3974 int length = new_mtu + MTK_RX_ETH_HLEN; 3975 struct mtk_mac *mac = netdev_priv(dev); 3976 struct mtk_eth *eth = mac->hw; 3977 3978 if (rcu_access_pointer(eth->prog) && 3979 length > MTK_PP_MAX_BUF_SIZE) { 3980 netdev_err(dev, "Invalid MTU for XDP mode\n"); 3981 return -EINVAL; 3982 } 3983 3984 mtk_set_mcr_max_rx(mac, length); 3985 dev->mtu = new_mtu; 3986 3987 return 0; 3988 } 3989 3990 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3991 { 3992 struct mtk_mac *mac = netdev_priv(dev); 3993 3994 switch (cmd) { 3995 case SIOCGMIIPHY: 3996 case SIOCGMIIREG: 3997 case SIOCSMIIREG: 3998 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 3999 default: 4000 break; 4001 } 4002 4003 return -EOPNOTSUPP; 4004 } 4005 4006 static void mtk_prepare_for_reset(struct mtk_eth *eth) 4007 { 4008 u32 val; 4009 int i; 4010 4011 /* disabe FE P3 and P4 */ 4012 val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3; 4013 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4014 val |= MTK_FE_LINK_DOWN_P4; 4015 mtk_w32(eth, val, MTK_FE_GLO_CFG); 4016 4017 /* adjust PPE configurations to prepare for reset */ 4018 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 4019 mtk_ppe_prepare_reset(eth->ppe[i]); 4020 4021 /* disable NETSYS interrupts */ 4022 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); 4023 4024 /* force link down GMAC */ 4025 for (i = 0; i < 2; i++) { 4026 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; 4027 mtk_w32(eth, val, MTK_MAC_MCR(i)); 4028 } 4029 } 4030 4031 static void mtk_pending_work(struct work_struct *work) 4032 { 4033 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 4034 unsigned long restart = 0; 4035 u32 val; 4036 int i; 4037 4038 rtnl_lock(); 4039 set_bit(MTK_RESETTING, ð->state); 4040 4041 mtk_prepare_for_reset(eth); 4042 mtk_wed_fe_reset(); 4043 /* Run again reset preliminary configuration in order to avoid any 4044 * possible race during FE reset since it can run releasing RTNL lock. 4045 */ 4046 mtk_prepare_for_reset(eth); 4047 4048 /* stop all devices to make sure that dma is properly shut down */ 4049 for (i = 0; i < MTK_MAX_DEVS; i++) { 4050 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 4051 continue; 4052 4053 mtk_stop(eth->netdev[i]); 4054 __set_bit(i, &restart); 4055 } 4056 4057 usleep_range(15000, 16000); 4058 4059 if (eth->dev->pins) 4060 pinctrl_select_state(eth->dev->pins->p, 4061 eth->dev->pins->default_state); 4062 mtk_hw_init(eth, true); 4063 4064 /* restart DMA and enable IRQs */ 4065 for (i = 0; i < MTK_MAX_DEVS; i++) { 4066 if (!eth->netdev[i] || !test_bit(i, &restart)) 4067 continue; 4068 4069 if (mtk_open(eth->netdev[i])) { 4070 netif_alert(eth, ifup, eth->netdev[i], 4071 "Driver up/down cycle failed\n"); 4072 dev_close(eth->netdev[i]); 4073 } 4074 } 4075 4076 /* enabe FE P3 and P4 */ 4077 val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3; 4078 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4079 val &= ~MTK_FE_LINK_DOWN_P4; 4080 mtk_w32(eth, val, MTK_FE_GLO_CFG); 4081 4082 clear_bit(MTK_RESETTING, ð->state); 4083 4084 mtk_wed_fe_reset_complete(); 4085 4086 rtnl_unlock(); 4087 } 4088 4089 static int mtk_free_dev(struct mtk_eth *eth) 4090 { 4091 int i; 4092 4093 for (i = 0; i < MTK_MAX_DEVS; i++) { 4094 if (!eth->netdev[i]) 4095 continue; 4096 free_netdev(eth->netdev[i]); 4097 } 4098 4099 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 4100 if (!eth->dsa_meta[i]) 4101 break; 4102 metadata_dst_free(eth->dsa_meta[i]); 4103 } 4104 4105 return 0; 4106 } 4107 4108 static int mtk_unreg_dev(struct mtk_eth *eth) 4109 { 4110 int i; 4111 4112 for (i = 0; i < MTK_MAX_DEVS; i++) { 4113 struct mtk_mac *mac; 4114 if (!eth->netdev[i]) 4115 continue; 4116 mac = netdev_priv(eth->netdev[i]); 4117 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4118 unregister_netdevice_notifier(&mac->device_notifier); 4119 unregister_netdev(eth->netdev[i]); 4120 } 4121 4122 return 0; 4123 } 4124 4125 static void mtk_sgmii_destroy(struct mtk_eth *eth) 4126 { 4127 int i; 4128 4129 for (i = 0; i < MTK_MAX_DEVS; i++) 4130 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); 4131 } 4132 4133 static int mtk_cleanup(struct mtk_eth *eth) 4134 { 4135 mtk_sgmii_destroy(eth); 4136 mtk_unreg_dev(eth); 4137 mtk_free_dev(eth); 4138 cancel_work_sync(ð->pending_work); 4139 cancel_delayed_work_sync(ð->reset.monitor_work); 4140 4141 return 0; 4142 } 4143 4144 static int mtk_get_link_ksettings(struct net_device *ndev, 4145 struct ethtool_link_ksettings *cmd) 4146 { 4147 struct mtk_mac *mac = netdev_priv(ndev); 4148 4149 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4150 return -EBUSY; 4151 4152 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 4153 } 4154 4155 static int mtk_set_link_ksettings(struct net_device *ndev, 4156 const struct ethtool_link_ksettings *cmd) 4157 { 4158 struct mtk_mac *mac = netdev_priv(ndev); 4159 4160 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4161 return -EBUSY; 4162 4163 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 4164 } 4165 4166 static void mtk_get_drvinfo(struct net_device *dev, 4167 struct ethtool_drvinfo *info) 4168 { 4169 struct mtk_mac *mac = netdev_priv(dev); 4170 4171 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 4172 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 4173 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 4174 } 4175 4176 static u32 mtk_get_msglevel(struct net_device *dev) 4177 { 4178 struct mtk_mac *mac = netdev_priv(dev); 4179 4180 return mac->hw->msg_enable; 4181 } 4182 4183 static void mtk_set_msglevel(struct net_device *dev, u32 value) 4184 { 4185 struct mtk_mac *mac = netdev_priv(dev); 4186 4187 mac->hw->msg_enable = value; 4188 } 4189 4190 static int mtk_nway_reset(struct net_device *dev) 4191 { 4192 struct mtk_mac *mac = netdev_priv(dev); 4193 4194 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4195 return -EBUSY; 4196 4197 if (!mac->phylink) 4198 return -ENOTSUPP; 4199 4200 return phylink_ethtool_nway_reset(mac->phylink); 4201 } 4202 4203 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4204 { 4205 int i; 4206 4207 switch (stringset) { 4208 case ETH_SS_STATS: { 4209 struct mtk_mac *mac = netdev_priv(dev); 4210 4211 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 4212 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 4213 data += ETH_GSTRING_LEN; 4214 } 4215 if (mtk_page_pool_enabled(mac->hw)) 4216 page_pool_ethtool_stats_get_strings(data); 4217 break; 4218 } 4219 default: 4220 break; 4221 } 4222 } 4223 4224 static int mtk_get_sset_count(struct net_device *dev, int sset) 4225 { 4226 switch (sset) { 4227 case ETH_SS_STATS: { 4228 int count = ARRAY_SIZE(mtk_ethtool_stats); 4229 struct mtk_mac *mac = netdev_priv(dev); 4230 4231 if (mtk_page_pool_enabled(mac->hw)) 4232 count += page_pool_ethtool_stats_get_count(); 4233 return count; 4234 } 4235 default: 4236 return -EOPNOTSUPP; 4237 } 4238 } 4239 4240 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 4241 { 4242 struct page_pool_stats stats = {}; 4243 int i; 4244 4245 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 4246 struct mtk_rx_ring *ring = ð->rx_ring[i]; 4247 4248 if (!ring->page_pool) 4249 continue; 4250 4251 page_pool_get_stats(ring->page_pool, &stats); 4252 } 4253 page_pool_ethtool_stats_get(data, &stats); 4254 } 4255 4256 static void mtk_get_ethtool_stats(struct net_device *dev, 4257 struct ethtool_stats *stats, u64 *data) 4258 { 4259 struct mtk_mac *mac = netdev_priv(dev); 4260 struct mtk_hw_stats *hwstats = mac->hw_stats; 4261 u64 *data_src, *data_dst; 4262 unsigned int start; 4263 int i; 4264 4265 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4266 return; 4267 4268 if (netif_running(dev) && netif_device_present(dev)) { 4269 if (spin_trylock_bh(&hwstats->stats_lock)) { 4270 mtk_stats_update_mac(mac); 4271 spin_unlock_bh(&hwstats->stats_lock); 4272 } 4273 } 4274 4275 data_src = (u64 *)hwstats; 4276 4277 do { 4278 data_dst = data; 4279 start = u64_stats_fetch_begin(&hwstats->syncp); 4280 4281 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4282 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 4283 if (mtk_page_pool_enabled(mac->hw)) 4284 mtk_ethtool_pp_stats(mac->hw, data_dst); 4285 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 4286 } 4287 4288 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 4289 u32 *rule_locs) 4290 { 4291 int ret = -EOPNOTSUPP; 4292 4293 switch (cmd->cmd) { 4294 case ETHTOOL_GRXRINGS: 4295 if (dev->hw_features & NETIF_F_LRO) { 4296 cmd->data = MTK_MAX_RX_RING_NUM; 4297 ret = 0; 4298 } 4299 break; 4300 case ETHTOOL_GRXCLSRLCNT: 4301 if (dev->hw_features & NETIF_F_LRO) { 4302 struct mtk_mac *mac = netdev_priv(dev); 4303 4304 cmd->rule_cnt = mac->hwlro_ip_cnt; 4305 ret = 0; 4306 } 4307 break; 4308 case ETHTOOL_GRXCLSRULE: 4309 if (dev->hw_features & NETIF_F_LRO) 4310 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 4311 break; 4312 case ETHTOOL_GRXCLSRLALL: 4313 if (dev->hw_features & NETIF_F_LRO) 4314 ret = mtk_hwlro_get_fdir_all(dev, cmd, 4315 rule_locs); 4316 break; 4317 default: 4318 break; 4319 } 4320 4321 return ret; 4322 } 4323 4324 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 4325 { 4326 int ret = -EOPNOTSUPP; 4327 4328 switch (cmd->cmd) { 4329 case ETHTOOL_SRXCLSRLINS: 4330 if (dev->hw_features & NETIF_F_LRO) 4331 ret = mtk_hwlro_add_ipaddr(dev, cmd); 4332 break; 4333 case ETHTOOL_SRXCLSRLDEL: 4334 if (dev->hw_features & NETIF_F_LRO) 4335 ret = mtk_hwlro_del_ipaddr(dev, cmd); 4336 break; 4337 default: 4338 break; 4339 } 4340 4341 return ret; 4342 } 4343 4344 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4345 struct net_device *sb_dev) 4346 { 4347 struct mtk_mac *mac = netdev_priv(dev); 4348 unsigned int queue = 0; 4349 4350 if (netdev_uses_dsa(dev)) 4351 queue = skb_get_queue_mapping(skb) + 3; 4352 else 4353 queue = mac->id; 4354 4355 if (queue >= dev->num_tx_queues) 4356 queue = 0; 4357 4358 return queue; 4359 } 4360 4361 static const struct ethtool_ops mtk_ethtool_ops = { 4362 .get_link_ksettings = mtk_get_link_ksettings, 4363 .set_link_ksettings = mtk_set_link_ksettings, 4364 .get_drvinfo = mtk_get_drvinfo, 4365 .get_msglevel = mtk_get_msglevel, 4366 .set_msglevel = mtk_set_msglevel, 4367 .nway_reset = mtk_nway_reset, 4368 .get_link = ethtool_op_get_link, 4369 .get_strings = mtk_get_strings, 4370 .get_sset_count = mtk_get_sset_count, 4371 .get_ethtool_stats = mtk_get_ethtool_stats, 4372 .get_rxnfc = mtk_get_rxnfc, 4373 .set_rxnfc = mtk_set_rxnfc, 4374 }; 4375 4376 static const struct net_device_ops mtk_netdev_ops = { 4377 .ndo_uninit = mtk_uninit, 4378 .ndo_open = mtk_open, 4379 .ndo_stop = mtk_stop, 4380 .ndo_start_xmit = mtk_start_xmit, 4381 .ndo_set_mac_address = mtk_set_mac_address, 4382 .ndo_validate_addr = eth_validate_addr, 4383 .ndo_eth_ioctl = mtk_do_ioctl, 4384 .ndo_change_mtu = mtk_change_mtu, 4385 .ndo_tx_timeout = mtk_tx_timeout, 4386 .ndo_get_stats64 = mtk_get_stats64, 4387 .ndo_fix_features = mtk_fix_features, 4388 .ndo_set_features = mtk_set_features, 4389 #ifdef CONFIG_NET_POLL_CONTROLLER 4390 .ndo_poll_controller = mtk_poll_controller, 4391 #endif 4392 .ndo_setup_tc = mtk_eth_setup_tc, 4393 .ndo_bpf = mtk_xdp, 4394 .ndo_xdp_xmit = mtk_xdp_xmit, 4395 .ndo_select_queue = mtk_select_queue, 4396 }; 4397 4398 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4399 { 4400 const __be32 *_id = of_get_property(np, "reg", NULL); 4401 phy_interface_t phy_mode; 4402 struct phylink *phylink; 4403 struct mtk_mac *mac; 4404 int id, err; 4405 int txqs = 1; 4406 u32 val; 4407 4408 if (!_id) { 4409 dev_err(eth->dev, "missing mac id\n"); 4410 return -EINVAL; 4411 } 4412 4413 id = be32_to_cpup(_id); 4414 if (id >= MTK_MAX_DEVS) { 4415 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4416 return -EINVAL; 4417 } 4418 4419 if (eth->netdev[id]) { 4420 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4421 return -EINVAL; 4422 } 4423 4424 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4425 txqs = MTK_QDMA_NUM_QUEUES; 4426 4427 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4428 if (!eth->netdev[id]) { 4429 dev_err(eth->dev, "alloc_etherdev failed\n"); 4430 return -ENOMEM; 4431 } 4432 mac = netdev_priv(eth->netdev[id]); 4433 eth->mac[id] = mac; 4434 mac->id = id; 4435 mac->hw = eth; 4436 mac->of_node = np; 4437 4438 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]); 4439 if (err == -EPROBE_DEFER) 4440 return err; 4441 4442 if (err) { 4443 /* If the mac address is invalid, use random mac address */ 4444 eth_hw_addr_random(eth->netdev[id]); 4445 dev_err(eth->dev, "generated random MAC address %pM\n", 4446 eth->netdev[id]->dev_addr); 4447 } 4448 4449 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4450 mac->hwlro_ip_cnt = 0; 4451 4452 mac->hw_stats = devm_kzalloc(eth->dev, 4453 sizeof(*mac->hw_stats), 4454 GFP_KERNEL); 4455 if (!mac->hw_stats) { 4456 dev_err(eth->dev, "failed to allocate counter memory\n"); 4457 err = -ENOMEM; 4458 goto free_netdev; 4459 } 4460 spin_lock_init(&mac->hw_stats->stats_lock); 4461 u64_stats_init(&mac->hw_stats->syncp); 4462 4463 if (mtk_is_netsys_v3_or_greater(eth)) 4464 mac->hw_stats->reg_offset = id * 0x80; 4465 else 4466 mac->hw_stats->reg_offset = id * 0x40; 4467 4468 /* phylink create */ 4469 err = of_get_phy_mode(np, &phy_mode); 4470 if (err) { 4471 dev_err(eth->dev, "incorrect phy-mode\n"); 4472 goto free_netdev; 4473 } 4474 4475 /* mac config is not set */ 4476 mac->interface = PHY_INTERFACE_MODE_NA; 4477 mac->speed = SPEED_UNKNOWN; 4478 4479 mac->phylink_config.dev = ð->netdev[id]->dev; 4480 mac->phylink_config.type = PHYLINK_NETDEV; 4481 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4482 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4483 4484 /* MT7623 gmac0 is now missing its speed-specific PLL configuration 4485 * in its .mac_config method (since state->speed is not valid there. 4486 * Disable support for MII, GMII and RGMII. 4487 */ 4488 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { 4489 __set_bit(PHY_INTERFACE_MODE_MII, 4490 mac->phylink_config.supported_interfaces); 4491 __set_bit(PHY_INTERFACE_MODE_GMII, 4492 mac->phylink_config.supported_interfaces); 4493 4494 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4495 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4496 } 4497 4498 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4499 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4500 mac->phylink_config.supported_interfaces); 4501 4502 /* TRGMII is not permitted on MT7621 if using DDR2 */ 4503 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 4504 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { 4505 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 4506 if (val & SYSCFG_DRAM_TYPE_DDR2) 4507 __clear_bit(PHY_INTERFACE_MODE_TRGMII, 4508 mac->phylink_config.supported_interfaces); 4509 } 4510 4511 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4512 __set_bit(PHY_INTERFACE_MODE_SGMII, 4513 mac->phylink_config.supported_interfaces); 4514 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4515 mac->phylink_config.supported_interfaces); 4516 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4517 mac->phylink_config.supported_interfaces); 4518 } 4519 4520 if (mtk_is_netsys_v3_or_greater(mac->hw) && 4521 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && 4522 id == MTK_GMAC1_ID) { 4523 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 4524 MAC_SYM_PAUSE | 4525 MAC_10000FD; 4526 phy_interface_zero(mac->phylink_config.supported_interfaces); 4527 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 4528 mac->phylink_config.supported_interfaces); 4529 } 4530 4531 phylink = phylink_create(&mac->phylink_config, 4532 of_fwnode_handle(mac->of_node), 4533 phy_mode, &mtk_phylink_ops); 4534 if (IS_ERR(phylink)) { 4535 err = PTR_ERR(phylink); 4536 goto free_netdev; 4537 } 4538 4539 mac->phylink = phylink; 4540 4541 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4542 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4543 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4544 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4545 4546 eth->netdev[id]->hw_features = eth->soc->hw_features; 4547 if (eth->hwlro) 4548 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4549 4550 eth->netdev[id]->vlan_features = eth->soc->hw_features & 4551 ~NETIF_F_HW_VLAN_CTAG_TX; 4552 eth->netdev[id]->features |= eth->soc->hw_features; 4553 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 4554 4555 eth->netdev[id]->irq = eth->irq[0]; 4556 eth->netdev[id]->dev.of_node = np; 4557 4558 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4559 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 4560 else 4561 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 4562 4563 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 4564 mac->device_notifier.notifier_call = mtk_device_event; 4565 register_netdevice_notifier(&mac->device_notifier); 4566 } 4567 4568 if (mtk_page_pool_enabled(eth)) 4569 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | 4570 NETDEV_XDP_ACT_REDIRECT | 4571 NETDEV_XDP_ACT_NDO_XMIT | 4572 NETDEV_XDP_ACT_NDO_XMIT_SG; 4573 4574 return 0; 4575 4576 free_netdev: 4577 free_netdev(eth->netdev[id]); 4578 return err; 4579 } 4580 4581 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 4582 { 4583 struct net_device *dev, *tmp; 4584 LIST_HEAD(dev_list); 4585 int i; 4586 4587 rtnl_lock(); 4588 4589 for (i = 0; i < MTK_MAX_DEVS; i++) { 4590 dev = eth->netdev[i]; 4591 4592 if (!dev || !(dev->flags & IFF_UP)) 4593 continue; 4594 4595 list_add_tail(&dev->close_list, &dev_list); 4596 } 4597 4598 dev_close_many(&dev_list, false); 4599 4600 eth->dma_dev = dma_dev; 4601 4602 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 4603 list_del_init(&dev->close_list); 4604 dev_open(dev, NULL); 4605 } 4606 4607 rtnl_unlock(); 4608 } 4609 4610 static int mtk_sgmii_init(struct mtk_eth *eth) 4611 { 4612 struct device_node *np; 4613 struct regmap *regmap; 4614 u32 flags; 4615 int i; 4616 4617 for (i = 0; i < MTK_MAX_DEVS; i++) { 4618 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); 4619 if (!np) 4620 break; 4621 4622 regmap = syscon_node_to_regmap(np); 4623 flags = 0; 4624 if (of_property_read_bool(np, "mediatek,pnswap")) 4625 flags |= MTK_SGMII_FLAG_PN_SWAP; 4626 4627 of_node_put(np); 4628 4629 if (IS_ERR(regmap)) 4630 return PTR_ERR(regmap); 4631 4632 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap, 4633 eth->soc->ana_rgc3, 4634 flags); 4635 } 4636 4637 return 0; 4638 } 4639 4640 static int mtk_probe(struct platform_device *pdev) 4641 { 4642 struct resource *res = NULL; 4643 struct device_node *mac_np; 4644 struct mtk_eth *eth; 4645 int err, i; 4646 4647 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 4648 if (!eth) 4649 return -ENOMEM; 4650 4651 eth->soc = of_device_get_match_data(&pdev->dev); 4652 4653 eth->dev = &pdev->dev; 4654 eth->dma_dev = &pdev->dev; 4655 eth->base = devm_platform_ioremap_resource(pdev, 0); 4656 if (IS_ERR(eth->base)) 4657 return PTR_ERR(eth->base); 4658 4659 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4660 eth->ip_align = NET_IP_ALIGN; 4661 4662 spin_lock_init(ð->page_lock); 4663 spin_lock_init(ð->tx_irq_lock); 4664 spin_lock_init(ð->rx_irq_lock); 4665 spin_lock_init(ð->dim_lock); 4666 4667 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4668 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 4669 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); 4670 4671 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4672 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 4673 4674 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4675 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4676 "mediatek,ethsys"); 4677 if (IS_ERR(eth->ethsys)) { 4678 dev_err(&pdev->dev, "no ethsys regmap found\n"); 4679 return PTR_ERR(eth->ethsys); 4680 } 4681 } 4682 4683 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 4684 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4685 "mediatek,infracfg"); 4686 if (IS_ERR(eth->infra)) { 4687 dev_err(&pdev->dev, "no infracfg regmap found\n"); 4688 return PTR_ERR(eth->infra); 4689 } 4690 } 4691 4692 if (of_dma_is_coherent(pdev->dev.of_node)) { 4693 struct regmap *cci; 4694 4695 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4696 "cci-control-port"); 4697 /* enable CPU/bus coherency */ 4698 if (!IS_ERR(cci)) 4699 regmap_write(cci, 0, 3); 4700 } 4701 4702 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4703 err = mtk_sgmii_init(eth); 4704 4705 if (err) 4706 return err; 4707 } 4708 4709 if (eth->soc->required_pctl) { 4710 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4711 "mediatek,pctl"); 4712 if (IS_ERR(eth->pctl)) { 4713 dev_err(&pdev->dev, "no pctl regmap found\n"); 4714 err = PTR_ERR(eth->pctl); 4715 goto err_destroy_sgmii; 4716 } 4717 } 4718 4719 if (mtk_is_netsys_v2_or_greater(eth)) { 4720 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4721 if (!res) { 4722 err = -EINVAL; 4723 goto err_destroy_sgmii; 4724 } 4725 } 4726 4727 if (eth->soc->offload_version) { 4728 for (i = 0;; i++) { 4729 struct device_node *np; 4730 phys_addr_t wdma_phy; 4731 u32 wdma_base; 4732 4733 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4734 break; 4735 4736 np = of_parse_phandle(pdev->dev.of_node, 4737 "mediatek,wed", i); 4738 if (!np) 4739 break; 4740 4741 wdma_base = eth->soc->reg_map->wdma_base[i]; 4742 wdma_phy = res ? res->start + wdma_base : 0; 4743 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4744 wdma_phy, i); 4745 } 4746 } 4747 4748 for (i = 0; i < 3; i++) { 4749 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4750 eth->irq[i] = eth->irq[0]; 4751 else 4752 eth->irq[i] = platform_get_irq(pdev, i); 4753 if (eth->irq[i] < 0) { 4754 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4755 err = -ENXIO; 4756 goto err_wed_exit; 4757 } 4758 } 4759 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4760 eth->clks[i] = devm_clk_get(eth->dev, 4761 mtk_clks_source_name[i]); 4762 if (IS_ERR(eth->clks[i])) { 4763 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 4764 err = -EPROBE_DEFER; 4765 goto err_wed_exit; 4766 } 4767 if (eth->soc->required_clks & BIT(i)) { 4768 dev_err(&pdev->dev, "clock %s not found\n", 4769 mtk_clks_source_name[i]); 4770 err = -EINVAL; 4771 goto err_wed_exit; 4772 } 4773 eth->clks[i] = NULL; 4774 } 4775 } 4776 4777 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 4778 INIT_WORK(ð->pending_work, mtk_pending_work); 4779 4780 err = mtk_hw_init(eth, false); 4781 if (err) 4782 goto err_wed_exit; 4783 4784 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 4785 4786 for_each_child_of_node(pdev->dev.of_node, mac_np) { 4787 if (!of_device_is_compatible(mac_np, 4788 "mediatek,eth-mac")) 4789 continue; 4790 4791 if (!of_device_is_available(mac_np)) 4792 continue; 4793 4794 err = mtk_add_mac(eth, mac_np); 4795 if (err) { 4796 of_node_put(mac_np); 4797 goto err_deinit_hw; 4798 } 4799 } 4800 4801 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 4802 err = devm_request_irq(eth->dev, eth->irq[0], 4803 mtk_handle_irq, 0, 4804 dev_name(eth->dev), eth); 4805 } else { 4806 err = devm_request_irq(eth->dev, eth->irq[1], 4807 mtk_handle_irq_tx, 0, 4808 dev_name(eth->dev), eth); 4809 if (err) 4810 goto err_free_dev; 4811 4812 err = devm_request_irq(eth->dev, eth->irq[2], 4813 mtk_handle_irq_rx, 0, 4814 dev_name(eth->dev), eth); 4815 } 4816 if (err) 4817 goto err_free_dev; 4818 4819 /* No MT7628/88 support yet */ 4820 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4821 err = mtk_mdio_init(eth); 4822 if (err) 4823 goto err_free_dev; 4824 } 4825 4826 if (eth->soc->offload_version) { 4827 u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1; 4828 4829 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); 4830 for (i = 0; i < num_ppe; i++) { 4831 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; 4832 4833 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i); 4834 4835 if (!eth->ppe[i]) { 4836 err = -ENOMEM; 4837 goto err_deinit_ppe; 4838 } 4839 } 4840 4841 err = mtk_eth_offload_init(eth); 4842 if (err) 4843 goto err_deinit_ppe; 4844 } 4845 4846 for (i = 0; i < MTK_MAX_DEVS; i++) { 4847 if (!eth->netdev[i]) 4848 continue; 4849 4850 err = register_netdev(eth->netdev[i]); 4851 if (err) { 4852 dev_err(eth->dev, "error bringing up device\n"); 4853 goto err_deinit_ppe; 4854 } else 4855 netif_info(eth, probe, eth->netdev[i], 4856 "mediatek frame engine at 0x%08lx, irq %d\n", 4857 eth->netdev[i]->base_addr, eth->irq[0]); 4858 } 4859 4860 /* we run 2 devices on the same DMA ring so we need a dummy device 4861 * for NAPI to work 4862 */ 4863 init_dummy_netdev(ð->dummy_dev); 4864 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx); 4865 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx); 4866 4867 platform_set_drvdata(pdev, eth); 4868 schedule_delayed_work(ð->reset.monitor_work, 4869 MTK_DMA_MONITOR_TIMEOUT); 4870 4871 return 0; 4872 4873 err_deinit_ppe: 4874 mtk_ppe_deinit(eth); 4875 mtk_mdio_cleanup(eth); 4876 err_free_dev: 4877 mtk_free_dev(eth); 4878 err_deinit_hw: 4879 mtk_hw_deinit(eth); 4880 err_wed_exit: 4881 mtk_wed_exit(); 4882 err_destroy_sgmii: 4883 mtk_sgmii_destroy(eth); 4884 4885 return err; 4886 } 4887 4888 static int mtk_remove(struct platform_device *pdev) 4889 { 4890 struct mtk_eth *eth = platform_get_drvdata(pdev); 4891 struct mtk_mac *mac; 4892 int i; 4893 4894 /* stop all devices to make sure that dma is properly shut down */ 4895 for (i = 0; i < MTK_MAX_DEVS; i++) { 4896 if (!eth->netdev[i]) 4897 continue; 4898 mtk_stop(eth->netdev[i]); 4899 mac = netdev_priv(eth->netdev[i]); 4900 phylink_disconnect_phy(mac->phylink); 4901 } 4902 4903 mtk_wed_exit(); 4904 mtk_hw_deinit(eth); 4905 4906 netif_napi_del(ð->tx_napi); 4907 netif_napi_del(ð->rx_napi); 4908 mtk_cleanup(eth); 4909 mtk_mdio_cleanup(eth); 4910 4911 return 0; 4912 } 4913 4914 static const struct mtk_soc_data mt2701_data = { 4915 .reg_map = &mtk_reg_map, 4916 .caps = MT7623_CAPS | MTK_HWLRO, 4917 .hw_features = MTK_HW_FEATURES, 4918 .required_clks = MT7623_CLKS_BITMAP, 4919 .required_pctl = true, 4920 .version = 1, 4921 .txrx = { 4922 .txd_size = sizeof(struct mtk_tx_dma), 4923 .rxd_size = sizeof(struct mtk_rx_dma), 4924 .rx_irq_done_mask = MTK_RX_DONE_INT, 4925 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4926 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4927 .dma_len_offset = 16, 4928 }, 4929 }; 4930 4931 static const struct mtk_soc_data mt7621_data = { 4932 .reg_map = &mtk_reg_map, 4933 .caps = MT7621_CAPS, 4934 .hw_features = MTK_HW_FEATURES, 4935 .required_clks = MT7621_CLKS_BITMAP, 4936 .required_pctl = false, 4937 .version = 1, 4938 .offload_version = 1, 4939 .hash_offset = 2, 4940 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 4941 .txrx = { 4942 .txd_size = sizeof(struct mtk_tx_dma), 4943 .rxd_size = sizeof(struct mtk_rx_dma), 4944 .rx_irq_done_mask = MTK_RX_DONE_INT, 4945 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4946 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4947 .dma_len_offset = 16, 4948 }, 4949 }; 4950 4951 static const struct mtk_soc_data mt7622_data = { 4952 .reg_map = &mtk_reg_map, 4953 .ana_rgc3 = 0x2028, 4954 .caps = MT7622_CAPS | MTK_HWLRO, 4955 .hw_features = MTK_HW_FEATURES, 4956 .required_clks = MT7622_CLKS_BITMAP, 4957 .required_pctl = false, 4958 .version = 1, 4959 .offload_version = 2, 4960 .hash_offset = 2, 4961 .has_accounting = true, 4962 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 4963 .txrx = { 4964 .txd_size = sizeof(struct mtk_tx_dma), 4965 .rxd_size = sizeof(struct mtk_rx_dma), 4966 .rx_irq_done_mask = MTK_RX_DONE_INT, 4967 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4968 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4969 .dma_len_offset = 16, 4970 }, 4971 }; 4972 4973 static const struct mtk_soc_data mt7623_data = { 4974 .reg_map = &mtk_reg_map, 4975 .caps = MT7623_CAPS | MTK_HWLRO, 4976 .hw_features = MTK_HW_FEATURES, 4977 .required_clks = MT7623_CLKS_BITMAP, 4978 .required_pctl = true, 4979 .version = 1, 4980 .offload_version = 1, 4981 .hash_offset = 2, 4982 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, 4983 .disable_pll_modes = true, 4984 .txrx = { 4985 .txd_size = sizeof(struct mtk_tx_dma), 4986 .rxd_size = sizeof(struct mtk_rx_dma), 4987 .rx_irq_done_mask = MTK_RX_DONE_INT, 4988 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4989 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4990 .dma_len_offset = 16, 4991 }, 4992 }; 4993 4994 static const struct mtk_soc_data mt7629_data = { 4995 .reg_map = &mtk_reg_map, 4996 .ana_rgc3 = 0x128, 4997 .caps = MT7629_CAPS | MTK_HWLRO, 4998 .hw_features = MTK_HW_FEATURES, 4999 .required_clks = MT7629_CLKS_BITMAP, 5000 .required_pctl = false, 5001 .has_accounting = true, 5002 .version = 1, 5003 .txrx = { 5004 .txd_size = sizeof(struct mtk_tx_dma), 5005 .rxd_size = sizeof(struct mtk_rx_dma), 5006 .rx_irq_done_mask = MTK_RX_DONE_INT, 5007 .rx_dma_l4_valid = RX_DMA_L4_VALID, 5008 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5009 .dma_len_offset = 16, 5010 }, 5011 }; 5012 5013 static const struct mtk_soc_data mt7981_data = { 5014 .reg_map = &mt7986_reg_map, 5015 .ana_rgc3 = 0x128, 5016 .caps = MT7981_CAPS, 5017 .hw_features = MTK_HW_FEATURES, 5018 .required_clks = MT7981_CLKS_BITMAP, 5019 .required_pctl = false, 5020 .version = 2, 5021 .offload_version = 2, 5022 .hash_offset = 4, 5023 .has_accounting = true, 5024 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5025 .txrx = { 5026 .txd_size = sizeof(struct mtk_tx_dma_v2), 5027 .rxd_size = sizeof(struct mtk_rx_dma_v2), 5028 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 5029 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 5030 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5031 .dma_len_offset = 8, 5032 }, 5033 }; 5034 5035 static const struct mtk_soc_data mt7986_data = { 5036 .reg_map = &mt7986_reg_map, 5037 .ana_rgc3 = 0x128, 5038 .caps = MT7986_CAPS, 5039 .hw_features = MTK_HW_FEATURES, 5040 .required_clks = MT7986_CLKS_BITMAP, 5041 .required_pctl = false, 5042 .version = 2, 5043 .offload_version = 2, 5044 .hash_offset = 4, 5045 .has_accounting = true, 5046 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 5047 .txrx = { 5048 .txd_size = sizeof(struct mtk_tx_dma_v2), 5049 .rxd_size = sizeof(struct mtk_rx_dma_v2), 5050 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 5051 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 5052 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5053 .dma_len_offset = 8, 5054 }, 5055 }; 5056 5057 static const struct mtk_soc_data mt7988_data = { 5058 .reg_map = &mt7988_reg_map, 5059 .ana_rgc3 = 0x128, 5060 .caps = MT7988_CAPS, 5061 .hw_features = MTK_HW_FEATURES, 5062 .required_clks = MT7988_CLKS_BITMAP, 5063 .required_pctl = false, 5064 .version = 3, 5065 .offload_version = 2, 5066 .hash_offset = 4, 5067 .has_accounting = true, 5068 .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, 5069 .txrx = { 5070 .txd_size = sizeof(struct mtk_tx_dma_v2), 5071 .rxd_size = sizeof(struct mtk_rx_dma_v2), 5072 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 5073 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 5074 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 5075 .dma_len_offset = 8, 5076 }, 5077 }; 5078 5079 static const struct mtk_soc_data rt5350_data = { 5080 .reg_map = &mt7628_reg_map, 5081 .caps = MT7628_CAPS, 5082 .hw_features = MTK_HW_FEATURES_MT7628, 5083 .required_clks = MT7628_CLKS_BITMAP, 5084 .required_pctl = false, 5085 .version = 1, 5086 .txrx = { 5087 .txd_size = sizeof(struct mtk_tx_dma), 5088 .rxd_size = sizeof(struct mtk_rx_dma), 5089 .rx_irq_done_mask = MTK_RX_DONE_INT, 5090 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, 5091 .dma_max_len = MTK_TX_DMA_BUF_LEN, 5092 .dma_len_offset = 16, 5093 }, 5094 }; 5095 5096 const struct of_device_id of_mtk_match[] = { 5097 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, 5098 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, 5099 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, 5100 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, 5101 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, 5102 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, 5103 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, 5104 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, 5105 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, 5106 {}, 5107 }; 5108 MODULE_DEVICE_TABLE(of, of_mtk_match); 5109 5110 static struct platform_driver mtk_driver = { 5111 .probe = mtk_probe, 5112 .remove = mtk_remove, 5113 .driver = { 5114 .name = "mtk_soc_eth", 5115 .of_match_table = of_mtk_match, 5116 }, 5117 }; 5118 5119 module_platform_driver(mtk_driver); 5120 5121 MODULE_LICENSE("GPL"); 5122 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 5123 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 5124