1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/regmap.h> 14 #include <linux/clk.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/if_vlan.h> 17 #include <linux/reset.h> 18 #include <linux/tcp.h> 19 #include <linux/interrupt.h> 20 #include <linux/pinctrl/devinfo.h> 21 #include <linux/phylink.h> 22 #include <linux/jhash.h> 23 #include <net/dsa.h> 24 25 #include "mtk_eth_soc.h" 26 27 static int mtk_msg_level = -1; 28 module_param_named(msg_level, mtk_msg_level, int, 0); 29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 30 31 #define MTK_ETHTOOL_STAT(x) { #x, \ 32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 33 34 /* strings used by ethtool */ 35 static const struct mtk_ethtool_stats { 36 char str[ETH_GSTRING_LEN]; 37 u32 offset; 38 } mtk_ethtool_stats[] = { 39 MTK_ETHTOOL_STAT(tx_bytes), 40 MTK_ETHTOOL_STAT(tx_packets), 41 MTK_ETHTOOL_STAT(tx_skip), 42 MTK_ETHTOOL_STAT(tx_collisions), 43 MTK_ETHTOOL_STAT(rx_bytes), 44 MTK_ETHTOOL_STAT(rx_packets), 45 MTK_ETHTOOL_STAT(rx_overflow), 46 MTK_ETHTOOL_STAT(rx_fcs_errors), 47 MTK_ETHTOOL_STAT(rx_short_errors), 48 MTK_ETHTOOL_STAT(rx_long_errors), 49 MTK_ETHTOOL_STAT(rx_checksum_errors), 50 MTK_ETHTOOL_STAT(rx_flow_control_packets), 51 }; 52 53 static const char * const mtk_clks_source_name[] = { 54 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 55 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 56 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 57 "sgmii_ck", "eth2pll", 58 }; 59 60 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 61 { 62 __raw_writel(val, eth->base + reg); 63 } 64 65 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 66 { 67 return __raw_readl(eth->base + reg); 68 } 69 70 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 71 { 72 u32 val; 73 74 val = mtk_r32(eth, reg); 75 val &= ~mask; 76 val |= set; 77 mtk_w32(eth, val, reg); 78 return reg; 79 } 80 81 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 82 { 83 unsigned long t_start = jiffies; 84 85 while (1) { 86 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 87 return 0; 88 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 89 break; 90 cond_resched(); 91 } 92 93 dev_err(eth->dev, "mdio: MDIO timeout\n"); 94 return -ETIMEDOUT; 95 } 96 97 static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 98 u32 write_data) 99 { 100 int ret; 101 102 ret = mtk_mdio_busy_wait(eth); 103 if (ret < 0) 104 return ret; 105 106 if (phy_reg & MII_ADDR_C45) { 107 mtk_w32(eth, PHY_IAC_ACCESS | 108 PHY_IAC_START_C45 | 109 PHY_IAC_CMD_C45_ADDR | 110 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 111 PHY_IAC_ADDR(phy_addr) | 112 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 113 MTK_PHY_IAC); 114 115 ret = mtk_mdio_busy_wait(eth); 116 if (ret < 0) 117 return ret; 118 119 mtk_w32(eth, PHY_IAC_ACCESS | 120 PHY_IAC_START_C45 | 121 PHY_IAC_CMD_WRITE | 122 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 123 PHY_IAC_ADDR(phy_addr) | 124 PHY_IAC_DATA(write_data), 125 MTK_PHY_IAC); 126 } else { 127 mtk_w32(eth, PHY_IAC_ACCESS | 128 PHY_IAC_START_C22 | 129 PHY_IAC_CMD_WRITE | 130 PHY_IAC_REG(phy_reg) | 131 PHY_IAC_ADDR(phy_addr) | 132 PHY_IAC_DATA(write_data), 133 MTK_PHY_IAC); 134 } 135 136 ret = mtk_mdio_busy_wait(eth); 137 if (ret < 0) 138 return ret; 139 140 return 0; 141 } 142 143 static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 144 { 145 int ret; 146 147 ret = mtk_mdio_busy_wait(eth); 148 if (ret < 0) 149 return ret; 150 151 if (phy_reg & MII_ADDR_C45) { 152 mtk_w32(eth, PHY_IAC_ACCESS | 153 PHY_IAC_START_C45 | 154 PHY_IAC_CMD_C45_ADDR | 155 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 156 PHY_IAC_ADDR(phy_addr) | 157 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 158 MTK_PHY_IAC); 159 160 ret = mtk_mdio_busy_wait(eth); 161 if (ret < 0) 162 return ret; 163 164 mtk_w32(eth, PHY_IAC_ACCESS | 165 PHY_IAC_START_C45 | 166 PHY_IAC_CMD_C45_READ | 167 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 168 PHY_IAC_ADDR(phy_addr), 169 MTK_PHY_IAC); 170 } else { 171 mtk_w32(eth, PHY_IAC_ACCESS | 172 PHY_IAC_START_C22 | 173 PHY_IAC_CMD_C22_READ | 174 PHY_IAC_REG(phy_reg) | 175 PHY_IAC_ADDR(phy_addr), 176 MTK_PHY_IAC); 177 } 178 179 ret = mtk_mdio_busy_wait(eth); 180 if (ret < 0) 181 return ret; 182 183 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 184 } 185 186 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 187 int phy_reg, u16 val) 188 { 189 struct mtk_eth *eth = bus->priv; 190 191 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 192 } 193 194 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 195 { 196 struct mtk_eth *eth = bus->priv; 197 198 return _mtk_mdio_read(eth, phy_addr, phy_reg); 199 } 200 201 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 202 phy_interface_t interface) 203 { 204 u32 val; 205 206 /* Check DDR memory type. 207 * Currently TRGMII mode with DDR2 memory is not supported. 208 */ 209 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 210 if (interface == PHY_INTERFACE_MODE_TRGMII && 211 val & SYSCFG_DRAM_TYPE_DDR2) { 212 dev_err(eth->dev, 213 "TRGMII mode with DDR2 memory is not supported!\n"); 214 return -EOPNOTSUPP; 215 } 216 217 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 218 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 219 220 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 221 ETHSYS_TRGMII_MT7621_MASK, val); 222 223 return 0; 224 } 225 226 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 227 phy_interface_t interface, int speed) 228 { 229 u32 val; 230 int ret; 231 232 if (interface == PHY_INTERFACE_MODE_TRGMII) { 233 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 234 val = 500000000; 235 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 236 if (ret) 237 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 238 return; 239 } 240 241 val = (speed == SPEED_1000) ? 242 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 243 mtk_w32(eth, val, INTF_MODE); 244 245 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 246 ETHSYS_TRGMII_CLK_SEL362_5, 247 ETHSYS_TRGMII_CLK_SEL362_5); 248 249 val = (speed == SPEED_1000) ? 250000000 : 500000000; 250 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 251 if (ret) 252 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 253 254 val = (speed == SPEED_1000) ? 255 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 256 mtk_w32(eth, val, TRGMII_RCK_CTRL); 257 258 val = (speed == SPEED_1000) ? 259 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 260 mtk_w32(eth, val, TRGMII_TCK_CTRL); 261 } 262 263 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 264 const struct phylink_link_state *state) 265 { 266 struct mtk_mac *mac = container_of(config, struct mtk_mac, 267 phylink_config); 268 struct mtk_eth *eth = mac->hw; 269 u32 mcr_cur, mcr_new, sid, i; 270 int val, ge_mode, err = 0; 271 272 /* MT76x8 has no hardware settings between for the MAC */ 273 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 274 mac->interface != state->interface) { 275 /* Setup soc pin functions */ 276 switch (state->interface) { 277 case PHY_INTERFACE_MODE_TRGMII: 278 if (mac->id) 279 goto err_phy; 280 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 281 MTK_GMAC1_TRGMII)) 282 goto err_phy; 283 fallthrough; 284 case PHY_INTERFACE_MODE_RGMII_TXID: 285 case PHY_INTERFACE_MODE_RGMII_RXID: 286 case PHY_INTERFACE_MODE_RGMII_ID: 287 case PHY_INTERFACE_MODE_RGMII: 288 case PHY_INTERFACE_MODE_MII: 289 case PHY_INTERFACE_MODE_REVMII: 290 case PHY_INTERFACE_MODE_RMII: 291 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 292 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 293 if (err) 294 goto init_err; 295 } 296 break; 297 case PHY_INTERFACE_MODE_1000BASEX: 298 case PHY_INTERFACE_MODE_2500BASEX: 299 case PHY_INTERFACE_MODE_SGMII: 300 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 301 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 302 if (err) 303 goto init_err; 304 } 305 break; 306 case PHY_INTERFACE_MODE_GMII: 307 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 308 err = mtk_gmac_gephy_path_setup(eth, mac->id); 309 if (err) 310 goto init_err; 311 } 312 break; 313 default: 314 goto err_phy; 315 } 316 317 /* Setup clock for 1st gmac */ 318 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 319 !phy_interface_mode_is_8023z(state->interface) && 320 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 321 if (MTK_HAS_CAPS(mac->hw->soc->caps, 322 MTK_TRGMII_MT7621_CLK)) { 323 if (mt7621_gmac0_rgmii_adjust(mac->hw, 324 state->interface)) 325 goto err_phy; 326 } else { 327 mtk_gmac0_rgmii_adjust(mac->hw, 328 state->interface, 329 state->speed); 330 331 /* mt7623_pad_clk_setup */ 332 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 333 mtk_w32(mac->hw, 334 TD_DM_DRVP(8) | TD_DM_DRVN(8), 335 TRGMII_TD_ODT(i)); 336 337 /* Assert/release MT7623 RXC reset */ 338 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 339 TRGMII_RCK_CTRL); 340 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 341 } 342 } 343 344 ge_mode = 0; 345 switch (state->interface) { 346 case PHY_INTERFACE_MODE_MII: 347 case PHY_INTERFACE_MODE_GMII: 348 ge_mode = 1; 349 break; 350 case PHY_INTERFACE_MODE_REVMII: 351 ge_mode = 2; 352 break; 353 case PHY_INTERFACE_MODE_RMII: 354 if (mac->id) 355 goto err_phy; 356 ge_mode = 3; 357 break; 358 default: 359 break; 360 } 361 362 /* put the gmac into the right mode */ 363 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 364 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 365 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 366 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 367 368 mac->interface = state->interface; 369 } 370 371 /* SGMII */ 372 if (state->interface == PHY_INTERFACE_MODE_SGMII || 373 phy_interface_mode_is_8023z(state->interface)) { 374 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 375 * being setup done. 376 */ 377 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 378 379 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 380 SYSCFG0_SGMII_MASK, 381 ~(u32)SYSCFG0_SGMII_MASK); 382 383 /* Decide how GMAC and SGMIISYS be mapped */ 384 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 385 0 : mac->id; 386 387 /* Setup SGMIISYS with the determined property */ 388 if (state->interface != PHY_INTERFACE_MODE_SGMII) 389 err = mtk_sgmii_setup_mode_force(eth->sgmii, sid, 390 state); 391 else if (phylink_autoneg_inband(mode)) 392 err = mtk_sgmii_setup_mode_an(eth->sgmii, sid); 393 394 if (err) 395 goto init_err; 396 397 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 398 SYSCFG0_SGMII_MASK, val); 399 } else if (phylink_autoneg_inband(mode)) { 400 dev_err(eth->dev, 401 "In-band mode not supported in non SGMII mode!\n"); 402 return; 403 } 404 405 /* Setup gmac */ 406 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 407 mcr_new = mcr_cur; 408 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 409 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; 410 411 /* Only update control register when needed! */ 412 if (mcr_new != mcr_cur) 413 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 414 415 return; 416 417 err_phy: 418 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 419 mac->id, phy_modes(state->interface)); 420 return; 421 422 init_err: 423 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 424 mac->id, phy_modes(state->interface), err); 425 } 426 427 static void mtk_mac_pcs_get_state(struct phylink_config *config, 428 struct phylink_link_state *state) 429 { 430 struct mtk_mac *mac = container_of(config, struct mtk_mac, 431 phylink_config); 432 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 433 434 state->link = (pmsr & MAC_MSR_LINK); 435 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 436 437 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 438 case 0: 439 state->speed = SPEED_10; 440 break; 441 case MAC_MSR_SPEED_100: 442 state->speed = SPEED_100; 443 break; 444 case MAC_MSR_SPEED_1000: 445 state->speed = SPEED_1000; 446 break; 447 default: 448 state->speed = SPEED_UNKNOWN; 449 break; 450 } 451 452 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 453 if (pmsr & MAC_MSR_RX_FC) 454 state->pause |= MLO_PAUSE_RX; 455 if (pmsr & MAC_MSR_TX_FC) 456 state->pause |= MLO_PAUSE_TX; 457 } 458 459 static void mtk_mac_an_restart(struct phylink_config *config) 460 { 461 struct mtk_mac *mac = container_of(config, struct mtk_mac, 462 phylink_config); 463 464 mtk_sgmii_restart_an(mac->hw, mac->id); 465 } 466 467 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 468 phy_interface_t interface) 469 { 470 struct mtk_mac *mac = container_of(config, struct mtk_mac, 471 phylink_config); 472 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 473 474 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 475 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 476 } 477 478 static void mtk_mac_link_up(struct phylink_config *config, 479 struct phy_device *phy, 480 unsigned int mode, phy_interface_t interface, 481 int speed, int duplex, bool tx_pause, bool rx_pause) 482 { 483 struct mtk_mac *mac = container_of(config, struct mtk_mac, 484 phylink_config); 485 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 486 487 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 488 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 489 MAC_MCR_FORCE_RX_FC); 490 491 /* Configure speed */ 492 switch (speed) { 493 case SPEED_2500: 494 case SPEED_1000: 495 mcr |= MAC_MCR_SPEED_1000; 496 break; 497 case SPEED_100: 498 mcr |= MAC_MCR_SPEED_100; 499 break; 500 } 501 502 /* Configure duplex */ 503 if (duplex == DUPLEX_FULL) 504 mcr |= MAC_MCR_FORCE_DPX; 505 506 /* Configure pause modes - phylink will avoid these for half duplex */ 507 if (tx_pause) 508 mcr |= MAC_MCR_FORCE_TX_FC; 509 if (rx_pause) 510 mcr |= MAC_MCR_FORCE_RX_FC; 511 512 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 513 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 514 } 515 516 static const struct phylink_mac_ops mtk_phylink_ops = { 517 .validate = phylink_generic_validate, 518 .mac_pcs_get_state = mtk_mac_pcs_get_state, 519 .mac_an_restart = mtk_mac_an_restart, 520 .mac_config = mtk_mac_config, 521 .mac_link_down = mtk_mac_link_down, 522 .mac_link_up = mtk_mac_link_up, 523 }; 524 525 static int mtk_mdio_init(struct mtk_eth *eth) 526 { 527 struct device_node *mii_np; 528 int ret; 529 530 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 531 if (!mii_np) { 532 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 533 return -ENODEV; 534 } 535 536 if (!of_device_is_available(mii_np)) { 537 ret = -ENODEV; 538 goto err_put_node; 539 } 540 541 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 542 if (!eth->mii_bus) { 543 ret = -ENOMEM; 544 goto err_put_node; 545 } 546 547 eth->mii_bus->name = "mdio"; 548 eth->mii_bus->read = mtk_mdio_read; 549 eth->mii_bus->write = mtk_mdio_write; 550 eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; 551 eth->mii_bus->priv = eth; 552 eth->mii_bus->parent = eth->dev; 553 554 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 555 ret = of_mdiobus_register(eth->mii_bus, mii_np); 556 557 err_put_node: 558 of_node_put(mii_np); 559 return ret; 560 } 561 562 static void mtk_mdio_cleanup(struct mtk_eth *eth) 563 { 564 if (!eth->mii_bus) 565 return; 566 567 mdiobus_unregister(eth->mii_bus); 568 } 569 570 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 571 { 572 unsigned long flags; 573 u32 val; 574 575 spin_lock_irqsave(ð->tx_irq_lock, flags); 576 val = mtk_r32(eth, eth->tx_int_mask_reg); 577 mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg); 578 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 579 } 580 581 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 582 { 583 unsigned long flags; 584 u32 val; 585 586 spin_lock_irqsave(ð->tx_irq_lock, flags); 587 val = mtk_r32(eth, eth->tx_int_mask_reg); 588 mtk_w32(eth, val | mask, eth->tx_int_mask_reg); 589 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 590 } 591 592 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 593 { 594 unsigned long flags; 595 u32 val; 596 597 spin_lock_irqsave(ð->rx_irq_lock, flags); 598 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 599 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 600 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 601 } 602 603 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 604 { 605 unsigned long flags; 606 u32 val; 607 608 spin_lock_irqsave(ð->rx_irq_lock, flags); 609 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 610 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 611 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 612 } 613 614 static int mtk_set_mac_address(struct net_device *dev, void *p) 615 { 616 int ret = eth_mac_addr(dev, p); 617 struct mtk_mac *mac = netdev_priv(dev); 618 struct mtk_eth *eth = mac->hw; 619 const char *macaddr = dev->dev_addr; 620 621 if (ret) 622 return ret; 623 624 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 625 return -EBUSY; 626 627 spin_lock_bh(&mac->hw->page_lock); 628 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 629 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 630 MT7628_SDM_MAC_ADRH); 631 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 632 (macaddr[4] << 8) | macaddr[5], 633 MT7628_SDM_MAC_ADRL); 634 } else { 635 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 636 MTK_GDMA_MAC_ADRH(mac->id)); 637 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 638 (macaddr[4] << 8) | macaddr[5], 639 MTK_GDMA_MAC_ADRL(mac->id)); 640 } 641 spin_unlock_bh(&mac->hw->page_lock); 642 643 return 0; 644 } 645 646 void mtk_stats_update_mac(struct mtk_mac *mac) 647 { 648 struct mtk_hw_stats *hw_stats = mac->hw_stats; 649 struct mtk_eth *eth = mac->hw; 650 651 u64_stats_update_begin(&hw_stats->syncp); 652 653 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 654 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 655 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 656 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 657 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 658 hw_stats->rx_checksum_errors += 659 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 660 } else { 661 unsigned int offs = hw_stats->reg_offset; 662 u64 stats; 663 664 hw_stats->rx_bytes += mtk_r32(mac->hw, 665 MTK_GDM1_RX_GBCNT_L + offs); 666 stats = mtk_r32(mac->hw, MTK_GDM1_RX_GBCNT_H + offs); 667 if (stats) 668 hw_stats->rx_bytes += (stats << 32); 669 hw_stats->rx_packets += 670 mtk_r32(mac->hw, MTK_GDM1_RX_GPCNT + offs); 671 hw_stats->rx_overflow += 672 mtk_r32(mac->hw, MTK_GDM1_RX_OERCNT + offs); 673 hw_stats->rx_fcs_errors += 674 mtk_r32(mac->hw, MTK_GDM1_RX_FERCNT + offs); 675 hw_stats->rx_short_errors += 676 mtk_r32(mac->hw, MTK_GDM1_RX_SERCNT + offs); 677 hw_stats->rx_long_errors += 678 mtk_r32(mac->hw, MTK_GDM1_RX_LENCNT + offs); 679 hw_stats->rx_checksum_errors += 680 mtk_r32(mac->hw, MTK_GDM1_RX_CERCNT + offs); 681 hw_stats->rx_flow_control_packets += 682 mtk_r32(mac->hw, MTK_GDM1_RX_FCCNT + offs); 683 hw_stats->tx_skip += 684 mtk_r32(mac->hw, MTK_GDM1_TX_SKIPCNT + offs); 685 hw_stats->tx_collisions += 686 mtk_r32(mac->hw, MTK_GDM1_TX_COLCNT + offs); 687 hw_stats->tx_bytes += 688 mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_L + offs); 689 stats = mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_H + offs); 690 if (stats) 691 hw_stats->tx_bytes += (stats << 32); 692 hw_stats->tx_packets += 693 mtk_r32(mac->hw, MTK_GDM1_TX_GPCNT + offs); 694 } 695 696 u64_stats_update_end(&hw_stats->syncp); 697 } 698 699 static void mtk_stats_update(struct mtk_eth *eth) 700 { 701 int i; 702 703 for (i = 0; i < MTK_MAC_COUNT; i++) { 704 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 705 continue; 706 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 707 mtk_stats_update_mac(eth->mac[i]); 708 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 709 } 710 } 711 } 712 713 static void mtk_get_stats64(struct net_device *dev, 714 struct rtnl_link_stats64 *storage) 715 { 716 struct mtk_mac *mac = netdev_priv(dev); 717 struct mtk_hw_stats *hw_stats = mac->hw_stats; 718 unsigned int start; 719 720 if (netif_running(dev) && netif_device_present(dev)) { 721 if (spin_trylock_bh(&hw_stats->stats_lock)) { 722 mtk_stats_update_mac(mac); 723 spin_unlock_bh(&hw_stats->stats_lock); 724 } 725 } 726 727 do { 728 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 729 storage->rx_packets = hw_stats->rx_packets; 730 storage->tx_packets = hw_stats->tx_packets; 731 storage->rx_bytes = hw_stats->rx_bytes; 732 storage->tx_bytes = hw_stats->tx_bytes; 733 storage->collisions = hw_stats->tx_collisions; 734 storage->rx_length_errors = hw_stats->rx_short_errors + 735 hw_stats->rx_long_errors; 736 storage->rx_over_errors = hw_stats->rx_overflow; 737 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 738 storage->rx_errors = hw_stats->rx_checksum_errors; 739 storage->tx_aborted_errors = hw_stats->tx_skip; 740 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 741 742 storage->tx_errors = dev->stats.tx_errors; 743 storage->rx_dropped = dev->stats.rx_dropped; 744 storage->tx_dropped = dev->stats.tx_dropped; 745 } 746 747 static inline int mtk_max_frag_size(int mtu) 748 { 749 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 750 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 751 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 752 753 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 754 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 755 } 756 757 static inline int mtk_max_buf_size(int frag_size) 758 { 759 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 760 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 761 762 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 763 764 return buf_size; 765 } 766 767 static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd, 768 struct mtk_rx_dma *dma_rxd) 769 { 770 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 771 if (!(rxd->rxd2 & RX_DMA_DONE)) 772 return false; 773 774 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 775 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 776 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 777 778 return true; 779 } 780 781 /* the qdma core needs scratch memory to be setup */ 782 static int mtk_init_fq_dma(struct mtk_eth *eth) 783 { 784 dma_addr_t phy_ring_tail; 785 int cnt = MTK_DMA_SIZE; 786 dma_addr_t dma_addr; 787 int i; 788 789 eth->scratch_ring = dma_alloc_coherent(eth->dev, 790 cnt * sizeof(struct mtk_tx_dma), 791 ð->phy_scratch_ring, 792 GFP_ATOMIC); 793 if (unlikely(!eth->scratch_ring)) 794 return -ENOMEM; 795 796 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 797 GFP_KERNEL); 798 if (unlikely(!eth->scratch_head)) 799 return -ENOMEM; 800 801 dma_addr = dma_map_single(eth->dev, 802 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 803 DMA_FROM_DEVICE); 804 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 805 return -ENOMEM; 806 807 phy_ring_tail = eth->phy_scratch_ring + 808 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 809 810 for (i = 0; i < cnt; i++) { 811 eth->scratch_ring[i].txd1 = 812 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 813 if (i < cnt - 1) 814 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 815 ((i + 1) * sizeof(struct mtk_tx_dma))); 816 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 817 } 818 819 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 820 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 821 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 822 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 823 824 return 0; 825 } 826 827 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 828 { 829 void *ret = ring->dma; 830 831 return ret + (desc - ring->phys); 832 } 833 834 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 835 struct mtk_tx_dma *txd) 836 { 837 int idx = txd - ring->dma; 838 839 return &ring->buf[idx]; 840 } 841 842 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 843 struct mtk_tx_dma *dma) 844 { 845 return ring->dma_pdma - ring->dma + dma; 846 } 847 848 static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma) 849 { 850 return ((void *)dma - (void *)ring->dma) / sizeof(*dma); 851 } 852 853 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 854 bool napi) 855 { 856 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 857 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 858 dma_unmap_single(eth->dev, 859 dma_unmap_addr(tx_buf, dma_addr0), 860 dma_unmap_len(tx_buf, dma_len0), 861 DMA_TO_DEVICE); 862 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 863 dma_unmap_page(eth->dev, 864 dma_unmap_addr(tx_buf, dma_addr0), 865 dma_unmap_len(tx_buf, dma_len0), 866 DMA_TO_DEVICE); 867 } 868 } else { 869 if (dma_unmap_len(tx_buf, dma_len0)) { 870 dma_unmap_page(eth->dev, 871 dma_unmap_addr(tx_buf, dma_addr0), 872 dma_unmap_len(tx_buf, dma_len0), 873 DMA_TO_DEVICE); 874 } 875 876 if (dma_unmap_len(tx_buf, dma_len1)) { 877 dma_unmap_page(eth->dev, 878 dma_unmap_addr(tx_buf, dma_addr1), 879 dma_unmap_len(tx_buf, dma_len1), 880 DMA_TO_DEVICE); 881 } 882 } 883 884 tx_buf->flags = 0; 885 if (tx_buf->skb && 886 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) { 887 if (napi) 888 napi_consume_skb(tx_buf->skb, napi); 889 else 890 dev_kfree_skb_any(tx_buf->skb); 891 } 892 tx_buf->skb = NULL; 893 } 894 895 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 896 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 897 size_t size, int idx) 898 { 899 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 900 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 901 dma_unmap_len_set(tx_buf, dma_len0, size); 902 } else { 903 if (idx & 1) { 904 txd->txd3 = mapped_addr; 905 txd->txd2 |= TX_DMA_PLEN1(size); 906 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 907 dma_unmap_len_set(tx_buf, dma_len1, size); 908 } else { 909 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 910 txd->txd1 = mapped_addr; 911 txd->txd2 = TX_DMA_PLEN0(size); 912 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 913 dma_unmap_len_set(tx_buf, dma_len0, size); 914 } 915 } 916 } 917 918 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 919 int tx_num, struct mtk_tx_ring *ring, bool gso) 920 { 921 struct mtk_mac *mac = netdev_priv(dev); 922 struct mtk_eth *eth = mac->hw; 923 struct mtk_tx_dma *itxd, *txd; 924 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 925 struct mtk_tx_buf *itx_buf, *tx_buf; 926 dma_addr_t mapped_addr; 927 unsigned int nr_frags; 928 int i, n_desc = 1; 929 u32 txd4 = 0, fport; 930 int k = 0; 931 932 itxd = ring->next_free; 933 itxd_pdma = qdma_to_pdma(ring, itxd); 934 if (itxd == ring->last_free) 935 return -ENOMEM; 936 937 /* set the forward port */ 938 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 939 txd4 |= fport; 940 941 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 942 memset(itx_buf, 0, sizeof(*itx_buf)); 943 944 if (gso) 945 txd4 |= TX_DMA_TSO; 946 947 /* TX Checksum offload */ 948 if (skb->ip_summed == CHECKSUM_PARTIAL) 949 txd4 |= TX_DMA_CHKSUM; 950 951 /* VLAN header offload */ 952 if (skb_vlan_tag_present(skb)) 953 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 954 955 mapped_addr = dma_map_single(eth->dev, skb->data, 956 skb_headlen(skb), DMA_TO_DEVICE); 957 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 958 return -ENOMEM; 959 960 WRITE_ONCE(itxd->txd1, mapped_addr); 961 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 962 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 963 MTK_TX_FLAGS_FPORT1; 964 setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb), 965 k++); 966 967 /* TX SG offload */ 968 txd = itxd; 969 txd_pdma = qdma_to_pdma(ring, txd); 970 nr_frags = skb_shinfo(skb)->nr_frags; 971 972 for (i = 0; i < nr_frags; i++) { 973 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 974 unsigned int offset = 0; 975 int frag_size = skb_frag_size(frag); 976 977 while (frag_size) { 978 bool last_frag = false; 979 unsigned int frag_map_size; 980 bool new_desc = true; 981 982 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) || 983 (i & 0x1)) { 984 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 985 txd_pdma = qdma_to_pdma(ring, txd); 986 if (txd == ring->last_free) 987 goto err_dma; 988 989 n_desc++; 990 } else { 991 new_desc = false; 992 } 993 994 995 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 996 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 997 frag_map_size, 998 DMA_TO_DEVICE); 999 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 1000 goto err_dma; 1001 1002 if (i == nr_frags - 1 && 1003 (frag_size - frag_map_size) == 0) 1004 last_frag = true; 1005 1006 WRITE_ONCE(txd->txd1, mapped_addr); 1007 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 1008 TX_DMA_PLEN0(frag_map_size) | 1009 last_frag * TX_DMA_LS0)); 1010 WRITE_ONCE(txd->txd4, fport); 1011 1012 tx_buf = mtk_desc_to_tx_buf(ring, txd); 1013 if (new_desc) 1014 memset(tx_buf, 0, sizeof(*tx_buf)); 1015 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 1016 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1017 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1018 MTK_TX_FLAGS_FPORT1; 1019 1020 setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr, 1021 frag_map_size, k++); 1022 1023 frag_size -= frag_map_size; 1024 offset += frag_map_size; 1025 } 1026 } 1027 1028 /* store skb to cleanup */ 1029 itx_buf->skb = skb; 1030 1031 WRITE_ONCE(itxd->txd4, txd4); 1032 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 1033 (!nr_frags * TX_DMA_LS0))); 1034 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1035 if (k & 0x1) 1036 txd_pdma->txd2 |= TX_DMA_LS0; 1037 else 1038 txd_pdma->txd2 |= TX_DMA_LS1; 1039 } 1040 1041 netdev_sent_queue(dev, skb->len); 1042 skb_tx_timestamp(skb); 1043 1044 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1045 atomic_sub(n_desc, &ring->free_count); 1046 1047 /* make sure that all changes to the dma ring are flushed before we 1048 * continue 1049 */ 1050 wmb(); 1051 1052 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1053 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 1054 !netdev_xmit_more()) 1055 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 1056 } else { 1057 int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd), 1058 ring->dma_size); 1059 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1060 } 1061 1062 return 0; 1063 1064 err_dma: 1065 do { 1066 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 1067 1068 /* unmap dma */ 1069 mtk_tx_unmap(eth, tx_buf, false); 1070 1071 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1072 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1073 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1074 1075 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1076 itxd_pdma = qdma_to_pdma(ring, itxd); 1077 } while (itxd != txd); 1078 1079 return -ENOMEM; 1080 } 1081 1082 static inline int mtk_cal_txd_req(struct sk_buff *skb) 1083 { 1084 int i, nfrags; 1085 skb_frag_t *frag; 1086 1087 nfrags = 1; 1088 if (skb_is_gso(skb)) { 1089 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1090 frag = &skb_shinfo(skb)->frags[i]; 1091 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1092 MTK_TX_DMA_BUF_LEN); 1093 } 1094 } else { 1095 nfrags += skb_shinfo(skb)->nr_frags; 1096 } 1097 1098 return nfrags; 1099 } 1100 1101 static int mtk_queue_stopped(struct mtk_eth *eth) 1102 { 1103 int i; 1104 1105 for (i = 0; i < MTK_MAC_COUNT; i++) { 1106 if (!eth->netdev[i]) 1107 continue; 1108 if (netif_queue_stopped(eth->netdev[i])) 1109 return 1; 1110 } 1111 1112 return 0; 1113 } 1114 1115 static void mtk_wake_queue(struct mtk_eth *eth) 1116 { 1117 int i; 1118 1119 for (i = 0; i < MTK_MAC_COUNT; i++) { 1120 if (!eth->netdev[i]) 1121 continue; 1122 netif_wake_queue(eth->netdev[i]); 1123 } 1124 } 1125 1126 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1127 { 1128 struct mtk_mac *mac = netdev_priv(dev); 1129 struct mtk_eth *eth = mac->hw; 1130 struct mtk_tx_ring *ring = ð->tx_ring; 1131 struct net_device_stats *stats = &dev->stats; 1132 bool gso = false; 1133 int tx_num; 1134 1135 /* normally we can rely on the stack not calling this more than once, 1136 * however we have 2 queues running on the same ring so we need to lock 1137 * the ring access 1138 */ 1139 spin_lock(ð->page_lock); 1140 1141 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1142 goto drop; 1143 1144 tx_num = mtk_cal_txd_req(skb); 1145 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1146 netif_stop_queue(dev); 1147 netif_err(eth, tx_queued, dev, 1148 "Tx Ring full when queue awake!\n"); 1149 spin_unlock(ð->page_lock); 1150 return NETDEV_TX_BUSY; 1151 } 1152 1153 /* TSO: fill MSS info in tcp checksum field */ 1154 if (skb_is_gso(skb)) { 1155 if (skb_cow_head(skb, 0)) { 1156 netif_warn(eth, tx_err, dev, 1157 "GSO expand head fail.\n"); 1158 goto drop; 1159 } 1160 1161 if (skb_shinfo(skb)->gso_type & 1162 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1163 gso = true; 1164 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1165 } 1166 } 1167 1168 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1169 goto drop; 1170 1171 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1172 netif_stop_queue(dev); 1173 1174 spin_unlock(ð->page_lock); 1175 1176 return NETDEV_TX_OK; 1177 1178 drop: 1179 spin_unlock(ð->page_lock); 1180 stats->tx_dropped++; 1181 dev_kfree_skb_any(skb); 1182 return NETDEV_TX_OK; 1183 } 1184 1185 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1186 { 1187 int i; 1188 struct mtk_rx_ring *ring; 1189 int idx; 1190 1191 if (!eth->hwlro) 1192 return ð->rx_ring[0]; 1193 1194 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1195 ring = ð->rx_ring[i]; 1196 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1197 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 1198 ring->calc_idx_update = true; 1199 return ring; 1200 } 1201 } 1202 1203 return NULL; 1204 } 1205 1206 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1207 { 1208 struct mtk_rx_ring *ring; 1209 int i; 1210 1211 if (!eth->hwlro) { 1212 ring = ð->rx_ring[0]; 1213 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1214 } else { 1215 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1216 ring = ð->rx_ring[i]; 1217 if (ring->calc_idx_update) { 1218 ring->calc_idx_update = false; 1219 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1220 } 1221 } 1222 } 1223 } 1224 1225 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1226 struct mtk_eth *eth) 1227 { 1228 struct dim_sample dim_sample = {}; 1229 struct mtk_rx_ring *ring; 1230 int idx; 1231 struct sk_buff *skb; 1232 u8 *data, *new_data; 1233 struct mtk_rx_dma *rxd, trxd; 1234 int done = 0, bytes = 0; 1235 1236 while (done < budget) { 1237 struct net_device *netdev; 1238 unsigned int pktlen; 1239 dma_addr_t dma_addr; 1240 u32 hash; 1241 int mac; 1242 1243 ring = mtk_get_rx_ring(eth); 1244 if (unlikely(!ring)) 1245 goto rx_done; 1246 1247 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1248 rxd = &ring->dma[idx]; 1249 data = ring->data[idx]; 1250 1251 if (!mtk_rx_get_desc(&trxd, rxd)) 1252 break; 1253 1254 /* find out which mac the packet come from. values start at 1 */ 1255 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) || 1256 (trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 1257 mac = 0; 1258 else 1259 mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 1260 RX_DMA_FPORT_MASK) - 1; 1261 1262 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1263 !eth->netdev[mac])) 1264 goto release_desc; 1265 1266 netdev = eth->netdev[mac]; 1267 1268 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1269 goto release_desc; 1270 1271 /* alloc new buffer */ 1272 new_data = napi_alloc_frag(ring->frag_size); 1273 if (unlikely(!new_data)) { 1274 netdev->stats.rx_dropped++; 1275 goto release_desc; 1276 } 1277 dma_addr = dma_map_single(eth->dev, 1278 new_data + NET_SKB_PAD + 1279 eth->ip_align, 1280 ring->buf_size, 1281 DMA_FROM_DEVICE); 1282 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 1283 skb_free_frag(new_data); 1284 netdev->stats.rx_dropped++; 1285 goto release_desc; 1286 } 1287 1288 dma_unmap_single(eth->dev, trxd.rxd1, 1289 ring->buf_size, DMA_FROM_DEVICE); 1290 1291 /* receive data */ 1292 skb = build_skb(data, ring->frag_size); 1293 if (unlikely(!skb)) { 1294 skb_free_frag(data); 1295 netdev->stats.rx_dropped++; 1296 goto skip_rx; 1297 } 1298 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1299 1300 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1301 skb->dev = netdev; 1302 skb_put(skb, pktlen); 1303 if (trxd.rxd4 & eth->rx_dma_l4_valid) 1304 skb->ip_summed = CHECKSUM_UNNECESSARY; 1305 else 1306 skb_checksum_none_assert(skb); 1307 skb->protocol = eth_type_trans(skb, netdev); 1308 bytes += pktlen; 1309 1310 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 1311 if (hash != MTK_RXD4_FOE_ENTRY) { 1312 hash = jhash_1word(hash, 0); 1313 skb_set_hash(skb, hash, PKT_HASH_TYPE_L4); 1314 } 1315 1316 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1317 (trxd.rxd2 & RX_DMA_VTAG)) 1318 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1319 RX_DMA_VID(trxd.rxd3)); 1320 skb_record_rx_queue(skb, 0); 1321 napi_gro_receive(napi, skb); 1322 1323 skip_rx: 1324 ring->data[idx] = new_data; 1325 rxd->rxd1 = (unsigned int)dma_addr; 1326 1327 release_desc: 1328 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1329 rxd->rxd2 = RX_DMA_LSO; 1330 else 1331 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1332 1333 ring->calc_idx = idx; 1334 1335 done++; 1336 } 1337 1338 rx_done: 1339 if (done) { 1340 /* make sure that all changes to the dma ring are flushed before 1341 * we continue 1342 */ 1343 wmb(); 1344 mtk_update_rx_cpu_idx(eth); 1345 } 1346 1347 eth->rx_packets += done; 1348 eth->rx_bytes += bytes; 1349 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 1350 &dim_sample); 1351 net_dim(ð->rx_dim, dim_sample); 1352 1353 return done; 1354 } 1355 1356 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 1357 unsigned int *done, unsigned int *bytes) 1358 { 1359 struct mtk_tx_ring *ring = ð->tx_ring; 1360 struct mtk_tx_dma *desc; 1361 struct sk_buff *skb; 1362 struct mtk_tx_buf *tx_buf; 1363 u32 cpu, dma; 1364 1365 cpu = ring->last_free_ptr; 1366 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1367 1368 desc = mtk_qdma_phys_to_virt(ring, cpu); 1369 1370 while ((cpu != dma) && budget) { 1371 u32 next_cpu = desc->txd2; 1372 int mac = 0; 1373 1374 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1375 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1376 break; 1377 1378 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1379 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1380 mac = 1; 1381 1382 skb = tx_buf->skb; 1383 if (!skb) 1384 break; 1385 1386 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1387 bytes[mac] += skb->len; 1388 done[mac]++; 1389 budget--; 1390 } 1391 mtk_tx_unmap(eth, tx_buf, true); 1392 1393 ring->last_free = desc; 1394 atomic_inc(&ring->free_count); 1395 1396 cpu = next_cpu; 1397 } 1398 1399 ring->last_free_ptr = cpu; 1400 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1401 1402 return budget; 1403 } 1404 1405 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 1406 unsigned int *done, unsigned int *bytes) 1407 { 1408 struct mtk_tx_ring *ring = ð->tx_ring; 1409 struct mtk_tx_dma *desc; 1410 struct sk_buff *skb; 1411 struct mtk_tx_buf *tx_buf; 1412 u32 cpu, dma; 1413 1414 cpu = ring->cpu_idx; 1415 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 1416 1417 while ((cpu != dma) && budget) { 1418 tx_buf = &ring->buf[cpu]; 1419 skb = tx_buf->skb; 1420 if (!skb) 1421 break; 1422 1423 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1424 bytes[0] += skb->len; 1425 done[0]++; 1426 budget--; 1427 } 1428 1429 mtk_tx_unmap(eth, tx_buf, true); 1430 1431 desc = &ring->dma[cpu]; 1432 ring->last_free = desc; 1433 atomic_inc(&ring->free_count); 1434 1435 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 1436 } 1437 1438 ring->cpu_idx = cpu; 1439 1440 return budget; 1441 } 1442 1443 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1444 { 1445 struct mtk_tx_ring *ring = ð->tx_ring; 1446 struct dim_sample dim_sample = {}; 1447 unsigned int done[MTK_MAX_DEVS]; 1448 unsigned int bytes[MTK_MAX_DEVS]; 1449 int total = 0, i; 1450 1451 memset(done, 0, sizeof(done)); 1452 memset(bytes, 0, sizeof(bytes)); 1453 1454 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1455 budget = mtk_poll_tx_qdma(eth, budget, done, bytes); 1456 else 1457 budget = mtk_poll_tx_pdma(eth, budget, done, bytes); 1458 1459 for (i = 0; i < MTK_MAC_COUNT; i++) { 1460 if (!eth->netdev[i] || !done[i]) 1461 continue; 1462 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1463 total += done[i]; 1464 eth->tx_packets += done[i]; 1465 eth->tx_bytes += bytes[i]; 1466 } 1467 1468 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 1469 &dim_sample); 1470 net_dim(ð->tx_dim, dim_sample); 1471 1472 if (mtk_queue_stopped(eth) && 1473 (atomic_read(&ring->free_count) > ring->thresh)) 1474 mtk_wake_queue(eth); 1475 1476 return total; 1477 } 1478 1479 static void mtk_handle_status_irq(struct mtk_eth *eth) 1480 { 1481 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1482 1483 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1484 mtk_stats_update(eth); 1485 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1486 MTK_INT_STATUS2); 1487 } 1488 } 1489 1490 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1491 { 1492 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1493 int tx_done = 0; 1494 1495 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1496 mtk_handle_status_irq(eth); 1497 mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg); 1498 tx_done = mtk_poll_tx(eth, budget); 1499 1500 if (unlikely(netif_msg_intr(eth))) { 1501 dev_info(eth->dev, 1502 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 1503 mtk_r32(eth, eth->tx_int_status_reg), 1504 mtk_r32(eth, eth->tx_int_mask_reg)); 1505 } 1506 1507 if (tx_done == budget) 1508 return budget; 1509 1510 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) 1511 return budget; 1512 1513 if (napi_complete_done(napi, tx_done)) 1514 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1515 1516 return tx_done; 1517 } 1518 1519 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1520 { 1521 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1522 int rx_done_total = 0; 1523 1524 mtk_handle_status_irq(eth); 1525 1526 do { 1527 int rx_done; 1528 1529 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1530 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 1531 rx_done_total += rx_done; 1532 1533 if (unlikely(netif_msg_intr(eth))) { 1534 dev_info(eth->dev, 1535 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 1536 mtk_r32(eth, MTK_PDMA_INT_STATUS), 1537 mtk_r32(eth, MTK_PDMA_INT_MASK)); 1538 } 1539 1540 if (rx_done_total == budget) 1541 return budget; 1542 1543 } while (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT); 1544 1545 if (napi_complete_done(napi, rx_done_total)) 1546 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1547 1548 return rx_done_total; 1549 } 1550 1551 static int mtk_tx_alloc(struct mtk_eth *eth) 1552 { 1553 struct mtk_tx_ring *ring = ð->tx_ring; 1554 int i, sz = sizeof(*ring->dma); 1555 1556 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1557 GFP_KERNEL); 1558 if (!ring->buf) 1559 goto no_tx_mem; 1560 1561 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1562 &ring->phys, GFP_ATOMIC); 1563 if (!ring->dma) 1564 goto no_tx_mem; 1565 1566 for (i = 0; i < MTK_DMA_SIZE; i++) { 1567 int next = (i + 1) % MTK_DMA_SIZE; 1568 u32 next_ptr = ring->phys + next * sz; 1569 1570 ring->dma[i].txd2 = next_ptr; 1571 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1572 } 1573 1574 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 1575 * only as the framework. The real HW descriptors are the PDMA 1576 * descriptors in ring->dma_pdma. 1577 */ 1578 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1579 ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1580 &ring->phys_pdma, 1581 GFP_ATOMIC); 1582 if (!ring->dma_pdma) 1583 goto no_tx_mem; 1584 1585 for (i = 0; i < MTK_DMA_SIZE; i++) { 1586 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 1587 ring->dma_pdma[i].txd4 = 0; 1588 } 1589 } 1590 1591 ring->dma_size = MTK_DMA_SIZE; 1592 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1593 ring->next_free = &ring->dma[0]; 1594 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1595 ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz)); 1596 ring->thresh = MAX_SKB_FRAGS; 1597 1598 /* make sure that all changes to the dma ring are flushed before we 1599 * continue 1600 */ 1601 wmb(); 1602 1603 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1604 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1605 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1606 mtk_w32(eth, 1607 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1608 MTK_QTX_CRX_PTR); 1609 mtk_w32(eth, ring->last_free_ptr, MTK_QTX_DRX_PTR); 1610 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, 1611 MTK_QTX_CFG(0)); 1612 } else { 1613 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 1614 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); 1615 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 1616 mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX); 1617 } 1618 1619 return 0; 1620 1621 no_tx_mem: 1622 return -ENOMEM; 1623 } 1624 1625 static void mtk_tx_clean(struct mtk_eth *eth) 1626 { 1627 struct mtk_tx_ring *ring = ð->tx_ring; 1628 int i; 1629 1630 if (ring->buf) { 1631 for (i = 0; i < MTK_DMA_SIZE; i++) 1632 mtk_tx_unmap(eth, &ring->buf[i], false); 1633 kfree(ring->buf); 1634 ring->buf = NULL; 1635 } 1636 1637 if (ring->dma) { 1638 dma_free_coherent(eth->dev, 1639 MTK_DMA_SIZE * sizeof(*ring->dma), 1640 ring->dma, 1641 ring->phys); 1642 ring->dma = NULL; 1643 } 1644 1645 if (ring->dma_pdma) { 1646 dma_free_coherent(eth->dev, 1647 MTK_DMA_SIZE * sizeof(*ring->dma_pdma), 1648 ring->dma_pdma, 1649 ring->phys_pdma); 1650 ring->dma_pdma = NULL; 1651 } 1652 } 1653 1654 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1655 { 1656 struct mtk_rx_ring *ring; 1657 int rx_data_len, rx_dma_size; 1658 int i; 1659 u32 offset = 0; 1660 1661 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1662 if (ring_no) 1663 return -EINVAL; 1664 ring = ð->rx_ring_qdma; 1665 offset = 0x1000; 1666 } else { 1667 ring = ð->rx_ring[ring_no]; 1668 } 1669 1670 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1671 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1672 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1673 } else { 1674 rx_data_len = ETH_DATA_LEN; 1675 rx_dma_size = MTK_DMA_SIZE; 1676 } 1677 1678 ring->frag_size = mtk_max_frag_size(rx_data_len); 1679 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1680 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1681 GFP_KERNEL); 1682 if (!ring->data) 1683 return -ENOMEM; 1684 1685 for (i = 0; i < rx_dma_size; i++) { 1686 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1687 if (!ring->data[i]) 1688 return -ENOMEM; 1689 } 1690 1691 ring->dma = dma_alloc_coherent(eth->dev, 1692 rx_dma_size * sizeof(*ring->dma), 1693 &ring->phys, GFP_ATOMIC); 1694 if (!ring->dma) 1695 return -ENOMEM; 1696 1697 for (i = 0; i < rx_dma_size; i++) { 1698 dma_addr_t dma_addr = dma_map_single(eth->dev, 1699 ring->data[i] + NET_SKB_PAD + eth->ip_align, 1700 ring->buf_size, 1701 DMA_FROM_DEVICE); 1702 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1703 return -ENOMEM; 1704 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1705 1706 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1707 ring->dma[i].rxd2 = RX_DMA_LSO; 1708 else 1709 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1710 } 1711 ring->dma_size = rx_dma_size; 1712 ring->calc_idx_update = false; 1713 ring->calc_idx = rx_dma_size - 1; 1714 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1715 /* make sure that all changes to the dma ring are flushed before we 1716 * continue 1717 */ 1718 wmb(); 1719 1720 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1721 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1722 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1723 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1724 1725 return 0; 1726 } 1727 1728 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1729 { 1730 int i; 1731 1732 if (ring->data && ring->dma) { 1733 for (i = 0; i < ring->dma_size; i++) { 1734 if (!ring->data[i]) 1735 continue; 1736 if (!ring->dma[i].rxd1) 1737 continue; 1738 dma_unmap_single(eth->dev, 1739 ring->dma[i].rxd1, 1740 ring->buf_size, 1741 DMA_FROM_DEVICE); 1742 skb_free_frag(ring->data[i]); 1743 } 1744 kfree(ring->data); 1745 ring->data = NULL; 1746 } 1747 1748 if (ring->dma) { 1749 dma_free_coherent(eth->dev, 1750 ring->dma_size * sizeof(*ring->dma), 1751 ring->dma, 1752 ring->phys); 1753 ring->dma = NULL; 1754 } 1755 } 1756 1757 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1758 { 1759 int i; 1760 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1761 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1762 1763 /* set LRO rings to auto-learn modes */ 1764 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1765 1766 /* validate LRO ring */ 1767 ring_ctrl_dw2 |= MTK_RING_VLD; 1768 1769 /* set AGE timer (unit: 20us) */ 1770 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1771 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1772 1773 /* set max AGG timer (unit: 20us) */ 1774 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1775 1776 /* set max LRO AGG count */ 1777 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1778 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1779 1780 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1781 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1782 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1783 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1784 } 1785 1786 /* IPv4 checksum update enable */ 1787 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1788 1789 /* switch priority comparison to packet count mode */ 1790 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1791 1792 /* bandwidth threshold setting */ 1793 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1794 1795 /* auto-learn score delta setting */ 1796 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1797 1798 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1799 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1800 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1801 1802 /* set HW LRO mode & the max aggregation count for rx packets */ 1803 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1804 1805 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1806 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1807 1808 /* enable HW LRO */ 1809 lro_ctrl_dw0 |= MTK_LRO_EN; 1810 1811 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1812 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1813 1814 return 0; 1815 } 1816 1817 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1818 { 1819 int i; 1820 u32 val; 1821 1822 /* relinquish lro rings, flush aggregated packets */ 1823 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1824 1825 /* wait for relinquishments done */ 1826 for (i = 0; i < 10; i++) { 1827 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1828 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1829 msleep(20); 1830 continue; 1831 } 1832 break; 1833 } 1834 1835 /* invalidate lro rings */ 1836 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1837 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1838 1839 /* disable HW LRO */ 1840 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1841 } 1842 1843 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1844 { 1845 u32 reg_val; 1846 1847 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1848 1849 /* invalidate the IP setting */ 1850 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1851 1852 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1853 1854 /* validate the IP setting */ 1855 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1856 } 1857 1858 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1859 { 1860 u32 reg_val; 1861 1862 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1863 1864 /* invalidate the IP setting */ 1865 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1866 1867 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1868 } 1869 1870 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1871 { 1872 int cnt = 0; 1873 int i; 1874 1875 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1876 if (mac->hwlro_ip[i]) 1877 cnt++; 1878 } 1879 1880 return cnt; 1881 } 1882 1883 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1884 struct ethtool_rxnfc *cmd) 1885 { 1886 struct ethtool_rx_flow_spec *fsp = 1887 (struct ethtool_rx_flow_spec *)&cmd->fs; 1888 struct mtk_mac *mac = netdev_priv(dev); 1889 struct mtk_eth *eth = mac->hw; 1890 int hwlro_idx; 1891 1892 if ((fsp->flow_type != TCP_V4_FLOW) || 1893 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1894 (fsp->location > 1)) 1895 return -EINVAL; 1896 1897 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1898 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1899 1900 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1901 1902 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1903 1904 return 0; 1905 } 1906 1907 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1908 struct ethtool_rxnfc *cmd) 1909 { 1910 struct ethtool_rx_flow_spec *fsp = 1911 (struct ethtool_rx_flow_spec *)&cmd->fs; 1912 struct mtk_mac *mac = netdev_priv(dev); 1913 struct mtk_eth *eth = mac->hw; 1914 int hwlro_idx; 1915 1916 if (fsp->location > 1) 1917 return -EINVAL; 1918 1919 mac->hwlro_ip[fsp->location] = 0; 1920 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1921 1922 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1923 1924 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1925 1926 return 0; 1927 } 1928 1929 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1930 { 1931 struct mtk_mac *mac = netdev_priv(dev); 1932 struct mtk_eth *eth = mac->hw; 1933 int i, hwlro_idx; 1934 1935 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1936 mac->hwlro_ip[i] = 0; 1937 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1938 1939 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1940 } 1941 1942 mac->hwlro_ip_cnt = 0; 1943 } 1944 1945 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1946 struct ethtool_rxnfc *cmd) 1947 { 1948 struct mtk_mac *mac = netdev_priv(dev); 1949 struct ethtool_rx_flow_spec *fsp = 1950 (struct ethtool_rx_flow_spec *)&cmd->fs; 1951 1952 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1953 fsp->flow_type = TCP_V4_FLOW; 1954 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1955 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1956 1957 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1958 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1959 fsp->h_u.tcp_ip4_spec.psrc = 0; 1960 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1961 fsp->h_u.tcp_ip4_spec.pdst = 0; 1962 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1963 fsp->h_u.tcp_ip4_spec.tos = 0; 1964 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1965 1966 return 0; 1967 } 1968 1969 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1970 struct ethtool_rxnfc *cmd, 1971 u32 *rule_locs) 1972 { 1973 struct mtk_mac *mac = netdev_priv(dev); 1974 int cnt = 0; 1975 int i; 1976 1977 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1978 if (mac->hwlro_ip[i]) { 1979 rule_locs[cnt] = i; 1980 cnt++; 1981 } 1982 } 1983 1984 cmd->rule_cnt = cnt; 1985 1986 return 0; 1987 } 1988 1989 static netdev_features_t mtk_fix_features(struct net_device *dev, 1990 netdev_features_t features) 1991 { 1992 if (!(features & NETIF_F_LRO)) { 1993 struct mtk_mac *mac = netdev_priv(dev); 1994 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1995 1996 if (ip_cnt) { 1997 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1998 1999 features |= NETIF_F_LRO; 2000 } 2001 } 2002 2003 return features; 2004 } 2005 2006 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2007 { 2008 int err = 0; 2009 2010 if (!((dev->features ^ features) & NETIF_F_LRO)) 2011 return 0; 2012 2013 if (!(features & NETIF_F_LRO)) 2014 mtk_hwlro_netdev_disable(dev); 2015 2016 return err; 2017 } 2018 2019 /* wait for DMA to finish whatever it is doing before we start using it again */ 2020 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2021 { 2022 unsigned int reg; 2023 int ret; 2024 u32 val; 2025 2026 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2027 reg = MTK_QDMA_GLO_CFG; 2028 else 2029 reg = MTK_PDMA_GLO_CFG; 2030 2031 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 2032 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 2033 5, MTK_DMA_BUSY_TIMEOUT_US); 2034 if (ret) 2035 dev_err(eth->dev, "DMA init timeout\n"); 2036 2037 return ret; 2038 } 2039 2040 static int mtk_dma_init(struct mtk_eth *eth) 2041 { 2042 int err; 2043 u32 i; 2044 2045 if (mtk_dma_busy_wait(eth)) 2046 return -EBUSY; 2047 2048 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2049 /* QDMA needs scratch memory for internal reordering of the 2050 * descriptors 2051 */ 2052 err = mtk_init_fq_dma(eth); 2053 if (err) 2054 return err; 2055 } 2056 2057 err = mtk_tx_alloc(eth); 2058 if (err) 2059 return err; 2060 2061 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2062 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2063 if (err) 2064 return err; 2065 } 2066 2067 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2068 if (err) 2069 return err; 2070 2071 if (eth->hwlro) { 2072 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2073 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2074 if (err) 2075 return err; 2076 } 2077 err = mtk_hwlro_rx_init(eth); 2078 if (err) 2079 return err; 2080 } 2081 2082 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2083 /* Enable random early drop and set drop threshold 2084 * automatically 2085 */ 2086 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2087 FC_THRES_MIN, MTK_QDMA_FC_THRES); 2088 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 2089 } 2090 2091 return 0; 2092 } 2093 2094 static void mtk_dma_free(struct mtk_eth *eth) 2095 { 2096 int i; 2097 2098 for (i = 0; i < MTK_MAC_COUNT; i++) 2099 if (eth->netdev[i]) 2100 netdev_reset_queue(eth->netdev[i]); 2101 if (eth->scratch_ring) { 2102 dma_free_coherent(eth->dev, 2103 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 2104 eth->scratch_ring, 2105 eth->phy_scratch_ring); 2106 eth->scratch_ring = NULL; 2107 eth->phy_scratch_ring = 0; 2108 } 2109 mtk_tx_clean(eth); 2110 mtk_rx_clean(eth, ð->rx_ring[0]); 2111 mtk_rx_clean(eth, ð->rx_ring_qdma); 2112 2113 if (eth->hwlro) { 2114 mtk_hwlro_rx_uninit(eth); 2115 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2116 mtk_rx_clean(eth, ð->rx_ring[i]); 2117 } 2118 2119 kfree(eth->scratch_head); 2120 } 2121 2122 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 2123 { 2124 struct mtk_mac *mac = netdev_priv(dev); 2125 struct mtk_eth *eth = mac->hw; 2126 2127 eth->netdev[mac->id]->stats.tx_errors++; 2128 netif_err(eth, tx_err, dev, 2129 "transmit timed out\n"); 2130 schedule_work(ð->pending_work); 2131 } 2132 2133 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 2134 { 2135 struct mtk_eth *eth = _eth; 2136 2137 eth->rx_events++; 2138 if (likely(napi_schedule_prep(ð->rx_napi))) { 2139 __napi_schedule(ð->rx_napi); 2140 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2141 } 2142 2143 return IRQ_HANDLED; 2144 } 2145 2146 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 2147 { 2148 struct mtk_eth *eth = _eth; 2149 2150 eth->tx_events++; 2151 if (likely(napi_schedule_prep(ð->tx_napi))) { 2152 __napi_schedule(ð->tx_napi); 2153 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2154 } 2155 2156 return IRQ_HANDLED; 2157 } 2158 2159 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 2160 { 2161 struct mtk_eth *eth = _eth; 2162 2163 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { 2164 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) 2165 mtk_handle_irq_rx(irq, _eth); 2166 } 2167 if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) { 2168 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) 2169 mtk_handle_irq_tx(irq, _eth); 2170 } 2171 2172 return IRQ_HANDLED; 2173 } 2174 2175 #ifdef CONFIG_NET_POLL_CONTROLLER 2176 static void mtk_poll_controller(struct net_device *dev) 2177 { 2178 struct mtk_mac *mac = netdev_priv(dev); 2179 struct mtk_eth *eth = mac->hw; 2180 2181 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2182 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2183 mtk_handle_irq_rx(eth->irq[2], dev); 2184 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2185 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2186 } 2187 #endif 2188 2189 static int mtk_start_dma(struct mtk_eth *eth) 2190 { 2191 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 2192 int err; 2193 2194 err = mtk_dma_init(eth); 2195 if (err) { 2196 mtk_dma_free(eth); 2197 return err; 2198 } 2199 2200 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2201 mtk_w32(eth, 2202 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 2203 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 2204 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 2205 MTK_RX_BT_32DWORDS, 2206 MTK_QDMA_GLO_CFG); 2207 2208 mtk_w32(eth, 2209 MTK_RX_DMA_EN | rx_2b_offset | 2210 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 2211 MTK_PDMA_GLO_CFG); 2212 } else { 2213 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2214 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 2215 MTK_PDMA_GLO_CFG); 2216 } 2217 2218 return 0; 2219 } 2220 2221 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 2222 { 2223 int i; 2224 2225 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2226 return; 2227 2228 for (i = 0; i < MTK_MAC_COUNT; i++) { 2229 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 2230 2231 /* default setup the forward port to send frame to PDMA */ 2232 val &= ~0xffff; 2233 2234 /* Enable RX checksum */ 2235 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2236 2237 val |= config; 2238 2239 if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0])) 2240 val |= MTK_GDMA_SPECIAL_TAG; 2241 2242 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2243 } 2244 /* Reset and enable PSE */ 2245 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 2246 mtk_w32(eth, 0, MTK_RST_GL); 2247 } 2248 2249 static int mtk_open(struct net_device *dev) 2250 { 2251 struct mtk_mac *mac = netdev_priv(dev); 2252 struct mtk_eth *eth = mac->hw; 2253 int err; 2254 2255 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 2256 if (err) { 2257 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 2258 err); 2259 return err; 2260 } 2261 2262 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 2263 if (!refcount_read(ð->dma_refcnt)) { 2264 u32 gdm_config = MTK_GDMA_TO_PDMA; 2265 2266 err = mtk_start_dma(eth); 2267 if (err) 2268 return err; 2269 2270 if (eth->soc->offload_version && mtk_ppe_start(ð->ppe) == 0) 2271 gdm_config = MTK_GDMA_TO_PPE; 2272 2273 mtk_gdm_config(eth, gdm_config); 2274 2275 napi_enable(ð->tx_napi); 2276 napi_enable(ð->rx_napi); 2277 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2278 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2279 refcount_set(ð->dma_refcnt, 1); 2280 } 2281 else 2282 refcount_inc(ð->dma_refcnt); 2283 2284 phylink_start(mac->phylink); 2285 netif_start_queue(dev); 2286 return 0; 2287 } 2288 2289 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 2290 { 2291 u32 val; 2292 int i; 2293 2294 /* stop the dma engine */ 2295 spin_lock_bh(ð->page_lock); 2296 val = mtk_r32(eth, glo_cfg); 2297 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 2298 glo_cfg); 2299 spin_unlock_bh(ð->page_lock); 2300 2301 /* wait for dma stop */ 2302 for (i = 0; i < 10; i++) { 2303 val = mtk_r32(eth, glo_cfg); 2304 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 2305 msleep(20); 2306 continue; 2307 } 2308 break; 2309 } 2310 } 2311 2312 static int mtk_stop(struct net_device *dev) 2313 { 2314 struct mtk_mac *mac = netdev_priv(dev); 2315 struct mtk_eth *eth = mac->hw; 2316 2317 phylink_stop(mac->phylink); 2318 2319 netif_tx_disable(dev); 2320 2321 phylink_disconnect_phy(mac->phylink); 2322 2323 /* only shutdown DMA if this is the last user */ 2324 if (!refcount_dec_and_test(ð->dma_refcnt)) 2325 return 0; 2326 2327 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 2328 2329 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2330 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2331 napi_disable(ð->tx_napi); 2332 napi_disable(ð->rx_napi); 2333 2334 cancel_work_sync(ð->rx_dim.work); 2335 cancel_work_sync(ð->tx_dim.work); 2336 2337 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2338 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 2339 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 2340 2341 mtk_dma_free(eth); 2342 2343 if (eth->soc->offload_version) 2344 mtk_ppe_stop(ð->ppe); 2345 2346 return 0; 2347 } 2348 2349 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 2350 { 2351 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2352 reset_bits, 2353 reset_bits); 2354 2355 usleep_range(1000, 1100); 2356 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2357 reset_bits, 2358 ~reset_bits); 2359 mdelay(10); 2360 } 2361 2362 static void mtk_clk_disable(struct mtk_eth *eth) 2363 { 2364 int clk; 2365 2366 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 2367 clk_disable_unprepare(eth->clks[clk]); 2368 } 2369 2370 static int mtk_clk_enable(struct mtk_eth *eth) 2371 { 2372 int clk, ret; 2373 2374 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 2375 ret = clk_prepare_enable(eth->clks[clk]); 2376 if (ret) 2377 goto err_disable_clks; 2378 } 2379 2380 return 0; 2381 2382 err_disable_clks: 2383 while (--clk >= 0) 2384 clk_disable_unprepare(eth->clks[clk]); 2385 2386 return ret; 2387 } 2388 2389 static void mtk_dim_rx(struct work_struct *work) 2390 { 2391 struct dim *dim = container_of(work, struct dim, work); 2392 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 2393 struct dim_cq_moder cur_profile; 2394 u32 val, cur; 2395 2396 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 2397 dim->profile_ix); 2398 spin_lock_bh(ð->dim_lock); 2399 2400 val = mtk_r32(eth, MTK_PDMA_DELAY_INT); 2401 val &= MTK_PDMA_DELAY_TX_MASK; 2402 val |= MTK_PDMA_DELAY_RX_EN; 2403 2404 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 2405 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 2406 2407 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 2408 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 2409 2410 mtk_w32(eth, val, MTK_PDMA_DELAY_INT); 2411 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2412 mtk_w32(eth, val, MTK_QDMA_DELAY_INT); 2413 2414 spin_unlock_bh(ð->dim_lock); 2415 2416 dim->state = DIM_START_MEASURE; 2417 } 2418 2419 static void mtk_dim_tx(struct work_struct *work) 2420 { 2421 struct dim *dim = container_of(work, struct dim, work); 2422 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 2423 struct dim_cq_moder cur_profile; 2424 u32 val, cur; 2425 2426 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 2427 dim->profile_ix); 2428 spin_lock_bh(ð->dim_lock); 2429 2430 val = mtk_r32(eth, MTK_PDMA_DELAY_INT); 2431 val &= MTK_PDMA_DELAY_RX_MASK; 2432 val |= MTK_PDMA_DELAY_TX_EN; 2433 2434 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 2435 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 2436 2437 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 2438 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 2439 2440 mtk_w32(eth, val, MTK_PDMA_DELAY_INT); 2441 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2442 mtk_w32(eth, val, MTK_QDMA_DELAY_INT); 2443 2444 spin_unlock_bh(ð->dim_lock); 2445 2446 dim->state = DIM_START_MEASURE; 2447 } 2448 2449 static int mtk_hw_init(struct mtk_eth *eth) 2450 { 2451 int i, val, ret; 2452 2453 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 2454 return 0; 2455 2456 pm_runtime_enable(eth->dev); 2457 pm_runtime_get_sync(eth->dev); 2458 2459 ret = mtk_clk_enable(eth); 2460 if (ret) 2461 goto err_disable_pm; 2462 2463 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2464 ret = device_reset(eth->dev); 2465 if (ret) { 2466 dev_err(eth->dev, "MAC reset failed!\n"); 2467 goto err_disable_pm; 2468 } 2469 2470 /* set interrupt delays based on current Net DIM sample */ 2471 mtk_dim_rx(ð->rx_dim.work); 2472 mtk_dim_tx(ð->tx_dim.work); 2473 2474 /* disable delay and normal interrupt */ 2475 mtk_tx_irq_disable(eth, ~0); 2476 mtk_rx_irq_disable(eth, ~0); 2477 2478 return 0; 2479 } 2480 2481 /* Non-MT7628 handling... */ 2482 ethsys_reset(eth, RSTCTRL_FE); 2483 ethsys_reset(eth, RSTCTRL_PPE); 2484 2485 if (eth->pctl) { 2486 /* Set GE2 driving and slew rate */ 2487 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 2488 2489 /* set GE2 TDSEL */ 2490 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 2491 2492 /* set GE2 TUNE */ 2493 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 2494 } 2495 2496 /* Set linkdown as the default for each GMAC. Its own MCR would be set 2497 * up with the more appropriate value when mtk_mac_config call is being 2498 * invoked. 2499 */ 2500 for (i = 0; i < MTK_MAC_COUNT; i++) 2501 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 2502 2503 /* Indicates CDM to parse the MTK special tag from CPU 2504 * which also is working out for untag packets. 2505 */ 2506 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 2507 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 2508 2509 /* Enable RX VLan Offloading */ 2510 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 2511 2512 /* set interrupt delays based on current Net DIM sample */ 2513 mtk_dim_rx(ð->rx_dim.work); 2514 mtk_dim_tx(ð->tx_dim.work); 2515 2516 /* disable delay and normal interrupt */ 2517 mtk_tx_irq_disable(eth, ~0); 2518 mtk_rx_irq_disable(eth, ~0); 2519 2520 /* FE int grouping */ 2521 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 2522 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 2523 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 2524 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 2525 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 2526 2527 return 0; 2528 2529 err_disable_pm: 2530 pm_runtime_put_sync(eth->dev); 2531 pm_runtime_disable(eth->dev); 2532 2533 return ret; 2534 } 2535 2536 static int mtk_hw_deinit(struct mtk_eth *eth) 2537 { 2538 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2539 return 0; 2540 2541 mtk_clk_disable(eth); 2542 2543 pm_runtime_put_sync(eth->dev); 2544 pm_runtime_disable(eth->dev); 2545 2546 return 0; 2547 } 2548 2549 static int __init mtk_init(struct net_device *dev) 2550 { 2551 struct mtk_mac *mac = netdev_priv(dev); 2552 struct mtk_eth *eth = mac->hw; 2553 int ret; 2554 2555 ret = of_get_ethdev_address(mac->of_node, dev); 2556 if (ret) { 2557 /* If the mac address is invalid, use random mac address */ 2558 eth_hw_addr_random(dev); 2559 dev_err(eth->dev, "generated random MAC address %pM\n", 2560 dev->dev_addr); 2561 } 2562 2563 return 0; 2564 } 2565 2566 static void mtk_uninit(struct net_device *dev) 2567 { 2568 struct mtk_mac *mac = netdev_priv(dev); 2569 struct mtk_eth *eth = mac->hw; 2570 2571 phylink_disconnect_phy(mac->phylink); 2572 mtk_tx_irq_disable(eth, ~0); 2573 mtk_rx_irq_disable(eth, ~0); 2574 } 2575 2576 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 2577 { 2578 int length = new_mtu + MTK_RX_ETH_HLEN; 2579 struct mtk_mac *mac = netdev_priv(dev); 2580 struct mtk_eth *eth = mac->hw; 2581 u32 mcr_cur, mcr_new; 2582 2583 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2584 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 2585 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 2586 2587 if (length <= 1518) 2588 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 2589 else if (length <= 1536) 2590 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 2591 else if (length <= 1552) 2592 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 2593 else 2594 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 2595 2596 if (mcr_new != mcr_cur) 2597 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 2598 } 2599 2600 dev->mtu = new_mtu; 2601 2602 return 0; 2603 } 2604 2605 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2606 { 2607 struct mtk_mac *mac = netdev_priv(dev); 2608 2609 switch (cmd) { 2610 case SIOCGMIIPHY: 2611 case SIOCGMIIREG: 2612 case SIOCSMIIREG: 2613 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 2614 default: 2615 break; 2616 } 2617 2618 return -EOPNOTSUPP; 2619 } 2620 2621 static void mtk_pending_work(struct work_struct *work) 2622 { 2623 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2624 int err, i; 2625 unsigned long restart = 0; 2626 2627 rtnl_lock(); 2628 2629 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2630 2631 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2632 cpu_relax(); 2633 2634 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2635 /* stop all devices to make sure that dma is properly shut down */ 2636 for (i = 0; i < MTK_MAC_COUNT; i++) { 2637 if (!eth->netdev[i]) 2638 continue; 2639 mtk_stop(eth->netdev[i]); 2640 __set_bit(i, &restart); 2641 } 2642 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2643 2644 /* restart underlying hardware such as power, clock, pin mux 2645 * and the connected phy 2646 */ 2647 mtk_hw_deinit(eth); 2648 2649 if (eth->dev->pins) 2650 pinctrl_select_state(eth->dev->pins->p, 2651 eth->dev->pins->default_state); 2652 mtk_hw_init(eth); 2653 2654 /* restart DMA and enable IRQs */ 2655 for (i = 0; i < MTK_MAC_COUNT; i++) { 2656 if (!test_bit(i, &restart)) 2657 continue; 2658 err = mtk_open(eth->netdev[i]); 2659 if (err) { 2660 netif_alert(eth, ifup, eth->netdev[i], 2661 "Driver up/down cycle failed, closing device.\n"); 2662 dev_close(eth->netdev[i]); 2663 } 2664 } 2665 2666 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2667 2668 clear_bit_unlock(MTK_RESETTING, ð->state); 2669 2670 rtnl_unlock(); 2671 } 2672 2673 static int mtk_free_dev(struct mtk_eth *eth) 2674 { 2675 int i; 2676 2677 for (i = 0; i < MTK_MAC_COUNT; i++) { 2678 if (!eth->netdev[i]) 2679 continue; 2680 free_netdev(eth->netdev[i]); 2681 } 2682 2683 return 0; 2684 } 2685 2686 static int mtk_unreg_dev(struct mtk_eth *eth) 2687 { 2688 int i; 2689 2690 for (i = 0; i < MTK_MAC_COUNT; i++) { 2691 if (!eth->netdev[i]) 2692 continue; 2693 unregister_netdev(eth->netdev[i]); 2694 } 2695 2696 return 0; 2697 } 2698 2699 static int mtk_cleanup(struct mtk_eth *eth) 2700 { 2701 mtk_unreg_dev(eth); 2702 mtk_free_dev(eth); 2703 cancel_work_sync(ð->pending_work); 2704 2705 return 0; 2706 } 2707 2708 static int mtk_get_link_ksettings(struct net_device *ndev, 2709 struct ethtool_link_ksettings *cmd) 2710 { 2711 struct mtk_mac *mac = netdev_priv(ndev); 2712 2713 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2714 return -EBUSY; 2715 2716 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 2717 } 2718 2719 static int mtk_set_link_ksettings(struct net_device *ndev, 2720 const struct ethtool_link_ksettings *cmd) 2721 { 2722 struct mtk_mac *mac = netdev_priv(ndev); 2723 2724 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2725 return -EBUSY; 2726 2727 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 2728 } 2729 2730 static void mtk_get_drvinfo(struct net_device *dev, 2731 struct ethtool_drvinfo *info) 2732 { 2733 struct mtk_mac *mac = netdev_priv(dev); 2734 2735 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2736 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2737 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2738 } 2739 2740 static u32 mtk_get_msglevel(struct net_device *dev) 2741 { 2742 struct mtk_mac *mac = netdev_priv(dev); 2743 2744 return mac->hw->msg_enable; 2745 } 2746 2747 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2748 { 2749 struct mtk_mac *mac = netdev_priv(dev); 2750 2751 mac->hw->msg_enable = value; 2752 } 2753 2754 static int mtk_nway_reset(struct net_device *dev) 2755 { 2756 struct mtk_mac *mac = netdev_priv(dev); 2757 2758 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2759 return -EBUSY; 2760 2761 if (!mac->phylink) 2762 return -ENOTSUPP; 2763 2764 return phylink_ethtool_nway_reset(mac->phylink); 2765 } 2766 2767 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2768 { 2769 int i; 2770 2771 switch (stringset) { 2772 case ETH_SS_STATS: 2773 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2774 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2775 data += ETH_GSTRING_LEN; 2776 } 2777 break; 2778 } 2779 } 2780 2781 static int mtk_get_sset_count(struct net_device *dev, int sset) 2782 { 2783 switch (sset) { 2784 case ETH_SS_STATS: 2785 return ARRAY_SIZE(mtk_ethtool_stats); 2786 default: 2787 return -EOPNOTSUPP; 2788 } 2789 } 2790 2791 static void mtk_get_ethtool_stats(struct net_device *dev, 2792 struct ethtool_stats *stats, u64 *data) 2793 { 2794 struct mtk_mac *mac = netdev_priv(dev); 2795 struct mtk_hw_stats *hwstats = mac->hw_stats; 2796 u64 *data_src, *data_dst; 2797 unsigned int start; 2798 int i; 2799 2800 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2801 return; 2802 2803 if (netif_running(dev) && netif_device_present(dev)) { 2804 if (spin_trylock_bh(&hwstats->stats_lock)) { 2805 mtk_stats_update_mac(mac); 2806 spin_unlock_bh(&hwstats->stats_lock); 2807 } 2808 } 2809 2810 data_src = (u64 *)hwstats; 2811 2812 do { 2813 data_dst = data; 2814 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2815 2816 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2817 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2818 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2819 } 2820 2821 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2822 u32 *rule_locs) 2823 { 2824 int ret = -EOPNOTSUPP; 2825 2826 switch (cmd->cmd) { 2827 case ETHTOOL_GRXRINGS: 2828 if (dev->hw_features & NETIF_F_LRO) { 2829 cmd->data = MTK_MAX_RX_RING_NUM; 2830 ret = 0; 2831 } 2832 break; 2833 case ETHTOOL_GRXCLSRLCNT: 2834 if (dev->hw_features & NETIF_F_LRO) { 2835 struct mtk_mac *mac = netdev_priv(dev); 2836 2837 cmd->rule_cnt = mac->hwlro_ip_cnt; 2838 ret = 0; 2839 } 2840 break; 2841 case ETHTOOL_GRXCLSRULE: 2842 if (dev->hw_features & NETIF_F_LRO) 2843 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2844 break; 2845 case ETHTOOL_GRXCLSRLALL: 2846 if (dev->hw_features & NETIF_F_LRO) 2847 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2848 rule_locs); 2849 break; 2850 default: 2851 break; 2852 } 2853 2854 return ret; 2855 } 2856 2857 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2858 { 2859 int ret = -EOPNOTSUPP; 2860 2861 switch (cmd->cmd) { 2862 case ETHTOOL_SRXCLSRLINS: 2863 if (dev->hw_features & NETIF_F_LRO) 2864 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2865 break; 2866 case ETHTOOL_SRXCLSRLDEL: 2867 if (dev->hw_features & NETIF_F_LRO) 2868 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2869 break; 2870 default: 2871 break; 2872 } 2873 2874 return ret; 2875 } 2876 2877 static const struct ethtool_ops mtk_ethtool_ops = { 2878 .get_link_ksettings = mtk_get_link_ksettings, 2879 .set_link_ksettings = mtk_set_link_ksettings, 2880 .get_drvinfo = mtk_get_drvinfo, 2881 .get_msglevel = mtk_get_msglevel, 2882 .set_msglevel = mtk_set_msglevel, 2883 .nway_reset = mtk_nway_reset, 2884 .get_link = ethtool_op_get_link, 2885 .get_strings = mtk_get_strings, 2886 .get_sset_count = mtk_get_sset_count, 2887 .get_ethtool_stats = mtk_get_ethtool_stats, 2888 .get_rxnfc = mtk_get_rxnfc, 2889 .set_rxnfc = mtk_set_rxnfc, 2890 }; 2891 2892 static const struct net_device_ops mtk_netdev_ops = { 2893 .ndo_init = mtk_init, 2894 .ndo_uninit = mtk_uninit, 2895 .ndo_open = mtk_open, 2896 .ndo_stop = mtk_stop, 2897 .ndo_start_xmit = mtk_start_xmit, 2898 .ndo_set_mac_address = mtk_set_mac_address, 2899 .ndo_validate_addr = eth_validate_addr, 2900 .ndo_eth_ioctl = mtk_do_ioctl, 2901 .ndo_change_mtu = mtk_change_mtu, 2902 .ndo_tx_timeout = mtk_tx_timeout, 2903 .ndo_get_stats64 = mtk_get_stats64, 2904 .ndo_fix_features = mtk_fix_features, 2905 .ndo_set_features = mtk_set_features, 2906 #ifdef CONFIG_NET_POLL_CONTROLLER 2907 .ndo_poll_controller = mtk_poll_controller, 2908 #endif 2909 .ndo_setup_tc = mtk_eth_setup_tc, 2910 }; 2911 2912 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2913 { 2914 const __be32 *_id = of_get_property(np, "reg", NULL); 2915 phy_interface_t phy_mode; 2916 struct phylink *phylink; 2917 struct mtk_mac *mac; 2918 int id, err; 2919 2920 if (!_id) { 2921 dev_err(eth->dev, "missing mac id\n"); 2922 return -EINVAL; 2923 } 2924 2925 id = be32_to_cpup(_id); 2926 if (id >= MTK_MAC_COUNT) { 2927 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2928 return -EINVAL; 2929 } 2930 2931 if (eth->netdev[id]) { 2932 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2933 return -EINVAL; 2934 } 2935 2936 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2937 if (!eth->netdev[id]) { 2938 dev_err(eth->dev, "alloc_etherdev failed\n"); 2939 return -ENOMEM; 2940 } 2941 mac = netdev_priv(eth->netdev[id]); 2942 eth->mac[id] = mac; 2943 mac->id = id; 2944 mac->hw = eth; 2945 mac->of_node = np; 2946 2947 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2948 mac->hwlro_ip_cnt = 0; 2949 2950 mac->hw_stats = devm_kzalloc(eth->dev, 2951 sizeof(*mac->hw_stats), 2952 GFP_KERNEL); 2953 if (!mac->hw_stats) { 2954 dev_err(eth->dev, "failed to allocate counter memory\n"); 2955 err = -ENOMEM; 2956 goto free_netdev; 2957 } 2958 spin_lock_init(&mac->hw_stats->stats_lock); 2959 u64_stats_init(&mac->hw_stats->syncp); 2960 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2961 2962 /* phylink create */ 2963 err = of_get_phy_mode(np, &phy_mode); 2964 if (err) { 2965 dev_err(eth->dev, "incorrect phy-mode\n"); 2966 goto free_netdev; 2967 } 2968 2969 /* mac config is not set */ 2970 mac->interface = PHY_INTERFACE_MODE_NA; 2971 mac->mode = MLO_AN_PHY; 2972 mac->speed = SPEED_UNKNOWN; 2973 2974 mac->phylink_config.dev = ð->netdev[id]->dev; 2975 mac->phylink_config.type = PHYLINK_NETDEV; 2976 /* This driver makes use of state->speed/state->duplex in 2977 * mac_config 2978 */ 2979 mac->phylink_config.legacy_pre_march2020 = true; 2980 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2981 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 2982 2983 __set_bit(PHY_INTERFACE_MODE_MII, 2984 mac->phylink_config.supported_interfaces); 2985 __set_bit(PHY_INTERFACE_MODE_GMII, 2986 mac->phylink_config.supported_interfaces); 2987 2988 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 2989 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 2990 2991 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 2992 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2993 mac->phylink_config.supported_interfaces); 2994 2995 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 2996 __set_bit(PHY_INTERFACE_MODE_SGMII, 2997 mac->phylink_config.supported_interfaces); 2998 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2999 mac->phylink_config.supported_interfaces); 3000 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 3001 mac->phylink_config.supported_interfaces); 3002 } 3003 3004 phylink = phylink_create(&mac->phylink_config, 3005 of_fwnode_handle(mac->of_node), 3006 phy_mode, &mtk_phylink_ops); 3007 if (IS_ERR(phylink)) { 3008 err = PTR_ERR(phylink); 3009 goto free_netdev; 3010 } 3011 3012 mac->phylink = phylink; 3013 3014 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 3015 eth->netdev[id]->watchdog_timeo = 5 * HZ; 3016 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 3017 eth->netdev[id]->base_addr = (unsigned long)eth->base; 3018 3019 eth->netdev[id]->hw_features = eth->soc->hw_features; 3020 if (eth->hwlro) 3021 eth->netdev[id]->hw_features |= NETIF_F_LRO; 3022 3023 eth->netdev[id]->vlan_features = eth->soc->hw_features & 3024 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 3025 eth->netdev[id]->features |= eth->soc->hw_features; 3026 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 3027 3028 eth->netdev[id]->irq = eth->irq[0]; 3029 eth->netdev[id]->dev.of_node = np; 3030 3031 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3032 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 3033 else 3034 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 3035 3036 return 0; 3037 3038 free_netdev: 3039 free_netdev(eth->netdev[id]); 3040 return err; 3041 } 3042 3043 static int mtk_probe(struct platform_device *pdev) 3044 { 3045 struct device_node *mac_np; 3046 struct mtk_eth *eth; 3047 int err, i; 3048 3049 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 3050 if (!eth) 3051 return -ENOMEM; 3052 3053 eth->soc = of_device_get_match_data(&pdev->dev); 3054 3055 eth->dev = &pdev->dev; 3056 eth->base = devm_platform_ioremap_resource(pdev, 0); 3057 if (IS_ERR(eth->base)) 3058 return PTR_ERR(eth->base); 3059 3060 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3061 eth->tx_int_mask_reg = MTK_QDMA_INT_MASK; 3062 eth->tx_int_status_reg = MTK_QDMA_INT_STATUS; 3063 } else { 3064 eth->tx_int_mask_reg = MTK_PDMA_INT_MASK; 3065 eth->tx_int_status_reg = MTK_PDMA_INT_STATUS; 3066 } 3067 3068 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3069 eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA; 3070 eth->ip_align = NET_IP_ALIGN; 3071 } else { 3072 eth->rx_dma_l4_valid = RX_DMA_L4_VALID; 3073 } 3074 3075 spin_lock_init(ð->page_lock); 3076 spin_lock_init(ð->tx_irq_lock); 3077 spin_lock_init(ð->rx_irq_lock); 3078 spin_lock_init(ð->dim_lock); 3079 3080 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3081 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 3082 3083 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3084 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 3085 3086 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3087 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3088 "mediatek,ethsys"); 3089 if (IS_ERR(eth->ethsys)) { 3090 dev_err(&pdev->dev, "no ethsys regmap found\n"); 3091 return PTR_ERR(eth->ethsys); 3092 } 3093 } 3094 3095 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 3096 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3097 "mediatek,infracfg"); 3098 if (IS_ERR(eth->infra)) { 3099 dev_err(&pdev->dev, "no infracfg regmap found\n"); 3100 return PTR_ERR(eth->infra); 3101 } 3102 } 3103 3104 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 3105 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 3106 GFP_KERNEL); 3107 if (!eth->sgmii) 3108 return -ENOMEM; 3109 3110 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 3111 eth->soc->ana_rgc3); 3112 3113 if (err) 3114 return err; 3115 } 3116 3117 if (eth->soc->required_pctl) { 3118 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3119 "mediatek,pctl"); 3120 if (IS_ERR(eth->pctl)) { 3121 dev_err(&pdev->dev, "no pctl regmap found\n"); 3122 return PTR_ERR(eth->pctl); 3123 } 3124 } 3125 3126 for (i = 0; i < 3; i++) { 3127 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 3128 eth->irq[i] = eth->irq[0]; 3129 else 3130 eth->irq[i] = platform_get_irq(pdev, i); 3131 if (eth->irq[i] < 0) { 3132 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 3133 return -ENXIO; 3134 } 3135 } 3136 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 3137 eth->clks[i] = devm_clk_get(eth->dev, 3138 mtk_clks_source_name[i]); 3139 if (IS_ERR(eth->clks[i])) { 3140 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 3141 return -EPROBE_DEFER; 3142 if (eth->soc->required_clks & BIT(i)) { 3143 dev_err(&pdev->dev, "clock %s not found\n", 3144 mtk_clks_source_name[i]); 3145 return -EINVAL; 3146 } 3147 eth->clks[i] = NULL; 3148 } 3149 } 3150 3151 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 3152 INIT_WORK(ð->pending_work, mtk_pending_work); 3153 3154 err = mtk_hw_init(eth); 3155 if (err) 3156 return err; 3157 3158 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 3159 3160 for_each_child_of_node(pdev->dev.of_node, mac_np) { 3161 if (!of_device_is_compatible(mac_np, 3162 "mediatek,eth-mac")) 3163 continue; 3164 3165 if (!of_device_is_available(mac_np)) 3166 continue; 3167 3168 err = mtk_add_mac(eth, mac_np); 3169 if (err) { 3170 of_node_put(mac_np); 3171 goto err_deinit_hw; 3172 } 3173 } 3174 3175 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 3176 err = devm_request_irq(eth->dev, eth->irq[0], 3177 mtk_handle_irq, 0, 3178 dev_name(eth->dev), eth); 3179 } else { 3180 err = devm_request_irq(eth->dev, eth->irq[1], 3181 mtk_handle_irq_tx, 0, 3182 dev_name(eth->dev), eth); 3183 if (err) 3184 goto err_free_dev; 3185 3186 err = devm_request_irq(eth->dev, eth->irq[2], 3187 mtk_handle_irq_rx, 0, 3188 dev_name(eth->dev), eth); 3189 } 3190 if (err) 3191 goto err_free_dev; 3192 3193 /* No MT7628/88 support yet */ 3194 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3195 err = mtk_mdio_init(eth); 3196 if (err) 3197 goto err_free_dev; 3198 } 3199 3200 if (eth->soc->offload_version) { 3201 err = mtk_ppe_init(ð->ppe, eth->dev, 3202 eth->base + MTK_ETH_PPE_BASE, 2); 3203 if (err) 3204 goto err_free_dev; 3205 3206 err = mtk_eth_offload_init(eth); 3207 if (err) 3208 goto err_free_dev; 3209 } 3210 3211 for (i = 0; i < MTK_MAX_DEVS; i++) { 3212 if (!eth->netdev[i]) 3213 continue; 3214 3215 err = register_netdev(eth->netdev[i]); 3216 if (err) { 3217 dev_err(eth->dev, "error bringing up device\n"); 3218 goto err_deinit_mdio; 3219 } else 3220 netif_info(eth, probe, eth->netdev[i], 3221 "mediatek frame engine at 0x%08lx, irq %d\n", 3222 eth->netdev[i]->base_addr, eth->irq[0]); 3223 } 3224 3225 /* we run 2 devices on the same DMA ring so we need a dummy device 3226 * for NAPI to work 3227 */ 3228 init_dummy_netdev(ð->dummy_dev); 3229 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 3230 MTK_NAPI_WEIGHT); 3231 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 3232 MTK_NAPI_WEIGHT); 3233 3234 platform_set_drvdata(pdev, eth); 3235 3236 return 0; 3237 3238 err_deinit_mdio: 3239 mtk_mdio_cleanup(eth); 3240 err_free_dev: 3241 mtk_free_dev(eth); 3242 err_deinit_hw: 3243 mtk_hw_deinit(eth); 3244 3245 return err; 3246 } 3247 3248 static int mtk_remove(struct platform_device *pdev) 3249 { 3250 struct mtk_eth *eth = platform_get_drvdata(pdev); 3251 struct mtk_mac *mac; 3252 int i; 3253 3254 /* stop all devices to make sure that dma is properly shut down */ 3255 for (i = 0; i < MTK_MAC_COUNT; i++) { 3256 if (!eth->netdev[i]) 3257 continue; 3258 mtk_stop(eth->netdev[i]); 3259 mac = netdev_priv(eth->netdev[i]); 3260 phylink_disconnect_phy(mac->phylink); 3261 } 3262 3263 mtk_hw_deinit(eth); 3264 3265 netif_napi_del(ð->tx_napi); 3266 netif_napi_del(ð->rx_napi); 3267 mtk_cleanup(eth); 3268 mtk_mdio_cleanup(eth); 3269 3270 return 0; 3271 } 3272 3273 static const struct mtk_soc_data mt2701_data = { 3274 .caps = MT7623_CAPS | MTK_HWLRO, 3275 .hw_features = MTK_HW_FEATURES, 3276 .required_clks = MT7623_CLKS_BITMAP, 3277 .required_pctl = true, 3278 }; 3279 3280 static const struct mtk_soc_data mt7621_data = { 3281 .caps = MT7621_CAPS, 3282 .hw_features = MTK_HW_FEATURES, 3283 .required_clks = MT7621_CLKS_BITMAP, 3284 .required_pctl = false, 3285 .offload_version = 2, 3286 }; 3287 3288 static const struct mtk_soc_data mt7622_data = { 3289 .ana_rgc3 = 0x2028, 3290 .caps = MT7622_CAPS | MTK_HWLRO, 3291 .hw_features = MTK_HW_FEATURES, 3292 .required_clks = MT7622_CLKS_BITMAP, 3293 .required_pctl = false, 3294 .offload_version = 2, 3295 }; 3296 3297 static const struct mtk_soc_data mt7623_data = { 3298 .caps = MT7623_CAPS | MTK_HWLRO, 3299 .hw_features = MTK_HW_FEATURES, 3300 .required_clks = MT7623_CLKS_BITMAP, 3301 .required_pctl = true, 3302 .offload_version = 2, 3303 }; 3304 3305 static const struct mtk_soc_data mt7629_data = { 3306 .ana_rgc3 = 0x128, 3307 .caps = MT7629_CAPS | MTK_HWLRO, 3308 .hw_features = MTK_HW_FEATURES, 3309 .required_clks = MT7629_CLKS_BITMAP, 3310 .required_pctl = false, 3311 }; 3312 3313 static const struct mtk_soc_data rt5350_data = { 3314 .caps = MT7628_CAPS, 3315 .hw_features = MTK_HW_FEATURES_MT7628, 3316 .required_clks = MT7628_CLKS_BITMAP, 3317 .required_pctl = false, 3318 }; 3319 3320 const struct of_device_id of_mtk_match[] = { 3321 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 3322 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 3323 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 3324 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 3325 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 3326 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 3327 {}, 3328 }; 3329 MODULE_DEVICE_TABLE(of, of_mtk_match); 3330 3331 static struct platform_driver mtk_driver = { 3332 .probe = mtk_probe, 3333 .remove = mtk_remove, 3334 .driver = { 3335 .name = "mtk_soc_eth", 3336 .of_match_table = of_mtk_match, 3337 }, 3338 }; 3339 3340 module_platform_driver(mtk_driver); 3341 3342 MODULE_LICENSE("GPL"); 3343 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 3344 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 3345